EE2354

LTPC 3003 UNIT I 8085 and 8086 PROCESSOR 9 Hardware Architecture pintouts - Signals Memory interfacing I/O ports and data transfer concepts Timing Diagram Interrupt structure. UNIT II PROGRAMMING OF 8085 PROCESSOR 9 Instruction format and addressing modes Assembly language format Data transfer, data manipulation & control instructions Programming: Loop structure with counting & Indexing Look up table - Subroutine instructions - stack. UNIT III PERIPHERAL INTERFACING 9 Study of Architecture and programming of ICs: 8255 PPI, 8259 PIC, 8251 USART, 8279 Key boarddisplay controller and 8253 Timer/ Counter Interfacing with 8085 - A/D and D/A converter interfacing. UNIT IV 8051 MICRO CONTROLLER 9 Functional block diagram - Instruction format and addressing modes Timing Diagram Interrupt structure Timer I/O ports Serial communication. UNIT V MICRO CONTROLLER PROGRAMMING & APPLICATIONS 9 Data Transfer, Manipulation, Control & I/O instructions Simple programming exercises key board and display interface Closed loop control of servo motor- stepper motor control Washing Machine Control. L = 45 T = 15 TOTAL : 60 PERIODS TEXT BOOKS 1. Microprocessor and Microcontrollers, Krishna Kant Eastern Company Edition, Prentice Hall of India, New Delhi , 2007. 2. Muhammad Ali Mazidi & Janice Gilli Mazidi, R.D.Kinely The 8051 Micro Controller and Embedded Systems, PHI Pearson Education, 5th Indian reprint, 2003. REFERENCES 1. R.S. Gaonkar, Microprocessor Architecture Programming and Application, Wiley Eastern Ltd., New Delhi. 2. The 8088 & 8086 Microprocessors , Walter A Tribal & Avtar Singh, Pearson, 2007, Fourth Edition.

MICROPROCESSORS AND MICRO CONTROLLER

SUBJECT NAME SUBJECT CODE

:MICROPROCESSORS AND MICRO CONTROLLER : EE2354 UNIT I 8085 and 8086 PROCESSOR PART-A

(1MARKS)

1.The devices that provide the means for a computer to communicate with the user or other computers are referred to as: a. CPU b. ALU c. I/O d. none 2. The software used to drive microprocessor-based systems is called: a. assembly language b. firmware c. I/O d. none 3. The circuits in the 8085A that provide the arithmetic and logic functions are called the: a. CPU b. ALU c. I/O d. none 4. How many buses are connected as part of the 8085A microprocessor? a. 2 b. 3 c. 5 d. 8 5. The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus. a. control bus b. control instructions c. I/O d. none 6. How many bits are used in the data bus? a. 7 b. 8 c. 9 d.16 7. The items that you can physically touch in a computer system are called: a. software b. firmware c. I/O d. none 8. Single-bit indicators that may be set or cleared to show the results of logical or arithmetic operations are the: a. flags b. registers c. Monitors d. decisions 9. When referring to instruction words, a mnemonic is: a. a short abbreviation for the operand address b. a short abbreviation for the operation to be performed c. a short abbreviation for the data word stored at the operand address d. shorthand for machine language 10. The technique of assigning a memory address to each I/O device in the computer system is called: a. memory-mapped I/O b. ported I/O c. I/O d. none 11. When was the first 8-bit microprocessor introduced? a. 1969 b. 1974 c. 1979 d. 1985 12. What type of circuit is used at the interface point of an output port? a. decoder b. latch c. tri-state buffer d. none 13. I/O mapped systems identify their input/output devices by giving them a(n) a. 8-bit port number b. 16 bit port numberc. 8 bit buffer number d.8bit instruction 14. What type of circuit is used at the interface point of an input port? a. decoder b. latch c. tri-state buffer d. none 15. The register in the 8085A that is used to keep track of the memory address of the next op-code to be run in the program is the: a. stack pointer b. program counter c. tri-state biffer d. none 16. The control bus and memories share________ a bus in a typical microprocessor system.

a. unidirectional b. bidirectional c. both a and b d. control 17. All computer programs for a machine are called: a. software b. firm ware c. tri-state buffer d. none 18. The 8085A is a(n): a. 16-bit parallel CPU b. 8-bit serial CPU c. tri-state buffer d. none 19. Because microprocessor CPUs do not understand mnemonics as they are, they have to be converted to ________. a. hexadecimal machine code b. binary machine code c. tri-state buffer d. none 20. A register in the microprocessor that keeps track of the answer or results of any arithmetic or logic operation is the: a. stack pointer b. program counter c. tri-state buffer d. none Answer: 1 c 2 a 3 b 4 b 5 c 6 b 7 c 8 a 9 b 10 11 12 13 14 15 16 17 18 19 20 a b b a c b b a c b d

PART B

(2 MARKS)

1. What is Microprocessor? It is a program controlled semiconductor device (IC}, which fetches, decodes and executes instructions. (or) A microprocessor is a multipurpose, programmable logic device that reads binary instructions from a storage device called memory accepts binary data as input and processes data according to those instructions and provides result as output. 2. What are the basic units of a microprocessor? [APRIL-2010] The basic units or blocks of a microprocessor are ALU, an array of registers and control unit. 3. What is Software and Hardware?[Nov-2009] The Software is a set of instructions or commands needed for performing a specific task by a programmable device or a computing machine. The Hardware refers to the components or devices used to form computing machine in which the software can be run and tested. Without software the Hardware is an idle machine. 4. What is assembly language?[NOV-2010] The language in which the mnemonics (short -hand form of instructions) are used to write a program is called assembly language. The manufacturers of microprocessor give the mnemonics. 5. What are machine language and assembly language programs? [Nov-2007] The software developed using 1's and 0's are called machine language, programs. The software developed using mnemonics are called assembly language programs. 6. What is the drawback in machine language and assembly language programs? The machine language and assembly language programs are machine dependent. The programs developed using these languages for a particular machine cannot be directly run on another machine.

7. Define bit, byte and word.[APRIL-2009] A digit of the binary number or code is called bit. Also, the bit is the fundamental storage unit of computer memory. The 8-bit (8-digit) binary number or code is called byte and 16-bit binary number or code is called word. 8. What is a bus? [NOV-2008] Bus is a group of conducting lines that carries data, address and control signals. 9. Why data bus is bi-directional? The microprocessor has to fetch (read) the data from memory or input device for processing and after processing, it has to store (write) the data to memory or output device. Hence the data bus is bi- directional. 10. Why address bus is unidirectional?[NOV-2008] The address is an identification number used by the microprocessor to identify or access a memory location or I / O device. It is an output signal from the processor. Hence the address bus is unidirectional. 11. What is the function of microprocessor in a system? [Nov-2010] The microprocessor is the master in the system, which controls all the activity of the system. It issues address and control signals and fetches the instruction and data from memory. Then it executes the instruction to take appropriate action. 12. What is the need for timing diagram? [April-2012] The timing diagram provides information regarding the status of various signals, when a machine cycle is executed. The knowledge of timing diagram is essential for system designer to select matched peripheral devices like memories, latches, ports, etc., to form a microprocessor system. 13. How many machine cycles constitute one instruction cycle in 8085? Each instruction of the 8085 processor consists of one to five machine cycles. 14. Define opcode and operand. Opcode (Operation code) is the part of an instruction / directive that identifies a specific operation.Operand is a part of an instruction / directive that represents a value on which the instruction acts. 15. What is opcode fetch cycle? [April-2007] The opcode fetch cycle is a machine cycle executed to fetch the opcode of an instruction stored in memory. Every instruction starts with opcode fetch machine cycle. 16. How many machine cycles does 8085 have, mention them? [may/june- 2011] In 8085 have 9 machine cycles, they are opcode fetch, memory read, memory write, I/O read, I/O write, Interrupt acknowledge, halt, hold & reset. 17. How does the microprocessor differentiate between data and instruction? When the first m/c code of an instruction is fetched and decoded in the instruction register, the microprocessor recognizes the number of bytes required to fetch the entire instruction. For example MVI A, Data, the second byte is always considered as data. If the data byte is omitted by mistake whatever is in that memory location will be considered as data & the byteafterthedatawillbetreated as the next instruction. 18. What is meant by polling? Polling or device polling is a process which identifies the device that has interrupted the microprocessor. 19. What is meant by interrupt?

Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine 20.Compare CALL and PUSH instructions CALL 1. When CALL is executed the microprocessor automatically stores the 16-bit address of the instruction next to CALL on the stack. 2.When CALL is executed the stack pointer is decremented by two PUSH 1.PUSH The programmer uses the instruction to save the contents of the register pair on the stack 2. When PUSH is executed the stack pointer is decremented by two

PART C

(16 MARKS)

1. Draw the block diagram of 8085 mp and explain?[MAY-2012] 2. Explain the instruction set of 8085? APRIL/MAY-2009] 3. Write notes on status flag? [APRIL/MAY-2009] 4. Explain the architecture of Intel 8085 with the help of a block diagram? [ may/june 2011] 5. Explain the similarities diff b/w subtract and compare instructions in 8085? 6. Describe the sequence of event that may occur during the different T state in the opcode fetch machine cycle of 8085? 7. Write an assembly language program to convert on array of ASCII code to corresponding binary (hex) value. The ASCII array is stored starting from 4200H.The first element of the number of elements in the array. 8. List out the mask able and non mask able interrupts available in 8085? 9. How do the instructions of 8085 is classified based on their function and word length? 10. Write an ALP to add two 8bit numbers? 11. Write an assembly language program to generate Fibonacci number.[may/june 2011] 12. Write a program to generate the factorial number from 0 to 8.[may/june 2011] 13. Write a program for stepper motor to rotate in clockwise direction using 8085.[ may/june 2011] UNIT II PROGRAMMING OF 8085 PROCESSOR PART A (1 MARKS) 1. What is the difference between a mnemonic code and machine code? a. There is no difference. b. Machine codes are in binary, mnemonic codes are in shorthand English. c. Machine codes are in shorthand English, mnemonic codes are in binary. d. none 2. Which bus is a bidirectional bus? a. address bus b. data bus c. tri-state buffer d. none

3. Which of the following buses is primarily used to carry signals that direct other ICs to find outwhat type of operation is being performed? a. data bus b. control bus c. address bus d. none 4. What kind of computer program is used to convert mnemonic code to machine code? a. debug b. assembler c. C++ d. fortran 5. Which of the following are the three basic sections of a microprocessor unit? a. operand, register, and arithmetic/logic unit (ALU) b. control and timing, register, and arithmetic/logic unit (ALU) c. control and timing, register, and memory d. arithmetic/logic unit (ALU), memory, and input/output 6. Which interrupt has the highest priority? A. INTR B. TRAP C. RST6.5 d. RST 5.5 7. In 8085 name the 16 bit registers? A) Stack pointer B) Program counter C) a & b D. none 8. Which of the following is hardware interrupts? a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b d. none 9. What is the RST for the TRAP? a) RST5.5 b) RST4.5 c) RST4 d) none 10. What are level Triggering interrupts? a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5 d) none 11. Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b. d) none 12. What are software interrupts? a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP d) none 13. Which stack is used in 8085? a) FIFO b) LIFO c) FILO d) LOFI 14. Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b. d) none 15. What is SIM? a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask. d) none 16. RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not c) a & b d) none 17. What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer. c) none d) a & b 18. In 8086, Example for Non maskable interrupts are a) Trap b) RST6.5 c) INTR d) none 19. What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width d) none

20. Can ROM be used as stack? a) Yes b) No c) sometimes yes, sometimes no Answer: 1 b 2 b 3 b 4 b 5 b 6 c 7 c 8 c 9 b 10 11 12 13 14 15 16 17 18 19 20 b b a b a c b b a c b

PART B

(2 MARKS)

1. What is a programmable peripheral device? [NOV-2008] If the functions performed by a peripheral device can be altered or changed by a program instruction then the peripheral device is called programmable device. Usually the programmable devices will have control registers. The device can be programmed by sending control word in the prescribed format to the control register. 2. What is synchronous data transfer scheme? [APRIL-2009] For synchronous data transfer scheme, the processor does not check the readiness of the device after a command has been issued for read/write operation. Fu this scheme the processor will request the device to get ready and then read/W1.ite to the device immediately after the request. In some synchronous schemes a small delay is allowed after the request. 3. What is asynchronous data transfer scheme? In asynchronous data transfer scheme, first the processor sends a request to the device for read/write operation. Then the processor keeps on polling the status of the device. Once the device is ready, the processor executes a data transfer instruction to complete the process. 4. What are the internal devices of 8255? [APRIL-2009] The internal devices of 8255 are port-A, port-B and port-C. The ports can be programmed for either input or output function in different operating modes. 5. What is USART? [NOV-2008] The device which can be programmed to perform Synchronous or Asynchronous serial communication is called USART (Universal Synchronous Asynchronous Receiver Transmitter). The INTEL 8251A is an example of USART. 6. What are the functions performed by INTEL 8251A? [Nov-2011] The INTEL 825lA is used for converting parallel data to serial or vice versa. The data transmission or reception can be either asynchronously or synchronously. The 8251A can be used to interface MODEM and establish serial communication through MODEM over telephone lines. 7. What is the information that can be obtained from the status word of 8251? The status word can be read by the CPU to check the readiness of the transmitter or receiver and to check the character synchronization in synchronous reception. It also provides information regarding various errors in the data received. The various error conditions that can be checked from the status word are parity error, overrun error and framing error. 8. What are the tasks involved in keyboard interface? [Nov-2012] The task involved in keyboard interfacing are sensing a key actuation, Debouncing the key and Generating key codes (Decoding the key).These task are performed software if the

keyboard is interfaced through ports and they are performed by hardware if the keyboard is interfaced through 8279. 9. How a keyboard matrix is formed in keyboard interface using 8279?[NOV-2008] The return lines, RLo to RL7 of 8279 are used to form the columns of keyboard matrix. In decoded scan the scan lines SLo to SL3 of 8279 are used to form the rows of keyboard matrix. In encoded scan mode, the output lines of external decoder are used as rows of keyboard matrix. 10. What is scanning in keyboard and what is scan time? The process of sending a zero to each row of a keyboard matrix and reading the columns for key actuation is called scanning. The scan time is the time taken by the processor to scan all the rows one by one starting from first row and coming back to the first row again. 11. What is the data and address size in 8086? [April-2012] The 8086 can operate on either 8-bit or 16-bit data. The 8086 uses 20 bit address to access memory and 16-bit address to access 1/0 devices. 12. Explain the function of M/IO in 8086.[NOV-2008] The signal M/IO is used to differentiate memory address and 1/0 address When the processor is accessing memory locations MI 10 is asserted high and when it is accessing 1/0 mapped devices it is asserted low. 13. Write the flags of 8086. [MAY-2012] The 8086 has nine flags and they are 1. Carry Flag (CF) 2. Overflow Flag (OF) 3. Parity Flag (PF) 4. Trace Flag (TF) 5. Auxiliary carries Flag (AF) 6. Interrupt Flag (IF) 7. Zero Flag (ZF) 8. Direction Flag (DF) 9. Sign Flag (SF) 14. What are the interrupts of 8086? [APRIL-2009] The interrupts of 8085 are INTR and NMI. The INTR is general maskable interrupt and NMI is non-maskable interrupt. 15. How clock signal is generated in 8086? What is the maximum internal clock frequency of 8086? The 8086 does not have on-chip clock generation circuit. Hence the clock generator chip, 8284 is connected to the CLK pin of8086. The clock signal supplied by 8284 is divided by three for internal use. The maximum internal clock frequency of8086 is 5MHz. 16. Write the special functions carried by the general purpose registers of 8086. The special functions carried by the registers of 8086 are the following. Register Special function 1. AX 16-bit Accumulator 2. AL 8-bit Accumulator 3. BX Base Register 4. CX Count Register 5. DX .Data Register 17. What is pipelined architecture? [APRIL-2009] In pipelined architecture the processor will have number of functional units and the execution time of functional units is overlapped. Each functional unit works independently most of the time. 18. What are the functional units available in 8086 architecture? [April-2005] The bus interface unit and execution unit are the two functional units available in 8086 architecture. 19. List the segment registers of 8086. [Nov-2004] The segment registers of 8086 are Code segment, Data segment, Stack segment and Extra segment registers.

20. Define machine cycle. [NOV-2008] Machine cycle is defined as the time required to complete one operation of accessing memory, I/O, or acknowledging an external request. This cycle may consist of three to six Tstates. 21. Define T-State. [APRIL-2009] T-State is defined as one subdivision of the operation performed in one clock period. These subdivisions are internal states synchronized with the system clock, and each T-State is precisely equal to one clock period. 22. List the components of microprocessor (single board microcomputer) based system The microprocessor based system consist of microprocessor as CPU, semiconductor memories like EPROM and RAM, input device, output device and interfacing devices. 23. What is settling or conversion time in DAC? [Nov-2004] The time taken by the DAC to convert a given digital data to corresponding analog signal is called conversion time. 24. How single stepping can be done in 8086? [may/june- 2011] By setting the Trace Flag (TF) the 8086 goes to single-step mode. In this mode, after the execution of each instruction s 8086 generates an internal interrupt and by writing some interrupt service routine we can display the content of desired registers and memory locations. So it is useful for debugging the program. 25. Differentiate between absolute and linear select coding [may/june- 2011] Absolute decoding Linear decoding All higher address lines are defined to select the Few higher address lines are decoded to select the memory or I/O device memory or I/O device More h/w is required to design decoding logic Higher cost for decoding circuit No multiple address Used in large systems Hardware required decoding logic is less Less cost for decoding circuit Has a disadvantage of multiple addressing Used in small systems to design

PART C

(16 MARKS)

1. Draw the Block diagram and explain the operations of 8251 serial communication Interface. [MAY-12] 2. Draw the Block diagram of 8279 and explain the functions of each block.[MAY-2009] 3. Draw the block diagram of programmable interrupt controller and explain its operations. 4. Discuss in detail about the operation of timer along with its various modes [MAY-12] 5. Draw the Block diagram of DMA controller and explain its operations.[MAY-2012] 6. Explain the DMA controller 8257? [A.U MAY-2008] 7. Draw the block diagram of 8255 and explain its working. What is Control Word? 8. Determine the control word for the following configuration of 8255:i) Port A Output ii) Mode of port A Mode 1 iii) Port B Output iv) Mode of port B Mode 0 v) Port C lower (pins PC0 PC2) Output 9. What is 8254? Discuss its various operating modes. What are its areas of Applications?

10. Explain major components of 8259 with the aid of suitable diagram. 11. Describe all the addressing modes of 8086 with suitable examples[A.U may/june 2011] 12. Explain in detail about the instruction sets of 8086. [A.U may/june 2011]Explain in detail about the different types of coprocessor configurations. [A.U may/june 2011] UNIT III PERIPHERAL INTERFACING PART A 1. Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors d) both a and 2. Address line for RST3 is? a) 0020H b) 0028H c) 0018H d) both a and 3. In 8086 the overflow flag is set when a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic operation c) Carry and sign flags are set d) During subtraction 4. The advantage of memory mapped I/O over I/O mapped I/O is, a) Faster b) Many instructions supporting memory mapped c) Require a bigger address decoder d) All the above 5. BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA 6. In 8086 microprocessor the following has the highest priority among all type interrupts. a) NMI b) DIV 0 c) TYPE 255 d) OVER FLOW 7. In 8086 microprocessor one of the following statements is not true. a) Coprocessor is interfaced in MAX mode b) Coprocessor is interfaced in MIN mode c) I/O can be interfaced in MAX / MIN mode d) Supports pipelining 8. 8088 microprocessor differs with 8086 microprocessor in a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode 9. Address line for TRAP is? a) 0023H b) 0024H c) 0033H d) 0045H 10. What is the shift register that will accept a parallel input, or a bidirectional serial load and internal shift features called, a) tristate b) end around c) universal d) conversation 11. Access time is faster for a) ROM b) SRAM c) DRAM d) PROM

(1 MARKS)

12. In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the____. a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte. 13.___ bit in ICW1 indicates whether the 8259A is cascade mode or not? a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1 14. In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2b) 2, Mode 2c) 4, Mode 3d) 3, Mode 2 15. In ADC 0808 if_______ pin high enables output. a) EOC b) I/P0-I/P7 c) SOC d) OE 16. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes____ to interrupt the CPU. a) CS, high b) A0,high c) IRQ, high d) STB, high 17. In 8279 Status Word, data is read when________ pins are low, and write to the display RAM with____________ are low. a) A0, CS, RD & A0, WR, CS. b) CS, WR, A0& A0, CS, RD c) A0, RD & WR, CS d) CS, RD & A0, CS. 18. In 8279, the keyboard entries are debounced and stored in an_________, that is further accessed by the CPU to read the key codes. a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO 19. The 8279 normally provides a maximum of_____ seven segment display interface with CPU. a) 8 b) 16 c) 32 d) 18 20. For the most Static RAM the write pulse width should be at least a) 10ns b) 60ns c) 300ns d) 1s Answer: 1 c 2 c 3 b 4 d 5 b 6 a 7 b 8 a 9 a 10 c 11 b 12 a 13 c 14 b 15 d 16 c 17 a 18 b 19 b 20 b

PART B

(2 MARKS)

1. What is the need of co- processors? Give an example? [may/june- 2011] The coprocessor is a processor which is specially designed processor to work under the control of the processor and to support special processing capabilities. For example, 8087 is a coprocessor. It works under the control of 8086 processor and has numeric processing capabilities. 2. Mention the advantages of using 8086 numeric data processor. [may/june- 2011]

However, some applications require extremely fast and complex math functions which are not provided by a general purpose processor. Such functions as square root, sine, cosine, and logarithms are not directly available in a general purpose processor. Providing fast, accurate, complex math can be quite complicated, requiring large areas of silicon on integrated circuits. 3. What are the advantages of multiprocessor system? 1. improves cost/ performance ratio of the system 2. tasks are divided among the modules. If failure occurs, it is easier and cheaper to find and replace the malfunctioning processor than replacing the falling part of complex processor. 4. What are the advantages of 8086 microprocessor system? 3. Better system throughput by having more than one processor. 4. system structure is more flexible 5. What are the instructions available in 8086? [may/june- 2009] b. Data transfer instructions c. arithmetic instructions d. compare instructions e. transcendental instructions f. load constant instructions g. processor control instructions 6. What are the features of 8086? [may/june- 2008] h. Instructions are specially designed for I/O processing. i. In addition to data transfer 8089 can perform arithmetic and logic operations, branches, searching and translation. PART C (16 MARKS ) 1. Explain the addressing modes of 8086 with the help of examples? And Write short notes on macro? [MAY-2012] 2. Explain the instruction set 8086? [MAY-2009] 3. Write an ALP in 8086 to find sum of numbers in array? 4. Explain the addressing modes of 8086 with the help of example? 5. Explain memory organization in 8086? 6. Explain the following assembler directives:[MAY-2012] i. ASSUME ii. EQU iii. DD IV. DW 7. With the neat sketch explain the architecture of 8086 processor? [NOV-2008] 8. Give the significance of O flag,Tflag,I flag &Dflag of 8086? 9. Describe the different techniques in which how CPU can communicate with IOP. [may/june 2011] 10. Explain briefly about an USART. [may/june 2012] UNIT IV 8051 MICRO CONTROLLER PART A (1 MARKS) 1. BURST refresh in DRAM is also called as a) Concentrated refresh b) distributed refresh c) Hidden refreshd) none

2. For the most Static RAM the maximum access time is about a) 1ns b) 10ns c) 100ns d) 1s 3. Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the internal buffers using RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii 4.8086 microprocessor is interfaced to 8253 a programmable interval timer.The maximum number by which the clock frequency on one of the timers is divided by a) 216 b) 28 c) 210 d) 220 5.8086 is interfaced to two 8259s (Programmable interrupt controllers).If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64 6. Which interrupt has the highest priority? a) INTR b) TRAP c) RST6.5 d) none 7. In 8085 name the 16 bit registers? a) Stack pointer b) Program counter c) a & b d) none 8. Which of the following is hardware interrupts? a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b d) none 9. What is the RST for the TRAP? a) RST5.5 b) RST4.5 c) RST4 d) none 10. What are level Triggering interrupts? a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5 d) none 11. Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b. d)none 12. What are software interrupts? a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP d) none 13. Which stack is used in 8085? a) FIFO b) LIFO c) FILO d) none 14.Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b. d) none 15. What is SIM? a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask. d)set info mask 16. RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not c) a & b d) none 17. What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer. c) none d) none 18. In 8086, Example for Non maskable interrupts are

a) Trap b) RST6.5 c) INTR d) none 19. What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width d) none 20. Can ROM be used as stack? d) none a) Yes b) No c) sometimes yes, sometimes no 21. What are software interrupts? a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP d) none Answer:
1 a 2 c 3 c 4 a 5 d 6 c 7 c 8 c 9 b 10 b 11 b 12 a 13 b 14 a 15 c 16 b 17 b 18 a 19 c 20 b

PART B

(2 MARKS)

1. What is mean by microcontroller?[April-2008] A device which contains the microprocessor with integrated p peripherals like memory, serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC is called microcontroller. 2. Why interfacing is needed for 1/0 devices? [Nov-2009] Generally I/O devices are slow devices. Therefore the speed of I/O devices does not match with the speed of microprocessor. And so an interface is provided between system bus and I/O devices. 3. What is the difference between CPU bus and system bus? The CPU bus has multiplexed lines but the system bus has separate lines for each signal. (The multiplexed CPU lines are demultiplexed by the CPU interface circuit to form system bus). 4. List the features of 8051 microcontroller?[APRIL-2012] The features are *single supply +5 volt operation using HMOS technology. *4096 bytes program memory on chip (not on 8031) *128 data memory on chip. *Four register banks. *Two multiple mode, 16-bit timer/counter. *Extensive Boolean processing capabilities. *64 KB external RAM size *32 bidirectional individually addressable I/O lines. *8 bit CPU optimized for control applications. 5. Explain the operating mode0 of 8051 serial ports? [Nov-2011] In this mode serial enters &exits through RXD, TXD outputs the shift clock.8 bits are transmitted/received:8 data bits(LSB first).The baud rate is fixed at 1/12 the oscillator frequency. 6. Explain the operating mode2 of 8051 serial ports? [NOV-2008] In this mode 11 bits are transmitted (through TXD) or received (through RXD):a start bit(0), 8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).ON transmit the 9th data bit (TB* in SCON)can be assigned the value of 0 or 1.Or for eg:, the parity bit(P, in the PSW)could be moved into TB8.On receive the 9th data bit go in to the RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32or1/64 the oscillator frequency. 7. Explain the mode3 of 8051 serial ports? [Nov-2009]

In this mode,11 bits are transmitted(through TXD)or received(through RXD):a start bit(0), 8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).In fact ,Mode3 is the same as Mode2 in all respects except the baud rate. The baud rate in Mode3 is variable. In all the four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode0 by the condition RI=0&REN=1.Reception is initiated in other modes by the incoming start bit if REN=1. 8. Explain the interrupts of 8051 microcontroller? [APRIL-2012] The interrupts are: Vector address External interrupt 0: IE0: 0003H Timer interrupt 0: TF0: 000BH External interrupts 1: IE1: 0013H Timer Interrupt 1: TF1: 001BH Serial Interrupt Receive interrupt: RI: 0023H Transmit interrupt: TI: 0023H 9. Write A program to perform multiplication of 2 nos using 8051?[NOV-2009] MOV A, data 1 MOV B, #data 2 MUL AB MOV DPTR, #5000 MOV @DPTR, A (lower value) INC DPTR MOV A, B MOVX @ DPTR, A 10. Write a program to mask the 0th &7th bit using 8051?[APRIL-2009] MOV A, data ANL A, #81 MOV DPTR, #4500 MOVX @DPTR, A LOOP SJMP LOOP 11. Write program to load accumulator, DPH, &DPL using 8051? [Nov-2007] MOV A,#30 MOV DPH, A MOV DPL, A 12. Write a program to find the 2s complement using 8051? [NOV-2008] MOV A, R0 CPL A INC A 13. Write the features of mode 0 in 8255. [ may/june 2010] In mode 0, port A and port B can be configured as simple 8-bit input or output ports without handshaking. The two halves of port C can be programmed separately as 4-bit input or output ports. 14. What is memory mapping? [ may/june 2011] Memory mapping may refer to: Memory-mapped file, also known as mmap()Memorymapped I/O, an alternative to port I/O; a communication between CPU and peripheral device using the same instructions, and same bus, as between CPU and memory Virtual memory, technique which gives an application program the impression that it has contiguous working memory, while in fact it is physically fragmented and may even overflow on to disk storage.

PART C (16 MARKS) 1. Describe the architecture of 8051 with a neat diagram.[MAY-2009] 2. Explain the interrupt structure, SFR and timers of 8051.[]MAY-2012] 3. List out the salient features of 8051 microcontroller 4. Explain the following instructions of 8051 with examples. i. CJNE destination, source, label ii. MUL AB iii. RRL A iv. SWAP A v. SETB P2.0. 5. How does 8051 differentiate between the external and internal memory? Explain with neat block diagram.[MAY-2011] 6. Write short notes on LCD interface. [May-2009]

UNIT V MICRO CONTROLLER PROGRAMMING & APPLICATIONS PART A (1 MARKS) 1. Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors d) none 2. Address line for RST3 is? a) 0020H b) 0028H c) 0018H 3. In 8086 the overflow flag is set when a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic operation c) Carry and sign flags are set d) During subtraction 4. The advantage of memory mapped I/O over I/O mapped I/O is, a) Faster b) Many instructions supporting memory mapped I/O c) Require a bigger address decoder d) All the above 5. BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA 6. In 8086 microprocessor the following has the highest priority among all type interrupts. a) NMI b) DIV 0 c) TYPE 255 d) OVER FLOW 7. In 8086 microprocessor one of the following statements is not true. a) Coprocessor is interfaced in MAX mode b) Coprocessor is interfaced in MIN mode c) I/O can be interfaced in MAX / MIN mode d) Supports pipelining 8. 8088 microprocessor differs with 8086 microprocessor in a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode 9. Address line for TRAP is? a) 0023H b) 0024H c) 0033H d) none 10. The internal RAM memory of the 8051 is: A.32 bytes B. 64 bytes C.28 bytes D. 256 bytes 11. The 8051 has ________ 16-bit counter/timers. A. 1 B. 2 C.3 D. 4

12. The 8051 can handle ________ interrupt sources. A. 3 B. 4 C. 5 D. 6 13.When the 8051 is reset and the line is HIGH, the program counter points to the first program instruction in the: A. internal code memory B. external code memory C. internal data memory D. external data memory 14. An alternate function of port pin P3.4 in the 8051 is: A. Timer 0 B.Timer 1 C.interrupt 0 D.interrupt 1 15. The I/O ports that are used as address and data for external memory are: A. ports 1 and 2 B. ports 1 and 3 C. ports 0 and 2 D. ports 0 and 3 16. Microcontrollers often have: A. CPUs B. RAM C. ROM D. all of the above 17. The 8051 has ________ parallel I/O ports. A. 2 B. 3 C. 4 D. 5 18. The total external data memory that can be interfaced to the 8051 is: A. 32K B. 64K C. 128K D. 256K 19. Which of the following instructions will load the value 35H into the high byte of timer 0? A. MOV TH0, #35H B. MOV TH0, 35H C. MOV T0, #35H D. MOV T0, 35H 20. Bit-addressable memory locations are: A.10H through 1FH B. 20H through 2FH C. 30H through 3FH D. 40H through 4FH Answer:
1 c 2 c 3 b 4 d 5 b 6 a 7 b 8 a 9 b 10 c 11 b 12 b 13 a 14 a 15 c 16 d 17 c 18 b 19 a 20 b

PART B

(2 MARKS)

1. List the addressing modes of 8051? [April-2008] Direct addressing Register addressing Register indirect addressing. Implicit addressing Immediate addressing Index addressing Bit addressing 2. Write about CALL statement in 8051? There are two subroutine CALL instructions. They are *LCALL (Long CALL) *ACALL (Absolute CALL) Each increments the PC to the 1st byte of the instruction & pushes them in to the stack. 3. Write about the jump statement? There are three forms of jump. They are LJMP (Long jump)-address 16 AJMP (Absolute Jump)-address 11 SJMP (Short Jump)-relative address 4. Write program to load accumulator, DPH, &DPL using 8051? [Nov-2011] MOV A, #30 MOV DPH, A MOV DPL, A

5. Write a program to find the 2s complement using 8051?[NOV-2010] MOV A, R0 CPL A INC A 6. Write a program to subtract the contents of R1 of Bank0 from the contents of R0 of Bank2. MOV PSW, #10 MOV A, R0 MOV PSW, #00 SUBB A, R1 7. Write a program to add 2 8-bit numbers using 8051?[APRIL-2009] MOV A,#30H ADD A, #50H 8. Explain the 16-bit registers DPTR and SP of 8051. [NOV-2008] DPTR: DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit data register or as two independent 8-bit registers. It serves as a base register in indirect jumps, lookup table instructions and external data transfer. SP: SP stands for stack pointer. SP is a 8- bit wide register. It is incremented before data is stored during PUSH and CALL instructions. The stack array can reside anywhere in on-chip RAM. The stack pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. 9. What is mean by microcontroller?[NOV-2010] A device which contains the microprocessor with integrated peripherals like memory, serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC is called microcontroller. 10. Explain DJNZ instructions of Intel 8051 microcontroller? [Nov-2012] a) DJNZ Rn, rel Decrement the content of the register Rn and jump if not zero. b) DJNZ direct, rel Decrement the content of direct 8-bit address and jump if not zero. 11. What is the function of NEU? [APRIL-2009] The numeric execution unit executes all the instructions including arithmetic, logical transcendental, and data transfer instructions. The numeric execution unit executes all the numeric processor instructions while the control unit (CU) receives, decodes instructions, reads and writes memory operands and executes the 8087 control instructions. 12. Give the disadvantages of bus window technique?[April-2010] The numeric execution unit executes all the instructions including arithmetic, logical transcendental, and data transfer instructions. The numeric execution unit executes all the numeric processor instructions while the control unit (CU) receives, decodes instructions, reads and writes memory operands and executes the 8087 control instructions. 13. What is swapping out? [APRIL-2009] A portion of the program or important partial results required for further execution may e saved back on secondary storage to make the physical memory free for further execution of another required portion of the program. This is called swapping out of the executable program. 14. Name the five interrupt sources of 8051. [ may/june 2011] External hardware interrupt 0 (INT 0), External hardware interrupt 1 (INT 1), Timer 0 interrupt (TF0), timer 1 interrupt (TF1) and serial communication interrupt (R1 & T1).

15. What is baud rate in 8051? [ may/june 2012] The Baud Rate is determined based on the oscillators frequency when in mode 0 and 2. In mode 0, the baud rate is always the oscillator frequency divided by 12. This means if youre crystal is 11.059Mhz, mode 0 baud rate will always be 921,583 baud. In mode 2 the baud rate is always the oscillator frequency divided by 64, so a 11.059Mhz crystal speed will yield a baud rate of 172,797. PART C (16 MARKS)

1. List the instruction set of 8051, microcontroller that affect the flag bits. 2. How 8051 micro controller can be interfaced with external ROM, Explain with Examples? [A.U Nov/Dec-2008] 3. Explain the matrix keyboard interface of 8051. 4. Draw the format of SCON register. Explain different bits in it. 5. Write an assembly language program to find Fibonacci Series of N given term. 6. Write an assembly language program for stepper motor control. 7. Discuss in detail stepper motor interfacing with 8051. [A.U MAY-2009] 8. Describe the architecture of 8051 microcontroller. [A.U may/june 2012] 9. Explain the interfacing of LCD with 8051 microcontroller. [A.U may/june 2012]