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Class No. Title Percentage of Portions Covered

This document provides an overview of the topics covered in a class on low power VLSI chip design. The class covers 1) sources of power dissipation in digital chips and emerging low power approaches, 2) device and technology impacts on low power, 3) power estimation and simulation techniques, 4) low power design at the circuit and logic levels, 5) low power architectures and systems, 6) low power clock distribution, and 7) algorithmic and architectural level methodologies for low power design. The class aims to cover these topics in detail across 10 sections spanning over 100 portions. Suggested textbooks are also provided.

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hrrameshhr
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84 views

Class No. Title Percentage of Portions Covered

This document provides an overview of the topics covered in a class on low power VLSI chip design. The class covers 1) sources of power dissipation in digital chips and emerging low power approaches, 2) device and technology impacts on low power, 3) power estimation and simulation techniques, 4) low power design at the circuit and logic levels, 5) low power architectures and systems, 6) low power clock distribution, and 7) algorithmic and architectural level methodologies for low power design. The class aims to cover these topics in detail across 10 sections spanning over 100 portions. Suggested textbooks are also provided.

Uploaded by

hrrameshhr
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Class No.

1. Introduction:

Title

Percentage of portions covered

1. Need for low power VLSI chips Digital Integrated circuits 2. Sources of power dissipation on 3. Emerging Low power approaches 01 - 06 4. Emerging Low power approaches. 5. Introduction to Verilog . !h"sics of power dissipation in #$%S de&ices. 2. Device & Technology Impact on Low Power: 1. D"namic dissipation in #$%S 2. 'ransistor si(ing ) gate o*ide thic+ness 3. 'ransistor si(ing ) gate o*ide thic+ness 07 - 12 4. impact of technolog" Scaling ,. impact of technolog" Scaling . 'echnolog" ) De&ice inno&ation 3. Power estimation, Simulation Power analysis 1. S!I#E circuit simulators2. gate le&el logic simulation 3. capaciti&e power estimation 4. static state power 13 - 1 ,. gate le&el capacitance estimation . architecture le&el anal"sis .. architecture le&el anal"sis- data correlation anal"sis in DS! s"stems $onte #arlo simulation !. Probabilistic power analysis/ 1. 0andom logic signals 2. 2. pro1a1ilit" ) fre2uenc" 3. pro1a1ilistic power anal"sis techni2ues 20 - 26 4. pro1a1ilistic power anal"sis techni2ues ,. signal entrop". . signal entrop". .. signal entrop" ". Low Power Design Circuit level/ 1. !ower consumption in circuits 2. .3lip 3lops) Latches design 3. high capacitance nodes 4. low power digital cells li1rar" 27 - 33 ,. Logic level: 4ate reorgani(ation. state machineencoding- pre5computation logic .. state machineencoding- pre5computation logic 6. state machineencoding- pre5computation logic 6. Low power Architecture & Systems 1. !ower ) performance management 2. !ower ) performance management 3. switching acti&it" reduction 3! - 3 4. parallel architecture with &oltage reduction ,. flow graph transformation . low power arithmetic components- low power memor" design. 7. Low power Cloc Distribution:

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23

36

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63

7"

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1. !ower dissipation in cloc+ distri1ution 2. !ower dissipation in cloc+ distri1ution 3. single dri&er Vs distri1uted 1uffers !0 - !6 4. single dri&er Vs distri1uted 1uffers ,. 7ero s+ew Vs tolera1le s+ew. chip )pac+age co design of cloc+ networ+ .. chip )pac+age co design of cloc+ networ+ #. Algorithm & Architectural Level !etho"ologies 1. Introduction 2. designflow 3. 8lgorithmic le&el anal"sis ) optimi(ation4. 8lgorithmic le&el anal"sis ) optimi(ation!7 - "2 ,. 8rchitectural le&elestimation ) s"nthesis . 8rchitectural le&elestimation ) s"nthesis .. 8rchitectural le&elestimation ) s"nthesis

100

'e*t 9oo+s/ #$:aushi+ 0o"- Sharat !rasad- ;Low%Power C!&S 'LSI Circuit Design< =ile"- 2>>> 2.4ar" :. ?eap- ;Practical Low Power Digital 'LSI Design<- :8!- 2>>2 3.0a1ae"- !edram- ;Low Power Design !etho"ologies< :luwer 8cademic- 1@@.

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