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EEC 581 Computer Architecture, Spring 2014

This paper proposes a technique called physical mechanism of high-programming-efficiency dynamic-threshold source-side injection in wrapped-select-gate SONOS for NOR-type flash memory. It details the structure of a WSG-SONOS memory cell and describes three programming methods: normal, dynamic threshold, and body mode. Simulation results show that the dynamic threshold mode exhibits higher programming efficiency through increased lateral electric fields and current compared to the other two modes. This enhanced programming efficiency improves the performance of WSG SONOS for NOR-type flash memory.

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79 views

EEC 581 Computer Architecture, Spring 2014

This paper proposes a technique called physical mechanism of high-programming-efficiency dynamic-threshold source-side injection in wrapped-select-gate SONOS for NOR-type flash memory. It details the structure of a WSG-SONOS memory cell and describes three programming methods: normal, dynamic threshold, and body mode. Simulation results show that the dynamic threshold mode exhibits higher programming efficiency through increased lateral electric fields and current compared to the other two modes. This enhanced programming efficiency improves the performance of WSG SONOS for NOR-type flash memory.

Uploaded by

jenil7042
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EEC 581 Computer Architecture, Spring 2014

Title: Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type flash memory Goal: To enhance the programming efficiency of WSG SONOS for NOR-type flash memory Overview: In this paper we used the source side injection technique for high programming efficiency. The major process and the cross sectional images of the WSG-SONOS memory structure are detailed in the paper. Based on the concepts they discussed in the paper, there are three kinds of programming methods for WSG-SONOS devices: normal, DT and body mode. To investigate the physical mechanism of SSI under these three different modes, an ISE TCAD with hot electron and Poisson equation calculation models are used. For DT mode, the selected gate is tied to a well, whereas Vwell in the body mode is fixed at 0.45 V. The power consumption can be lower than DT mode in the body mode during the charging process of programming due to variation of the threshold voltage in the DT mode. Under the same programming conditions a typical bell-shaped distribution is observed in both normal and body modes but not in the DT mode. Across all the three modes, the higher Vwl exhibits a larger programming window. This is because high Vwl not only enhances the collection ability with increasing normal electric field but also raises the hot electron generation rate by increasing the voltage drop across the gap region. This is because, as the wrapped MOSFET overdrive becomes higher, the voltage drop across the neutral gap region decreases, decreasing the efficiency of programming. Furthermore, the DT mode exhibits different behavior from the normal and body modes. The typical programming characteristics of the DTSSI have a higher memory window while Vsg is still a low voltage. The DT mode processes a larger acceleration electrical field between the WSG and the word gate. Therefore, the hot-electron generation rate can be enhanced. Under DT mode, the devices exhibited increased lateral electric field and current. These changes enhanced the programming efficiency of WSG SONOS for NOR-type flash memory. References: [1] L.Breuil, L.Haspeslagh, P.Blomme, D.Wellekens, J.D Vos, M. Lorenzini and J.V.Houdt, A new scalable self-aligned dual-bit Split gate charge- trapping memory device, IEEE Trans. Electron Devices, vol.52,no.10, pp. 2250-2257, oct-2005 [2] H. Tomiye, T. Terano, K. Nomoto and T. Kobayashi, A novel 2 bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection, in VLSI symp. Tech. Dig., 2002, pp.206-207 [3] C. Y. Lu, T.C. Lu, and R.Liu, Non-volatile memory technology- Today and tomorrow, in Proc. IPFA , 2006, pp. 18-23

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