SIMetrix

SPICE and Mixed Mode Simulation

Simulator Reference Manual

Copyright 1992-2004 Catena Software Ltd.

Trademarks PSpice is a trademark of Cadence Design Systems Inc. Star-Hspice is a trademark of Synopsis Inc. Contact Catena Software Ltd., Terence House, 24 London Road, Thatcham, RG18 4LQ, United Kingdom Tel.: Fax: Email: Internet +44 1635 866395 +44 1635 868322 [email protected] http://www.catena.uk.com

Copyright Catena Software Ltd 1992-2004 SIMetrix 5.0 Simulator Reference Manual 23/8/04 Catena Software Ltd. is a member of the Catena group of companies. See http://www.catena.nl

Table of Contents

Table of Contents
Chapter 1 Introduction
The SIMetrix Simulator - What is it? ................................ 10 A Short History of SPICE................................................. 10

Chapter 2

Running the Simulator

Using the Simulator with the SIMetrix Schematic Editor.. 12 Adding Extra Netlist Lines ........................................ 12 Displaying Net and Pin Names................................. 12 Editing Device Parameters ....................................... 13 Editing Literal Values - Using shift-F7 ...................... 13 Running in non-GUI Mode ............................................... 14 Overview................................................................... 14 Syntax....................................................................... 14 Aborting .................................................................... 15 Reading Data............................................................ 16 Configuration Settings ..................................................... 16 Netlist Format .................................................................. 18 File Format ............................................................... 19 Language Declaration .............................................. 19 Comments ................................................................ 20 Device Lines ............................................................. 20 Simulator Controls .................................................... 22 Simulator Output.............................................................. 22 The List File .............................................................. 22 The Binary Data File................................................. 23 Output Data Names.................................................. 24

Chapter 3

Simulator Devices
Overview.......................................................................... 26 Using XSPICE Devices.................................................... 26 Vector Connections .................................................. 26 Connection Types..................................................... 27 Using Expressions ........................................................... 28 Overview................................................................... 28 Using Expressions for Device Parameters ............... 29 Using Expressions for Model Parameters ................ 29 Expression Syntax.................................................... 29 Optimisation.............................................................. 38 3

Simulator Reference Manual Subcircuits....................................................................... 39 Overview .................................................................. 39 Subcircuit Definition ................................................. 39 Subcircuit Instance................................................... 41 Passing Parameters to Subcircuits .......................... 41 Nesting Subcircuits .................................................. 42 Global Nodes ........................................................... 42 Subcircuit Preprocessing ......................................... 42 Model Binning.................................................................. 43 Overview .................................................................. 43 Defining Binned Models ........................................... 43 Example ................................................................... 43 Language Differences ..................................................... 44 Inline Comment ........................................................ 44 Unlabelled Device Parameters................................. 44 LOG() and PWR() .................................................... 45

Chapter 4

Analog Device Reference

Overview ......................................................................... 46 Arbitrary Source .............................................................. 46 Notes on Arbitrary Expression ................................. 47 Charge and Flux Devices......................................... 47 Arbitrary Source Examples ...................................... 48 PSpice and Star-Hspice syntax................................ 50 Bipolar Junction Transistor (SPICE Gummel Poon)........ 50 Bipolar Junction Transistor (VBIC without self heating) .. 53 Bipolar Junction Transistor (VBIC with self heating) ....... 57 Bipolar Junction Transistor (MEXTRAM) ........................ 58 Capacitor ......................................................................... 58 Capacitor with Voltage Initial Condition........................... 60 Current Controlled Current Source.................................. 61 Polynomial Specification .......................................... 62 Current Controlled Voltage Source ................................. 62 Current Source ................................................................ 63 Diode ............................................................................... 64 GaAsFET......................................................................... 68 Inductor (Ideal) ................................................................ 70 Inductor (Saturable)......................................................... 70 Inductor with Current Initial Condition ............................. 73 Insulated Gate Bipolar Transistor.................................... 74 Junction FET ................................................................... 75 Lossy Transmission Line................................................. 77 MOSFET ......................................................................... 79

Table of Contents BSIM3 MOSFETs ............................................................ 84 BSIM4 MOSFETs ............................................................ 85 EKV MOSFETs................................................................ 86 MOSFET GMIN Implementation...................................... 86 Resistor............................................................................ 87 S-domain Transfer Function Block .................................. 88 Subcircuit Instance .......................................................... 94 Transmission Line............................................................ 94 Voltage Controlled Current Source.................................. 95 Voltage Controlled Switch................................................ 95 Voltage Controlled Voltage Source.................................. 96 Voltage Source ................................................................ 97 Pulse Source ............................................................ 98 Piece-Wise Linear Source ........................................ 99 PWL File Source..................................................... 100 Sinusoidal Source................................................... 101 Exponential Source ................................................ 102 Single Frequency FM ............................................. 102 Noise Source .......................................................... 103 Mutual Inductor .............................................................. 103 Philips Compact Models ................................................ 104 Introduction............................................................. 104 Using Philips Devices ............................................. 106 Examples................................................................ 107 Documentation ....................................................... 108

Chapter 5

Digital/Mixed Signal Device Reference

Digital Device Overview................................................. 109 Common Parameters ............................................. 109 Delays..................................................................... 110 And Gate........................................................................ 110 D-type Latch .................................................................. 112 D-type Flip Flop ............................................................. 114 Buffer ............................................................................. 116 Frequency Divider.......................................................... 117 Digital Initial Condition ................................................... 119 Digital Pulse................................................................... 120 Digital Signal Source ..................................................... 121 Inverter........................................................................... 124 JK Flip Flop.................................................................... 125 Arbitrary Logic Block...................................................... 129 Nand Gate ..................................................................... 131 Nor Gate ........................................................................ 132 5

Simulator Reference Manual Open-Collector Buffer.................................................... 133 Open-Emitter Buffer ...................................................... 134 Or Gate.......................................................................... 135 Pulldown Resistor.......................................................... 136 Pullup Resistor .............................................................. 137 Random Access Memory .............................................. 137 Set-Reset Flip-Flop ....................................................... 138 SR Latch........................................................................ 141 State Machine ............................................................... 143 Toggle Flip Flop............................................................. 144 Tri-State Buffer .............................................................. 146 Exclusive NOR Gate ..................................................... 148 Exclusive OR Gate ........................................................ 149 Analog-Digital Converter ............................................... 150 Analog-Digital Interface Bridge...................................... 153 Digital-Analog Converter ............................................... 157 Digital-Analog Interface Bridge...................................... 160 Controlled Digital Oscillator ........................................... 163 Analog-Digital Schmitt Trigger...................................... 165

Chapter 6

Command Reference
Overview ....................................................................... 167 General Sweep Specification ........................................ 168 Overview ................................................................ 168 Syntax .................................................................... 169 Multi Step Analyses....................................................... 170 Overview ................................................................ 170 Syntax .................................................................... 170 .AC ................................................................................ 171 .ALIAS ........................................................................... 173 .DC ................................................................................ 174 .FILE and .ENDF ........................................................... 175 .FUNC ........................................................................... 176 .GLOBAL ....................................................................... 177 .GRAPH......................................................................... 177 Parameters............................................................. 177 Using Multiple .GRAPH Controls ........................... 181 Creating X-Y Plots.................................................. 181 Using .GRAPH in Subcircuits................................. 181 Using Expressions with .GRAPH ........................... 181 Plotting Spectra with .GRAPH................................ 182 .IC.................................................................................. 183 Alternative Initial Condition Implementations ......... 183

Table of Contents .INC................................................................................ 184 .KEEP ............................................................................ 184 .LIB ................................................................................ 186 SIMetrix Native Form.............................................. 186 HSPICE Form........................................................ 187 .MODEL ......................................................................... 187 .NODESET .................................................................... 190 .NOISE........................................................................... 191 .OP................................................................................. 194 .OPTIONS...................................................................... 195 .PARAM ......................................................................... 205 .PRINT ........................................................................... 207 .PZ ................................................................................. 209 .SENS ............................................................................ 209 .SUBCKT and .ENDS .................................................... 210 .TEMP............................................................................ 211 .TF ................................................................................. 211 .TRACE.......................................................................... 213 .TRAN ............................................................................ 213 Real Time Noise Analysis.............................................. 216

Chapter 7

Monte Carlo Analysis

Overview........................................................................ 218 Specifying a Monte Carlo Run ....................................... 218 Specifying a Single Step Monte Carlo Sweep ............... 219 Log File .......................................................................... 219 Seeding the Random Number Generator ...................... 220 Specifying Tolerances ................................................... 221 Overview................................................................. 221 Distribution Functions ............................................. 221 TOL, MATCH and LOT Device Parameters ........... 225 Tolerance Models ................................................... 226

Chapter 8

Convergence and Accuracy

Overview........................................................................ 228 DC Operating Point........................................................ 228 Overview................................................................. 228 Source and GMIN Stepping.................................... 229 Pseudo Transient Analysis ..................................... 230 Junction Initialised Iteration .................................... 232 Using Nodesets ...................................................... 232 Transient Analysis ......................................................... 233 7

Simulator Reference Manual What Causes Non-convergence? .......................... 233 Fixes for Transient Non-convergence .................... 234 DC Sweep ..................................................................... 234 DC Operating Point Algorithms ..................................... 235 Junction Initialised Iteration.................................... 235 Source Stepping..................................................... 235 Diagonal GMIN Stepping ....................................... 236 Junction GMIN Stepping ........................................ 236 Pseudo Transient Analysis..................................... 236 Controlling DC Method Sequence.......................... 237 Singular Matrix Errors.................................................... 237 Transient Analysis - Time step too small Error ............ 238 Accuracy and Integration Methods................................ 238 A Simple Approach ................................................ 238 Iteration Accuracy .................................................. 238 Time Step Control .................................................. 240 Accuracy of AC analyses ....................................... 240 Summary of Tolerance Options ............................. 241 Integration Methods - METHOD option.................. 241

Chapter 9

Digital Simulation
Overview ....................................................................... 244 Logic States................................................................... 244 State resolution table ............................................. 245 Analog to Digital Interfaces ........................................... 245 How A-D Bridges are Selected .............................. 247 Logic Families ............................................................... 247 Logic Family Model Parameters............................. 248 Logic Compatibility Tables ..................................... 248 Logic Compatibility File Format.............................. 249 Supported Logic Families....................................... 250 Universal Logic Family ........................................... 251 Internal Tables ....................................................... 251 Load Delay .................................................................... 251 Overview ................................................................ 251 Output Resistance.................................................. 251 Input Delay ............................................................. 251 Wire Delay.............................................................. 252 Digital Model Libraries................................................... 252 Using Third Party Libraries..................................... 252 Arbitrary Logic Block - User Defined Models................. 252 Overview ................................................................ 252 An Example............................................................ 252

Table of Contents Example 2 - A Simple Multiplier.............................. 255 Example 3 - A ROM Lookup Table......................... 255 Example 4 - D Type Flip Flop ................................. 256 Device Definition - Netlist Entry & .MODEL Parameters 256 Language Definition - Overview ............................. 258 Language Definition - Constants and Names......... 258 Language Definition - Ports .................................... 258 Language Definition - Registers and Variables ...... 260 Language Definition - Assignments........................ 263 Language Definition - User and Device Values...... 266 Diagnostics: Trace File ........................................... 266 Mixed-mode Simulator - How it Works .......................... 267 Event Driven Digital Simulator................................ 267 Interfacing to the Analog Simulator ........................ 268 Enhancements over XSPICE......................................... 268

Chapter 10

SIMetrix vs SPICE

Simulator Reference Manual

Chapter 1 Introduction
This manual provides full reference documentation for the SIMetrix simulator. Essentially the simulator receives a netlist as its input and creates a binary data file and list file as its output. The netlist defines the circuit topology and also specifies the analyses to be performed by the simulator. The netlist may directly include any device models required or these may be automatically imported from a device model library. The simulator may be operated in GUI mode or non-GUI mode. GUI mode is the normal method of operation and requires the SIMetrix front end. In non-GUI mode the simulator runs stand alone in a non-interactive fashion and may be set to run at low priority in the background.

The SIMetrix Simulator - What is it?

The SIMetrix simulator core comprises a direct matrix analog simulator closely coupled with an event driven digital simulator. This combination is often described as Mixed-Mode and has the ability to efficiently simulate both analog and digital circuits together. The analog simulator is a derivation of SPICE 3 developed by the CAD/IC group at the University of California at Berkeley while the event driven digital simulator is based on XSPICE from the Georgia Technical Research Institute. However, only about 50% of the SIMetrix simulator code can be directly traced to these programs. We have rewritten some parts while added our own original code to others. The additions and changes we have made are to improve speed, add new functionality and improve convergence. We have not, however, implemented all of the original SPICE3 features. We have omitted items that we feel are of limited use. A summary of the differences between SIMetrix, SPICE2 and SPICE3 can be found in SIMetrix vs SPICE on page 270

A Short History of SPICE

SPICE is an acronym for Simulation Program with Integrated Circuit Emphasis. It was developed by the University of California at Berkeley and it's origins can be traced back to the late 1960s. A number of research groups at that time were working on ways to simulate integrated circuits as it was becoming increasingly obvious that traditional breadboarding techniques could not be used. The first program to emerge from Berkeley had the unattractive name of CANCER and this was then developed into what is now known as SPICE1. SPICE1 was first released in 1972 but was fairly primitive. SPICE2 followed in 1975 and was a considerable improvement and in fact had all the major elements used in current SPICE and SPICE-like analog simulators. The final version of SPICE2 was SPICE2G.6 and was released in April 1983. SPICE2 was just a simulator and had no user interface in the modern sense. The input was a netlist, usually prepared by hand, and the output was a line printer listing containing time point values or crude plots using asterix characters. From the beginning SPICE was made publicly and freely available in source code form (in FORTRAN) and this led to its wide acceptance throughout the industry. In the early

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Chapter 1 Introduction
1980s it was run mainly on DEC VAX machines with PC versions for DOS appearing in the mid 1980s SPICE3 started to appear at around the same time. SPICE3 is written in 'C' and was developed for UNIX machines. It features a front end known as Nutmeg which consists of a graphical waveform viewer and interactive command shell but no schematic entry. The simulator itself is an improvement on SPICE2 but not a vast one with only small developments to improve convergence problems. The last version of SPICE3 to be released was SPICE3f.5.

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Simulator Reference Manual

Chapter 2 Running the Simulator

Using the Simulator with the SIMetrix Schematic Editor
Full documentation on using the SIMetrix schematic editor for simulation is described in the SIMetrix User's manual. However, just a few features of the schematic editor are of particular importance for running the simulator and for convenience their description is repeated here.

Adding Extra Netlist Lines

The analysis mode selected using the schematic editor's Simulator|Choose Analysis... menu is stored in text form in the schematic's simulator command window. If you wish, it is possible to edit this directly. Users familiar with SPICE syntax may prefer this approach. Note that the text entered in the simulator command window and the Choose Analysis dialog settings remain synchronised so you can freely switch between the two methods. To open the simulator command window, select the schematic then press the F11 key. It has a toggle action, pressing it again will hide it. If you have already selected an analysis mode using the Choose Analysis dialog, you will see the simulator controls already present. The window has a popup menu selected with the right key. The top item Edit file at cursor will open a text editor with the file name pointed to by the cursor or selected text item if there is one. The simulator command window can be resized using the splitter bar between it and the schematic drawing area. You can add anything you like to this window not just simulator commands. The contents are simply appended to the netlist before being presented to the simulator. So, you can place .PARAM controls, device models, inductor coupling specifications, .OPTION controls or simply comments. The Choose Analysis dialog will parse and possibly modify analysis controls and some .OPTIONS settings but will leave everything else intact.

Displaying Net and Pin Names

It is sometimes necessary to know the name used for a particular net on the schematic to be referenced in a simulator control (such as .NOISE) or for an arbitrary source input. There are two approaches: Find out the default name generated by the schematic editor's netlist generator. To do this, place the mouse cursor over the net of interest then press control-S. The net name will be displayed in the command shell's message window. Force a net name of your choice. For this, use a terminal or small terminal symbol. These can be found under the Parts|Connectors menu. After placing on the schematic, select it then press F7 to edit its name. This name will be used to name the net to which it is connected.

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Chapter 2 Running the Simulator

Editing Device Parameters

To use any of the additional parameters in a schematic, use the Parameters button in the dialog box opened by F7 or the equivalent menu. For example you see this box when editing a resistor

Pressing the Parameters button will open another dialog from which you can edit parameter values:

You can also bring up this box directly using the menu Parts|Edit Additional Parameters.... Note you can only supply constant values by this method. If you wish to define a parameter as an expression, you will need to use shift-F7 - see below.

Editing Literal Values - Using shift-F7

The above method is not infallible as it requires the schematic editor to know about the device being edited. In some circumstances, this will require special properties to be present on the symbol and these may have not been defined. (for example something to tell the schematic what level a MOSFET is)

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Simulator Reference Manual

Another situation where the usual device editing methods are unsuitable is when you need to define a parameter as an expression. In these situations you can use shift-F7. This will edit the device's literal value including any model names exactly as it will be placed in the netlist. shift-F7 bypasses all smart algorithms and presents you with the raw values and you must also supply raw values. For example, here is what you might enter for a MOSFET referencing a model called N1
N1 L={LL-2*EDGE} W={WW-2*EDGE}

Note the model name must be included.

Running in non-GUI Mode

Overview
The simulator can be run in a non-interactive non-GUI mode independently of the front end. This is useful for running simulation batches controlled by a proprietary script or batch language such as shell scripts or DOS batch files. Under Linux this allows a simulation to be run without an X-server. Under Windows, the simulator will run as a console mode application and no GUI elements will be created. When run in this mode, the simulator will read in the specified netlist, run the simulation then close and return control to the calling program. It will generate a binary data file and a list file.

Syntax
The command syntax is as follows:

SIM [/config "config_location"] [/check] [/an "analysis_line"] [/list list_filename] [/options "options"] [/nolist] [/lowPriority] [/nodata] [/k] netlist_file [data_file]
config_location Location of file holding configuration settings. Configuration settings include global options and global model library locations. The value must be of the form: PATH;pathname pathname may use system symbolic path values such as %EXEPATH%. See Users Manual for details. If not specified, the configuration settings will be taken from the Base.sxprj file. See the Users Manual for details on where this file is located. Alternatively, you can specify the location using a setting in the

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Chapter 2 Running the Simulator

startup.ini file. Add a value called SimConfig to the [Startup] section and give it a value of: PATH;pathname The startup.ini file must be located in the same directory as the SIMetrix executable binary. (SIMetrix.exe on Windows, SIMetrix on Linux). See the Users Manual for more information on the startup.ini file. Note that the /config switch if present must always appear be the first argument to the command. analysis_line If /an switch is specified, analysis_line specifies the analysis to be performed and overrides all analysis lines specified in the netlist. Name of list file. Default is main netlist file name with extension .OUT. Enclose path name in quotes if it contains spaces. List of options valid for .OPTIONS control. File name of netlist. File to receive binary data output. If specified, the netlist will be read in and parsed but no simulation will be run. Used to check syntax If specified, no list file will be created If specified, the simulator will be run as a low priority process, i.e. in the background. Recommended for long runs. Only vectors explicitly specified using .KEEP or .PRINT will be output to the binary file. Equivalent to .KEEP /nov /noi /nodig in the netlist. If specified, the program will not finally terminate until the user has pressed enter and a message to that effect will be displayed. Under Windows, if the program is not called from the DOS prompt but from another program, a console will be created for receiving messages. The console will close when the program exits sometimes before the user has had a chance to read the messages. This switch delays the exit of the program and hence the destruction of the console.

list_filename

options netlist_file data_file /check /nolist /lowPriority /nodata

/k

Aborting
Press cntrl-C - you will be asked to confirm. The simulation will be paused while waiting for your response and will continue if you enter No. This is an effective means of pausing the run if you need CPU cycles for another task, or you wish to copy the data file. See Reading Data below.

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Simulator Reference Manual

Reading Data
A data file will be created for the simulation results as normal (see The Binary Data File on page 23). You can read this file with the waveform viewer using the Load Data menu. However, it is strongly recommended that the simulation is paused first by pressing cntrl-C. Important: if you read the data file before the simulation is complete or aborted, the file entries that provide the size of each vector will not have been filled. This means that the waveform viewer will have to scan the whole file in order to establish the size of the vectors. This could take a considerable time if the data file is large.

Configuration Settings
Configuration settings consist of a number of persistent global options as well as the locations for installed model libraries. When the simulator is run in GUI mode, its configuration settings are controlled by the front end and stored wherever the front ends settings are stored. See the User's Manual for more details. When the simulator is run in non-GUI mode, these settings are stored in a .INI file which is, by default, SIM.INI in the same directory as the executable file. This can be changed with the /config switch detailed above (page 14) The format of the configuration file is: [Options] option_settings [Models] model_libraries Where: option_settings These are of the form name=value and specify a number of global settings. Boolean values are of the form name= without a value. If the entry is present it is TRUE if absent it is FALSE. Available global settings are detailed below. A list of entries specifying search locations for model libraries. These are of the form name=value where name is a string and value is a search location. The string used for name is arbitrary but must be unique. Entries are sorted alphabetically according to the name and used to determine the search order. value is a path name and may contain wildcards (i.e. '*' and '?')

model_libraries

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Chapter 2 Running the Simulator

Global Settings

Name

Type

Default

Description

SearchDefaultTol

Boolean

false

If true, the model library will be searched for Monte Carlo default models If true, unknown model parameters will be ignored See Data Buffering below

NoStopOnUnknownParam

Boolean

false

MaxVectorBufferSize TotalVectorBufferSize TempDataDir

Numeric Numeric String

32768

Available RAM/10 See Data Buffering below %STARTDIR% Location of temporary binary data file if data_file is not specified on command line Controls output of messages relating to model library search. Specify None to disable

LibraryDiagnostics

String

Full

Data Buffering The simulator buffers data before writing it to disk. By doing so the binary data file can be organised more efficiently allowing data to be recovered from it quickly. There is a relationship between buffer size and read in time as illustrated by the following table. This shows the time taken to read in a 1.2MByte vector from a 53MByte data file with the system disk cache cleared. These tests were performed using a 500MHz P3 with an IDE disk system.

Vector buffer size/bytes

256 512 1k 2k 4k

Read in time seconds

26 18 14.9 6.5 3.5

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Simulator Reference Manual

Vector buffer size/bytes

8k 16k 32k 64k

Read in time seconds

2.3 1.8 1.2 1.1

Note that the buffer size referred to in the above table is for each vector. By default, the simulator won't allocate more than 10% of your system RAM to vector buffers. Clearly if you are running a large circuit and saving many vectors, the buffer sizes could reduce to levels that would make data retrieval very slow. In this case you may wish to consider increasing the memory that is allowed for these buffers. Two configuration settings control the vector buffering. These are: MaxVectorBufferSize. This sets the maximum size that will be used for any individual vector. The default is 32768 bytes. If you have a high performance SCSI disk system, you may benefit from increasing this value. TotalVectorBufferSize. This sets the maximum amount of memory in bytes used for all buffers. It defaults to a value equal to 10% of your system RAM. If your system has a large memory - for example 2GBytes - you may like to set this to up to about half of your available RAM

The disk will not be written to until the buffers are full. With an all analog circuit all the buffers reach their full state at the same time so they all get written to disk at the same time. If you have 256M of RAM and are simulating a largish circuit, approximately 25M of data will be written to the disk at regular intervals. This will result in a pause in the simulation coupled with a great deal of disk activity. Note that both MaxVectorBufferSize and TotalVectorBufferSize may be set from the front end using the Set command. See the Users Manual for details.

Netlist Format
The SIMetrix netlist format follows the general format used for all SPICE and SPICE compatible simulators. However, with so many SPICE derivatives and with two significantly different versions of SPICE itself (SPICE 2 and SPICE 3) it is not possible to define a standard SPICE format. SIMetrix has been developed to be as compatible as possible with model libraries that can be obtained from external sources. For discrete devices, models are usually SPICE 2 compatible but some use extensions originally developed for PSpice. IC designers usually receive model files from fabrication companies and these tend to be developed for Star-Hspice. SIMetrix is compatible with all of these but simultaneous compatibility with all formats is not technically possible due to a small number of syntax details - such as the character used for in line comments. To overcome these minor difficulties, a language declaration can be placed at the top of the netlist and any file included using .INC (page 184) or the Star-Hspice variant of .LIB (page 186). This is described in the following sections.

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Chapter 2 Running the Simulator

File Format
A complete netlist consists of: A title line Optional language declaration Device lines Control lines Comment lines

The title line must be the first line of the file and may be empty. The remaining lines with some exceptions - may be placed in any order All other lines are defined by their first non-whitespace character as follows. Control lines begin with a period: '.' Comment lines begin with an asterix: '*' Device lines begin with a letter

A line is usually terminated with a new line character but may be continued using the '+' continuation character. So if the first non-whitespace character is a '+' the line will be considered to be an extension of the previous line. SPICE requires the '+' to be the first character, SIMetrix allows whitespace (space or tab) to precede it.

Language Declaration
SIMetrix is able to read PSpice, Star-Hspice and native SIMetrix netlists, but in some cases needs to be instructed what format netlist it is reading. Currently there are three areas where simultaneous compatibility has not been possible. These are: Inline comment character. Unlabelled device parameters The meaning of LOG() and PWR() functions

SIMetrix can be instructed to use any of the three languages by using the language declaration. This is one of: *#SIMETRIX *#HSPICE *#PSPICE The language declaration must be placed at the top of the file immediately below the title line. It can also be placed in files referenced using .INC or the HSPICE version of .LIB in which case it will apply only to that file and any others that it calls. A language declaration placed anywhere else in a file will be ignored. For details see Language Differences on page 44. The *#SIMETRIX language declaration can also be supplied with a parameter to specify the separator letter used for devices. See Device Lines section below for details.

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Simulator Reference Manual

Comments
Any line other than a language declaration beginning with a '*' is defined as a comment and will be ignored. Also anything between a semi-colon ';' ('$' in HSPICE mode) and the end of the line will be treated as comment and will also be ignored. Some SPICE simulators require the '*' character to be the first character of the line. SIMetrix allows it to be preceded by white space (spaces and tabs).

Device Lines
Device lines usually follow the following basic form but each type of device tends to have its own nuances:

Name nodelist value [parameters]

value may be an actual number e.g. in the case of passive components such as resistors, or it may be a model name in the case of semiconductor devices such as bipolar transistors. Models are defined using a .MODEL control line. nodelist is a list of netnames. The number and order of these is device dependent. The netname itself may consist of any collection of non-control ASCII characters except whitespace, '.' and '#'. All other ASCII characters are accepted although it is suggested that the following characters are avoided if possible: \"%&+-*/^<>[]'@{} If any of these characters are used in a netname, a special syntax will be needed to plot any signal voltage on that net. This is explained in Output Data Names on page 24. The name is the circuit reference of the device. The first letter of this name determines the type of device as shown in the table below. The Pin Names column in the following table is relevant to the vector name used for values of device pin current. See Output Data Names on page 24.

Letter Number Device of pins

Manual Pin Names Page

A B C D E F

Any 2 2 2 4 2

XSPICE devices Arbitrary source Capacitor Diode Voltage controlled voltage source Current controlled current source 46 58 64 96 60

depends on device P, N P, N P, N P, N, CP, CN P, N

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Chapter 2 Running the Simulator

Letter Number Device of pins

G H I J K L M N O P Q R S T U V W X Y Z 4 2 2 3 0 2 4 4 3-5 2 4 4 2 Any 3 Voltage controlled current source Current controlled voltage source Fixed current source JFET Coupling for inductors Inductor MOSFET Not used Lossy transmission line Not used Bipolar transistor Resistor Voltage controlled switch Lossless transmission line Not used Voltage source Not used Subcircuit Not used GaAs FET IGBT

Manual Pin Names Page

95 62 63 75 103 70 79 77 50 87 95 94 97 94 68 74 D, G, S C, G, E P, N D, G, S, B P1, N1, P2, N2 C, B, E, S, DT P, N P, N, CP, CN P1, N1, P2, N2 P, N P, N, CP, CN P, N P, N D, G, S

To remove the naming restriction that this system imposes, SIMetrix supports an extension to the above to allow the user to use any name for all devices. If the device letter is followed by a dollar '$' symbol (by default but can be changed - see below), the remainder of the name following the '$' will be used as the device name. E.g.: Q$TR23 will define a bipolar transistor with the name TR23. All output generated by the simulator will refer to TR23 not Q$TR23. The above mechanism can be disabled and also the character can be changed by adding a parameter to the language declaration (see page 19). To disable, add this to the top of the netlist:

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Simulator Reference Manual

*#SIMETRIX sep=none

To change the character use:

*#SIMETRIX sep=character

character must be a single letter, anything else will be ignored. Although any character will be accepted it should clearly not be alpha-numeric. The above mechanism will also be disabled if HSPICE or PSPICE languages are specified.

Simulator Controls
Instructions to the simulator other than device definitions and comments are referred to as controls and always begin with a period '.' . Full documentation for SIMetrix controls see Command Reference on page 167

Simulator Output
The List File
SIMetrix produces a list file by default. This receives all text output except for the Monte Carlo log. This includes operating point results, model parameters, noise analysis results, sensitivity analysis results, pole-zero analysis results and tabulated vectors specified by .PRINT. The list file is generated in the same directory as the netlist. It has the same name as the netlist but with the extension .OUT. There are a number of options that control the list file output.

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Chapter 2 Running the Simulator

Option name Description

PARAMLOG Valid values: Full Given Brief None All instance and model parameter values reported All user specified model parameters and parameterised instance parameters Parameterised model and instance parameters None

Default = Given EXPAND EXPANDFILE NOMOD WIDTH Flag. If specified, the netlist with all sub-circuits expanded will be output to the list file String. If specified the expand netlist will be output to the specified file rather than the list file Same as PARAMLOG=none. Model parameters will not be output Page width in number of characters. (The list file is formatted assuming that it will be read or printed using a fixed width font such as Courier.) The default is 80 but any value may be used not just 80 and 132 as in SPICE 2. If set DC operating point info file is created for all analyses (except .SENS). Normally it is created only for .OP analyses

OPINFO

The Binary Data File

The simulation data is stored in a binary data file. The format is proprietary to SIMetrix and is not compatible with SPICE raw files. The name and location of the binary file depends on configuration settings and in what mode the simulator is run. Usually, the file is located in the directory specified by the TEMPDATADIR configuration setting (see page 16) and is named according to the analysis type and appended with the extension .sxdat. E.g.tran1.sxdat, ac2.sxdat, dc3.sxdat etc. The name and location can be overridden at the program command line if operated in non-GUI mode or at the front end Run command line if run in GUI mode. Only the SIMetrix front end can read the simulator's binary data file. When run in GUI mode, the file is automatically loaded and in fact it is not usually necessary to know anything about it except perhaps when it grows very large and fills up your disk. If the simulator is run in non-GUI mode, it becomes necessary to explicitly load the data into the front end when the run is complete. This can be done with the command shell menu File|Data|Load. After the data is loaded, the results can be plotted in the usual manner. See the User's Manual for further details.

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Output Data Names

For transient, DC and AC analyses, SIMetrix calculates and stores the circuits node voltages and device pin currents and these are all given unique names. If using probing techniques with the front end's schematic editor you don't usually need to know anything about the names used. However there are situations where it is necessary or helpful to know how these names are derived. An example is when compiling an expression relating voltages and currents to be used in a .PRINT control. Another is when plotting results created by simulating a netlist that was not generated using the schematic editor. The names used are documented in the following notes. Top Level Node Voltages The vector names used for node voltages at the top level (i.e. not in a subcircuit) are simply the name of the node used in the netlist. Subcircuit Node Voltages For nodes within a subcircuit, the name is prefixed with the subcircuit reference and a '.'. For example:
X1 N1 N2 N3 SubName X2 N4 N5 N6 SubName .SUBCKT 1 2 3 SubName X3 N1 2 N3 SubName2 R1 VIN 0 1k ... .ENDS .SUBCKT 1 2 3 SubName2 V1 VCC 0 5 ... .ENDS

The internal node VIN in definition SubName referenced by X1 would be called X1.VIN. The same node referenced by X2 would be called X2.VIN. The node VCC defined in subcircuit SubName2 would be named X1.X3.VCC and X2.X3.VCC for X1 and X2 respectively. Nodes with Non-standard Names A non-standard node name is one that begins with a digit or which contains one or more of the characters: \"%&+-*/^<>[]'@{} These are legal but introduce problems when accessing the voltage data that they carry. The above characters can be used in arithmetic expressions so cause a conflict if used as a node name. In order to access the voltage data on a node so named, use the Vec() function: Vec('node_name')

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Example with .PRINT and node called V+
.PRINT TRAN {Vec('V+')}

A similar syntax is required when using the front end plotting commands. Device Pin Currents Device pin currents are named in the following form:

device_name#pin_name
For primitive devices (i.e. not sub-circuits) pin_name must comply with the table on page 20. For example the current into the collector of Q23 would be Q23#c. The pin names for sub-circuits depend on whether the pinnames: specifier (see Subcircuit Instance on page 94) is included in the netlist entry for the device. If it is the pin current name will be the name listed after pinnames:. If it isn't then they are numbered in sequence starting from 1. The order is the same as the order they appear in the netlist device line. For example, if the subcircuit line is:
X$U10 N1 N2 N3 N4 N5 LM324 pinnames: VINP VINN VP VN VOUT

The current into the last pin (connected to N5) would be U10#VOUT (Note that 'X$' is stripped off as explained above - page 20). If the netlist line is:
X$U10 N1 N2 N3 N4 N5 LM324

The same current would be U10#5 Internal Node Voltages Some devices have internal nodes and the voltages on these are output by the simulator. These are named in a similar manner to pin currents i.e.

device_name#internal_node_name
The internal_node_name depends on the device. For example, bipolar transistors create an internal node for each terminal that specifies a corresponding resistance parameter. So if the RE parameter is specified an internal node will be created called emitter.

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Chapter 3 Simulator Devices

Overview
This chapter is an introduction to the Analog Device Reference on page 46 and the Digital/Mixed Signal Device Reference on page 109. The device reference chapters describe all simulator devices at the netlist level. The netlist consists of a list of component definitions, along with simulator commands, which the simulator can understand. Simple components, such as resistors just need a value to define them. Other more complicated devices such as transistors need a number of parameters to describe their characteristics. The device references includes details of all device and model parameters. Using the schematic editor and model library you may not often need to read this section. Some of the devices, however, have advanced options not directly supported by the user interface. For example, many devices allow a local temperature to be specified. This requires the component value to be appended with TEMP=. This device parameter and others are documented here. Note that many parts either supplied with SIMetrix or available from component manufacturers are implemented as subcircuits. These are circuit designs to simulate the behaviour of high level devices such as opamps. SIMetrix (and all other SPICE simulators) do not have an opamp device built in but use these macro models instead. Full documentation for these devices is beyond the scope of this manual but can sometimes be obtained from their suppliers.

Using XSPICE Devices

Some devices are implemented as part of the XSPICE code modelling framework. This framework introduces some new features at the netlist level not supported by standard SPICE devices. These new features are described in this section. Most of the devices that use this framework are digital or mixed signal devices and the reference for these can be found at Digital/Mixed Signal Device Reference on page 109. However there are three all analog devices that are also XSPICE devices. These are: Capacitor with Voltage Initial Condition on page 60 Inductor with Current Initial Condition on page 73 S-domain Transfer Function Block on page 88

Vector Connections
Some models feature an arbitrary number of inputs or/and outputs. For example, an AND gate can have any number of inputs. It would be inflexible to have a separate model for every configuration of AND gate so a method of grouping connections together has been devised. These are known as vector connections. Vector connections are enclosed in square brackets. E.g. the netlist entry for an AND gate is:

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Chapter 3 Simulator Devices Axxxx [ in_0 in_1 .. in_n ] out model_name

The pins in_0 in_1 to in_n form a single vector connection. Any number of pins may be placed inside the square brackets, in fact the same model may be used for devices with different numbers of inputs. Some devices have a minimum and/or maximum number of pins that may be used in a vector connection. This is known as vector bounds and if they apply will be listed in the vector bounds column of the Connection Details table provided with every device definition.

Connection Types
In the device references that follow, each has a table titled Connection Details. Each table have a Type column and some have an Allowed types column. The type referred to here is the type of electrical connection e.g. voltage, current, differential or single-ended. Some devices allow some or all of their connections to be specified with a range of types. For example, the analog-digital converter described on page 150 has a single ended voltage input by default. However, using a simple modification to the netlist entry, an ADC can be specified with a differential voltage input or even a differential current. Changing the type of connection involves no changes to the .MODEL control, only to the netlist entry. The following table lists all the available types. The modifier is the text used to alter a connection type at the netlist level. This is explained below

Description

Modifier

Single ended voltage Single ended current Differential voltage Differential current Digital Grounded conductance (voltage input current output) Grounded resistance (current input, voltage output) Differential conductance (voltage input current output) Differential resistance (voltage input current output)

%v %i %vd %id %d %g %h %gd %hd

With the models supplied with SIMetrix, only the first four in the above table are ever offered as options. The others are used but are always compulsory, and an understanding of their meaning is not necessary to make full use the system.

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As well as type, all connections also have a flow referring to the direction of the signal flow. This can be in, out or inout. Voltage, current and digital connections may be in or out while the conductance and resistance connections may only be inout. Voltage inputs are always open circuit, current inputs are always short circuit, voltage outputs always have zero output impedance and current outputs always have infinite output impedance. The conductance connections are a combined voltage input and current output connected in parallel. If the output is made to be proportional to the input, the connection would be a conductor with a constant of proportionality equal to its conductance, hence the name. Similarly, the resistance connections are a combined current input and voltage output connected in series. If the output is made to be proportional to the input, the connection would be a resistor with a constant of proportionality equal to its resistance. Changing Connection Type If a model allows one or more of its connections to be given a different type, this can be done by preceding the connection entry with the appropriate modifier listed in the table above. For example if you wish to specify a 4 bit ADC with a differential voltage input, the netlist entry would be something like: A1 %vd ANALOG_INP ANALOG_INN CLOCK_IN [ DATA_OUT_0 DATA_OUT_1 DATA_OUT_2 DATA_OUT_3 ] DATA_VALID ADC_4

Using Expressions
Overview
Expressions consist of arithmetic operators, functions, variables and constants and may be employed in the following locations: As device parameters As model parameters To define a variable (see .PARAM on page 205) which can itself be used in an expression As the governing expression used for arbitrary sources (see page 46).

They have a wide range of uses. For example: To define a number of device or model parameters that depend on some common characteristic. This could be a circuit specification such as the cut-off frequency of a filter or maybe a physical characteristic to define a device model. To define tolerances used in Monte Carlo analyses. Used with an arbitrary source, to define a non-linear device.

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Using Expressions for Device Parameters

Device or instance parameters are placed on the device line. For example the length parameter of a MOSFET, L, is a device parameter. A MOSFET line with constant parameters might be:
M1 1 2 3 4 MOS1 L=1u W=2u

L and W could be replaced by expressions. For example

M1 1 2 3 4 MOS1 L={LL-2*EDGE} W={WW-2*EDGE}

Device parameter expressions must usually be enclosed with either single quotation marks ( ' ) double quotation marks ( " ) or braces ( '{' and '}' ). The expression need not be so enclosed if it consists of a single variable. For example:
.PARAM LL=2u WW=1u M1 1 2 3 4 MOS1 L=LL W=WW

Using Expressions for Model Parameters

The rules for using expressions for device parameters also apply to model parameters. E.g.
.MODEL N1 NPN IS=is BF={beta*1.3}

Expression Syntax
The expression describing an arbitrary source consists of the following elements: Circuit variables Parameters Constants. Operators Functions Look up tables

These are described in the following sections Circuit Variables Circuit variables may only be used in expressions used to define arbitrary sources and to define variables that themselves are accessed only in arbitrary source expressions. Circuit variables allow an expression to reference voltages and currents in any part of the circuit being simulated. Voltages are of the form:

V(node_name)

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Where node_name is the name of the node carrying the voltage of interest. If using the schematic editor nodenames are normally allocated by the netlist generator. For information on how to display and edit the schematic's node names, refer to Displaying Net and Pin Names on page 12. Currents are of the form:

I(source_name)
Where source_name is the name of a voltage source carrying the current of interest. The source may be a fixed voltage source, a current controlled voltage source, a voltage controlled voltage source or an arbitrary voltage source. It is legal for an expression used in an arbitrary source to reference itself e.g.:
B1 n1 n2 V=100*I(B1)

Implements a 100 ohm resistor. Parameters These are defined using the .PARAM control. See page 205 for details. For example
.PARAM res=100 B1 n1 n2 V=res*I(B1)

Also implements a 100 ohm resistor. For release 4 and later it is possible to put circuit variables in .PARAM controls. For example:
.PARAM VMult = { V(a) * V(b) } B1 1 2 V = Vmult + V(c)

Built-in Parameters A number of parameter names are assigned by the simulator. These are:

Parameter name
TIME

Description
Resolves to time for transient analysis. Resolves to 0 otherwise including during the pseudo transient operation point algorithm. Resolves to current circuit temperature Resolves to frequency during AC sweep and zero in other analysis modes Resolves to value of ramp during pseudo transient operating point algorithm.

TEMP HERTZ PTARAMP

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Constants Apart from simple numeric values, arbitrary expressions may also contain the following built-in constants:

Constant name
PI E TRUE FALSE ECHARGE BOLTZ

Value

Description

3.14159265358979323846 2.71828182845904523536 e 1.0 0.0 1.6021918e-19 1.3806226e-23 Charge on an electron in coulombs Boltzman's constant

If the simulator is run from the front end in GUI mode, it is also possible to access variables defined on the Command Shell command line or in a script. The variable must be global and enclosed in braces. E.g.
B1 n1 n2 V = V(n3, n3) * { global:amp_gain }

amp_gain could be defined in a script using the LET command. E.g. Let global:amp_gain = 100 Operators These are listed below and are listed in order of precedence. Precedence controls the order of evaluation. So 3*4 + 5*6 = (3*4) + (5*6) = 42 and 3+4*5+6 = 3 + (4*5) + 6 = 29 as '*' has higher precedence than '+'.

Operator
~!^ or ** *, / +, >=, <=, > < ==, != or <>

Description
Digital NOT, Logical NOT, Unary minus Raise to power. Multiply, divide Plus, minus Comparison operators Equal, not equal

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Operator
& | && ||

Description
Digital AND (see below) Digital OR (see below) Logical AND Logical OR

Comparison, Equality and Logical Operators These are Boo lean in nature either accepting or returning Boo lean values or both. A Boo lean value is either TRUE or FALSE. FALSE is defined as equal to zero and TRUE is defined as not equal to zero. So, the comparison and equality operators return 1.0 if the result of the operation is true otherwise they return 0.0. The arguments to equality operators should always be expressions that can be guaranteed to have an exact value e.g. a Boo lean expression or the return value from functions such as SGN. The == operator, for example, will return TRUE only if both arguments are exactly equal. So the following should never be used: v(n1)==5.0 v(n1) is never likely to be exactly 5.0. It may be 4.9999999999 or 5.00000000001 but only by fluke will it be 5.0. These operators are intended to be used with the IF() function described below. Digital Operators These are the operators '&', '|' and '~'. These were introduced in release 2.0 as a simple means of implementing digital gates in the analog domain. Their function has largely been superseded by gates in the event driven simulator but they are nevertheless still supported. Although they are used in a digital manner the functions implemented by these operators are continuous in nature. They are defined as follows:

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Expression Condition
out = x & y x<vtl OR y<vtl x>vth AND y>vth x>vth AND vth>y>vtl vtl<x< vth AND y>vth vtl<x< vth AND vth>y>vtl x<vtl AND y<vtl x>vth OR y>vth x<vtl AND vth>y>vtl vtl<x< vth AND y<vtl vtl<x< vth AND vth>y>vtl x<vtl x>vth vtl<x< vth

Result
out = vl out = vh out = (y-vtl)*(vh-vl)/(vth-vtl)+vl out = (x-vtl)*(vh-vl)/(vth-vtl)+vl out = (y-vtl)*(x-vtl)*(vh-vl)/(vthvtl)2+vl out = vl out = vh out = vh-(vth-y)*(vh-vl)/(vth-vtl) out = vh-(vth-x)*(vh-vl)/(vth-vtl) out = vh-(vth-y)*(vth-x)*(vh-vl)/ (vth-vtl)2 out = vh out = vl out = (vth-x)/(vth-vtl)*(vh-vl)+vl

out = x|y

out = ~x

Where: vth = upper input threshold vtl = lower input threshold vh = output high vl = output low These values default to 2.2, 2.1, 5 and 0 respectively. These values are typical for high speed CMOS logic (74HC family). They can be changed with four simulator options set by the .OPTIONS simulator control. These are respectively, LOGICTHRESHHIGH, LOGICTHRESHLOW, LOGICHIGH, LOGICLOW To change the lower input threshold to 1.9, add the following line to the netlist:
.OPTIONS LOGICTHRESHLOW=1.9

To find out how to add additional lines to the netlist when using the schematic editor, refer to Adding Extra Netlist Lines on page 12.

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Functions

Function
ABS(x) ACOS(x) ACOSH(x) ASIN(x) ASINH(x) ATAN(x) ATAN2(x,y) ATANH(x) COS(x) COSH(x) DDT(x) EXP(x) FLOOR(x) IF(cond, x, y) IFF(cond, x, y) LIMIT(x, lo, hi) LN(x) LOG(x) LOG10(x) MAX(x, y) MIN(x,y) PWR(x,y) PWRS(x,y) SDT(x) SGN(X) SIN(x) SINH(x) SQRT(x) STP(x)

Description
Magnitude of x. if x>=0 result=x otherwise result=-x Arc cosine. Result is in radians Inverse COSH Arc sine. Result is in radians Inverse SINH Arc tangent. Result is in radians =ATAN(x/y). Valid if y=0. Result in radians Inverse TANH Cosine of x in radians Hyperbolic cosine Differential of x with respect to time ex Next lowest integer of x. if cond is TRUE result=x else result=y As IF(cond, x, y) if x<lo result=lo else if x>hi result=hi else result=x Log to base e of x. If x<10-100 result=-230.2585093 Log to base 10 of x. If x<10-100 result=-100 Log to base 10 of x. If x<10-100 result=-100 Returns larger of x and y Returns smaller of x and y |x|y if x>=0 |x|y else -|x|y Integral of x with respect to time If x>0 result = 1 else if x<0 result = -1 else result = 0 Sine of x in radians Hyperbolic sine if x>=0 x else -x If x<=0 result = 0 else result = 1

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Function
TAN(x) TANH(x) U(x) URAMP(x)

Description
Tangent of x in radians Hyperbolic tangent as STP(x) if x<0 result =0 else result = x

Monte Carlo Distribution Functions To specify Monte Carlo tolerance for a model parameter, use an expression containing one of the following 12 functions:

Name
GAUSS GAUSSL UNIF UNIFL WC WCL GAUSSE GAUSSEL UNIFE UNIFEL WCE WCEL

Distribution
Gaussian Gaussian Uniform Uniform Worst case Worst case Gaussian logarithmic Gaussian logarithmic Uniform logarithmic Uniform logarithmic Worst case logarithmic Worst case logarithmic

Lot?
No Yes No Yes No Yes No Yes No Yes No Yes

A full discussion on the use of Monte Carlo distribution functions is given in Specifying Tolerances on page 221 Look-up Tables Expressions may contain any number of look-up tables. This allows a transfer function of a device to be specified according to - say - measured values without having to obtain a mathematical equation. Look-up tables are specified in terms of x, y value pairs which describe a piece-wise linear transfer function. Look up tables are of the form:

TABLE[ xy_pairs ]( input_expression ) 35

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Where: xy_pairs

A sequence of comma separated pairs of constant values that define the input and output values of the table. For each pair, the first value is the x or input value and the second is the y or output value. Only explicit numeric constants may be used. Even internal constants such as PI may not be used. Expression defining the input or x values of the table.

input_expression Example

The following arbitrary source definition implements a soft limiting function

B1 n2 n3 V=table[-10, -5, -5, -4, -4, -3.5, -3, -3, 3, 3, 4, 3.5, 5, 4, 10, 5](v(N1))

and has the following transfer function:

2 :b1_p / V

-2

-4 -20 v 1/V -15 -10 -5 0 5 10 15 5V /div

It is possible to assign expressions to component values which are evaluated when the circuit is simulated. This has a number of uses. For example you might have a filter design for which several component values affect the roll off frequency. Rather than recalculate and change each component every time you wish to change the roll of frequency it is possible to enter the formula for the component's value in terms of this frequency.

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Example
{C1} C1

{2/(2*pi*f 0*C1*alpha)} {2/(2*pi*f 0*C1*alpha)} R2 AC 1 0 V1 {C1*alpha*alpha/4} C2 R1

1 VOUT

E1

The above circuit is that of a two pole low-pass filter. C1 is fixed and R1=R2. The design equations are:
R1=R2=2/(2*pi*f0*C1*alpha) C2=C1*alpha*alpha/4

where f0 is the cut off frequency and alpha is the damping factor. The complete netlist for the above circuit is:
V1 C2 C1 E1 R1 R2 V1_P 0 AC 1 0 0 R1_P {C1*alpha*alpha/4} VOUT R1_N {C1} VOUT 0 R1_P 0 1 R1_P R1_N {2/(2*pi*f0*C1*alpha)} R1_N V1_P {2/(2*pi*f0*C1*alpha)}

Before running the above circuit you must assign values to the variables. This can be done by one of three methods: With the .PARAM control placed in the netlist. With Let command from the command line or from a script. (If using a script you must prefix the parameter names with global:) By sweeping the value with using parameter mode of a swept analysis (page 168) or multi-step analysis (page 170).

Expressions for device values must be entered enclosed in curly braces ('{' and '}'). Suppose we wish a 1kHz roll off for the above filter. Using the .PARAM control, add these lines to the netlist
.PARAM f0 1k .PARAM alpha 1 .PARAM C1 10n

For more information on .PARAM see page 205

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Using the Let command, you would type:
Let f0=1k Let alpha=1 Let C1=10n

If you then wanted to alter the damping factor to 0.8 you only need to type in its new value:
Let alpha=0.8

then re-run the simulator. To execute the Let commands from within a script, prefix the parameter names with global:. E.g. Let global:f0=1k In many cases the .PARAM approach is more convenient as the values can be stored with the schematic.

Optimisation
Overview An optimisation algorithm may be enabled for expressions used to define arbitrary sources and any expression containing a swept parameter. This can improve performance if a large number of such expressions are present in a design. The optimiser dramatically improves the simulation performance of the power device models developed by Infineon. See Optimiser Performance below. Why is it Needed? The simulators core algorithms use the Newton-Raphson iteration method to solve non-linear equations. This method requires the differential of each equation to be calculated and for arbitrary sources, this differentiation is performed symbolically. So as well calculating the user supplied expression, the simulator must also evaluate the expressions differential with respect to each dependent variable. These differential expressions nearly always have some sub-expressions in common with subexpressions in the main equation and other differentials. Calculation speed can be improved by arranging to evaluate these sub-expressions only once. This is the main task performed by the optimiser. However, it also eliminates factors found on both the numerator and denominator of an expression as well as collecting constants together wherever possible. Using the Optimiser The optimiser will automatically be enabled for any arbitrary source or swept expression that uses a function defined using .FUNC (see .FUNC on page 176). To enable for all expressions, use the following option setting:
.OPTIONS optimise=2

Conversely, optimisation can be disable completely with:

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.OPTIONS optimise=0

Optimiser Performance The optimisation algorithm was added to SIMetrix primarily to improve the performance of some publicly available power device models from Infineon. These models make extensive use of arbitrary sources and many expressions are defined using .FUNC. The performance improvement gained for these model is in some cases dramatic. For example a simple switching PSU circuit using a SGP02N60 IGBT ran around 5 times faster with the optimiser enabled and there are other devices that show an even bigger improvement. Accuracy The optimiser simply changes the efficiency of evaluation and doesnt change the calculation being performed in any way. However, performing a calculation in a different order can alter the least significant digits in the final result. In some simulations, these tiny changes can result in much larger changes in circuit solution. So, you may find that switching the optimiser on and off may change the results slightly.

Subcircuits
Overview
Subcircuits are a method of defining a circuit block which can be referenced any number of times by a single netlist line or schematic device. Subcircuits are the method used to define many device models such as op-amps.

Subcircuit Definition
Subcircuits begin with the .SUBCKT control and end with .ENDS. A subcircuit definition is of the form:

.SUBCKT subcircuit_name nodelist [[params:] default_parameter_list] definition_lines .ENDS

subcircuit_name nodelist Name of the subcircuit and is used to reference it in the main netlist. Any number of node names and are used for external connections. The subcircuit call (using an X device) would use a matching number of nodes in the same order. List of parameters and their default values in the form name=value. Subcircuit parameters are explained in Using Expressions on

default_parameter_list

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page 28. definition_lines List of valid device and model lines. In addition, .NODESET, .IC and .KEEP lines may also be placed in a subcircuit.

Example This is an example of an opamp subcircuit called SXOA1000. VINP, VINN VOUT VCC and VEE are its external connections. The three .model lines define devices that are local, that is, they are only accessible within the subcircuit definition.
.subckt SXOA1000 VINP VINN VOUT VCC VEE I2 D2_N VEE 100u I1 Q3_E VEE 100u C1 VOUT R1_P 10p D1 Q7_C D1_N D1 D2 D1_N D2_N D1 D3 VEE Q3_E D1 Q2 VEE D2_N VOUT 0 P1 Q3 Q3_C R3_P Q3_E 0 N1 Q1 VCC Q7_C VOUT 0 N1 Q6 Q3_C Q3_C VCC 0 P1 Q7 Q7_C Q5_C VCC 0 P1 R1 R1_P Q5_C 100 Q4 Q5_C R2_N Q3_E 0 N1 R2 VINP R2_N 1K Q5 Q5_C Q3_C VCC 0 P1 R3 R3_P VINN 1K .model N1 NPN VA=100 TF=1e-9 .model P1 PNP VA=100 TF=1e-9 .model D1 D .ends

Where to Place Subcircuit Definition Subcircuit definitions may be placed in a number of locations. Directly in the netlist. This is the best place if the subcircuit is specific to a particular design. If you are entering the circuit using the schematic editor, see Adding Extra Netlist Lines on page 12. to find out how to add additional lines to the netlist. Put in a separate file and pull in to the schematic with .INC (page 184) control placed in the netlist. Put in a library file and reference in schematic with SIMetrix form of .LIB (page 186) control placed in the netlist. Similar to 2. but more efficient if library has many models not used in the schematic. Only the devices required will be read in. Put in a library file and install as a model library. See User's Manual for full details.

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Subcircuit Instance
Once a subcircuit has been defined, any number of instances of it may be created. These are of the form:

Xxxxx nodelist sub_circuitname [ [params:|:] parameters]

nodelist List of nodes, each of which will connect to its corresponding node in the subcircuit's definition. The number of nodes in the instance must exactly match the number of nodes in the definition. Name of the subcircuit definition. List of parameter names and their values in the form name=value. These may be referenced in the subcircuit definition. Subcircuit parameters are explained below.

sub_circuitname parameters

Passing Parameters to Subcircuits

You can pass parameters to a subcircuit. Consider the filter example provided in Using Expressions above. Supposing we wanted to define several filters with different characteristics. We could use a subcircuit to define the filter but the values of the components in the filter need to be different for each instance. This can be achieved by passing the parameter values to each instance of the subcircuit. So:
** Definition .SUBCKT Filter IN OUT params: C1=1n alpha=1 f0=1k C2 0 R1_P {C1*alpha*alpha/4} C1 OUT R1_N {C1} E1 OUT 0 R1_P 0 1 R1 R1_P R1_N {2/(2*pi*f0*C1*alpha)} R2 R1_N IN {2/(2*pi*f0*C1*alpha)} .ENDS ** Subcircuit instance X1 V1_P VOUT Filter : C1=10n alpha=1 f0=10k ** AC source V1 V1_P 0 AC 1 0

In the above example the parameters after params: in the .subckt line define default values should any parameters be omitted from the subcircuit instance line. It is not compulsory to define defaults but is generally recommended. Note In the syntax definition for both subcircuit definitions and subcircuit instances, the params: specifier is shown as optional. This is for compatibility with Star-Hspice and is new for release 4. If params: is included the '=' separating the parameter names and their values becomes optional.

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Nesting Subcircuits
Subcircuit definitions may contain both calls to other subcircuits and local subcircuit definitions. If a subcircuit definition is placed within another subcircuit definition, it becomes local. That is, it is only available to its host subcircuit. Calls to subcircuits may not be recursive. A subcircuit may not directly or indirectly call its own definition.

Global Nodes
Sometimes it is desirable to refer to a node at the circuit's top level from within a subcircuit without having to explicitly pass it. This is sometimes useful for supply rails. SIMetrix provides three methods. '#' prefix. Any node within a subcircuit prefixed with '#' will connect to a top level node of the same name without the '#' prefix. '$g_' prefix. Any node in the circuit prefixed '$g_' will be treated as global Using .GLOBAL see page 177

The second approach is compatible with PSpice. The third approach is compatible with Star-Hspice Note the first two approaches are subtly different. In the second approach the '$g_' prefix must be applied to all connected nodes, whereas in the first approach the '#' prefix must be applied only to subcircuit nodes.

Subcircuit Preprocessing
SIMetrix features a netlist preprocessor that is usually used for SIMPLIS simulations and was developed for that purpose. The preprocessor has some features that arent available in the native simulator and for this reason it would be useful to be able to use the preprocessor for SIMetrix simulations. It is not necessary to apply the preprocessor to the entire netlist. Any subcircuit call that defines preprocessor variables using the vars: specifier will be passed to the preprocessor. For example:
X$C1 R1_P 0 ELEC_CAP_L13 vars: LEVEL=3 CC=1m + RSH_CC=1Meg IC=0 RESR=10m LESL=100n USEIC=1

calls the ELEC_CAP_L13 subcircuit but passes it through the preprocessor first. This model is a model for an electrolytic capacitor and uses a number of .IF controls to select model features according to the LEVEL parameter. The preprocessor also provides a means of generating multiple devices using .WHILE. For information on the preprocessor, see the SIMPLIS Reference Manual. A PDF version of this is available on the install CD.

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Chapter 3 Simulator Devices

Model Binning
Overview
Some devices can be binned. This means that a number of different model definitions can be provided for the same device with each being valid over a limited range of some device parameter or parameters. The simulator will automatically select the appropriate model according to the value given for the device parameters. Currently only BSIM3 MOSFETs may be binned. The binning is controlled by the length and width device parameters (L and W) while the LMIN, LMAX, WMIN and WMAX model parameters specify the valid range for each model. Important Note The binned models should be placed directly in the netlist or called using either .INC or the Star-Hspice form of .LIB. They will not work correctly when installed as a model library or accessed with the SIMetrix form of .LIB.

Defining Binned Models

Binned models are defined as a set consisting of two or more .MODEL definitions. Each of the definitions must be named using the following format:

root_name.id
root_name id Name used by the device to call the model. Must be the same for all model definitions in a set Arbitrary name that must be unique for each model in a set. This would usually be a number but this is not a requirement

Each model definition must also contain a MIN/MAX parameter pair for each bin control parameter. For the BSIM3 MOSFET there are two bin control parameters, namely L and W with corresponding MIN/MAX pairs LMIN/LMAX and WMIN/ WMAX. For a binned BSIM3 model, all four must be present. These parameters define the range of L and W over which the model is valid. When a model is required, the simulator searches all models with the same root_name for a definition whose LMIN/ LMAX and WMIN/WMAX parameters are compatible with the device's L and W.

Example
.MODEL N1.1 NMOS LEVEL=49 ... parameters ... + LMIN=1u LMAX=4u WMIN=1u WMAX=4u .MODEL N1.2 NMOS LEVEL=49 ... parameters ... + LMIN=4u LMAX=10u WMIN=1u WMAX=4u .MODEL N1.3 NMOS LEVEL=49 ... parameters ... + LMIN=1u LMAX=4u WMIN=4u WMAX=10u .MODEL N1.4 NMOS LEVEL=49 ... parameters ... + LMIN=4u LMAX=10u WMIN=4u WMAX=10u

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** This device will use N1.1 M1 1 2 3 4 N1 L=2u W=2u ** This device will use N1.2 M2 1 2 3 4 N1 L=6u W=2u ** This device will use N1.3 M3 1 2 3 4 L=2u W=7u ** This device will use N1.4 M4 1 2 3 4 L=6u W=7u

Language Differences
SIMetrix is compatible with some PSpice and Star-Hspice extensions mainly so that it can read external model files. Some aspects of these alternative formats are incompatible with the SIMetrix native format and in such cases it is necessary to declare the language being used. See Language Declaration on page 19 for details on how to do this. The following sections describe the incompatibilities between the three languages.

Inline Comment
Star-Hspice uses the dollar ('$') symbol for inline comments while SIMetrix and PSpice use a semi-colon (';'). The language declaration described above determines what character is used.

Unlabelled Device Parameters

The problem with unlabelled device parameters is illustrated with the following examples. The following lines are legal in Star-Hspice mode but illegal in SIMetrix mode.
.PARAM area=2 Q1 C B E S N1 area

Q1 will have an area of 2. Conversely the following is legal in SIMetrix but is illegal in Star-Hspice:
.PARAM area=2 Q1 C B E S N1 area area

Again Q1 has an area of 2. The problem is that SIMetrix does not require '=' to separate parameter names with their values whereas Star-Hspice does. area is a legal BJT parameter name so in the first example SIMetrix can't tell whether area refers to the name of the BJT parameter or the name of the .PARAM parameter defined in the previous line. Star-Hspice can tell the difference because if area meant the BJT parameter name it would be followed by an '='. This line is legal and will be correctly interpreted in both modes

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Chapter 3 Simulator Devices

.PARAM area=2 Q1 C B E S N1 area=area

Although Hspice always requires the '=' to separate parameter names and values, it continues to be optional in SIMetrix even in Hspice mode. It only becomes compulsory where an ambiguity needs to be resolved as in the second example above.

LOG() and PWR()

The LOG() function means log to the base 10 in SIMetrix but in PSpice and StarHspice means log to the base e. PWR() in PSpice and SIMetrix means |x|y whereas in Star-Hspice it means if x>=0 |x|y else -|x|y. The language declaration only affects the definition when used in expressions to define model and device parameters. When used in arbitrary source expressions, the language assumed is controlled by the method of implementing the device as follows: SIMetrix:
B1 1 2 V=expression

PSpice
E1 1 2 VALUE = {expression }

Star-Hspice
E1 1 2 VOL = 'expression'

Note that the function LN() always means log to base e and LOG10() always means log to base 10. We recommend that these functions are always used in preference to LOG to avoid confusion.

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Chapter 4 Analog Device Reference

Overview
This chapter provides the full details of every option and parameter available with every primitive analog device that the simulator supports. For documentation on digital and mixed signal devices supplied with SIMetrix, please see Digital/Mixed Signal Device Reference on page 109.

Arbitrary Source
Netlist Entry

Voltage source: Bxxxx n+ n- [MIN=min_value] [MAX=max_value] V=expression Current source: Bxxxx n+ n- [MIN=min_value] [MAX=max_value] I=expression Charge source: Bxxxx n+ n- Q=expression Flux source: Bxxxx n+ n- FLUX=expression
An arbitrary source is a voltage or current source whose output can be expressed as an arbitrary relationship to other circuit voltages or currents. expression Algebraic expression describing voltage or current output in terms of circuit nodes or sources. See Expression Syntax on page 29 for full details. Minimum value of source Maximum value of source Component reference Positive output node. Negative output node.

min_value max_value Bxxxx n+ n-

The small-signal AC behaviour of the non-linear source is a linear dependent source with a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point. Note that if MIN and/or MAX parameters are specified, they must precede the defining expression.

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Charge and flux sources implement capacitors and inductors respectively. See Charge and Flux Devices below for details. If the source is a current, the direction of flow is into the positive node (n+).

Notes on Arbitrary Expression

It is generally beneficial if the expression used for an arbitrary source is well conditioned. This means that it is valid for all values of its input variables (i.e. circuit voltages and currents) and that it is continuous. It is also desirable - although rarely absolutely necessary - for the function to be continuous in its first derivative; i.e. it does not have any abrupt changes in slope. If the expression is used in a feedback loop then these conditions are more or less essential for reliable and rapid convergence. If the arbitrary source is used open loop then these conditions can be relaxed especially if the input signal is well defined e.g. derived directly from a signal source. Some functions are not continuous in nature. E.g. the STP() and SGN() functions are not. These may nevertheless be used in an expression as long as the end result is continuous. Similarly, the IF() function should be used with care. The following IF() function is continuous:
IF(v1>v2, 0, (v1-v2)*2)

When v1=v2 both true and false values equate to zero so the function has no abrupt change. The function still has a discontinuous first derivative with respect to both v1 and v2 which is still undesirable but will work satisfactorily in most situations. The following example is not continuous:
IF(v1>v2, 0, 5)

The result of this will switch abruptly from 0 to 5 when v1=v2. This is not something that the simulator can be guaranteed to handle and cannot be implemented in real life. A better, albeit less intuitive method, of achieving the intent of the above is:
(TANH((v2-v1)*factor)+1)*2.5+2.5

where factor is some number that determines the abruptness of the switching action. For a value of 147, 95% of the full output will be achieved with just 10mV overdrive.

Charge and Flux Devices

From release 4 it is possible to define capacitors and inductors directly using the arbitrary source. Capacitors must be defined in terms of their charge and inductors by their flux. These are defined in the same as voltage and current arbitrary sources but using q or flux instead of v or i. E.g. the following defines a simple linear capacitor:
B1 n1 n2 Q = C*V(n1,n2)

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Similarly a linear inductor is:
B1 n1 n2 flux = L * i(B1)

The main benefit of this feature is that it makes it possible to define non-linear capacitors and inductors directly. Previously, this was only possible by making up a circuit consisting of a number of components including a primitive capacitor. As with voltage and current arbitrary sources, it is possible to use any combination of voltages and currents in the expression. So, for example, the following defines a transformer:
Bprimary p1 p2 flux = Lp*i(Bprimary) + M*i(Bsecondary) Bsecondary s1 s2 flux = Ls*i(Bsecondary) + M*i(Bprimary)

Arbitrary Source Examples

Example 1 - Ideal Power Converter This examples also demonstrates the use of expressions within subcircuits. (See Using Expressions on page 28) The following subcircuit implements an idealised power converter with an efficiency of eff and whose output voltage is proportional to the input voltage (vinn,vinp) multiplied by the control voltage (vcp,vcn). It is intended to simulate the voltage/ current characteristics of a switching power converter.
.subckt powerconv voutp voutn vinp vinn vcp vcn biin1 vinp vinn i=-v(voutp,voutn)/v(vinp,vinn)*i(vout1)/{eff} vout1 bmult1_n voutn 0 bmult1 voutp bmult1_n v=v(vinp,vinn)*v(vcp,vcn) r1 vcp vcn 1meg .ends

Once again, with an appropriate schematic symbol, the device can be placed on the schematic as a block as shown below:

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D2 ideal C1 270u R5 1meg

U1

1000

powerconv : ef f =0.7 v1 pulse (100 0 0 1m) V2 12 E1

R1 1K

Example 2 - Voltage Multiplier The expression for an arbitrary source must refer to other voltages and/or currents on the schematic. Currents are referenced as voltage sources and voltages as netnames. Netnames are usually allocated by the netlister. For information on how to display and edit the schematic's netnames, refer to Displaying Net and Pin Names on page 12.

R4 10k 1K R1

n1 B1 V=V(n2)*V(n1) n2 1K R3 1K R2

In the above circuit the voltage across B1 will be equal to the product of the voltages at nodes n1 and n2. An alternative approach is to define the arbitrary source within a subcircuit. E.g.
.subckt MULT out in1 in2 B1 out 0 V=V(in1)*V(in2) .ends

which can be added to the netlist manually. (To find out how to add additional lines to the netlist when using the schematic editor, refer to Adding Extra Netlist Lines on page 12). A symbol could be defined for it and then placed on the schematic as a block as shown below:

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R4 1K

R1 1K

X1

R2 1K R3 1K MULT

Example 3 - Voltage comparator

B3 q3_b 0 V=atan(V(n1,n2)*1000)

This can also be added to the schematic in the same way as for the multiplier described above.

PSpice and Star-Hspice syntax

SIMetrix supports the PSpice and Hspice syntax for arbitrary sources. This is for compatibility with some manufacturers device models. For PSpice the VALUE = and TABLE = devices are supported and for Star-Hspice VOL= and CUR= are supported.

Bipolar Junction Transistor (SPICE Gummel Poon)

Netlist Entry

Qxxxx collector base emitter [substrate] modelname [area] [OFF] [IC=vbe,vce] [TEMP=local_temp]
collector base emitter substrate modelname area Collector node name Base node name Emitter node name Substrate node name Name of model. Must begin with a letter but can contain any character except whitespace and ' . ' . Area multiplying factor. Area scales up the device. E.g. an area of 3 would make the device behave like 3 transistors in parallel. Default is 1. Instructs simulator to calculate operating point analysis with device initially off. This is used in latching circuits such as

OFF

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thyristors and bistables to induce a particular state. See .OP on page 194 for more details. vbe,vce Initial conditions for base-emitter and collector-emitter junctions respectively. These only have an effect if the UIC parameter is specified on the .TRAN control (see .TRAN on page 213). Local temperature. Overrides specification in .OPTIONS (page 195) or .TEMP (page 211) controls.

local_temp

NPN BJT Model Syntax

.model modelname NPN ( parameters )

PNP BJT Model Syntax

.model modelname PNP ( parameters )

Lateral PNP BJT Model Syntax

.model modelname LPNP ( parameters )

BJT Model Parameters The symbols ' ' and ' ' in the Area column means that that parameter should be multiplied or divided by the area factor respectively.

Name
IS BF NF VAF IKF ISE NE BR NR VAR IKR ISC NC

Description
Transport saturation current Ideal maximum forward beta Forward current emission coefficient Forward Early voltage Corner for forward beta high current roll-off B-E leakage saturation current B-E leakage emission coefficient Ideal maximum reverse beta Reverse current emission coefficient Reverse Early voltage Corner for reverse beta high current roll-off B-C leakage saturation current B-C leakage emission coefficient

Units
A

Default Area
1e-16 100 1.0

V A A

0 1.5 1 1

V A A

0 2

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Name
RB IRB RBM RE RC CJE VJE MJE TF XTF VTF ITF PTF CJC VJC MJC XCJC TR ISS NS CJS VJS MJS XTB EG

Description
Zero bias base resistance Current at which base resistance falls halfway to its minimum value Minimum base resistance at high currents Emitter resistance Collector resistance B-E zero-bias depletion capacitance B-E built in potential B-E junction exponential factor Ideal forward transit time Coefficient for bias dependence of TF

Units
W A W W W F V Sec.

Default Area
0 RB 0 0 0 0.75 0.33 0 0 0 0 0 0.75 0.33 1

Voltage describing VBC dependence of V TF High-current parameter for effect on TF A Excess phase at freq=1.0/(TF2) Hz B-C zero-bias depletion capacitance B-C built-in potential B-C junction exponential factor Fraction of B-C depletion capacitance connected to internal base node Ideal reverse transit time Substrate diode saturation current Substrate diode emission coefficient Zero-bias collector substrate capacitance Substrate junction built-in potential Substrate junction exponential factor Forward and reverse beta temperature exponent Energy gap eV F V Sec. A degree F V

0 0 1 0 0.75 0 0 1.11

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Name
XTI KF AF FC

Description
Temperature exponent for effect on IS Flicker noise coefficient Flicker noise exponent Coefficient for forward-bias depletion capacitance formula

Units

Default Area
3 0 1 0.5

Notes

The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model will automatically simplify to the simpler Ebers-Moll model when certain parameters are not specified. The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the forward current gain characteristics, IS, BR, NR, ISC, IKR, and NC which determine the reverse current gain characteristics, and VAF and VAR which determine the output conductance for forward and reverse regions. Three ohmic resistances RB, RC, and RE are included, where RB can be high current dependent. Base charge storage is modelled by forward and reverse transit times, TF and TR, the forward transit time TF being bias dependent if desired, and non-linear depletion layer capacitances which are determined by CJE, VJE, and MJE for the B-E junction, CJC, VJC, and MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction. The temperature dependence of the saturation current, IS, is determined by the energy-gap, EG, and the saturation current temperature exponent, XTI. Additionally base current temperature dependence is modelled by the beta temperature exponent XTB in the new model.

Bipolar Junction Transistor (VBIC without self heating)

Netlist Entry

Qxxxx collector base emitter [substrate] modelname [M=multiplier] [AREA|SCALE=area]

collector base emitter substrate modelname multiplier Collector node name Base node name Emitter node name Substrate node name Name of model. Must begin with a letter but can contain any character except whitespace and ' . ' . Device scale. Has an identical effect as putting multiplier devices in parallel.

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area Scales certain model parameters as described in the parameter table under Area column. A entry means the parameter is multiplied by the area while a means the parameter is divided by the area.

Model Syntax

.MODEL modelname NPN|PNP LEVEL=4 parameters

Model Parameters

Name
TNOM/ TREF RCX RCI VO GAMM HRCF RBX RBI RE RS RBP IS NF NR FC CBEO/ CBE0 CJE PE ME AJE CBCO/ CBC0

Description
Nominal ambient temperature Extrinsic collector resistance Intrinsic collector resistance Epi drift saturation voltage Epi doping parameter High-current RC factor Extrinsic base resistance Intrinsic base resistance Emitter resistance Substrate resistance Parasitic base resistance Transport saturation current Forward emission coefficient Reverse emission coefficient Forward bias junction capacitance threshold Base-emitter small signal capacitance Base-emitter zero-bias junction capacitance Base-emitter grading coefficient Base-emitter junction exponent Base-emitter capacitance smoothing factor Extrinsic base-collector overlap capacitance

Units
Celsius Ohms Ohms

Default Area
27 0.0 0.0 0.0 0.0 1.0 0.0 0.0 0.0 0.0 0.0 1.0E-16 1.0 1.0 0.9 0.0 0.0 0.75 0.33 -0.5 0.0

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Name
CJC QCO/ QC0 CJEP PC MC AJC CJCP PS MS AJS IBEI WBE NEI IBEN NEN IBCI NCI IBCN NCN AVC1 AVC2 ISP WSP NFP

Description
Base-collector zero-bias capacitance Collector charge at zero bias Base-emitter extrinsic zero-bias capacitance Base-collector grading coefficient Base-collector junction exponent Base-collector capacitance smoothing factor Base-collector zero-bias extrinsic capacitance Collector-substrate grading coefficient Collector-substrate junction exponent Collector-substrate capacitance smoothing factor Ideal base-emitter saturation current Portion of IBEI from Vbei, (1-WBE) from Vbex Ideal base-emitter emission coefficient Non-ideal base-emitter saturation current Non-ideal base-emitter emission coefficient Ideal base-collector saturation current Ideal base-collector emission coefficient Non-ideal base-collector saturation current Non-ideal base- collector emission coefficient Base-collector weak avalanche parameter 1 Base-collector weak avalanche parameter 2 Parasitic transport saturation current Portion of Iccp from Vbep, (1-WSP) from Vbci Parasitic forward emission coefficient

Units

Default Area
0.0 0.0 0.0 0.75 0.33 -0.5 0.0 0.75 0.33 -0.5 1E-18 1.0 1.0 0.0 2.0 1.0E-16 1.0 0.0 2.0 0.0 0.0 0.0 1.0 1.0

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Name
IBEIP IBENP IBCIP NCIP IBCNP NCNP VEF VER IKF IKR IKP TF QTF XTF VTF ITF TR TD KFN AFN BFN XRE XRB XRC XRS

Description
Ideal parasitic base-emitter saturation current Non-ideal parasitic base-emitter saturation current Ideal parasitic base-collector saturation current Ideal parasitic base-collector emission coefficient Non-ideal parasitic base-collector saturation current Non-ideal parasitic base-collector emission coefficient Forward Early voltage (0=infinity) Reverse Early voltage (0=infinity) Forward knee current, (0=inifinity) Reverse knee current, (0=infinity) Parasitic knee current (0=infinity) Forward transit time Variation of TF with base width modulation Coefficient of TF bias dependence Coefficient of TF dependence on Vbc Coefficient of TF dependence of Icc Ideal reverse transit time Forward excess phase delay time Flicker noise coefficient Flicker noise exponent Flicker noise frequency exponent Temperature exponent of emitter resistance Temperature exponent of base resistance Temperature exponent of collector resistance Temperature exponent of substrate resistance

Units

Default Area
0.0 0.0 0.0 1.0 0.0 2.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 1.0 1.0 0.0 0.0 0.0 0.0

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Name
XV0/ XV0 EA EAIE EAIC EAIS EANE EANC EANS XIS XII XIN TNF TAVC Notes

Description
Temperature exponent of Vo Activation energy for IS Activation energy for IBEI Activation energy for IBCI/IBEIP Activation energy for IBCIP Activation energy for IBEN Activation energy for IBCN/IBENP Activation energy for IBCNP Temperature exponent of Is Temperature exponent of IBEI/IBCI/ IBEIP/IBCIP Temperature exponent of IBEN/IBCN/ IBENP/IBCNP Temperature coefficient of NF Temperature coefficient of AVC

Units

Default Area
0.0 1.12 1.12 1.12 1.12 1.12 1.12 1.12 3.0 3.0 3.0 0.0 0.0

The VBIC model is only available with Micron versions. The Vertical Bipolar Inter-Company (VBIC) model is an advanced bipolar junction transistor model. This is the 4-terminal non-thermal version. There is also a version that supports self-heating effects and has 5 terminals, see Bipolar Junction Transistor (VBIC with self heating) below. For more information about VBIC, please refer to this link: http://www.designers-guide.com/VBIC/references.html

Bipolar Junction Transistor (VBIC with self heating)

Netlist Entry

Qxxxx collector base emitter substrate thermal_node modelname [M=multiplier] [AREA|SCALE=area]

collector base emitter substrate Collector node name Base node name Emitter node name Substrate node name

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thermal_node modelname multiplier area See notes Name of model. Must begin with a letter but can contain any character except whitespace and ' . ' . Device scale. Has an identical effect as putting multiplier devices in parallel. Scales certain model parameters as described in the parameter table under Area column. A entry means the parameter is multiplied by the area while a means the parameter is divided by the area.

Model Syntax

.MODEL modelname NPN|PNP LEVEL=1004 parameters

Model Parameters Model parameters are identical to the non-thermal version except for the addition of the following:

Name
RTH CTH Notes

Description
Thermal resistance Thermal capacitance

Units

Default Area
0.0 0.0

The VBIC model is only available with Micron versions. This model is the same as the VBIC non-thermal model except for the addition of selfheating effects. Use the non-thermal version if you do not need self-heating as its implementation is simpler and will run faster. The thermal_node may be used to connect external thermal networks to model thermal flow. Power in watts is represented by current and temperature rise in Kelvin is represented by the voltage. Note that the voltage is temperature rise above the simulation temperature, not an absolute value.

Bipolar Junction Transistor (MEXTRAM)

See Philips Compact Models on page 104

Capacitor
Netlist Entry

Cxxxx n1 n2 [model_name] value [IC=initial_condition] [TEMP=local_temp] [TC1=tc1] [TC2=tc2] [VC1=vc1] [VC2=vc2] 58

Chapter 4 Analog Device Reference [BRANCH=0|1]

n1 n2 model_name value initial_condition local_temp tc1 tc2 vc1 vc2 BRANCH Node 1 Node 2 (Optional) Name of model . Must begin with a letter but can contain any character except whitespace and period '.' Capacitance (Farads) Initial voltage if UIC specified on .TRAN control (page 213). Capacitor temperature (C) First order temperature coefficient Second order temperature coefficient First order voltage coefficient Second order voltage coefficient May be 0 or 1. 0 is the default. This parameter determines the internal formulation of the capacitor and affects how the IC parameter is implemented. When BRANCH=0, the capacitor looks like an open circuit during the DC operating point and the IC parameter has no effect unless UIC is specified for a transient analysis. If BRANCH=1, the capacitor looks like a voltage source during dc operating point with a magnitude equal to the value of the IC parameter. BRANCH=1 makes it possible to specify circuit startup conditions. See Alternative Initial Condition Implementations on page 183 for an example.

Capacitor Model Syntax

.model modelname CAP ( parameters )

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Capacitor Model Parameters

Name
C TC1 TC2 VC1 VC2

Description
Capacitor multiplier First order temperature coefficient Second order temperature coefficient First order voltage coefficient Second order voltage coefficient

Units
1/C 1/C
2

Default
1 0 0 0 0

Volt-1 Volt-2

Capacitor with Voltage Initial Condition

Netlist entry:

Axxxx cap_p cap_n model_name

Model format:

.MODEL model_name cm_cap parameters

Model parameters:

Name
c ic

Description
Capacitance Voltage initial condition

Type
real real

Default Limits
none 0 1E-21 - none

Description This device is now obsolete. Use a standard capacitor with BRANCH=1. This is like a standard capacitor but the internal implementation is different and permits the specification of an initial condition which works without having to specify the transient UIC switch. Also, unlike normal initial conditions, the initial voltage is applied with a zero source resistance. In some circumstances, large value capacitors are better implemented using this device than the standard capacitor but note that during the DC operating point solution, the device looks like a short circuit, not an open circuit as is the case with the normal SPICE device.

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Current Controlled Current Source

Netlist Entry: Linear Source

Fxxxx nout+ nout- vc current_gain

nout+ noutvc current_gain Positive output node Negative output node Controlling voltage source Output current/Input current

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for IC's. (Most operational amplifier models for example use several polynomial sources). In general, however the arbitrary source (page 46) is more flexible and easier to use. Netlist Entry: Polynomial Source

Fxxxx nout+ nout- POLY( num_inputs ) vc1 vc2 ... + polynomial_specification

vc1, vc2 num_inputs polynomial_specification Controlling voltage sources Number of controlling currents for source. See Polynomial Specification on page 62

The specification of the controlling voltage source or source requires additional netlist lines. The schematic netlister automatically generates these for the four terminal device supplied in the symbol library. Example
R2 1K 0.1

R1 1K F1

In the above circuit, the current in the output of F1 (flowing from top to bottom) will be 0.1 times the current in R2.

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Polynomial Specification
The following is an extract from the SPICE2G.6 user manual explaining polynomial sources. SPICE allows circuits to contain dependent sources characterised by any of the four equations i=f(v) v=f(v) i=f(i) v=f(i) where the functions must be polynomials, and the arguments may be multidimensional. The polynomial functions are specified by a set of coefficients p0, p1, ..., pn. Both the number of dimensions and the number of coefficients are arbitrary. The meaning of the coefficients depends upon the dimension of the polynomial, as shown in the following examples: Suppose that the function is one-dimensional (that is, a function of one argument). Then the function value fv is determined by the following expression in fa (the function argument): fv = p0 + (p1.fa) + (p2.fa2) + (p3.fa3) + (p4.fa4) + (p5.fa5) + ... Suppose now that the function is two-dimensional, with arguments fa and fb. Then the function value fv is determined by the following expression: fv = p0 + (p1.fa) + (p2.fb) + (p3.fa2) + (p4.fa.fb) + (p5.fb2) + (p6.fa3) + (p7.fa2.fb) + (p8.fa.fb2) + (p9.fb3) + ... Consider now the case of a three-dimensional polynomial function with arguments fa, fb, and fc. Then the function value fv is determined by the following expression: fv = p0 + (p1.fa) + (p2.fb) + (p3.fc) + (p4.fa2) + (p5.fa.fb) + (p6.fa.fc) + (p7.fb2) + (p8.fb.fc) + (p9.fc2) + (p10.fa3) + (p11.fa2.fb) + (p12.fa2.fc) + (p13.fa.fb2) + (p14.fa.fb.fc) + (p15.fa.fc2) + (p16.fb3) + (p17.fb2.fc) + (p18.fb.fc2) + (p19.fc3) + (p20.fa4) + ... Note If the polynomial is one-dimensional and exactly one coefficient is specified, then SPICE assumes it to be p1 (and p0 = 0.0), in order to facilitate the input of linear controlled sources.

Current Controlled Voltage Source

Netlist Entry: Linear Source

Hxxxx nout+ nout- vc transresistance

nout+ Positive output node

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noutvc transresistance Negative output node Controlling voltage source Output current/Input current ()

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for IC's. (Most Op-amp models use several polynomial sources). In general, however the arbitrary source is more flexible and easier to use. Netlist Entry: Polynomial Source

Hxxxx nout+ nout- POLY( num_inputs ) vc1 vc2 ... + polynomial_specification

vc1, vc2 num_inputs polynomial_specification Controlling voltage sources Number of controlling currents for source. See Polynomial Specification on page 62.

The specification of the controlling voltage source or source requires additional netlist lines. The schematic netlister automatically generates these for the four terminal device supplied in the symbol library.

Current Source
Netlist Entry

Ixxxx n+ n- [DC dcvalue] [AC magnitude [phase]] [transient_spec]

n+ ndcvalue magnitude phase transient_spec Positive node Negative node Value of source for dc operating point analysis AC magnitude for AC sweep analysis. phase for AC sweep analysis Specification for time varying source. Can be one of following:

Pulse - see page 98 Piece wise linear - see page 99 Sine - see page 101 Exponential - see page 102 Single frequency FM - see page 102

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Diode
Netlist Entry

Dxxxx n+ n- model_name [area] [OFF] [IC=vd] [TEMP=local_temp] + [M=mult] [PJ=periphery] [L=length] [W=width]
n+ nmodel_name Anode Cathode Name of model defined in a .MODEL control (page 187). Must begin with a letter but can contain any character except whitespace and ' . ' . Area multiplying factor. Area scales up the device. E.g. an area of 3 would make the device behave like 3 diodes in parallel. Default is 1. Instructs simulator to calculate operating point analysis with device initially off. This is used in latching circuits such as thyristors and bistables to induce a particular state. See .OP on page 194 for more details. Initial condition for diode voltage. This only has an effect if the UIC parameter is specified on the .TRAN control (page 213). Local temperature. Overrides specification in .OPTIONS (page 195) or .TEMP (page 211) controls. Level 3 only. Similar to area. See below. Level 3 only. Junction periphery used for calculating sidewall effects. Level 3 only. Used to calculate area. See below. Level 3 only. Used to calculate area. See below.

area

OFF

vd local_temp mult periphery length width Examples

D1 D1N4148

D2 5 BYT12

D3 D1N914 TEMP=100

Diode Model Syntax

.model modelname D ( LEVEL=[1|3] parameters )

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Diode Model Parameters - Level = 1 The symbols ' ' and ' ' in the Area column means that that parameter should be multiplied or divided by the area factor respectively.

Name
IS ISR N NR IKF RS TT CJO or CJ0 VJ M EG XTI KF AF FC BV IBV TNOM TRS1 TRS2 TBV1 TBV2 Notes

Description
Transport saturation current Recombination current parameter Emission coefficient Emission Coefficient for ISR High injection knee current Series resistance Transit time Zero bias junction capacitance Junction potential Grading coefficient Energy gap Saturation current temperature exponent Flicker noise coefficient Flicker noise exponent Forward bias depletion capacitance coefficient Reverse breakdown voltage Current at breakdown voltage Parameter measurement temperature First order tempco RS Second order tempco RS First order tempco BV Second order tempco BV

Units
A A

Default Area
1e-14 0 1 2

A W sec F V eV

0 0 0 1 0.5 1.11 3 0 1 0.5

V A C /C /C2 /C /C2

1e-10 27 0 0

The dc characteristics of the diode are determined by the parameters IS, N, ISR, NR and IKF. An ohmic resistance, RS, is included. Charge storage effects are modelled by a transit time, TT, and a non-linear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the energy and XTI, the saturation current temperature

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exponent. Reverse breakdown is modelled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).

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Diode Model Parameters - Level = 3

Name
AF BV CJO, CJ CJSW CTA CTP EG FC FCS GAP1

Description
Flicker noise exponent Reverse breakdown voltage Zero bias junction capacitance Zero bias sidewall capacitance CJO temp coefficient. (TLEVC=1) CJSW temp coefficient. (TLEVC=1) Energy gap Forward bias depletion capacitance coefficient Forward bias sidewall capacitance coefficient 7.02e-4 - silicon (old value) 4.73e-4 - silicon 4.56e-4 - germanium 5.41e-4 - gallium arsenide 1108 - silicon (old value) 636 - silicon 210 - germanium 204 - gallium arsenide Current at breakdown voltage High injection knee current Reverse high injection knee current Saturation current Recombination current Sidewall saturation current Flicker noise exponent Grading coefficient Sidewall grading coefficient Forward emission coefficient Recombination emission coefficient Sidewall built in potential Series resistance Shrink factor BV temp coefficient

Units

Default
1.0 0.0 0.0

V F F C-1 C-1 ev

1.11 0.5 0.5

eV/

7.02e-4

GAP2

1108

IBV IKF, IK IKR IS, JS ISR JSW KF MJ, M MJSW N, NF NR PHP RS SHRINK TCV

A A A A A A

1E-3 1E-14 0 0 0 0.5 0.33 1.0 2.0 PB

W C-1

0 1.0 0

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Name
TLEV TLEVC

Description
Temperature model selector. Valid values: 0, 1, 2 Temperature model selector. Valid values: 0 or 1 VJ temp coefficient (TLEVC=1) PHP temp. coefficient (TLEVC=1) RS temp. coefficient Transit time Built-in potential Shrink factor

Units

Default
0 0 27

TNOM, TREF Parameter measurement temperature TPB TPHP TRS TT VJ, PB XW V/C V/C C S V
-1

0.0 0.0 0.0 0.0 0.8 0.0

The parameters CJSW and JSW are scaled by the instance parameter PJ whose default value is 0.0. If L and W instance parameters are supplied, the diode is scaled by the factor: M*(L*SHRINK-XW)*(W*SHRINK-XW) otherwise it is scaled by M*AREA. M and AREA are instance parameters which default to 1.0

GaAsFET
Netlist Entry

Zxxxx drain gate source modelname [area] [OFF] [IC=vds , vgs]

drain gate source modelname Drain node Gate node Source node Name of model defined in a .model control. Must begin with a letter but can contain any character except whitespace and period '.' . Area multiplying factor. Area scales up the device. E.g. an area of 3 would make the device behave like 3 transistors in parallel. Default is one. Instructs simulator to calculate operating point analysis with device initially off. This is used in latching circuits such as thyristors and bistables to induce a particular state. See .OP on page 194 for more details.

area

OFF

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Chapter 4 Analog Device Reference

vds,vgs Initial conditions for drain-source and gate-source junctions respectively. These only have an effect if the UIC parameter is specified on the .TRAN control.

GaAsFET Model Syntax

.model modelname NMF ( parameters )

GaAsFET Model Parameters The symbols ' ' and ' ' in the Area column means that parameter should be multiplied or divided by the area factor respectively.

Name
VTO BETA B ALPHA LAMBD A RD RS CGS CGD PB IS FC KF AF Notes

Description
Pinch-off Voltage Transconductance parameter Doping tail extending parameter Saturation voltage parameter Channel length modulation parameter Drain ohmic resistance Source ohmic resistance Zero bias gate source capacitance Zero bias gate drain capacitance Gate junction potential Gate p-n saturation current Forward bias depletion capacitance coefficient Flicker noise coefficient Flicker noise exponent

Units
V A/V 1/V 1/V 1/V W W F F V A
2

Default Area
-2.0 2.5e-3 0.3 2 0 0 0 0 0 1 1e-14 0.5

0 1

The GaAsFET model is derived from the model developed by Statz. The DC characteristics are defined by parameters VTO, B and BETA, which determine the variation of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which determines the output conductance. IS determines the gate-source and gate-drain dc characteristics. Two ohmic resistances are included. Charge storage is modelled by total gate charge as a function of gate-drain and gate-source voltages and is defined by the parameters CGS, CGD and PB.

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Inductor (Ideal)
Netlist Entry

Lxxxx n1 n2 value [IC=init_cond] [BRANCH=0|1]

n1 n2 value init_cond BRANCH Node 1 Node 2 Value in henries Initial current in inductor. Only effective if UIC option is specified on .TRAN control. set to 0 or 1. 1 is default value. This parameter determines the internal formulation of the inductor and affects how the IC parameter is implemented. When BRANCH=1, the inductor looks like a short circuit during DC operating point and the IC parameter has no effect unless UIC is specified for a transient analysis. If BRANCH=0, the inductor looks like a current source during dc operating point with a magnitude equal to the value of the IC parameter. BRANCH=0 makes it possible to specify circuit startup conditions.

See Also Mutual Inductance page 103

Inductor (Saturable)
Netlist Entry

Lxxxx n1 n2 modelname [N=num_turns] [LE=le] [AE=ae] [UE=ue]

n1 n2 modelname num_turns le ae ue Node 1 Node 2 Model name referring to a .MODEL control describing the core characteristics. See details below. Number of turns on winding Effective path length of core in metres. Default = PATH/100. PATH is defined in .MODEL. Effective area of core in metres2. Default = AREA/10000 where AREA is define in .MODEL. Effective permeability of core. Overrides model parameter of the same name.

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Model format - Jiles-Atherton model with hysteresis

.MODEL model_name CORE parameters

Model format - simple model without hysteresis

.MODEL model_name CORENH parameters

Jiles-Atherton Parameters

Name
PATH C K MS GAP GAPM A AREA UE

Description
Effective path length Domain flexing parameter Domain anisotropy parameter Magnetisation saturation Air gap (centi-metres) Air gap (metres) Thermal energy parameter Effective area Effective permability. Overrides GAP and GAPM if >0. See notes

Units
cm
-1

Default
1 0.2 500 1E6

amp.m cm m amp.m cm2

0 GAP/100
-

1000 0.1

AHMODE Anhysteric function selector (see notes) Non-hysteresis Model Parameters

Name
PATH MS GAP GAPM A AREA

Description
Effective path length Magnetisation saturation Air gap (centi-metres) Air gap (metres) Thermal energy parameter Effective area

Units
cm cm m amp.mcm2

Default
1 1E6 0 GAP/100 1000 0.1 0

AHMODE Anhysteric function selector (see notes)

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Notes on the Jiles-Atherton model The Jiles-Atherton model is based on the theory developed by D.C. Jiles and D.L.Atherton in their 1986 paper Theory of Ferromagnetic Hysteresis. The model has been modified to correct non-physical behaviour observed at the loop tips whereby the slope of the B-H curve reverses. This leads to non-convergence in the simulator. The modification made is that proposed by Lederer et al. (See refs below). Full details of the SIMetrix implementation of this model including all the equations are provided in a technical note. This is located on the install CD at Docs/Magnetics/Jiles-AthertonModel.pdf. The AHMODE parameter selects the equation used for the anhysteric function, that is the non-linear curve describing the saturating behaviour. When set to 0 the function is the same as that used by PSpice. When set to 1 the function is the original equation proposed by Jiles and Atherton. See the Jiles-Atherton-Model.pdf technical note for details. If the UE parameters is specified either on the device line or in the model, an air gap value is calculated and the parameters GAP and GAPM are ignored. See the JilesAtherton-Model.pdf technical note for the formula used. The parameter names and their default values for the Jiles-Atherton model are compatible with PSpice, but the netlist entry is different. Notes on the non-hysteresis model This is simply a reduced version of the Jiles-Atherton model with the hysteresis effects removed. The anhysteric function and the air-gap model are the same as the JilesAtherton model. Implementing Transformers This model describes only a 2 terminal inductor. A transformer can be created using a combination of controlled sources along with a single inductor. The SIMetrix schematic editor uses this method. The schematic editor provides a means of creating transformers and this uses an arrangement of controlled sources to fabricate a non-inductive transformer. Any inductor can be added to this arrangement to create an inductive transformer. The method is simple and efficient. The following shows how a non-inductive three winding transformer can be created from simple controlled sources:
F1 E1 F2 E2 F3 E3 0 n1 E1 W1A W1B 0 n1 E2 W2A W2B 0 n1 E3 W3A W3B 1 n1 0 1 1 n1 0 1 1 n1 0 1

Connecting an inductor between n1 and 0 in the above provides the inductive behaviour. This is in fact how the SIMetrix schematic editor creates non-linear transformers. Note that you cannot use the mutual inductor device with the saturable inductor.

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Plotting B-H curves Both models can be enabled to output values for flux density in Tesla and magnetising force in A.m-1. To do this, add the following line to the netlist:
.KEEP Lxxx#B Lxxx#H

Replace Lxxx with the reference for the inductor. (e.g. L23 etc). You will find vectors with the names Lxxx#B Lxxx#H available for plotting in the waveform viewer. References 1. 2. Theory of Ferrmagnetic Hysteresis, DC.Jiles, D.L. Atherton, Journal of Magnetism and Magnetic Materials, 1986 p48-60. On the Parameter Identification and Application of the Jiles-Atherthon Hysteresis Model for Numerical Modelling of Measured Characteristics, D Lederer, H Igarashi, A Kost and T Honma, IEEE Transactions on Magnetics, Vol. 35, No. 3, May 1999

Inductor with Current Initial Condition

Netlist entry

Axxxx ind_p ind_n model_name

Model format

.MODEL model_name cm_ind parameters

Model parameters

Name
l ic

Description
Inductance Current initial condition

Type
real real

Default Limits
none 0 1e-18 - none

Description This device is now obsolete. Use standard inductor with BRANCH=0. This is like a standard inductor but the internal implementation is different and permits the specification of a current initial condition which works without having to specify the transient UIC switch. In some circumstances, large value inductors are better implemented using this device than the standard inductor but note that during the DC operating point solution, the device looks like an open circuit, not a short circuit as is the case with the normal SPICE device.

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Note that this type of inductor cannot be coupled using the 'K' device.

Insulated Gate Bipolar Transistor

Netlist Entry

Zxxxx collector gate emitter [AREA=area] [AGD=agd] [KP=kp] [TAU=tau] [WB=wb]

collector gate emitter area agd kp tau wb Collector node Gate node Emitter node Device area in m2 (overrides model parameter of the same name) Gate-drain overlap area in m2 (overrides model parameter of the same name) Transconductance (overrides model parameter of the same name) Ambipolar recombination lifetime (overrides model parameter of the same name) Base width in metres (overrides model parameter of the same name)

Model syntax

.MODEL model_name NIGBT parameters

Name
AGD AREA BVF BVN CGS COXD JSNE KF

Description
Gate-drain overlap area Device active area Breakdown voltage nonplanar junction factor Avalanche multiplication exponent Gate-source capacitance per unit area

Units
m2 m2

Default
5E-6 1E-5 1.0 4.0

Fcm

-2

1.24E-8 3.5E-8 6.5E-13 1.0

Gate-drain overlap oxide capacitance per unit Fcm-2 area Emitter electron saturation current density Triode region MOSFET transconductance factor Acm-2

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Chapter 4 Analog Device Reference

Name
KP MUN MUP NB TAU THETA VT VTD WB Notes

Description
MOSFET transconductance factor Electron mobility Hole mobility Base doping concentration Ambipolar recombination lifetime Transverse field transconductance factor MOSFET channel threshold voltage Gate-drain overlap depletion threshold Metallurgical base width

Units
AV-2

Default
0.38

cm-2(Vs)-1 1.5E3 cm-2(Vs)-1 4.5E2 cm-3 s V V m

-1

2E14 7.1E-6 0.02 4.7 1E-3 9.0E-5

The IGBT model is based on the model developed by Allen R. Hefner at the National Institute of Standards and Technology. The parameter names, default values and units have been chosen to be compatible with the PSpice implementation of the same model. For more information, please refer to: Modelling Buffer Layer IGBTs for Circuit Simulation, Allen R. Hefner Jr, IEEE Transactions on Power Electronics, Vol. 10, No. 2, March 1995 An Experimentally Verified IGBT Model Implemented in the Saber Circuit Simulator, Allen R. Hefner, Jr., Daniel M. Diebolt, IEE Transactions on Power Electronics, Vol. 9, No. 5, September 1994

Junction FET
Netlist Entry

Jxxxx drain gate source modelname [area] [OFF] [IC=vds,vgs] + [TEMP=local_temp]

drain gate source modelname Drain node Gate node Source node Name of model defined in a .model control. Must begin with a letter but can contain any character except whitespace and period '.' . Area multiplying factor. Area scales up the device. E.g. an area of 3 would make the device behave like 3 transistors in parallel.

area

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Default is 1. OFF Instructs simulator to calculate operating point analysis with device initially off. This is used in latching circuits such as thyristors and bistables to induce a particular state. See .OP on page 194 for more details. Initial conditions for drain-source and gate-source junctions respectively. These only have an effect if the UIC parameter is specified on the .TRAN control (page 213). Local temperature. Overrides specification in .OPTIONS (page 195) or .TEMP (page 211) controls.

vds,vgs

local_temp

N Channel JFET: Model Syntax

.model modelname NJF ( parameters )

P Channel JFET: Model Syntax

.model modelname PJF ( parameters )

JFET: Model Parameters The symbols ' ' and ' ' in the Area column means that parameter should be multiplied or divided by the area factor respectively.

Name
VTO VTOTC BETA

Description
Threshold voltage VTO temp coefficient Transconductance parameter

Units
V V/C A/V % 1/V
2

Default Area
-2.0 0 1e-4 0 0 0

BETATC BETA temperature coefficient E LAMDA ALPHA VK RS CGS CGD M PB IS N Channel length modulation parameter Impact ionisation coefficient Impact ionisation knee voltage Source ohmic resistance Zero-bias G-S junction capacitance Zero-bias G-D junction capacitance Grading coefficient Gate junction potential Gate junction saturation current Gate junction emission coefficient

V W F F V A

0 0 0 0 1.0 1 1e-14 1

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Name
ISR NR XTI KF AF FC TNOM

Description
Recombination current ISR emission coefficient IS temperature coefficient Flicker noise coefficient Flicker noise exponent Coefficient for forward bias depletion capacitance Parameter measurement temperature

Units

Default Area
0 3 0 1 0.5

27

Examples

BF244

U430 Temp=100

Q1

Q2

Q2 is a U430 with a local temperature of 100C.

Lossy Transmission Line

Netlist Entry

Oxxxx p1 n1 p2 n2 modelname [IC=v1,i1,v2,i2]

p1 n1 p2 n2 modelname Positive input port 1 Negative input port 1 Positive input port 2 Negative input port 2 Name of model defined in a .MODEL control (page 187). Must begin with a letter but can contain any character except whitespace and period '.' . Initial conditions for voltage at port 1, current at port 1, voltage at port 2 and current at port 2 respectively. These only have an effect if the UIC parameter is specified on the .TRAN control (page 213).

v1,i1,v2,i2

Model Syntax

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Model Parameters

Name
R L G C LEN REL ABS

Description
Resistance/unit length Inductance/unit length Capacitance/unit length Length

Units
/unit length Henrys/unit length Farads/unit length

Default
0.0 0.0 0.0 Required 1.0 1.0

Conductance/unit length Siemens(mhos)/unit length 0.0

Relative rate of change of derivative for breakpoint Absolute rate of change of derivative for breakpoint

The parameters REL and ABS control the way the line is simulated rather than its electrical characteristics. More accurate results (at the expense of simulation time) can be obtained by using lower values. Notes The uniform RLC/RC/LC/RG transmission line model (LTRA) models a uniform constant-parameter distributed transmission line. The LC case may also be modelled using the lossless transmission line model. The operation of the lossy transmission line model is based on the convolution of the transmission line's impulse responses with its inputs. The following types of lines have been implemented: RLC RC LC RG Transmission line with series loss only Uniform RC line Lossless line Distributed series resistance and parallel conductance

All other combinations will lead to an error. REL and ABS are model parameters that control the setting of breakpoints. A breakpoint is a point in time when an analysis is unconditionally performed. The more there are the more accurate the result but the longer it will take to arrive. Reducing REL and/or ABS will yield greater precision. Example
T1 RG58_10m

The above could represent a 10 metre length of RG58 cable. The parameters would be described in a .model control e.g.
.model RG58_10m LTRA(R=0.1 C=100p L=250n LEN=10)

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MOSFET
Note Level 1,2,3 and 7 MOSFETs are described in this section. For BSIM3 devices see page 84 and for BSIM4 see page 85. For MOS9, MOS11 and other Philips devices see page 104

Netlist Entry

Mxxxx drain gate source bulk modelname [L=length] [W=width] + [AD=drain_area] [AS=source_area] + [PD=drain_perimeter] [PS=source_perimeter] + [NRD=drain_squares] [NRS=source_squares] + [OFF] [IC=vds,vgs,vbs] [TEMP=local_temp] [M=area]
drain gate source bulk modelname Drain node Gate node Source node Bulk (substrate) node Name of model. Must begin with a letter but can contain any character except whitespace and period '.'

(The following 8 parameters are not supported by the level 7 MOSFET model) length Channel length (metres). width drain_area source_area drain_perimeter source_perimeter drain_squares source_squares OFF Channel width (metres). Drain area (m2). Source area (m2). Drain perimeter (metres). Source perimeter (metres). Equivalent number of squares for drain diffusion. Equivalent number of squares for source diffusion. Instructs simulator to calculate operating point analysis with device initially off. This is used in latching circuits such as thyristors and bistables to induce a particular state. See page 194 for more details. Initial condition voltages for drain-source gate-source and bulk(=substrate)-source respectively. These only have an effect if the UIC parameter is specified on the .TRAN control (page 213). Local temperature. Overrides specification in .OPTIONS (page 195) or .TEMP (page 211) controls. SIMetrix supports four types of MOSFET model specified in the model definition. These are referred to as levels 1, 2, 3 and 7. Levels 1,2, and 3 are the same as the SPICE2 and SPICE3 equivalents. Level 7 is proprietary to

vds, vgs, vbs

local_temp Notes

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SIMetrix. For further information see Level 7 MOSFET parameters below. NMOS Model Syntax

.model modelname NMOS ( level=level_number parameters )

PMOS Model Syntax

.model modelname PMOS ( level=level_number parameters )

MOS Levels 1, 2 and 3: Model Parameters

Name
VTO or VT0 KP

Description
Threshold voltage Transconductance parameter

Units
V A/V2 V V 1/V W W W F F A V F/m F/m /sq.

Default
0.0 2.0e-5 0.0 0.6 0.0 0.0 0.0 0.0 0.0 0.0 1.0e-14 0.8 0.0 0.0 0.0 0.0 0.0

Levels
all all all all all 1&3 all all all all all all all all all all all

GAMMA Bulk threshold parameter PHI LAMBD A RG RD RS CBD CBS IS PB CGSO CGDO CGBO RSH CJ Surface potential Channel length modulation Gate ohmic resistance Drain ohmic resistance Source ohmic resistance B-D junction capacitance B-S junction capacitance Bulk junction sat. current Bulk junction potential Gate-drain overlap capacitance Gate-bulk overlap capacitance Drain and source diffusion resistance

Gate-source overlap capacitance F/m

Zero bias bulk junction bottom F/m2 capacitance/sq-metre of junction area Bulk junction bottom grading coefficient Zero bias bulk junction sidewall capacitance F/m

MJ CJSW

0.5 0.0

all all

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Chapter 4 Analog Device Reference

Name
MJSW JS TOX NSUB NSS NFS TPG

Description
Bulk junction sidewall grading coefficient Bulk junction saturation current/ sq-metre of junction area Oxide thickness Substrate doping Surface state density Fast surface state density Type of gate material: +1 opposite. to substrate -1 same as substrate 0 Al gate Metallurgical junction depth Lateral diffusion Surface mobility Critical field for mobility Critical field exponent in mobility degradation Transverse field coefficient (mobility)

Units

Default

Levels

0.5 - L1 all 0.33 - L2&3 A/m2 metre 1/cm3 1/cm2 1/cm2 0.0 1e-7 0.0 0.0 0.0 all all all all 2,3 all

XJ LD UO UCRIT UEXP UTRA VMAX NEFF FC TNOM KF AF DELTA THETA ETA KAPPA W L

metre metre cm2/Vs V/cm

0.0 0.0 600 0.0 0.0 0.0 0.0 1.0 0.5

2,3 all all 2 2 1,3 2,3 2 all all all all 2,3 3 3 3 1,2,3 1,2,3

Maximum drift velocity of carriers m/s Total channel charge (fixed and mobile) coefficient Forward bias depletion capacitance coefficient Parameter measurement temperature Flicker noise coefficient Flicker noise exponent Width effect on threshold voltage Mobility modulation Static feedback Saturation field factor Width Length metre metre 1/V C

27 0.0 1.0 0.0 0.0 0.0 0.2 DEFW DEFL

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Notes for levels 1, 2 and 3: The three levels 1 to 3 are as follows: LEVEL 1. LEVEL 2 LEVEL 3 Shichman-Hodges model. The simplest and is similar to the JFET model. A complex model which models the device according to an understanding of the device physics. Simpler than level 2. Uses a semi-empirical approach i.e. the device equations are partly based on observed effects rather than the theory governing its operation.

The L and W parameters perform the same function as the L and W parameters on the device line. If omitted altogether they are set to the option values (set with .OPTIONS control - see page 195) DEFL and DEFW respectively. These values in turn default to 100 microns. The above models differ from all other SIMetrix (and SPICE) models in that they contain many geometry relative parameters. The geometry of the device (length, width etc.) is entered on a per component basis and various electrical characteristics are calculated from parameters which are scaled according to those dimensions. This is approach is very much geared towards integrated circuit simulation and is inconvenient for discrete devices. If you are modelling a particular device by hand we recommend you use the level 7 model which is designed for discrete vertical devices. MOS Level 7: Model Parameters

Name
VTO or VT0 KP GAMMA PHI RD RS CBD CBS IS PB CGSO CGBO CJ

Description
Threshold voltage Transconductance parameter Bulk threshold parameter Surface potential Drain ohmic resistance Source ohmic resistance B-D junction capacitance B-S junction capacitance Bulk junction sat. current Bulk junction potential Gate-source overlap capacitance Gate-bulk overlap capacitance Zero bias bulk junction bottom capacitance

Units
V A/V2 V V 1/V W W F F A V F F F

Default
0.0 2.0e-5 0.0 0.6 0.0 0.0 0.0 0.0 0.0 1.0e-14 0.8 0.0 0.0 0.0

LAMBDA Channel length modulation

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Chapter 4 Analog Device Reference

Name
MJ CJSW MJSW FC TNOM KF AF

Description
Bulk junction bottom grading coefficient Zero bias bulk junction sidewall capacitance Bulk junction sidewall grading coefficient Forward bias depletion capacitance coefficient Parameter measurement temperature Flicker noise coefficient Flicker noise exponent

Units

Default
0.5

0.0 0.5 0.5

27 0.0 1.0

CGDMAX Maximum value of gate-drain capacitance CGDMIN Minimum value of gate-drain capacitance XG1CGD cgd max-min crossover gradient XG2CGD cgd max-min crossover gradient VTCGD TC1RD TC2RD cgd max-min crossover threshold voltage First order temperature coefficient of RD Second order temperature coefficient of RD

F F

0.0 0.0 1.0 1.0

V 1/C 1/C2

0.0 0.0 0.0

Notes for level 7 The level 7 MOSFET was developed to model discrete vertical MOS transistors rather than the integrated lateral devices that levels 1 to 3 are aimed at. Level 7 is based on level 1 but has the following important additions and changes: New parameters to model gate-drain capacitance 2 new parameters to model rdson variation with temperature. All parameters are absolute rather than geometry relative. (e.g. capacitance is specified in farads not farads/meter)

All MOSFET models supplied with SIMetrix are level 7 types. Many models supplied by manufacturers are subcircuits made up from a level 1, 2 or 3 device with additional circuitry to correctly model the gate-drain capacitance. While the latter approach can be reasonably accurate it tends to be slow because of its complexity. Gate-drain capacitance equation:
1 Cgd = ( 0. 5 . tan 1 (( VTCGD v ). XG1CGD)).CGDMIN 1 + ( 0. 5 . tan 1 (( VTCGD v ). XG2CGD)).CGDMAX

where v is the gate-drain voltage. This is an empirical formula devised to fit measured characteristics. Despite this it has been found to follow actual measured capacitance to remarkable accuracy.

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To model gate-drain capacitance quickly and to acceptable accuracy set the five Cgd parameters as follows: 1. 2. Set CGDMIN to minimum possible value of Cgd i.e. when device is off and drain voltage at maximum. Set CGDMAX to maximum value of Cgd i.e. when device is on with drain-source voltage low and gate-source voltage high. If this value is not known use twice the value of Cgd for Vgd=0. Set XG2CGD to 0.5, XG1CGD to 0.1 and leave VTCGD at default of 0.

3.

Although the parasitic reverse diode is modelled, it is connected inside the terminal resistances, RD and RS which does not represent real devices very well. Further, parameters such as transit time (TT) which model the reverse recovery characteristics of the parasitic diode are not included. For this reason it is recommended that the reverse diode is modelled as an external component. Models supplied with SIMetrix are subcircuits which include this external diode.

BSIM3 MOSFETs
Notes The BSIM3 model is only available with the Micron versions of SIMetrix. Two versions are supplied namely 3.1 and 3.2. Our implementation of version 3.1 includes all bug fixes applied to the latest version but the device equations and supported parameters are for the original version 3.1. See below to find out how to switch versions. BSIM3 models can be accessed using one of three values for the LEVEL parameter: LEVEL=8 specifies the standard Berkeley BSIM3 model. LEVEL=49 specifies the Star-Hspice implementation using the Hspice junction capacitance model. LEVEL=53 is also a Star-Hspice version but uses the standard Berkeley junction cap model. The following Star-Hspice parameters are supported when using level 49/53: CJGATE, HDIF, LDIF, WMLT, XL, XW, IS, N, NDS, VNDS, PHP, LMLT, CTA, CTP, PTA, PTP, TREF, RD, RS, RDC, RSC, CBD, CBS, FC, TT, LD, WD, EG, GAP1, GAP2, XLREF, XWREF, ACM, CALCACM, TLEV, TLEVC The Star-Hspice noise model is also supported for NLEV=0,1 and 2. The 'M' instance parameter has also been implemented. This specifies the number of equivalent parallel devices. Version Selector The VERSION parameter can be specified to select which version is used. If omitted or 3.2, the latest version will be used. If it is set to 3.1 or 3.0, version 3.1 will be used.

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Further Documentation Original Berkeley documentation is provided on the CDROM in PDF form. Process Binning BSIM3 devices may be binned according to length and width. Refer to Model Binning on page 43 for details.

BSIM4 MOSFETs
Notes The BSIM4 model is only available with the Micron versions of SIMetrix. BSIM4 models are accessed using LEVEL=14. Versions 4.2, 4.3 and 4.4 are currently supported. To set the version to be used, use the VERSION parameter as defined in the following table:

VERSION parameter value BSIM4 version used

4.3, 4.30, 4.3.0 4.4, 4.40, 4.4.0 4.3 4.4

4.0, 4.0.0, 4.1, 4.1.0, 4.10, 4.2, 4.2 4.2.0, 4.20, 4.2.1, 4.21 Omitted Other 4.2 See notes

If the version parameter is set to a value not listed above, SIMetrix will raise an error condition. This can be overridden by setting .OPTION AnyVersion. The implementation is standard Berkeley but with the addition of the 'M' instance parameter which specifies the number of equivalent parallel devices. Further Documentation Original Berkeley documentation is provided on the CDROM in PDF form. Note the document covers version 4.4 of the model. Earlier versions are available from the BSIM3/4 web site at http://www-device.eecs.berkeley.edu/~bsim3. Process Binning BSIM4 devices may be binned according to length and width. Refer to Model Binning on page 43 for details.

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EKV MOSFETs
Notes This is the Enz-Krummenacher-Vittoz MOSFET model version 2.6 and is only available with the Micron versions of SIMetrix. The models are accessed using LEVEL=44. Our version implements the full charge conserving capacitance model but in the absence of benchmark circuits this is not yet fully tested. The DC characteristics have been successfully tested using published test circuits and results.

MOSFET GMIN Implementation

GMIN is a conductance added to all non-linear devices to improve DC convergence. For LEVEL 1-3 and LEVEL 7 MOSFETs, the default GMIN is implemented as shown below:

GMIN

GMIN

This is compatible with SPICE and earlier versions of SIMetrix. For BSIM3, BSIM4 and EKV devices, and also for LEVEL1-3 and LEVEL 7 devices if the NEWGMIN .OPTIONS setting is set, the GMIN implementation is:

OLDMOSGMIN MOSGMIN

OLDMOSGMIN

OLDMOSGMIN is a .OPTIONS setting with the default value of zero. MOSGMIN is also a .OPTIONS setting with the default value of GMIN. Using the above configuration with OLDMOSGMIN =0 often converges faster especially if the Junction GMIN stepping algorithm is used.

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Resistor
Netlist Entry

Rxxxx n1 n2 [model_name] [value] [L=length] [W=width] [ACRES=ac_resistance] [TEMP=local_temp] [TC1=tc1] [TC2=tc2]

n1 n2 model_name value length width ac_resistance Node 1 Node 2 (Optional) Name of model. Must begin with a letter but can contain any character except whitespace and ' . ' Resistance (W) Length of resistive element in metres. Only used if value is omitted. See notes below Width of resistive element in metres. Only used if value is omitted. See notes below Resistance used for AC analyses and for the calculation of thermal noise. If omitted, value defaults to final resistance value. Resistor temperature (C) First order temperature coefficient Second order temperature coefficient

local_temp tc1 tc2 Notes

If model_name is omitted, value must be specified. If model_name is present and value is omitted, length and width must be specified in which case the value of the resistance is RES * RSH * L/W where RSH is the sheet resistance model parameter and RES is the resistance multiplier. See model parameters below. If ACRES is specified and non-zero its value will be used unconditionally for AC analyses and the calculation of thermal noise.

Resistor Model Syntax

.model modelname R ( parameters )

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Resistor Model Parameters

Name
RES TC1 TC2 RSH KF EF Notes

Description
Resistance multiplier First order temperature coefficient Second order temperature coefficient Sheet resistance Flicker noise coefficient Flicker noise exponent

Units
1/C 1/C2 /sq m 2 / 2

Default
1 0 0 0 0 1

The flicker noise parameters are proprietary to SIMetrix. Flicker noise voltage is: Vn2 = KF * RSH2/(L*W) * Vr2 * f/fEF Where: Vr = Voltage across resistor. The equation has been formulated so that KF is constant for a given resistive material. If one of L, W is not specified, the flicker noise voltage becomes: vn2 = KF * R2 * Vr2 * f/fEF Where R is the final resistance. i.e. the noise current is independent of resistance. This doesn't have any particular basis in physical laws and is implemented this way simply for convenience. When resistor dimensions and resistivity are unavailable, the value of KF will need to be extracted for each individual value.

S-domain Transfer Function Block

Netlist entry:

Axxxx input output model_name

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Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Default Allowed type types

v v v, vd, i, id v, vd, i, id

.MODEL model_name s_xfer parameters

Model parameters

Name
in_offset gain laplace

Description
Input offset Gain

Type Default Limits Vector bounds

real real 0 1 none none none n/a n/a n/a

Laplace expression string none (overrides num_coeff and den_coeff) Numerator real none polynomial coefficient vector Denominator real none polynomial coefficient vector Integrator stage initial real 0 conditions vector Frequency (radians/ second) at which to denormalize coefficients real 1

num_coeff den_coeff int_ic

denormalized_freq

none none none none

1- 1- none n/a

Description This device implements an arbitrary linear transfer function expressed in the frequency domain using the 'S' variable. The operation and specification of the device is illustrated with the following examples.

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Example 1 - A single pole filter
1/(s+1) LAP1 LAP1-OUTP

V1 AC 1 0

1K R1

Model for above device:

.model Laplace s_xfer laplace="1/(s+1)" denormalized_freq=1

This is a simple first order roll off with a 1 second time constant as shown below
1

400m

200m

100m

40m

20m

10m

20m

40m

100m

200m

400m

10

Frequency / Hertz

Example 1 Frequency response Example 2 - Single pole and zero

.model Laplace s_xfer + laplace="(1/s)/(1/s + 1/(0.1*s+1))" + denormalized_freq=1

The laplace expression has been entered how it might have been written down without any attempt to simplify it. The above actually simplifies to (0.1*s+1)/(1.1*s+1)

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500m

200m

100m

10m

20m

40m

100m

200m

400m

10

Frequency / Hertz

Example 2 Frequency response Example 3 - Underdamped second order response

.model Laplace s_xfer + laplace="1/(s2+1.1*s+1)" + denormalized_freq=2k

The above expression is a second order response that is slightly underdamped. The following graph shows the transient response.

0.8

0.6

0.4

0.2

0 0 Time/mSecs

10 2mSecs/div

Example 3 Frequency response

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Example 4 - 5th order Chebyshev low-pass filter The S-domain transfer block has a number of built in functions to implement standard filter response. Here is an example. This is a 5th order chebyshev with -3dB at 100Hz and 0.5dB passband ripple.
.model Laplace s_xfer + laplace="chebyshevLP(5,100,0.5)" + denormalized_freq=1

and the response:

1

100m

10m

1m

100

10

11

10

20

40

100

200

400

1k

Frequency / Hertz

Example 3 Frequency response The Laplace Expression As seen in the above examples, the transfer function of the device is defined by the model parameter LAPLACE. This is a text string and must be enclosed in double quotation marks. This may be any arithmetic expression containing the following elements: Operators: +-*/^ ^ means raise to power. Only integral powers may be specified. Constants Any decimal number following normal rules. SPICE style engineering suffixes are accepted. S Variable This can be raised to a power with '^' or by simply placing a constant directly after it (with no spaces). E.g. s^2 is the same as s2. Filter response functions These are:

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BesselLP(order, cut-off)Bessel low-pass BesselHP(order, cut-off)Bessel high-pass ButterworthLP(order, cut-off)Butterworth low-pass ButterworthHP(order, cut-off)Butterworth high-pass ChebyshevLP(order, cut-off, passband_ripple)Chebyshev low-pass ChebyshevHP(order, cut-off, passband_ripple)Chebyshev high-pass Where: order Integer specifying order of filter. There is no maximum limit but in practice orders larger than about 50 tend to give accuracy problems. -3dB Frequency in Hertz Chebyshev only. Passband ripple spec. in dB

cut-off passband_ripple

Other Model Parameters DENORMALISED_FREQ is a frequency scaling factor. INT_IC specifies the initial conditions for the device. This is an array of maximum size equal to the order of the denominator. The right-most value is the zeroth order initial condition. NUM_COEFF and DEN_COEFF are largely redundant but included for compatibility with other XSPICE products. They allow the literal definition of the numerator and denominator coefficients as an array. GAIN and IN_OFFSET are the DC gain and input offset respectively

Limitations SIMetrix expands the expression you enter to create a quotient of two polynomials. If the constant terms of both numerator and denominator are both zero, both are divided by S. That process is repeated until one or both of the polynomials has a non-zero constant term. The result of this process must satisfy the following: The order the denominator must be greater than or equal to that of the numerator. The constant term of the denominator may not be zero.

The XSPICE S_XFER model The SIMetrix Laplace transfer model is compatible with the original XSPICE version but the transient analysis portion of it has been completely rewritten. The original XSPICE version was seriously flawed and would only give accurate results if the timestep was forced to be very small. Further, convergence would fail if the device was used inside a feedback loop. The ability to enter the laplace transform as an arbitrary expression is a SIMetrix enhancement. The original version required the user to enter the coefficients of the numerator and denominator explicitly. The filter response functions are also a SIMetrix enhancement.

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Subcircuit Instance
Netlist Entry

Xxxxx n1 n2 n3 ... subcircuit_name [pinnames: pin1 pin2 pin3 ...] [[params]: expression1 expression2 ....]
n1, n2 etc. pin1, pin2 etc. Subcircuit nodes If the pinnames: keyword is included the names following it will be used to name subcircuit current vectors generated by the simulator. Subcircuit name referred to in subcircuit definition (i.e. with .SUBCKT control page 210) Parameter expressions. See Using Expressions on page 28.

subcircuit_name expression1 etc.

See Subcircuits on page 39 for more information.

Transmission Line
Netlist Entry

Txxxx p1 n1 p2 n2 Z0=impedance [TD=delay] [F=frequency [NL=norm_length]] [rel=rel] [abs=abs]

p1 n1 p2 n2 impedance delay frequency norm_length Positive input port 1 Negative input port 2 Positive input port 1 Negative input port 2 characteristic impedance Line delay (Seconds) Alternative means of specifying delay=norm_length/frequency See frequency. Default 0.25 if omitted.

TD takes precedence over NL/F. Either TD or F must be specified. These remaining parameters control the way the line is simulated rather than its electrical characteristics. More accurate results (at the expense of simulation time) can be obtained by using lower values. rel abs Relative rate of change of derivative for breakpoint Absolute rate of change of derivative for breakpoint

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Example
T1 Z0=50 TD=1u

The above line has an impedance of 50 and a delay of 1S.

Voltage Controlled Current Source

Netlist Entry

Gxxxx nout+ nout- vc+ vc- transconductance

nout+ noutvc+ vctransconductance Positive output node Negative output node Positive control node Negative control node Output current/Input voltage (Siemens or mhos)

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for IC's. (Most operational amplifier models for example use several polynomial sources). In general, however the arbitrary source (see page 46) is more flexible and easier to use. The netlist format for a polynomial source is:

Gxxxx nout+ nout- POLY( num_inputs ) vc1+ vc1- vc2+ vc2- ... + polynomial_specification
vc1+ etc. num_inputs polynomial_specification Controlling nodes Number of controlling node pairs for source. See Polynomial Specification on page 62

Voltage Controlled Switch

Netlist Entry

Sxxxx nout1 nout2 vc+ vc- modelname

nout1 nout2 Switch node 1 Switch node 2

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vc+ vcmodelname Positive control node Negative control node Name of model. Must begin with a letter but can contain any character except whitespace and period '.' .

Voltage Controlled Switch Model Syntax

.model modelname VSWITCH ( parameters )

OR

.model modelname SW ( parameters )

Voltage Controlled Switch Model Parameters

Name

Description

Units

Default

RON ROFF VON VOFF

On resistance Off resistance Voltage at which switch begins to turn on Voltage at which switch begins to turn off

W W V V

1 1/GMIN 1 0

Voltage Controlled Switch Notes The voltage controlled switch is a type of voltage controlled resistor. Between VON and VOFF the resistance varies gradually following a cubic law. GMIN is a simulation parameter which defaults to 10-12 but which can changed using the .OPTION control (page 195). The SIMetrix voltage controlled switch is compatible with PSpice but is incompatible with the standard SPICE 3 version. The latter has an abrupt switching action which can give convergence problems with some circuits.

Voltage Controlled Voltage Source

Netlist Entry

Exxxx nout+ nout- vc+ vc- gain

nout+ noutvc+ vcPositive output node Negative output node Positive control node Negative control node

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gain Output voltage/Input voltage

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for ICs. (Most opamp models for example use several polynomial sources). In general, however the arbitrary source is more flexible and easier to use. The netlist format for a polynomial source is:

Exxxx nout+ nout- POLY( num_inputs ) vc1+ vc1- vc2+ vc2- ... polynomial_specification
vc1+ etc. num_inputs polynomial_specification Controlling nodes Number of controlling node pairs for source. See Polynomial Specification on page 62

Voltage Source
Netlist Entry

Vxxxx n+ n- [[DC] dcvalue] [DCOP] [INFCAP] [AC magnitude [phase]] [transient_spec]

N+ NDCOP Positive node Negative node If this is specified, the voltage source will only be active during the DC operating point solution. In other analyses, it will behave like an open circuit. This is an effective method of creating a hard initial condition. See Alternative Initial Condition Implementations on page 183 for an example. If specified, the voltage source will behave as an infinite capacitor. During the DC operating point solution it will behave like an open circuit. In the subsequent analysis, it will behave like a voltage source with a value equal to the solution found during the operating point. Note that the device is inactive for DC sweeps - as all capacitors are. Value of source for dc operating point analysis AC magnitude for AC sweep analysis. phase for AC sweep analysis Specification for time varying source as described in the following table.

INFCAP

dcvalue magnitude phase transient_spec

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Type
PULSE PWL PWLFILE SIN EXP SFFM NOISE

Description
Pulse source. Also generates, ramps, sawtooths and triangles As PWL but get definition from a file Sine wave Exponential signal Single frequency FM Real time noise source

Page
98

Piece wise linear source. Can create any waveform 99 100 101 102 102 103

Pulse Source
PULSE ( v1 v2 [td [tr [tf [pw [per ]]]]] )
Where:

Name
v1 v2 td tr tf pw per
a. b.

Description
Initial value (V,A) Delay time (S) Rise time (S) Fall time (S) Pulse width (S) Period (S)

Default
Compulsory Default if omitted = 0 Default if omitted, negative or zero = Time stepa Default if omitted, negative or zero = Time step Default if omitted or negative = Stop timeb Default if omitted, negative or zero = Stop time

Pulsed value (V,A) Compulsory

Time step is set up by the .TRAN simulator control which defines a transient analysis. Refer to .TRAN on page 213 Stop time refers to the end time of the transient analysis.

SIMetrix deviates from standard SPICE in the action taken for a pulse width of zero. Standard SPICE treats a zero pulse width as if it had been omitted and changes it to the stop time. In SIMetrix a zero pulse width means just that. Both the above examples give a pulse lasting 5S with a period of 10S, rise and fall times of 100nS and a delay of 0. The voltage source has a 0V base line and a pulse of 5V while the current source has a 0mA base line and a pulse of 1mA.

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t=0

TD

PW

TF

TR PER

Examples

V1 pulse ( 0 5 0 100n 100n 5u 10u )

I1 pulse ( 0 1mA 0 100n 100n 5u 10u )

Piece-Wise Linear Source

PWL ( t1 v1 [t2 v2 [t3 v3 [... ]]] )
Each pair of values (ti vi) specifies that the value of the source is vi at time = ti. The value of the source at intermediate values of time is determined by using linear interpolation on the input values. Although the example given below is for a voltage source, the PWL stimulus may be used for current sources as well. Example

V1 pwl ( 0 -5 10n -5 11n -3 17n -3 18n -7 50n -7 )

Gives:-

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1: :r1_p

-3.5 -4 -4.5 -5 -5.5 -6 -6.5 -70 20 40 60 80 100 V

Time/nSecs

20nSecs/div

PWL File Source

PWLFILE filename
This performs the same function as the normal piece wise linear source except that the values are read from a file named filename. The file contains a list of time voltage pairs in text form separated by any whitespace character (space, tab, new line). It is not necessary to add the '+' continuation character for new lines but they will be ignored if they are included. Any non-numeric data contained in the file will also be ignored. Notes The PWLFILE source is considerably more efficient at reading large PWL definitions than the standard PWL source. Consequently it is recommended that all PWL definitions with more than 200 points are defined in this way. The data output by Show /file is directly compatible with the PWLFILE source making it possible to save the output of one simulation and use it as a stimulus for another. It is recommended, however, that the results are first interpolated to evenly spaced points using the Interp() function. The use of engineering suffixes (e.g. k, m, p etc.) is not supported by PWLFILE. The PWLFILE source is a feature of SIMetrix and does not form part of standard SPICE. Note, you can use the simulator controls .FILE and .ENDF to define the contents of the file. E.g.
Vpwl1 N1 N2 PWLFILE pwlSource ... .FILE pwlSource ... ... .ENDF

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This will be read in much more efficiently than the standard PWL and is recommended for large definitions. See .FILE and .ENDF on page 175 .

Sinusoidal Source
SIN[E] ( vo va [freq [delay [theta [ phase]]]] )
Where:

Name
vo va freq delay theta phase
a.

Description
Offset (V,A) Peak (V,A) Frequency (Hz) Delay (seconds)

Default
Compulsory Compulsory Default if omitted or zero= 1/Stop timea Default if omitted = 0

Damping factor (1/ Default if omitted = 0 seconds) Phase in degrees Default if omitted = 0
Stop time refers to the end time of the transient analysis.

The shape of the waveform is described by: 0 to delay: delay to Stop time Example vo vo + va.e-(t-delay)..theta.sin(2..(freq.(t - delay) + phase/360))

V1 sin ( 0 1 100meg 10nS )

Gives output of:

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1: :r1_p 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -10 Time/nSecs 5 10 15 20 25 5nSecs/div V

Exponential Source
EXP ( v1 v2 [td1 [tau1 [td2 [tau2 ]]]] )
Where:

Name
v1 v2 td1 tau1 td2 tau2
a.

Description
Initial value (V,A) Pulsed value (V,A) Rise delay time Rise time constant Fall delay time Fall time constant

Default
Compulsory Compulsory Default if omitted or zero: 0 Default if omitted or zero: Time stepa Default if omitted or zero: td1 + Time step Default if omitted or zero: Time step

Time step is set up by the .TRAN simulator directive which defines a transient analysis. Refer to .TRAN on page 213

Defined by: td1 to td2: v1 + (v2 - v1). [ 1 - e-(t-td1)/tau1] td2 to stop time: v1 + (v2 - v1). [ 1 - e-(t-td1)/tau1] + v1 + (v2 - v1). [ 1 - e-(t-td2)/tau2]

Single Frequency FM
SFFM ( vo va [fc [mdi [fs ]]] )
Where:

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Name
vo va fc mdi fs
a.

Description
Offset (V,A) Amplitude (V,A) Carrier frequency (Hz) Modulation index Signal frequency (Hz)

Default
Compulsory Compulsory Default if omitted or zero = 1/Stop timea Default if omitted = 0 Default if omitted or zero = 1/Stop time

Stop time refers to the end time of the transient analysis.

Defined by: vo + va.sin[2..fc.t + mdi.sin(2..fs.t)]

Noise Source
noise interval rms_value [start_time [stop_time]]
Source generates a random value at interval with distribution such that spectrum of signal generated is approximately flat up to frequency equal to 1/(2*interval). Amplitude of noise is rms_value volts. start_time and stop_time provide a means of specifying a time window over which the source is enabled. Outside this time window, the source will be zero. If stop_time is omitted or zero a value of infinity will be assumed.

Mutual Inductor
Specifies coupling between two inductors. Netlist Entry

Kxxxx l1 l2 coupling_factor
l1 l2 coupling_factor Component reference of first inductor Component reference of second inductor Coupling factor, K

L1 1mH

L2 1mH

If mutual inductance is M then:

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v L1 = L1 d i L1 dt di L 2 dt +M di L 2 dt d i L1 dt

v L2 = L2

+M

K=

M L1 . L2

K cannot be greater than 1. Notes You can only couple ideal inductors using this method. The saturable inductor devices may not be coupled in this way. See Inductor (Saturable) on page 70 for more information. To use the mutual inductor directly on a schematic you will need to add the device line to the netlist. See Adding Extra Netlist Lines on page 12 for information about how to do this. If you wish to couple more than two inductors, the coupling coefficient (K value) must be specified for every possible combination of two inductors. An error will result if this is not done. For iron cored transformers values of K between 0.99 and 0.999 are typical. For ferrites lower values should be used. If the windings are concentric (i.e. one on top of the other) then 0.98 to 0.99 are reasonable. If the windings are side by side on a sectioned former, K values are lower - perhaps 0.9 to 0.95. The addition of air gaps tends to lower K values. Example A transformer with 25:1 turns ratio and primary inductance of 10mH
** Inductors Lprimary N1 N2 10m Lsecondary N3 N4 16u ** Coupling of 0.99 typical for ungapped ferrite K1 Lprimary Lsecondary 0.99

Philips Compact Models

Introduction
SIMetrix supports a range of device models developed by Philips the most important of which are the MOS9 and MOS11 MOSFETs, the Mextram BJT and the JUNCAP diode which is usually used with MOS9 and MOS11. These models are only available with the Micron versions of SIMetrix. Fully supported modes are:

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MOS 9 MOSFET, version 9.02 and 9.03 MOS 11 MOSFET Mextram BJT version 5.03 and 5.04 Juncap (used with MOS 9 and 11) The following devices are also included but are not fully supported. Contact technical support if you wish to use one of these devices. Level 500 Diode Level 30 and 30.02 MOSFET Level 40 SOI MOSFET Modella lateral BJT These device have been implemented in SIMetrix by developing an interface between the SIMetrix simulator and the original Philips source code which was developed for their own PSTAR simulator. By using this method, we only needed to make small changes to the original Philips code and most of these have been to implement real time noise analysis which is not supported by the Philips interface. The MOS9 and JUNCAP devices have been tested by comparing the simulations of a benchmark design between SIMetrix and PSTAR. Simulations of bias point, DC sweep, AC frequency sweep, transient and noise were carried out. The comparison showed near identical results, in most cases within 0.01%. Other devices were tested using supplied benchmark results

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Using Philips Devices

Description Philips name
MNE_902 MPE_902 MNE_903 MPE_903 MN_902 MP_902 MN_903 MP_903

SPICE model type

nmos, pmos nmos, pmos nmos, pmos nmos, pmos

SPICE Device Number Level letter of terminals

102 103 202 203 500 600 501 601 611 M M M M M M M M M 4 4 4 4 4 4 4 4 4

MOS 9 Electrical, version 9.02 MOS 9 Electrical, version 9.03 MOS 9 Geometric, version 9.02 MOS 9 Geometric, version 9.03 MOS 11 Electrical MOS 11 Geometric MOS 11.01 Electrical

MNE_1100 nmos, MPE_1100 pmos MN_1100 MP_1100 nmos, pmos

MNE_1101 nmos, MPE_1101 pmos

MOS 11.01 Geometric MN_11010 nmos, MP_11010 pmos MOS 11.01 Geometric MN_11011 nmos, binned. Not fully MP_11011 pmos supported - see notes Juncap Mextram 4 term 5.03 Mextram 4 term 5.04 JC_1 TNS_503, TPS_503 TNS_504, TPS_504 d npn, pnp npn, pnp

101 103 104 1104

D Q Q Q

2 4 4 5

Mextram 4 term 5.04, TNST_504 npn, pnp thermal TPST_504 Notes

The geometric binned version of MOS 11.01 id not yet integrated with the library binning system. So, to use the binning features of this model, you will need to manually generate separate model names for each bin. Some other simulator products add junction capacitance parameters to the original Philips model. Star-Hspice level 50 is the most common of these. These parameters need to be modelled with an external device using either a standard SPICE diode or a JUNCAP device. The Philips model uses JUNCAP and the usual procedure is to make up the complete model using a subcircuit of MOS9/11 and JUNCAP devices.

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Currently, 3 terminal Mextram devices are not available, due to the confusion regarding the optional substrate node in SPICE BJTs. MOS9/11 and Real Time Noise Currently the gate thermal noise of the MOS9/11 device is not implemented for realtime noise analysis. In practice the effect of this noise component is usually small and only occurs at high frequencies. To investigate the contribution of this component to overall circuit behaviour, it can be disabled in AC noise analysis by setting the option NoMos9GateNoise.

Examples
The following is an example showing an nmos MOS 9 device
.MODEL M9 + LER + LVAR + WVAR + TR + STVTO + SWVTO + KOR + SWKO + SLK + PHIBR + SLVSBX + BETSQ + THE1R + SLTHE1R + SWTHE1 + STTHE2R + STLTHE2 + THE3R + SLTHE3R + SWTHE3 + SLGAM1 + ETADSR + ETAALP + SWALP + GAMOOR + ETAGAMR + STMO + ETAMR + ETAZET + VSBTR + A1R + SLA1 + A2R + SWA2 + SLA3 + TOX + NTR + W nmos LEVEL = = 0.203E-06, = 0.000E-00, = 0.000E-00, = 21.000E-00, = 0.000E-00, = 5.000E-09, = 0.431E-00, = 3.610E-09, = -93.200E-09, = 0.700E-00, = -2.280E-06, = 0.255E-03, = 0.739E-00, = 0.103E-06, = -63.200E-09, = 0.000E-00, = 0.000E-00, = 0.416E-00, = 85.200E-09, = 12.400E-09, = 20.600E-09, = 0.600E-00, = 0.000E-00, = 0.000E-00, = 33.869E-03, = 1.000E-00, = 0.000E-00, = 1.000E-00, = 0.500E-00, = -0.109E-00, = 28.876E-00, = -1.940E-06, = 21.540E-00, = 0.523E-06, = -0.112E-06, = 5.800E-09, = 21.000E-21, = 10.0e-6 , 202, WER LAP WOT VTOR SLVTO SL2VTO SLKO KR SWK VSBXR SWVSBX ETABET STTHE1R STLTHE1 THE2R SLTHE2R SWTHE2 STTHE3R STLTHE3 GAM1R SWGAM1 ALPR SLALP VPR SLGAMOO MOR SLMO ZET1R SLZET1 SLVSBT STA1 SWA1 SLA2 A3R SWA3 COL NFR L = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 10.056E-06, 23.500E-09, -28.000E-09, 0.500E-00, 35.400E-09, -8.260E-15, -3.230E-09, 0.234E-00, -68.800E-09, -6.232E+00, 0.000E-00, 0.000E-00, 0.000E-00, 0.000E-00, -0.164E-00, -0.064E-06, 3.690E-09, 0.000E-00, 0.000E-00, 90.460E-03, 3.630E-09, 10.000E-03, 0.000E-00, 0.388E-00, 1.370E-15, 0.337E-00, 20.500E-06, 1.419E-00, -0.451E-03, -0.481E-06, 0.000E-00, 12.400E-06, -0.124E-06, 0.441E-00, -16.500E-09, 0.275E-09, 130.450E-12, 0.13e-6

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Documentation
Original Philips documentation on these models can be found in a number of PDF files on the installation CDROM.

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Chapter 5 Digital/Mixed Signal Device Reference

Digital Device Overview
Common Parameters
A number of model parameters are common to most of the digital models. These are described below. Family Parameters These identify the logic family to which the input and outputs belong. Logic families are explained in detail on page 247. Most models have three family parameters:

Family name Description

in_family out_family family Specifies family for inputs. If omitted, the input family is specified by the FAMILY parameter Specifies family for outputs. If omitted, the output family is specified by the FAMILY parameter Default value for IN_FAMILY and OUT_FAMILY

Output Parameters

Parameter name
out_res

Description
This is used to calculate loading delay. It has dimensions of Ohms so is referred to as a resistance. The additional loading delay is calculated by multiplying OUT_RES by the total capacitative load detected on the node to which the output connects. Used to calculate static loading effects. This is the current that the device is able to sink. Current flowing out of the pin is positive so this parameter is usually negative. If the total sink load current is arithmetically smaller (i.e. more negative) than this parameter then the output will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic. Used to calculate static loading effects. This is the current that the device is able to source. Current flowing out of the pin is positive. If the total source load current is larger than this parameter then the output will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic.

min_sink

max_source

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Input Parameters

Parameter name
sink_current

Description
Current that the input sinks. Positive current flows into the device so this parameter is usually negative. The total of all the input sink currents are added together when a node is in the logic '0' state. If the total sink load current is arithmetically smaller (i.e. more negative) than the MIN_SINK parameter of the device driving the node, then it will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic.

source_current Current that the input sources. Positive current flows into the device. The total of all the input source currents are added together when a node is in the logic '1' state. If the total source load current is larger than the MAX_SOURCE parameter of the device driving the node, then it will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic.

Delays
Most digital devices have at least one model parameter that specifies a time delay. Unless otherwise noted, all delays are inertial. This means that glitches shorter than the delay time will be swallowed and not passed on. For example, the following waveforms show the input and output of a gate that has a propagation delay of 10nS. The first pulse is only 5nS so does not appear at the output. The second pulse is 20nS so therefore is present at the output delayed by 10nS.
Input Output 0 Time/nSecs 20 40 60 80 20nSecs/div

The Buffer device has an optional stored delay parameter that makes possible the specification of pure delays.

And Gate
Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

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Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type

Vector bounds

d, vector 2 - d n/a

.MODEL model_name d_and parameters

Model parameters

Name
rise_delay fall_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c min_sink max_source sink_current

Description
Rise delay Fall delay Input load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope Open collector output Minimum sink current Maximum source current Input sink current

Type
real real real string string string real

Default Limits
1nS 1nS 1pF UNIV UNIV UNIV 100 out_res out_res 1e-12 - 1e-12 - none none none none 0- 0- 0- none none none none none

Digital output res. pos. slope real

boolean FALSE real real real real -0.001 0.001 0 0

source_current Input source current Device operation

If the model parameter OPEN_C is false, The output will be at logic '0' if either input is at logic '0'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '1'. If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '0' the output strength will be STRONG. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state.

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D-type Latch
D SET Q EN QN RST

Netlist entry

Axxxx data enable set reset out nout model_name

Connection details

Name
data enable set reset out nout Model format

Description
Input data Enable Asynchronous set Asynchronous reset Data output Inverted data output

Flow
in in in in out out

Type
d d d d d d

.MODEL model_name d_dlatch parameters

Model parameters

Name
data_delay enable_delay set_delay reset_delay ic

Description
Delay from data Delay from enable Delay from set Delay from reset Output initial state 0: logic '0' 1: logic '1 2: UNKNOWN Rise delay Fall delay

Type
real real real real integer

Default Limits
1nS 1nS 1nS 1nS 0 1e-12 - 1e-12 - 1e-12 - 1e-12 - 0-2

rise_delay fall_delay

real real

1nS 1nS

1e-12 - 1e-12 -

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Name
data_load enable_load set_load reset_load family in_family out_family out_res out_res_pos out_res_neg min_sink max_source sink_current

Description
Data load value (F) Enable load value (F) Set load value (F) Reset load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope Minimum sink current Maximum source current Input sink current

Type
real real real real string string string real

Default Limits
1pF 1pF 1pF 1pF UNIV UNIV UNIV 100 out_res out_res -0.001 0.001 0 0 none none none none none none none 0- 0- 0- none none none none

Digital output res. pos. slope real real real real real

source_current Input source current Device Operation

The device is a level triggered latch with a single data input, complimentary outputs and active high asynchronous set and reset. The operation of the device is illustrated in the following diagram:
DATA

ENABLE

OUTPUT 0 Time/Secs 1 2 3 4 5 1Secs/div

data_delay+fall_delay enable_delay+fall_delay data_delay+rise_delay

The asynchronous inputs (set and reset) override the action of the enable and data lines.

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D-type Flip Flop

D SET Q QN RST

Netlist entry

Axxxx data clk set reset out nout model_name

Connection details

Name
data clk set reset out nout Model format

Description
Input data Clock Asynchronous set Asynchronous reset Data output Inverted data output

Flow
in in in in out out

Type
d d d d d d

.MODEL model_name d_dff parameters

Model parameters

Name
clk_delay set_delay reset_delay ic

Description
Delay from clk Delay from set Delay from reset Output initial state 0: logic '0' 1: logic '1 2: UNKNOWN Rise delay Fall delay Data load value (F)

Type
real real real integer

Default Limits
1nS 1nS 1nS 0 1e-12 - 1e-12 - 1e-12 - 0-2

rise_delay fall_delay data_load

real real real

1nS 1nS 1pF

1e-12 - 1e-12 - none

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Name
clk_load set_load reset_load family in_family out_family out_res out_res_pos out_res_neg min_sink max_source sink_current

Description
Clk load value (F) Set load value (F) Reset load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope Minimum sink current Maximum source current Input sink current

Type
real real real string string string real

Default Limits
1pF 1pF 1pF UNIV UNIV UNIV 100 out_res out_res -0.001 0.001 0 0 none none none none none none 0- 0- 0- none none none none

Digital output res. pos. slope real real real real real

source_current Input source current Device Operation

The device is an edge triggered D-type flip flop with active high asynchronous set and reset. The operation of the device is illustrated by the following diagram
CLOCK

RESET 0 Time/Secs 1 2 3 4 5 1Secs/div

clk_delay+fall_delay

reset_delay+fall_delay clk_delay+rise_delay

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Buffer
Netlist entry

Axxxx in out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type
d d

.MODEL model_name d_buffer parameters

Model parameters

Name
rise_delay fall_delay stored_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c min_sink max_source sink_current open_e

Description
Rise delay Fall delay Stored delay (overrides rise_delay and fall_delay) Input load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope Open collector output Minimum sink current Maximum source current Input sink current Open emitter output

Type
real real real real string string string real

Default Limits
1nS 1nS 0 1pF UNIV UNIV UNIV 100 out_res out_res 1e-12 - 1e-12 - 0- none none none none 0- 0- 0- none none none none none none

Digital output res. pos. slope real

boolean FALSE real real real real -0.001 0.001 0 0

source_current Input source current

boolean FALSE

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Device Operation This device is a simple buffer with a single input and output. It can optionally be specified to have an open collector (open_c parameter) or open emitter (open_e parameter) output. Further, if the stored_delay parameter is specified, the device will act as a pure delay. This means that it will pass pulses that are shorter than the delay time whereas normally (delay specified by rise_delay and fall_delay) such pulse would be swallowed. The following table describes the device operation in detail

OPEN_C OPEN_E Input parameter parameter

FALSE FALSE FALSE FALSE FALSE FALSE TRUE TRUE TRUE TRUE TRUE TRUE FALSE FALSE FALSE TRUE TRUE TRUE FALSE FALSE FALSE TRUE TRUE TRUE 0 1 UNKNOWN 0 1 UNKNOWN 0 1 UNKNOWN 0 1 UNKNOWN

Output state
0 1 UNKNOWN 0 1 UNKNOWN 0 0 0 1 0 UNKNOWN

Output strength
STRONG STRONG STRONG HI-IMPEDANCE STRONG UNDETERMINED STRONG HI-IMPEDANCE UNDETERMINED HI-IMPEDANCE HI-IMPEDANCE UNDETERMINED

Note the difference between open emitter and open collector operation. These modes have been designed to be as close to as possible to real devices, in particular their behaviour into an open circuit. An open emitter output, when switching from high to low is likely to follow the voltage on the device's base due to the base-emitter capacitance so the output state follows the input state. An open collector (or open drain) output on the other hand will remain in the low state when its input switches.

Frequency Divider
Freq. Div

Netlist entry

Axxxx freq_in freq_out model_name

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Connection details

Name
freq_in freq_out Model format

Description
Frequency input Frequency output

Flow
in out

Type
d d

.MODEL model_name d_fdiv parameters

Model parameters

Name
div_factor high_cycles i_count rise_delay fall_delay freq_in_load family in_family out_family out_res out_res_pos out_res_neg min_sink max_source sink_current

Description
Divide factor Number of high clock cycles Output initial count value Rise delay Fall delay Freq_in load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope Minimum sink current Maximum source current Input sink current

Type
integer integer integer real real real string string string real

Default Limits
2 1 0 1nS 1nS 1pF UNIV UNIV UNIV 100 out_res out_res -0.001 0.001 0 0 1- 1- 0- 1e-12 - 1e-12 - none none none none 0- 0- 0- none none none none

Digital output res. pos. slope real real real real real

source_current Input source current Device Operation

This device is a positive edge triggered frequency divider. Three model parameters allow arbitrary definition of the divide ratio, output duty cycle, output phase and initial delay. Operation of the frequency divider is illustrated by the following diagram which shows the output of a frequency divider with a DIV_FACTOR of 10 and two alternative values of HIGH_CYCLES.

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Clock

high_cycles=1

high_cycles=4 0 Time/Secs 10 20 30 40 50 10Secs/div

The above was carried out with I_COUNT=0. I_COUNT is the initial value of the internal counter. The output first goes high when it attains a value of 1 or 1+DIVIDE_RATIO so when I_COUNT is zero (the default) the output first goes high after the first rising edge. If I_COUNT is set to 5 the output first goes high after the 6th rising edge and if I_COUNT is -20, the 21st rising edge.

Digital Initial Condition

Netlist entry

Axxxx out model_name

Connection details

Name
out Model format

Description
Output

Flow
out

Type
d

.MODEL model_name d_init parameters

Model parameters

Name
ic is

Description
Initial state Initial strength 1 = STRONG 0 = RESISTIVE Output logic family

Type
integer integer

Default Limits
0 1 none none

out_family

string

UNIV

none

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Device Operation This device has the defined initial state (IC parameter) and initial strength (IS parameter) during the DC operating point solution, then reverts to HI-IMPEDANCE for the remainder of the analysis.

Digital Pulse
Netlist entry

Axxxx out model_name : parameters

Connection details

Name
out

Description
Output

Flow
out

Type
d

Instance parameters

Name
period delay duty width open_out Model format

Description
Pulse period Delay Duty cycle Pulse width Open emitter output

Type
real real real real boolean

.MODEL model_name d_pulse parameters

Model parameters

Name
duty delay period

Description
Duty cycle Initial delay Period If zero, a single pulse will be output

Type
real real real

Default Limits
0.5 0 1 S 1e-06 0.999999 0- 1e-12 -

width

Pulse width (overrides duty if real specified)

period * duty

0-

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Name
open_out out_family out_res out_res_pos out_res_neg min_sink max_source

Description
Open emitter output Output logic family Digital output resistance Digital output res. neg. slope Minimum sink current Maximum source current

Type

Default Limits
none none 0- 0- 0- none none

boolean FALSE string real UNIV 100 out_res out_res real real -0.001 0.001

Digital output res. pos. slope real

Device Operation This device supplies a repetitive or single pulse of defined period, delay and width. Optionally, the device may be specified to have an open emitter output allowing several pulse sources to be wire OR'ed to create complex pulses. All 5 main .MODEL parameters may also be specified on the device line as instance parameters in which case they override any values specified in the .MODEL control. If OPEN_OUT is specified and true, a pull down resistor must be connected to the output.

Digital Signal Source

Netlist entry

Axxxx [ out_0 out_1 .. out_n ] model_name

Connection details

Name
out Model format

Description
Output

Flow
out

Type
d, vector

.MODEL model_name d_source parameters

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Model parameters

Name
input_file out_family out_res out_res_pos out_res_neg min_sink max_source

Description
Digital input vector filename Output logic family Digital output resistance Digital output res. neg. slope Minimum sink current Maximum source current

Type
string string real

Default Limits
none UNIV 100 out_res out_res -0.001 0.001 none none 0- 0- 0- none none

Digital output res. pos. slope real real real

Device Operation The digital signal source provides a multi bit arbitrary digital signal defined in a file. File Format The file is in ASCII format and is in the form of a table each row being on a new line. The first column defines the time values while the entries in the remaining columns define the output value for each of the outputs. So the total number of columns must be the number of outputs plus one. The output values must appear in the same order as the outputs in the netlist entry. So, the values for out_0 will be in column 2, out_1 in column 3 etc. The file may include blank lines and comment lines beginning with a '*'. The output values must specify the state as well as the strength using the following codes:

Code
0S 1S US 0R 1R UR 0Z 1Z

State-Strength
LOW-STRONG HIGH-STRONG UNKNOWN-STRONG LOW-RESISTIVE HIGH-RESISTIVE UNKNOWN-RESISTIVE LOW-HI-Z HIGH-HI-Z

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Code
UZ 0U 1U UU

State-Strength
UNKNOWN-HI-Z LOW-UNDETERMINED HIGH-UNDETERMINED UNKNOWN-UNDETERMINED

Note, these codes are not case sensitive. Example The following file:
* This 0.0 1u 2u 5u 22e-6 50u 60u 70u 80u 90u is an example source file 0s 0s 0r 1s 0s 0s 0r 0z 0s 0s 1r 0z 1s 0s 1r 0z 1s 1s 1r 0z 0s 1s 1r 0z 0s 1s 1r 0z 0s 1s 1r 0z 0s 1s 1r 0z Us Us Ur 0s

and this circuit:

U2 OUT_0 SOURCE OUT_1 OUT_2 OUT_3

4.7k R1 1n C1 V1 2.5

Produces the following waveforms

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OUT_0

OUT_1

OUT_2

OUT_3 0 Time/Secs 20 40 60 80 20Secs/div

An error will result if the file fails in any way to comply with the format. There must be the exact number of entries in each row and the time values must be monotonic. Totally blank lines or lines containing only white space are permitted but any other non-comment line not complying with the format will fail.

Inverter

Netlist entry

Axxxx in out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type
d d

.MODEL model_name d_inverter parameters

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Model parameters

Name
rise_delay fall_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c min_sink max_source sink_current

Description
Rise delay Fall delay Input load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope Open collector output Minimum sink current Maximum source current Input sink current

Type
real real real string string string real

Default Limits
1nS 1nS 1pF HC UNIV UNIV 100 out_res out_res 1e-12 - 1e-12 - none none none none 0- 0- 0- none none none none none

Digital output res. pos. slope real

boolean FALSE real real real real -0.001 0.001 0 0

source_current Input source current Device Operation

If the OPEN_C parameter is not specified or is FALSE, this device simply inverts the state of its input. I.e. if the input is logic '0' the output will be logic '1' and vice-versa. If the input is UNKNOWN the output will also be UNKNOWN. If OPEN_C is TRUE, the output state is always at logic '0' and the input determines its strength. If the input is at logic '1' the output strength is STRONG and if it is at logic '0' the output strength is HI-IMPEDANCE. The output strength will be UNDETERMINED if the input is UNKNOWN.

JK Flip Flop
Netlist entry

Axxxx j k clk set reset out nout model_name

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Connection details

Name
j k clk set reset out nout Model format

Description
J input K input Clock Asynchronous set Asynchronous reset Data output Inverted data output

Flow
in in in in in out out

Type
d d d d d d d

.MODEL model_name d_jkff parameters

Model parameters

Name
clk_delay set_delay reset_delay ic rise_delay fall_delay jk_load clk_load set_load reset_load family in_family out_family out_res out_res_pos out_res_neg

Description
Delay from clk Delay from set Delay from reset Output initial state Rise delay Fall delay J,k load values (F) Clk load value (F) Set load value (F) Reset load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope

Type
real real real integer real real real real real real string string string real

Default Limits
1nS 1nS 1nS 0 1nS 1nS 1pF 1pF 1pF 1pF UNIV UNIV UNIV 100 out_res out_res 1e-12 - 1e-12 - 1e-12 - 0-2 1e-12 - 1e-12 - none none none none none none none 0- 0- 0-

Digital output res. pos. slope real

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Name
min_sink max_source sink_current

Description
Minimum sink current Maximum source current Input sink current

Type
real real real real

Default Limits
-0.001 0.001 0 0 none none none none

source_current Input source current Device Operation

The following circuit and graph illustrate the operation of this device:
Counter_4 U3 D0 D1 D2 D3 U2 U1-CLK U1-K J U1-J U1 JK_FlipFlop Q QN RST U1-QN

SET

U1-Q

U1-CLK

U1-J

U1-K

U1-Q

U1-QN 0 2 4 6 8 10 12 14 16 18 20

Time/Secs

clk_delay+rise_delay clk_delay+fall_delay

2Secs/div

The following table describes the operation of the device when both inputs are at known states: The output can only change on a positive edge of the clock.

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J input
0 0 1 1

K input
0 1 0 1

Output
No change 0 1 toggle

When either input is UNKNOWN, the situation is more complicated. There are some circumstances when a known state can be clocked to the output even if one of the inputs is unknown. The following table describes the operation for all possible input states. X means UNKNOWN.

J input
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 X X X

K input
0 0 0 1 1 1 X X X 0 0 0 1 1 1 X X X 0 0 0

old output
0 1 X 0 1 X 0 1 X 0 1 X 0 1 X 0 1 X 0 1 X

new output
0 1 X 0 0 0 0 X X 1 1 1 1 0 X 1 X X X 1 X

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J input
X X X X X X

K input
1 1 1 X X X

old output
0 1` X 0 1 X

new output
X 0 X X X X

Arbitrary Logic Block

Netlist entry

Axxxx [ in_0 in_1 .. in_n ] [ out_0 out_1 .. out_n ] + model_name : parameters

Connection details

Name
in out

Description
Input Output

Flow
in out

Type
d, vector d, vector

Instance Parameters

Name
trace_file user

Description
Trace file User device params

Type
string real vector

Model format

.MODEL model_name d_logic_block parameters

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Model parameters

Name
file def out_delay reg_delay setup_time hold_time min_clock trace_file user user_scale input_load family in_family out_family out_res out_res_pos out_res_neg sink_current

Description

Type

Default Limits Vector bounds

none none 1n 1n 0 0 0 none none 1p - 0- 0- 0- 0- none none 1 1p UNIV UNIV UNIV 100 out_res out_res none 0- none none none none 0- 0- 0- none none n/a n/a n/a n/a n/a n/a n/a n/a none n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a

Definition file name string Definition Default internal register delay string real Default output delay real

Default level real triggered setup time Default edge triggered hold time Default minimum clock width Trace log file User defined parameters real real string real vector

Scale of user values real Input load value (F) real Logic family Input logic family Output logic family Digital output resistance Digital output res. pos. slope Digital output res. neg. slope Input sink current real string string string real real

0 0

source_current Input source current real Device Operation

See Arbitrary Logic Block - User Defined Models on page 252.

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Nand Gate
Netlist entry

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type

Vector bounds

d, vector 2 - d n/a

.MODEL model_name d_nand parameters

Model parameters

Name
rise_delay fall_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c min_sink max_source sink_current

Description
Rise delay Fall delay Input load value (F) Logic family Input logic family Output logic family Digital output resistance Digital output res. neg. slope Open collector output Minimum sink current Maximum source current Input sink current

Type
real real real string string string real

Default Limits
1nS 1nS 1pF UNIV UNIV UNIV 100 out_res out_res FALSE -0.001 0.001 0 0 1e-12 - 1e-12 - none none none none 0- 0- 0- none none none none none

Digital output res. pos. slope real boolean real real real real

source_current Input source current Device operation

If the model parameter OPEN_C is false, The output will be at logic '1' if either input is at logic '0'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '0'.

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If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '0' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.

Nor Gate
Netlist entry

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type

Vector bounds

d, vector 2 - d n/a

.MODEL model_name d_nor parameters

Model parameters

Name
rise_delay fall_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c

Description
Rise delay Fall delay Input load value (F) Logic family Input logic family Output logic family Digital output resistance

Type
real real real string string string real

Default Limits
1nS 1nS 1pF UNIV UNIV UNIV 100 out_res out_res FALSE 1e-12 - 1e-12 - none none none none 0- 0- 0- none

Digital output res. pos. slope real Digital output res. neg. slope real Open collector output boolean

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Name
min_sink max_source sink_current

Description
Minimum sink current Maximum source current Input sink current

Type
real real real real

Default Limits
-0.001 0.001 0 0 none none none none

source_current Input source current Device operation

If the model parameter OPEN_C is false, The output will be at logic '0' if either input is at logic '1'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '1'. If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '1' the output strength will be STRONG. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state.

Open-Collector Buffer
Netlist entry

Axxxx in out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type
d d

.MODEL model_name d_open_c parameters

Model parameters

Name
open_delay fall_delay input_load

Description
Open delay Fall delay Input load value (F)

Type
real real real

Default Limits
1nS 1nS 1pF 1e-12 - 1e-12 - none

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Device Operation This device is included for compatibility with other XSPICE products. It is recommended that you use the digital buffer device (see page 116) for new designs as this supports the additional common parameters such as static input loads and families. The logic description for the open-collector buffer is described by the following table

Input
0 1 UNKNOWN

Output state
0 1 UNKNOWN

Output strength
STRONG HI-IMPEDANCE UNDETERMINED

Open-Emitter Buffer
Netlist entry

Axxxx in out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type
d d

.MODEL model_name d_open_e parameters

Model parameters

Name
rise_delay open_delay input_load

Description
Rise delay Open delay Input load value (F)

Type
real real real

Default Limits
1nS 1nS 1pF 1e-12 - 1e-12 - none

Device Operation This device is included for compatibility with other XSPICE products. It is recommended that you use the digital buffer device (see page 116) for new designs as this supports the additional common parameters such as static input loads and families.

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The logic description for the open-collector buffer is described by the following table

Input
0 1 UNKNOWN

Output state
0 1 UNKNOWN

Output strength
HI-IMPEDANCE STRONG UNDETERMINED

Or Gate
Netlist entry

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type

Vector bounds

d, vector 2 - d n/a

.MODEL model_name d_or parameters

Model parameters

Name
rise_delay fall_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c

Description
Rise delay Fall delay Input load value (F) Logic family Input logic family Output logic family Digital output resistance

Type
real real real string string string real

Default Limits
1nS 1nS 1pF UNIV UNIV UNIV 100 out_res out_res 1e-12 - 1e-12 - none none none none 0- 0- 0- none

Digital output res. pos. slope real Digital output res. neg. slope real Open collector output

boolean FALSE

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Name
min_sink max_source sink_current

Description
Minimum sink current Maximum source current Input sink current

Type
real real real real

Default Limits
-0.001 0.001 0 0 none none none none

source_current Input source current Device operation

If the model parameter OPEN_C is false, The output will be at logic '1' if either input is at logic '1'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '0'. If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '1' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.

Pulldown Resistor
Netlist entry

Axxxx out model_name

Connection details

Name
out Model format

Description
Output

Flow
out

Type
d

.MODEL model_name d_pulldown parameters

Model parameters

Name
load strong out_family

Description
Load value (F) Strong output Output logic family

Type
real string

Default Limits
0 UNIV none none none

boolean FALSE

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Device Operation This is a single terminal device that can provide either a RESISTIVE or STRONG logic '0'. When resistive it can be used for wire-OR connected open emitter outputs. If STRONG is specified (by the STRONG parameter) its main application is as a digital ground connection.

Pullup Resistor
Netlist entry

Axxxx out model_name

Connection details

Name
out Model format

Description
Output

Flow
out

Type
d

.MODEL model_name d_pullup parameters

Model parameters

Name
load strong out_family

Description
Load value (F) Strong output Output logic family

Type
real string

Default Limits
0 UNIV none none none

boolean FALSE

Device Operation This is a single terminal device that can provide either a RESISTIVE or STRONG logic '1'. When resistive it can be used for wire-AND connected open collector outputs. If STRONG is specified (by the STRONG parameter) its main application is as a digital VCC connection.

Random Access Memory

Netlist entry

Axxxx [ data_in_0 data_in_1 .. data_in_n ] [ data_out_0 data_out_1 .. + data_out_n ] [ address_0 address_1 .. address_n ] write_en + [ select_0 select_1 .. select_n ] model_name 137

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Connection details

Name
data_in data_out address write_en select Model format

Description
Data input line(s) Data output line(s) Address input line(s) Write enable Chip select line(s)

Flow
in out in in in

Type

Vector bounds

d, vector 1 - d, vector 1 - d, vector 1 - d n/a d, vector 1 - 16

.MODEL model_name d_ram parameters

Model parameters

Name
select_value ic read_delay data_load address_load select_load enable_load

Description
Decimal active value for select line comparison Initial bit state @ DC Read delay from address/ select/write_en active Data_in load value (F) Address line load value (F) Select load value (F) Enable line load value (F)

Type
integer integer real real real real real

Default Limits
1 2 1.00E07 1pF 1pF 1pF 1pF 0 - 32767 0-2 1e-12 - none none none none

Device Operation This device is provided for compatibility with other XSPICE products and is not recommended for new designs. In some circumstances, this device can consume large quantities of system (i.e. your PC's) RAM as it uses an inefficient method of storing state history. RAM's can also be implemented using the arbitrary logic block (see page 252) which is much more efficient. An example of a simple 256X8 RAM can be found amongst the supplied example circuits (Examples\ALB_Examples\RAM.sxsch and RAM.ldf).

Set-Reset Flip-Flop
Netlist entry

Axxxx s r clk set reset out nout model_name 138

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Connection details

Name
s r clk set reset out nout Model format

Description
S input R input Clock Asynchronous set Asynchronous reset Data output Inverted data output

Flow
in in in in in out out

Type
d d d d d d d

.MODEL model_name d_srff parameters

Model parameters

Name
clk_delay set_delay reset_delay ic rise_delay fall_delay sr_load clk_load set_load reset_load family in_family out_family out_res out_res_pos out_res_neg open_c

Description
Delay from clk Delay from set Delay from reset Output initial state Rise delay Fall delay S,r load values (F) Clk load value (F) Set load value (F) Reset load value (F) Logic family Input logic family Output logic family Digital output resistance

Type
real real real integer real real real real real real string string string real

Default Limits
1nS 1nS 1nS 0 1nS 1nS 1pF 1pF 1pF 1pF UNIV UNIV UNIV 100 out_res out_res 1e-12 - 1e-12 - 1e-12 - 0-2 1e-12 - 1e-12 - none none none none none none none 0- 0- 0- none

Digital output res. pos. slope real Digital output res. neg. slope real Open collector output

boolean FALSE

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Name
min_sink max_source sink_current

Description
Minimum sink current Maximum source current Input sink current

Type
real real real real

Default Limits
-0.001 0.001 0 0 none none none none

source_current Input source current Device Operation

The SR flip flop is similar to a JK flip flop except that the output is UNKNOWN when both S and R inputs are high. In a JK the output toggles in the same circumstances. The following table describes the operation of the device when both inputs are at known states: The output can only change on a positive edge on the clock.

S input
0 0 1 1

R input
0 1 0 1

Output
No change 0 1 UNKNOWN

When either input is UNKNOWN, the situation is more complicated. There are some circumstances when a known state can be clocked to the output even if one of the inputs is unknown. The following table describes the operation for possible input states. X means UNKNOWN.

S input
0 0 0 0 0 0 0 0 0 1

R input
0 0 0 1 1 1 X X X 0

old output
0 1 X 0 1 X 0 1 X 0

new output
0 1 X 0 0 0 0 X X 1

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S input
1 1 1 1 1 1 1 1 X X X X X X X X X

R input
0 0 1 1 1 X X X 0 0 0 1 1 1 X X X

old output
1 X 0 1 X 0 1 X 0 1 X 0 1` X 0 1 X

new output
1 1 X X X X X X X 1 X X X X X X X

SR Latch
Netlist entry

Axxxx s r enable set reset out nout model_name

Connection details

Name
s r enable set reset out nout

Description
S input R input Enable Asynchronous set Asynchronous reset Data output Inverted data output

Flow
in in in in in out out

Type
d d d d d d d

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Model format

.MODEL model_name d_srlatch parameters

Model parameters

Name
sr_delay enable_delay set_delay reset_delay ic rise_delay fall_delay sr_load enable_load set_load reset_load family in_family out_family out_res out_res_pos out_res_neg min_sink max_source sink_current

Description
Delay from s or r input change Delay from clk Delay from set Delay from reset Output initial state Rise delay Fall delay S & r load values (F) Clk load value (F) Set load value (F) Reset load value (F) Logic family Input logic family Output logic family Digital output resistance

Type
real real real real integer real real real real real real string string string real

Default Limits
1nS 1nS 1nS 1nS 0 1nS 1nS 1pF 1pF 1pF 1pF UNIV UNIV UNIV 100 out_res out_res -0.001 0.001 0 0 1e-12 1e-12 - 1e-12 - 1e-12 - 0-2 1e-12 - 1e-12 - none none none none none none none 0- 0- 0- none none none none

Digital output res. pos. slope real Digital output res. neg. slope real Minimum sink current Maximum source current Input sink current real real real real

source_current Input source current Device Operation

This device is identical to the SR flip flop except that it is level not edge triggered. That is the output may change whenever the enable input is high.

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State Machine
Netlist entry

Axxxx [ in_0 in_1 .. in_n ] clk reset [ out_0 out_1 .. out_n ] model_name
Connection details

Name
in clk reset out

Description
Input Clock Reset Output

Flow
in in in out

Type

Vector bounds

d, vector none d d n/a n/a

d, vector 1 - no upper bound

Model format

.MODEL model_name d_state parameters

Model parameters

Name
clk_delay reset_delay state_file reset_state input_load clk_load reset_load family in_family out_family

Description
Delay from CLK Delay from reset State transition specification file name

Type
real real string

Default Limits
1nS 1nS none 0 1pF 1pF 1pF UNIV UNIV UNIV none none none none none none none none none none

Default state on RESET & at integer DC Input loading capacitance (F) real Clock loading capacitance (F) Reset loading capacitance (F) Logic family Input logic family Output logic family real real string string string

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Notes Currently this model is unsupported as it has not undergone testing or analysis. It is part of the original XSPICE system and should be compatible with other implementations but this cannot be guaranteed. The following is an example of a state transition specification file
* This is a simple example of a state machine state file * It is a 2 bit up down counter with synchronous reset *Present *State 0 Outputs for state 0S 0S Inputs (reset, up/down) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 State destination -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> 3 1 0 0 0 2 0 0 1 3 0 0 2 0 0 0

0S

1S

1S

0S

1S

1S

See Examples\Digital_Devices\state_updown.sxsch

Toggle Flip Flop

Netlist entry

Axxxx t clk set reset out nout model_name

Connection details

Name
t clk set reset out nout

Description
Toggle input Clock Asynchronous set Asynchronous reset Data output Inverted data output

Flow
in in in in out out

Type
d d d d d d

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Model format

.MODEL model_name d_tff parameters

Model parameters

Name
clk_delay set_delay reset_delay ic rise_delay fall_delay t_load clk_load set_load reset_load family in_family out_family out_res out_res_pos out_res_neg min_sink max_source sink_current

Description
Delay from clk Delay from set Delay from reset Output initial state Rise delay Fall delay Toggle load value (F) Clk load value (F) Set load value (F) Reset load value (F) Logic family Input logic family Output logic family Digital output resistance

Type
real real real integer real real real real real real string string string real

Default Limits
1nS 1nS 1nS 0 1nS 1nS 1pF 1pF 1pF 1pF UNIV UNIV UNIV 100 out_res out_res -0.001 0.001 0 0 1e-12 - 1e-12 - 1e-12 - 0-2 1e-12 - 1e-12 - none none none none none none none 0- 0- 0- none none none none

Digital output res. pos. slope real Digital output res. neg. slope real Minimum sink current Maximum source current Input sink current real real real real

source_current Input source current Device Operation

The operation of the toggle flip flop is illustrated by the following diagrams. When the T input is high, the output toggles on each rising edge of the clock. If the T input is UNKNOWN the output will be UNKNOWN.

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U3

U1-T

U2 U1-CK

SET

Toggle U1 U1-QP

RST

U1-CK

U1-QP

U1-T 0 Time/Secs 2 4 6 8 10 12 14 2Secs/div

clk_delay+fall_delay

Tri-State Buffer

Netlist entry

Axxxx in enable out model_name

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Connection details

Name
in enable out Model format

Description
Input Enable Output

Flow
in in out

Type
d d d

.MODEL model_name d_tristate parameters

Model parameters

Name
delay input_load enable_load family in_family out_family out_res out_res_pos out_res_neg min_sink max_source sink_current

Description
Delay Input load value (F) Enable load value (F) Logic family Input logic family Output logic family Digital output resistance

Type
real real real string string string real

Default Limits
1nS 1pF 1pF UNIV UNIV UNIV 100 out_res out_res -0.001 0.001 0 0 1e-12 - none none none none none 0- 0- 0- none none none none

Digital output res. pos. slope real Digital output res. neg. slope real Minimum sink current Maximum source current Input sink current real real real real

source_current Input source current Device Operation

This is a three terminal buffer device. The output state is equal to the input state and the output strength is determined by the enable input as follows:

Enable
0 1 UNKNOWN

Output Strength
HI-IMPEDANCE STRONG UNDETERMINED

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Exclusive NOR Gate

Netlist entry

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type

Vector bounds

d, vector 2 - d n/a

.MODEL model_name d_xnor parameters

Model parameters

Name
rise_delay fall_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c min_sink max_source sink_current

Description
Rise delay Fall delay Input load value (pF) Logic family Input logic family Output logic family Digital output resistance

Type
real real real string string string real

Default Limits
1nS 1nS 1 UNIV UNIV UNIV 100 out_res out_res -0.001 0.001 0 0 1e-12 - 1e-12 - 0- none none none 0- 0- 0- none none none none none

Digital output res. pos. slope real Digital output res. neg. slope real Open collector output Minimum sink current Maximum source current Input sink current real real real real

boolean FALSE

source_current Input source current Device Operation

If the OPEN_C parameter is FALSE, the output is at logic '1' if an even number of inputs are at logic '1'. If any input is UNKNOWN the output will be UNKNOWN, otherwise the output will be at logic '0'.

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If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If n even number of inputs are at logic '1' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. If any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.

Exclusive OR Gate
Netlist entry

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in out

Type

Vector bounds

d, vector 2 - d n/a

.MODEL model_name d_xor parameters

Model parameters

Name
rise_delay fall_delay input_load family in_family out_family out_res out_res_pos out_res_neg open_c

Description
Rise delay Fall delay Input load value (F) Logic family Input logic family Output logic family Digital output resistance

Type
real real real string string string real

Default Limits
1nS 1nS 1pF UNIV UNIV UNIV 100 out_res out_res 1e-12 - 1e-12 - none none none none 0- 0- 0- none

Digital output res. pos. slope real Digital output res. neg. slope real Open collector output

boolean FALSE

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Name
min_sink max_source sink_current

Description
Minimum sink current Maximum source current Input sink current

Type
real real real real

Default Limits
-0.001 0.001 0 0 none none none none

source_current Input source current Device Operation

If the OPEN_C parameter is FALSE, the output is at logic '1' if an odd number of inputs are at logic '1'. If any input is UNKNOWN the output will be UNKNOWN, otherwise the output will be at logic '0'. If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If an odd number of inputs are at logic '1' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. If any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.

Analog-Digital Converter
Netlist entry

Axxxx analog_in clock_in [ data_out_0 data_out_1 .. data_out_n ] + data_valid model_name

Connection details

Name
analog_in clock_in data_out data_valid Model format

Description
Analog input Clock input Data output Data valid output

Flow
in in out out

Type
v d d

Allowed Vector types bounds

v, vd, i, id n/a d d n/a 1 - 32 n/a

d, vector d

.MODEL model_name ad_converter parameters

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Model parameters

Name
input_offset input_range

Description
Offset voltage

Type
real

Default Limits
0 1 none none none

Input full scale signal range real

twos_complement Use 2's complement output. (default - offset binary) convert_time min_clock data_valid_delay in_family out_family family input_load out_res out_res_pos out_res_neg min_sink max_source sink_current source_current Device Operation Total conversion time Minimum clock period Data valid inactive time Input logic family Output logic family Logic family Input load Digital output resistance Digital output res. pos. slope Digital output res. neg. slope Minimum sink current Maximum source current Input sink current Input source current

boolean FALSE

real real real string string string real real real real real real real real

1 S 500n 100n UNIV UNIV UNIV 1pF 100 out_res out_res -0.001 0.001 0 0

0- 0- 0- none none none 0- 0- 0- 0- none none none none

This is a 1-32 bit analog to digital converter. The operation of this device is illustrated by the following diagrams:

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U1-In

ADC_4 U1 In D0 D1 D2 D3

U2 U1-Clock V1 Pulse(-2.5 2.5 0 160u 160u)

U1-D0 U1-D1 U1-D2 U1-D3 U1-Data_Valid

Data_Valid

convert_time
U1-Clock

U1-D0

U1-D1

U1-D2

U1-D3

U1-Data_Valid

2 1 Analog in / V 0 -1 -2 0 20 40 60 80 100 120 140 160

Time/Secs

20Secs/div

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convert_time data_valid_delay
U1-Clock

U1-Data_Valid

U1-D0 19 Time/Secs 20 21 22 23 24 1Secs/div

Conversion timings. The ADC starts the conversion at the rising edge of the clock. The analog input signal is also sampled at this point. The output data changes in response to this, CONVERT_TIME seconds later. At the same time the data_valid output goes low (inactive) then high again after a delay equal to DATA_VALID_DELAY. It is possible to start a new conversion before the previous conversion is complete provided it is started later than MIN_CLOCK seconds after the previous conversion was started. MIN_CLOCK must always be less than CONVERT_TIME. If the MIN_CLOCK specification is violated, the conversion will not start.

Analog-Digital Interface Bridge

Netlist entry

Axxxx in out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
inout out

Type
g d

.MODEL model_name adc_bridge parameters

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Model parameters

Name
in_low in_high rise_delay fall_delay time_tol out_low out_high clamp_low

Description
Maximum 0-valued analog input Minimum 1-valued analog input Rise delay Fall delay Threshold time tolerance Used to calculate reflected static load. See text Used to calculate reflected static load. See text Clamp threshold 'ZERO' digital input. Default to out_low

Type
real real real real real real real real

Default Limits
0.1 0.9 1nS 1nS 100pS 0 5 out_low none none 1e-12 - 1e-12 - 1e-12 - none none none

clamp_high clamp_res clamp_bias out_family

Clamp threshold 'ONE' digital real input. Default to out_high Clamp minimum resistance Clamp voltage Output logic family real real string

out_high none 1 0.8 UNIV 1e-06 - 0.2 - 2 none

Device Operation The analog-digital interface bridge is the main device used to connect analog signals to digital inputs. The device produces a digital signal that is in the logic '1' state when the analog input is above the high threshold (IN_HIGH) and a logic '0' state when it is below the low threshold (IN_LOW). When the analog input is in between these two states the output will be in the UNKNOWN state. The changes in state will be delayed according to the RISE_DELAY and FALL_DELAY parameters. Analog input load The analog input presents a load to its driving circuit according to the digital load that is being driven. In other words the digital load is reflected to the analog input. Both static (i.e. DC) and dynamic (i.e. capacitance) elements of the load are reflected. To accurately reflect the sink and source currents, the interface bridge needs to know the voltage levels of the device it is driving. The digital device will (usually) have a SINK_CURRENT and a SOURCE_CURRENT model parameter each of which apply at defined logic voltage levels. These levels must be specified in the OUT_LOW and OUT_HIGH parameters of the AD interface bridge model. The input is modelled by a current source in parallel with a resistor. The values of these components are calculated from the above mentioned parameters and the digital load.

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Input clamp The analog input is clamped at the voltages specified by CLAMP_LOW and CLAMP_HIGH. The clamping device has a characteristic similar but not identical to a junction diode in series with a resistance. Basically it has the characteristic of a diode up to a voltage excess of CLAMP_BIAS after which it becomes resistive with a dynamic resistance of CLAMP_RES. The diode characteristics are calculated so that the transition between the two regions is smooth. Time Step Control - TIME_TOL parameter Consider the following circuit and waveform
HC00 U1-IN2 U1-OUT

V1 Pulse(0 5 0 5u 5u 50u 100u)

U1

U1-OUT

5 4 3 2 1 0

30 Time/Secs

35

40

45

50

55

60

65

70 5Secs/div

The graph shows the input and output of the NAND gate. Because the input is analog an implicit AD interface bridge will have been connected by the simulator. In the above example the parameters for this bridge have been set to:
.model HC_adc adc_bridge + in_low=2.1 + in_high=2.2 + rise_delay=1e-12 + fall_delay=1e-12

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+ + + + + + out_family = "HC" out_low = 0 out_high = 5 clamp_bias=0.5 clamp_res=10 time_tol=10u

The last parameter, TIME_TOL has been deliberately set ridiculously high to demonstrate what happens without time step control on the input. The input thresholds of the HC gate are 2.1 and 2.2 volts yet the output in the above example doesn't switch until the input has reached 0V. Because there is little activity in the analog circuit, the time steps are quite large. In fact in the above example the transient timepoints are at 55uS, 55.04uS, 56.2uS, 57.8uS and 60uS. The timepoint at 57.8u is just before the 2.2 volt threshold is reached and it isn't until the next time point, 2.2uS later that the lower threshold is broken. The result is the location of the negative edge at the output is delayed by approx. 2.2uS from where it should be. The problem is that the analog system knows nothing of what is happening in the digital domain so carries on with large timesteps oblivious to the errors in the digital system. To overcome this problem. SIMetrix features a mechanism (not in the original XSPICE system) that detects that the threshold has been passed and cuts back the time step to ensure that the digital edge occurs at an accurate point. The accuracy of this mechanism is controlled by the TIME_TOL parameter. The smaller this parameter, the more accurately the exact threshold will be hit at the expense of short time steps and longer simulation runs. TIME_TOL defaults to 100pS and in most applications this is a good choice. The following shows the result when TIME_TOL is set to the default.

U1-OUT

5 4 3 2 1 0

50 Time/Secs

52

54

56

58

60

62 2Secs/div

Here you can see the edge at the correct time. The effect of not correctly simulating the threshold point has serious consequences when attempting to simulate relaxation oscillators constructed with digital inverters as the following graphs illustrate:

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8 6 4 2 0 -2

8 6 4 2 0 -2 0 Time/mSecs 0.2 0.4 0.6 0.8 1 200Secs/div

The top trace is without threshold control and the bottom trace is with it.

Digital-Analog Converter
Netlist entry

Axxxx [ digital_in_0 digital_in_1 .. digital_in_n ] + analog_out model_name

Connection details

Name
digital_in analog_out Model format

Description
Data output Analog output

Flow
in out

Type
d v

Allowed Vector types bounds

d 1 - 32

v, vd, i, id n/a

.MODEL model_name da_converter parameters

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Model parameters

Name
output_offset output_range

Description
Offset voltage Input signal range

Type
real real

Default Limits
0 1 none none none 1e-12 - none 0- none none

twos_complement Use 2's complement input. boolean FALSE (Default is offset binary) output_slew_time in_family input_load sink_current source_current Device Operation Output slew time Input logic family Input load Input sink current Input source current real string real real real 10nS UNIV 1pF 0 0

This device is a 1-32 bit digital to analog converter. Its operation is illustrated by the following diagrams.
U3 Counter_4 U2 D0 D1 D2 D3 U2-D0 U2-D1 U2-D2 U2-D3 DAC_4 U4 D0 D1 D2 D3 OUT U1-OUT

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U2-D0

U2-D1

U2-D2

U2-D3

2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 Time/Secs 10 20 30 40 50 10Secs/div

DAC waveforms
U2-D0

U2-D1

U2-D2

U2-D3

400

200

-200

-400 7.985 7.99 7.995 8 8.005 8.01 8.015 8.02 8.025 5nSecs/div

Time/Secs

output_slew_time

DAC waveforms expanded to show output slew

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The device illustrated above has the following model definition:
.model DAC_4 da_converter + output_slew_time 1e-08 + output_range 5 + output_offset 0

In offset binary mode the D-A converter produce an output voltage equal to: -OUTPUT_RANGE/2 + OUTPUT_OFFSET + code * OUTPUT_RANGE/2n where n is the number of bits and code is the digital input code represented as an unsigned number between 0 and 2n-1. In 2's complement mode the output is: OUTPUT_OFFSET + code * OUTPUT_RANGE/2n where n is the number of bits and code is the digital input code represented as a signed number between -2n/2 and 2n/2-1. Whenever the input code changes, the output is set on a trajectory to reach the target value in the time specified by OUTPUT_SLEW_TIME. UNKNOWN states are ignored. That is the input will be assumed to be at the most recent known state.

Digital-Analog Interface Bridge

Netlist entry

Axxxx in out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
in inout

Type
d g

.MODEL model_name dac_bridge parameters

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Model parameters

Name
out_low out_high g_resistive g_pullup g_pulldown g_hiz input_load t_rise t_fall knee_high knee_low sink_current v_smooth in_family

Description
Analog output for 'ZERO' digital input Analog output for 'ONE' digital input Output conductance for 'RESISTIVE' digital input Output conductance for 'STRONG' digital high input Output conductance for 'STRONG' digital low input Output conductance for 'HI_IMPEDANCE' strength Capacitive input load (F) Rise time 0 -> 1 Fall time 1 -> 0 Knee voltage logic low Input sink current Smoothing function offset voltage Input logic family

Type
real real real real real real real real real real real real real string

Default Limits
0 5 0.001 0.01 0.01 1.00E09 1pF 1nS 1nS 3 2 0 0 0 UNIV none none none none none none none 1e-12 - 1e-12 - none none none none 0- none

Knee voltage logic high state real

source_current Input source current

DC characteristics This digital to analog interface bridge is the main device used to connect digital signals to analog devices. The output provides an analog voltage and source resistance according to the state and strength of the driving digital input. The output has a nonlinear characteristic that is a simplified model of a typical digital output stage. The following graphs show the output characteristics for the supplied high speed CMOS DA bridge. This has the following model parameters:
.model HC_dac dac_bridge + out_high=5 ; Logic high voltage + input_load=-31p ; Compensates for added rise and fall time + t_rise=2n ; Output rise time + t_fall=2n ; Output fall time + g_pullup=0.024 ; 1/(logic high output resistance) + g_pulldown=0.034 ; 1/(logic low output resistance) + g_hiz=1e-9 ; 1/(high impedance output res) + knee_low = 2.0 ; voltage at resistive/constant current

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+ + knee_high =2.75 + + v_smooth = 0.5 + in_family="HC" ; knee logic low ; voltage at resistive/constant current ; knee logic high ; Knee smoothing band

knee_low

60

Slope = g_pulldown
50
Output Current/mA 40

30

20

10

0 0 v1/V

0.5

1.5

2.5

3.5

4.5

500mV/div

Knee smoothing band

Logic '0' state - strength = STRONG In the above graph, the slope of the curve at V=0 is determined by the G_PULLDOWN parameter. The knee smoothing band is a transitional area where the output switches from a constant resistance to a constant current. The smoothing characteristic is a quadratic and is calculated to be smooth at all points. This is required for good convergence behaviour. The knee smoothing band starts at KNEE_LOWV_SMOOTH and finishes at KNEE_LOW+V_SMOOTH.

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-10

Slope = g_pullup

-20 Output Current/mA -30

-40

-50 0 v1/V 1 2 3 4 5 1V/div

knee_high

Logic '1' state - strength = STRONG If a state with RESISTIVE strength is applied to the input of a digital to analog interface bridge, the output has the characteristic of a pure resistor connected to the voltage associated with the input's state. In the example given above, this would be a 1k resistor connected to 0V for the logic '0' state and a 1k resistor connected to +5V for the logic '1' state. (1k is 1/G_RESISTIVE) For the HI-IMPEDANCE strength, the output will look like a resistor of value 1/ G_HIZ connected to a voltage half way between the two analog output states. (1G connected to 2.5V in the above example.) When the input state is UNKNOWN the output will be as if it were half way between the two known states. This is a compromise solution. The UNKNOWN state does not have a parallel in the analog domain so instead it is treated as a transitional state. In some cases the UNKNOWN state occurs in transitional cases although this is not the correct meaning of UNKNOWN. Switching Characteristics When the logic state at the input changes, the output will transition from the current state to the target state in a time determined by T_RISE or T_FALL according to the direction of the state change.

Controlled Digital Oscillator

Netlist entry

Axxxx cntl_in out model_name : parameters

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Connection details

Name
cntl_in out

Description
Control input Output

Flow
in out

Type
v d

Allowed types
v, vd, i, id d

Instance Parameters

Name
init_phase Model format

Description
Initial phase

Type
real

.MODEL model_name d_osc parameters

Model parameters

Name
cntl_array freq_array duty_cycle init_phase rise_delay fall_delay phase_tol out_family out_res

Description
Control array Frequency array Output duty cycle Initial phase of output Rise delay Fall delay Phase tolerance/ degrees Output logic family Digital output resistance

Type

Default Limits
none 0-

Vector bounds
2- 2-

real vector N/A real vector N/A real real real real real string real real real 0.5 0 1n 1n 10 UNIV 100 out_res out_res

1 n/a 0.999999 -180 +360 0- 0- 0 - 45 none 0- 0- 0- n/a n/a n/a n/a n/a n/a n/a n/a

out_res_pos Digital output res. pos. slope out_res_neg Digital output res. neg. slope

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Device Operation This device produces an output frequency controlled by an analog input signal following an arbitrary piece-wise linear law. The input to output frequency characteristic is defined by two parameters CNTL_ARRAY and FREQ_ARRAY. The following is an example of a .MODEL control:
.model vco d_osc + cntl_array=[-1,0,1,2,3,4,5] + freq_array=[0,10000,40000,90000,160000,250000,360000]

The frequency characteristic described by the above example follows a square law. The two arrays CNTL_ARRAY and FREQ_ARRAY must be the same length. These define the frequency output for a given analog input. Time Step Control In order to control the accuracy of the phase of the output signal, this model may cut back the analog time step. At each analog time point, the required frequency is calculated and the digital output is set at that frequency. If the analog input changes by too large an amount between time points, the digital output phase could be substantially in error as the frequency is constant between analog time points. The actual error is calculated and if this exceeds PHASE_TOL, the time point is rejected and a time point at which the error will be in tolerance is estimated. Note: This model was included with the original XSPICE code but the SIMetrix version has been completely re-written. The original did not have any phase error control and could not give accurate results unless the analog time step was artificially kept small.

Analog-Digital Schmitt Trigger

Netlist entry

Axxxx in out model_name

Connection details

Name
in out Model format

Description
Input Output

Flow
inout out

Type
g d

Allowed types
g, gd d

.MODEL model_name adc_schmitt parameters

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Model parameters

Name
in_low in_high rise_delay fall_delay time_tol out_low out_high clamp_res clamp_bias out_family init_cond

Description
Maximum 0-valued analog input Minimum 1-valued analog input Rise delay Fall delay Threshold time tolerance Analog out for 'ZERO' input Analog output 'ONE' input Clamp minimum resistance Clamp voltage Output logic family Initial condition

Type
real real real real real real real real real string real

Default Limits
0.1 0.9 1nS 1nS 100pS 0 5 1 0.8 UNIV 0 none none 1e-12 - 1e-12 - 1e-12 - none none 1e-06 - 0.2 - 2 none none

Device Operation This device is basically identical to the Analog-Digital Interface Bridge described on page 153. The only difference is the behaviour of the device when the analog input lies between the threshold voltages. With the interface bridge, the output is UNKNOWN under these circumstances but with this Schmitt Trigger, the output retains its previous value and so is always in a known state. In summary, the output will only switch from low to high when the input exceeds the higher threshold (IN_HIGH) and will only switch from high to low when the input descends below the lower threshold (IN_LOW). If initial input voltage lies between the hysteresis thresholds, the output state is determined by the init_cond parameter.

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Chapter 6 Command Reference

Overview
Simulator commands instruct the simulator how to read in and simulate the circuit. All simulator commands begin with a period ( . ) . For the remainder of this chapter and elsewhere in this manual, simulator commands are referred to as Controls to distinguish them from commands entered in the command shell. The schematic editor supports some of the controls described in this chapter but not all. Unsupported analysis controls may be added manually to the schematic's netlist. See Adding Extra Netlist Lines on page 12 for details. .MODEL and .SUBCKT controls may also appear in model library files (in fact that is where they would usually reside) see User's Manual for details. The .ALIAS control may only appear in model library files. The following simulator controls are recognised by SIMetrix.

Control
.AC .DC .ENDF .ENDS .FILE .GLOBAL .GRAPH .IC .INC .KEEP .LIB .MODEL .NODESET .NOISE .OP .OPTIONS .PARAM

Manual Page
171 174 175 210 175 177 177 183 184 184 186 187 190 191 194 195 205

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Control
.PRINT .PZ .SENS .SUBCKT .TEMP .TF .TRACE .TRAN

Manual Page
207 209 209 210 211 211 213 213

The following control is only recognised in model library files. .ALIAS page 173

General Sweep Specification

Overview
SIMetrix features a common sweeping algorithm which is used to define the swept analysis modes: .DC, .AC, .NOISE and (now) .TF, along with multiple analyses such as Monte Carlo. The sweep algorithm has 6 modes: Device. Sweeps a single default value of a specified device. E.g. voltage of a voltage source, resistance of a resistor or the capacitance of a capacitor. Temperature Parameter. Parameter can be referenced in an expression for a model or instance parameter. Model parameter. Named model parameter. Frequency. (Not applicable to .DC) Monte Carlo. Perform a specified number of steps with distribution functions (i.e tolerances) enabled.

Standard SPICE only provides a subset of the above. .DC can only sweep voltage and current sources, .AC and .NOISE can only sweep frequency while .TF can't be swept at all. As well as providing 6 modes, each of the modes can sweep in four different ways. These are linear, decade, octave and list.

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Syntax
All the swept analysis modes use the same general syntax to specify the sweep parameters. However, to maintain compatibility with SPICE and its derivatives including earlier versions of SIMetrix, each analysis mode allows variations to this standard syntax. The general syntax is described below while the variations allowed for each analysis mode are described in the section dedicated to that analysis mode. All of the analysis modes can optionally be entered in a similar manner to .MODEL statements i.e. as an unordered list of parameter names followed by their values. For example, the following is a perfectly legal noise analysis specification:
.noise V=vout DEVICE=V1 VN=0 F=1k LIN=(100 -10m 10m) + INSRC=V1

In the various forms of the syntax described in the following sections, some of the parameter names may be omitted as long as they are entered in a particular order. It is sometimes, however, easier to remember parameter names rather than a default order, so the method described above may be more convenient for some users. General syntax for swept analyses

.AC|.DC|.NOISE|.TF sweep_spec [ analysis specific parameters ]

sweep_spec: One of the following:

DEVICE device_name step_spec F frequency TEMP step_spec F frequency PARAM param_name step_spec F frequency MODEL model [PARAM] mod_param_name step_spec F frequency FREQ step_spec MONTE num_steps F frequency
Where device_name Name of device to be swept. The following components may be swept: Capacitors, all controlled sources, fixed current source, fixed voltage source, inductors and resistors. Name of parameter used in expression. Expressions may be used to define an instance or model parameter and may also be used in arbitrary sources. Name of model containing parameter to be swept Name of model parameter Number of steps to be performed for Monte Carlo sweep. Specified frequency for which .NOISE, .AC and .TF analyses

param_name

model mod_param_name num_steps frequency

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are to be performed. May be zero for .AC and .TF. step_spec: One of the following:

STP start stop step LIN num_points start stop DEC num_points_decade start stop OCT num_points_octave start stop LIST val1 [ val2 ... ]
Where: start stop step num_points num_points_decade num_points_octave First value Last value (inclusive) Interval Total number of points Number of points per decade Number of points per octave

STP and LIN modes are both linear sweeps but specified differently. STP specifies start, stop and a step size, while LIN specifies start, stop and the total number of points.

Multi Step Analyses

Overview
The sweep specification described in General Sweep Specification on page 168 can also be applied to define multiple analyses including Monte Carlo analysis. This can be applied to the swept modes .DC, .AC, .NOISE and .TF along with .TRAN. The analyses .SENS, .PZ and .OP cannot be run in multi-step mode. A multi-step .OP is in fact the same as .DC so this is not required. Monte Carlo analysis is the subject of its own chapter (see page 218) but it is invoked in the same way as other multi-step modes. As well as the standard 6 sweep modes, small-signal multi-step analyses can be run in snapshot mode which uses snapshots created by a previous transient analysis.

Syntax
The general form is:

.analysis_name analysis_parameters SWEEP + [sweep_spec] | [SNAPSHOT STP snapstart snapstop snapstep]

Where: .analysis_name Dot control for analysis

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analysis_parameters Specific parameters for that analysis sweep_spec SNAPSHOT snapstart See General Sweep Specification on page 168 Use snapshots created by a previous transient analysis. For full details, see Snapshots on page 215 Index of first snapshot. Snapshots are counted in the order in which they are created. The first is 0. Use STP 0 0 0 to specify all available snapshots. Index of last snapshot Snapshot interval (usually 1)

snapstep snapstep Examples

Run 10 Monte Carlo runs for 1mS transient analysis

.TRAN 1m SWEEP MONTE 10

Sweep V1 from 0 to 5 volts in 0.1V steps for 200us transient

.TRAN 200u SWEEP DEVICE V1 STP 0 5 0.1

AC sweep of voltage source V5 from -300mV to 300mV. Repeat 6 times for parameter restail from 450 to 550.
.AC DEVICE=V5 LIN 100 -300m 300m F=100000 + SWEEP PARAM=restail LIN 6 450 550

Run AC sweep using all available snapshots

.AC DEC 100k 10G SWEEP SNAPSHOT STP 0 0 0

.AC
.AC inner_sweep_spec [ F frequency ] [ SWEEP outer_sweep_spec ] Spice compatible frequency sweep: .AC DEC|LIN|OCT num_points start stop
Instructs the simulator to perform a swept small signal AC analysis. SIMetrix AC analysis is not limited to a frequency sweep as it is with generic SPICE and derivatives. See General Sweep Specification on page 168 and examples below for more details. frequency inner_sweep_spec outer_sweep_spec Frequency at which analysis will be performed for nonfrequency sweeps. Default 0. See General Sweep Specification on page 168 for syntax. Defines sweep mode. FREQ keyword is optional. If specified, analysis will be repeated according to this

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specification. See General Sweep Specification on page 168 for syntax. num_points LIN: total number of points DEC: number of points per decade OCT: number of points per octave Start frequency for SPICE compatible mode Stop frequency for SPICE compatible mode

start stop

Except for frequency sweep, the frequency at which the analysis is being performed should be specified. If omitted, the frequency will be assumed to be zero. For non-frequency sweeps, a new dc operating point may be calculated at each step depending on what is being swept. If a capacitor, inductor or an AC only model parameter is being swept, then no new dc operating point will be required. Otherwise one will be performed. An AC only parameter is one that does not affect DC operating point such as device capacitance. Notes An AC analysis calculates the small signal frequency response of the circuit about the dc operating point. The latter is automatically calculated prior to commencing the frequency sweep. One or more inputs may be specified for AC analysis by using voltage or current sources with the AC specification (See Voltage Source on page 97). The results of an AC analysis are always complex. Examples SPICE compatible. Sweep frequency from 1kHz to 1Meg
.AC DEC 25 1k 1MEG

Sweep voltage source V1 100 points from -100mV to 100mV. Frequency = 100kHz
.AC DEVICE V1 LIN 100 -100m 100m F=100k

Sweep parameter Rscale from 0.5 to 3 in steps of 0.1. Frequency=20Meg

.AC PARAM Rscale STP 0.5 3 0.1 F=20Meg

Sweep resistor R1 with values 10k 12k 15k 18k 22k 27k 33k, Frequency =1.1KHz
.AC DEVICE R1 LIST 10k 12k 15k 18k 22k 27k 33k F=1.1K

Monte Carlo sweep 100 steps. Frequency = 10K. This is useful if - say - you are interested in the gain of an amplifier at one frequency and it needs to lie within a defined tolerance. Previously you would need to repeat an AC sweep at a single frequency to achieve this which could take a long time especially if the circuit has a difficult to find operating point. The analysis defined by the following line will take very little time even for a large circuit.
.AC MONTE 100 F=10K

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Examples of Nested Sweeps As Monte Carlo above but repeated from 0 to 100C
.AC MONTE 100 F=10K SWEEP TEMP STP 0 100 10

... and at a number of frequencies

.AC MONTE 100 SWEEP FREQ DEC 5 1k 100k

.ALIAS
.ALIAS alias_name device_name device_type
This control may only be used in device model library files. It is not recognised by the simulator. It permits a device model or subcircuit to be referenced by a different name. This allows one model definition to be used for multiple part numbers. alias_name device_name device_type Alias name Device to which alias refers Type of device to which alias refers. Must be one of the following C, D, LTRA, NJF, NMF, NMOS, NPN, PJF, PMF, PMOS, PNP, R, SW or SUBCKT. see .MODEL on page 187 for more details.

Example
.MODEL BC547C NPN + IS=7.59E-15 VAF=19.3 BF=500 IKF=0.0710 NE=1.3808 + ISE=7.477E-15 IKR=0.03 ISC=2.00E-13 NC=1.2 NR=1 BR=5 + RC=0.75 CJC=6.33E-12 FC=0.5 MJC=0.33 VJC=0.65 + CJE=1.25E-11 MJE=0.55 VJE=0.65 TF=4.12E-10 ITF=0.4 VTF=3 + XTF=12.5 RB=172 IRB=0.000034 RBM=65 .ALIAS BC549C BC547C NPN

The above would provide identical definitions for both BC547C and BC549C bipolar transistors. Notes .ALIAS definitions will recognise models defined in other files provided the file in which the alias resides and the file in which the model definition resides are part of the same library specification. A library specification is a single pathname possibly with a wildcard ('?' or '*') to refer to multiple files. E.g. \simetrix\models\*.mod is a library specification and refers to all files with the extension '.mod' in the directory \simetrix\models. Aliases must refer directly to a model or subcircuit definition and not to other aliases.

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.DC
.DC inner_sweep_spec [ SWEEP outer_sweep_spec ] Spice compatible: .DC device_name start stop step The remainder are SIMetrix 2.5 - 3.1 compatible: .DC TEMP start stop step .DC PARAM param_name start stop step .DC MODEL model [PARAM] mod_param_name start stop step
Instructs simulator to perform a DC sweep analysis. A dc analysis performs a dc operating point analysis for a range of values according to the sweep specification. SIMetrix DC analysis is not limited to sweeping a voltage or current source as with generic SPICE. Any mode defined by the general sweep specification (page 168) may be used although frequency sweep has no useful purpose. inner_sweep_spec See General Sweep Specification on page 168 for syntax. Defines sweep mode. DEVICE keyword is optional. If specified, analysis will be repeated according to this specification. See Multi Step Analyses on page 170 for details. Component reference of voltage source, current source, resistor or controlled source to be swept. (Only voltage and current sources are SPICE compatible) Start value for sweep Stop value for sweep Increment at each point Parameter name. This would be used in an expression to define a component or model value. Model name e.g. Q2N2222 Model parameter name e.g. IS

outer_sweep_spec

device_name

start stop step param_name

model_name model_parameter_name

If start is arithmetically greater than stop then step must be negative. It is not necessary to declare parameters with .PARAM if using parameter sweep. Examples SPICE compatible. Sweep V1 from 0 to 5 volts in steps of 0.1 volt

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.DC V1 0 5 0.1

SIMetrix 3.1 compatible temperature sweep

.DC TEMP 0 100 2

Decade (i.e. logarithmic) sweep. Sweep V1 from 1mV to 1V with 25 points per decade
.DC V1 DEC 25 1m 1v

Note that the DEVICE keyword has been omitted. This is the default sweep mode for .DC. Do 1000 Monte Carlo steps. This performs the same task as a Monte Carlo analysis applied to a DC operating point. In other products and earlier versions of SIMetrix this task would take a long time as the operating point is solved from scratch each time. With the mode described by the following example, the operating point need only be calculated from scratch once. All subsequent steps are seeded by the previous one and usually require only a few iterations. The end result is a sometimes spectacular increase in speed.
.DC MONTE 1000

Examples of Nested Sweeps Decade sweep at temperatures 0 to 100 in steps of 10

.DC V1 DEC 25 1m 1v SWEEP TEMP STP 0 100 10

Note the STP keyword is necessary to signify the start-stop-step method of defining a linear sweep. Alternatively LIN can be used which defines the sweep in terms of the total number of points. The following is equivalent to the above:
.DC V1 DEC 25 1m 1v SWEEP TEMP LIN 11 0 100

Do 100 run Monte Carlo analysis for temperature sweep

.DC TEMP 0 100 2 SWEEP MONTE 100

.FILE and .ENDF

.FILE filename file_contents .ENDF
The .FILE control allows the contents of a file referenced in a .MODEL control to be placed directly in the netlist. Files are referenced in arbitrary logic blocks (page 252), PWLFILE voltage and current sources (page 100), digital sources (page 121) and digital state machines (page 143). Each of these may refer to files defined using .FILE and .ENDF.

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Example
.MODEL COUNT_8 d_logic_block file=counter_def .FILE counter_def PORT (DELAY = 10n) CountOut out[0:7] ; EDGE (DELAY=5n, WIDTH=8, CLOCK=in[0]) Count ; Count = Count + 1 ; CountOut = count ; .ENDF

The .MODEL control refers to a file called counter_def. This could be a real disk file called counter_def or counter_def.ldf, but in the above example it is instead defined directly in the netlist using .FILE and .ENDF Important Note .FILE and .ENDF will not be recognised in library files.

.FUNC
.FUNC name ( arglist ) { body }
name arglist body Name of function. Must begin with a letter and not match one of the built in functions. List of comma separated argument names Body of function. This is an expression referring to the names in arglist that defines the operation performed by the function

.FUNC defines a function that can be used in a model or device parameter expression, a parameter defined using .PARAM or in an arbitrary source expression. Examples
.FUNC FREQ(V) { (V)*120K } .FUNC SWEEP(V) { SIN(TIME*FREQ(v)*2*PI) }

Optimiser Any expression that uses a function defined with .FUNC will be automatically processed by an optimisation algorithm. For more information see Optimisation on page 38 The optimiser attempts to speed simulations by making the expression evaluation more efficient. The optimiser is effective when .FUNC is used to create very complex expressions perhaps to develop a semiconductor device. In simple applications it may not make a noticeable improvement to performance. The optimiser can be enabled for all expressions and can also be disabled completely. To enable for all expressions use:
.OPTIONS optimise=2

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To disable:
.OPTIONS optimise=0

.GLOBAL
.GLOBAL node [ node... ]
Identifies nodes as global. This allows nodes specified at the top level of a circuit to be accessed within a subcircuit definition. For more information see Subcircuits on page 39.

.GRAPH
Parameters
.GRAPH signal_name|"expression" + [ persistence = persistence ] + [ axisname = axisname ] + [ graphname = graphname ] + [ axistype = digital|grid|axis|auto ] + [ curvelabel = curvelabel ] + [ xlabel = xlabel ] + [ ylabel = ylabel ] + [ xunit = xunit ] + [ yunit = yunit ] + [ xmin = xmin ] + [ ymin = ymin ] + [ xmax = xmax ] + [ ymax = ymax ] + [ analysis = analyses_list ] + [ ylog = lin|log|auto ] + [ xlog = lin|log|auto ] + [ nowarn = true|false ] + [ initXLims = true|false] + [ complete = true|false ]
.GRAPH instructs SIMetrix to plot a graph of the specified signal or expression. The graph can be plotted incrementally as the simulation proceeds or may be delayed until the run is complete.

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Parameter name
signal_name | expression persistence

Type
string

Description
Specifies item to be plotted. If this is an expression, then it must be enclosed in double quotation marks or curly braces. Number of curves to be displayed at once. On repeated runs, any curves from earlier runs remain until the number of curves exceeds this value at which point the oldest is deleted automatically. If this parameter is absent or zero, the curves are never deleted. If specified, the curves will be directed to their own graph sheet within the current window. The value of graphname is arbitrary and is used to identify the graph so that multiple .graph controls can specify the same one. It works in a similar way to axisname an example of which is given below. This name is not used as a label for display purposes but simply as a means of identification. Can be one of four values to specify type of yaxis: DIGITAL. Use a digital axis. This is a small axis that carries only one curve. It is intended for digital signals but may also carry analog curves. GRID. Use a separate grid stacked on top of the main one. The AXISNAME parameter may be used to identify a particular grid used by another .GRAPH control. AXIS. Use a separate y-axis alongside the main one. The AXISNAME parameter may be used to identify a particular axis used by another .GRAPH control. AUTO. This is the default value. A suitable axis is chosen automatically.

integer

graphname

string

axistype

string

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Parameter name
axisname

Type
string

Description
This is only used if AXISTYPE is specified. The value of AXISNAME is arbitrary and is used to identify the axis so that multiple .graph controls can specify the same one. An example of this is given below. This name is not used as a label for display purposes but simply as a means of identification. Axes can be labelled using ylabel and xlabel. Label for curve displayed in graph legend. If omitted, the label will be the signal name or expression. Label for x-axis. Default is reference of curve being plotted (E.g. time, frequency etc.) Label for y-axis. If there is only a single curve, this will default to the label for the curve otherwise the default is blank. Units for x-axis. Default is units of reference. Units for y-axis. Default is units of curves plotted provided they are all the same. If any conflict, the default will be blank Minimum limit for x-axis. Must be used with xmax. Maximum limit for x-axis. Must be used with xmin. Minimum limit for y-axis. Must be used with ymax. Maximum limit for y-axis. Must be used with ymin. Specifies for what analysis modes the plot should be enabled. By default it will be enabled for all analysis modes. Any combination of the following strings, separated by a pipe ('|') symbol. TRAN. Transient analysis AC. AC analysis DC. DC sweep analysis NOISE. Noise analysis POP. POP analysis - SIMPLIS only Other analysis modes do not produce results that can be probed

curvelabel

string

xlabel ylabel

string string

xunit yunit

string string

xmin xmax ymin ymax analysis

real real real real string

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Parameter name
ylog

Type
string

Description
One of three values LIN LOG AUTO Use linear axis Use log axis Axis will be log if x values are log spaced. (E.g for decade AC sweep) and all values are positive. Default if omitted: LIN

xlog

string

One of three values LIN LOG AUTO Use linear axis Use log axis Axis will be log if x values are log spaced. (E.g for decade AC sweep) and all values are positive. Default if omitted: AUTO

nowarn

Boolean

If true, no warnings are given if an attempt is made to plot a non-existent signal. Default: false. When this is TRUE, the x-axis limits are initialised according to the analysis. E.g. if the analysis is transient and runs from 0 to 1mS, the x-axis will start with these limits. If set to FALSE, the x-axis limits are calculated to fit the curve and updated incrementally. You should set this to FALSE if you are plotting an expression whose x values are not the same as the x values for the analysis e.g. using the XY() function for an X-Y plot. The default value of this option is usually true but can be changed using the option NoInitXAxisLimits . Type at the command line: Set NoInitXAxisLimits to change default to false.

initXLims

Boolean

complete

Boolean

If true, the plot is not produced until the analysis is completed. Otherwise the plot is updated at a rate determined by the global option ProbeUpdatePeriod. This is forced for some types of plot as certain expressions cannot be plotted incrementally. This can be set using the options dialog box (File|Options|General). Default: false.

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The .GRAPH control is the underlying simulator mechanism used by the schematic's fixed probes. See User's Manual for details. .GRAPH supersedes the older and less flexible .TRACE (page 213). The latter is, however, still supported and may sometimes be convenient for specifying multiple signals on one line.

Using Multiple .GRAPH Controls

If specifying several .GRAPH controls to plot a number of curves on the same graph, you should make sure that the various parameters are consistent. If for example, a conflict arises if you specify xmin and xmax for two .GRAPHs that plot curves in the same graph sheet, and the values for xmin and xmax are different for each. You can specify xmin and ymin for just one of the .GRAPH controls or you can specify for all and make sure they are all the same. The same applies to other non-Boolean parameters i.e. ymin, ymax, xlabel, ylabel, xunits and yunits. The parameter initXLims, however must be specified with the same value for all .GRAPH controls specifying the same graph sheet. Conflicting values of ylog and xlog are resolved by plotting the curves on separate axes or graph sheets respectively.

Creating X-Y Plots

To create an X-Y plot, use the XY() function (See User's Manual or Script Reference Manual for full details of available functions). You should also specify "initXLims=false". E.g.
.GRAPH "XY( imag(vout), real(vout) )" initXLims=false + xlog=LIN complete=true

The above will create a Nyquist plot of the vector VOUT.

Using .GRAPH in Subcircuits

.GRAPH maybe used in a subcircuit in which case a plot will be produced for all instances of that subcircuit. Note, however, that it will only work for single values and not for expressions when inside a subcircuit. The value of the curveLabel parameter will be prefixed with the instance name so that the displayed curves can be correctly identified.

Using Expressions with .GRAPH

You can enter an expression as well as single vectors to be plotted. A problem arises when plotting expressions incrementally that are regularly updated while the simulation is running. SIMetrix versions prior to v5 could not incrementally evaluate expressions, so each time the plot of an expression was updated, the expression had to be recalculated from the beginning. This was inefficient and it has always been recommended that the complete=true flag was added in these circumstance to inhibit incremental plotting. SIMetrix - from version 5 - now has the ability to incrementally evaluate some expressions and there is no longer a recommendation to set complete=true. However,

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certain expression cannot be incrementally evaluated and when such expressions are entered, incremental plotting will automatically be disabled and the plot won't appear until the run is complete. A notable example of expressions that cannot be incrementally evaluated is anything containing the phase() function. This is because the phase() function uses a state machine to determine when the phase wraps from -180 to 180 and back. An offset is then applied to make the phase plot continuous. Because of the state machine, it is always necessary to evaluate this function from start to finish which makes incremental evaluation difficult. An alternative is to use instead the arg() function. This is the same as phase, but does not have the state machine and always gives an output that lies between +/- 180 degrees.

Plotting Spectra with .GRAPH

You can use .GRAPH to create spectrum plots using FFTs or Fourier. However, FFT is quite difficult to use on its own as it needs interpolated data. So, a new user defined function called Spectrum() has been developed that is especially designed for use with .GRAPH. Usage is:

Spectrum(vector, numPoints [, start [, stop]])

Where: vector numPoints start stop Vector or expression FFT size - must be a binary power of 2 Start time - default = 0 Stop time - default = end of data

Spectrum() cannot be incrementally evaluated and so incremental plotting will automatically be disabled for any .GRAPH control that uses it. See above Using Expressions with .GRAPH. Examples
.GRAPH C2_P curveLabel="Amplifier output" nowarn=true

Plots the vector C2_P and gives it the label Amplifier output. As NOWARN is TRUE, no warning will be given if C2_P does not exist.
.GRAPH vout_quad + axisType="grid" + axisName="grid1" + persistence=2 + curveLabel="Quadrature" + nowarn=true + analysis = TRAN|DC .GRAPH vout + axisType="grid" + axisName="grid1" + persistence=2 + curveLabel="In Phase" + yLabel="Filter Outputs"

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+ nowarn=true + analysis = TRAN|DC

The above illustrates the use of the parameters AXISTYPE and AXISNAME. Both the vectors specified by the above .GRAPH controls will be plotted on the same but separate grid. Because both grids have been given the AXISNAME grid1, each curve will be plotted on the same one. If the values of axisname for the above were different, each curve would be plotted on a separate grid. The ANALYSIS parameter has been specified in both cases, so plots will only be created for transient and dc sweep analyses.

.IC
.IC V(node1)=val1 [ V(node2)=val2 ]...
OR

.IC node1 val1 [ node2 val2 ]

This control sets transient analysis initial conditions. node1, node2 etc. val1, val2 etc. Name of circuit node (or net) to which initial condition is to be applied. See notes below. Voltage to be applied to net as initial condition.

If the UIC parameter is specified with the .TRAN control no DC operating point will be calculated so an initial condition will set the bias point in the same way as an IC=... parameter on a BJT, capacitor, diode, JFET or MOSFET. If the UIC parameter is absent from the .TRAN control then a DC operating point is calculated before the transient analysis. In this case the net voltages specified on the .IC control are forced to the desired initial values during the DC operating point solution. Once transient analysis begins this constraint is released. By default the voltage force is effectively carried out via a 1 resistor. This can be changed with the option setting ICRES. (page 195).

Alternative Initial Condition Implementations

An initial condition can also be specified using a voltage source with the DCOP parameter specified. E.g.
VIC1 2 3 3.5 DCOP

Will force a voltage of 3.5 volts between nodes 2 and 3 during the DC operating point solution. This has two advantages over .IC: 1. 2. It has zero force resistance It can be applied differentially

You can also use a capacitor with the BRANCH parameter set to 1. E.g.:
C1 2 3 10u BRANCH=1 IC=3.5

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This will behave identically to the voltage source in the above example during the DC operating point but during a subsequent small-signal or transient analysis will present a 10F capacitance to nodes 2 and 3. See also: Capacitor on page 58 and Voltage Source on page 97.

.INC
.INC pathname
Insert the contents of the specified file. pathname File system pathname for file to be included

The .INC control is replaced by the specified file in its entirety as if was part of the original file. .INC controls may also be nested i.e. there may be .INC controls within the included file. Nesting may be to any level.

.KEEP
.KEEP signal_spec [signal_spec ...]
This control tells the simulator what values to store during a simulation. By default, all top level voltages and currents and digital data are stored. signal_spec /TOP | /SUBS | /NOV | /NOI | /NODIG | *V | *I | *D | **V | **I | **D | subref.*V | subref.*I | subref.*D | subref.**V | subref.**I | subref.**D | ^wildcard_filter | signal_name Sub-circuit reference Don't store top level (i.e. not in a subcircuit) voltages. Don't store top level currents Don't store top level digital data. Store all subcircuit data. Overrides /subs. This is to inhibit storing signals in child schematics in hierarchical designs. General specification that selects values to store based on their name alone. Would usually use one of the special characters '*' and '?'. '*' means match one or more characters while '?' means match a single character. Some examples: * X1.* X?.* matches anything matches any signal name that starts with the three letters: X1. matches any name that starts with an X and with a '.' for the third letter.

subref /NOV /NOI /NODIG /SUBS /TOP ^wildcard_filter

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*.q10#c *V matches any name ending with q10#c.

Store all top level voltages. This is actually implicit and need not be specified at the top level of the netlist. It can be usefully used in sub-circuit definitions - see notes. Store all top level currents. This is actually implicit and need not be specified at the top level of the netlist. It can be usefully used in sub-circuit definitions - see notes. Store all top level digital data. This is actually implicit and need not be specified at the top level of the netlist. It can be usefully used in sub-circuit definitions - see notes. Store all voltages including those inside sub-circuits descending to all levels Store all currents including those inside sub-circuits descending to all levels Store all digital data including those inside sub-circuits descending to all levels Store all voltages within sub-circuit subref excluding voltages within children of subref. Store all currents within sub-circuit subref excluding currents within children of subref. Store all digital data within sub-circuit subref excluding digital data within children of subref. Store all voltages within sub-circuit subref including voltages within children of subref descending to all levels. Store all currents within sub-circuit subref including currents within children of subref descending to all levels. Store all digital data within sub-circuit subref including digital data within children of subref descending to all levels. Explicit voltage or current.

*I

*D

**V **I **D subref.*V subref.*I subref.*D subref.**V subref.*I subref.*D signal_name

This control instructs the simulator what values to store during a simulation. By default, all voltages and currents not within subcircuits are stored. /SUBS /NOV /NOI /TOP signalname. Store all available voltages and currents including subcircuit data. (Overrides /NOV and /NOI). Don't store currents in voltage sources and inductors or any voltages. Don't store currents. (Except those in voltage sources and inductors) If present, overrides /SUBS. Name of explicit signal (e.g. voltage or current) to store.

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Notes .KEEP may be used inside a sub-circuit definition in which case .KEEP operates at a local level. For example .KEEP *v inside a sub-circuit definition specifies that all voltages within that subcircuit (for all instances) will be saved. .KEEP **v does the same but also includes any descendant sub-circuit instances. In earlier versions, voltage also meant currents in voltage sources and inductors as these values are obtained as part of the matrix solution. This is no longer the case, voltage and current mean what they say. Examples Store only voltages and currents in sub-circuit X1 excluding descendants.
.KEEP /noi /nov /top X1.*v X1.*i

Store only voltages and currents in sub-circuit X1 including descendants.

.KEEP /noi /nov /top X1.**v X1.**i

Store voltages within U3.U12 along with VOUT and VIN

.KEEP /noi /nov /top U3.U12.*v VOUT VIN

Store all top level voltages and currents in U7

.KEEP /noi /top U7.*i

.LIB
There are two forms of .LIB and the behaviour of each is completely different from each other. The SIMetrix Native Form specifies a file or group of files to be searched for any model or subcircuit that has not yet been found. The HSPICE version is a selective version of .INC but unlike .INC it doesn't include the whole file, just a specified portion of it.

SIMetrix Native Form

.LIB pathname
pathname File system path name specifying a single file or, by using a wildcard (* or ?), a group of files. If the path name contains spaces, it must be enclosed in quotation marks (").

The SIMetrix form of this control specifies a pathname to be searched for model and subcircuit libraries. Any number of .LIB controls may be specified and wildcards (i.e. * and ? ) may be used. If a model or subcircuit is called up by a device line but that definition was not present in the netlist, SIMetrix will search for it in files specified using the .LIB control.

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SIMetrix will also search for definitions for unresolved parameters specified in expressions. These are defined using .PARAM (see page 205). Example The following control instructs the simulator to search all files with the .mod extension in c:\Spice Model Library\ for any required subcircuits or device models.
.lib "c:\Spice Model Library\*.mod"

HSPICE Form
.LIB 'filename' entryname
filename entryname File system path name specifying a single file. Name used to identify sections within filename

When HSPICE the form of .LIB is encountered, SIMetrix will search the file specified by filename for a section enclosed by:

.LIB entryname
and

.ENDL
.LIB calls may be nested as long as they are not recurrent. That is a .LIB call within a .LIB .ENDL block may not call itself but it may call another block within the same file. (HSPICE itself does not permit this). This form of .LIB is commonly used in model files issued by semiconductor fabrication plants which tend to be designed for use with HSPICE. The entry name parameter is used for process corner and skew selection. Typically the model file would have entries for - say - slow, nominal and fast models. These would reside under entry names of, perhaps, SS, NOM, and FF respectively. You can very rapidly switch between these model sets simply by changing the entry name on the .LIB line e.g.
.LIB 'c:\models\fab1\process_a\top.mod' NOM

would select the nominal models. Changing to:

.LIB 'c:\models\fab1\process_a\top.mod' SS

would switch to the slow models.

.MODEL
.MODEL modelname modeltype ( param1=val1 [ param2=val2 ]... )
This control specifies a set of model parameters that are used by one or more devices. .model controls often reside in model libraries.

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modelname Model name. Any text string to uniquely identify model. Must begin with a letter but may contain any legal ASCII character other than a space and period '.' . Model type. See tables below for possible values

modeltype

param1, param2 etc. Parameter name. Valid values depend on the model type. (See Simulator Devices on page 26) val1, val2 etc. Parameter value.

XSPICE Model Types

Model name
ad_converter adc_bridge adc_schmitt cm_cap cm_ind d_and d_buffer d_cap d_dff d_dlatch d_fdiv d_init d_inverter d_jkff d_logic_block d_nand d_nor d_open_c d_open_e d_or d_osc d_pulldown d_pullup d_pulse

Description
analog-to-digital converter analog-to-digital interface bridge analog-to-digital schmitt trigger Capacitor with voltage initial condition Inductor with current initial condition digital n-input and gate digital one-bit-wide buffer Digital capacitor digital d-type flip flop digital d-type latch digital frequency divider Digital initial condition digital one-bit-wide inverter digital jk-type flip flop arbitrary logic block digital n-input nand gate digital n-input nor gate digital one-bit-wide open-collector buffer digital one-bit-wide open-emitter buffer digital n-input or gate controlled digital oscillator digital pulldown resistor digital pullup resistor digital pulse

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Model name
d_ram d_res d_source d_srff d_srlatch d_state d_tff d_tristate d_xnor d_xor da_converter dac_bridge s_xfer SPICE Model Types

Description
digital random-access memory Digital resistor digital signal source digital set-reset flip flop digital sr-type latch digital state machine digital toggle flip flop digital one-bit-wide tristate buffer digital n-input xnor gate digital n-input xor gate digital-to-analog converter digital-to-analog interface bridge s-domain transfer function block

Model name
C CORE CORENH D LTRA NIGBT NJF NMF NMOS NPN PJF PMF PMOS PNP R SW

Description
Capacitor Jiles-Atherton core model Simple core model Diode Lossy transmission line IGBT N-channel JFET N-channel GaAsFET N-channel MOSFET NPN BJT (Bipolar junction transistor) P-channel JFET P-channel GaAsFET P-channel MOSFET PNP BJT Resistor Voltage controlled switch

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Example The following is a model for a 1N5404 diode.
.MODEL D1n5404 + + D(Is=15.48f Rs=7.932m Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=150p M=.3 Vj=.75 Fc=.5 Isr=120n Nr=2 Bv=525 Ibv=100u)

.NODESET
.NODESET V(node1)=val1 [ V(node2)=val2 ]...
OR

.NODESET node1 val1 [ node2 val2 ]

This control sets an initial guess voltage at the specified node for the dc operating point solution. node1, node2 etc. val1, val2 etc. Name of circuit node (or net) to which nodeset is to be applied. See notes below. Nodeset voltage to be applied.

Initially nodesets work exactly the same way as initial conditions. The nodeset voltage is applied via a 1 Ohm (by default but can be changed using NODESETRES option see page 195) resistor and the solution is completed to convergence (by any of the methods). The nodeset is then released and the solution repeated. If the nodeset voltage is close to the actual solution the convergence of the second solution should be rapid. Nodesets can be used to force a particular solution for circuits that have more than one stable state. Consider the following circuit:

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5V V1 1K R1 1K R2

4.60195 10k R5 Q2 Q2N2222 100k R3 100k R4 10k R6

0.0646829 .nodeset 0 Q1 Q2N2222

A nodeset has been applied to the collector of Q1. This has forced Q1 to be on and Q2 to be off. If the nodeset were absent the solution would actually leave both Q1 and Q2 partially on. In real life this would not be stable but it is numerically accurate. The other application of nodesets is to help convergence for the DC bias point. With SIMetrix, it is rarely necessary to use nodeset's to find the DC solution of a circuit. They can, however, be useful for speeding up the operating point analysis for circuits that have already been solved. You may wish to do this for a Monte-Carlo analysis, for example. SIMetrix features a method of creating nodesets for this purpose using the SaveRhs command. See Using Nodesets on page 232. Nodeset's should not be confused with initial conditions. (see .IC on page 183). Initial conditions tie a node to a particular voltage and keep it there throughout the DC operating point analysis. Nodesets merely suggest a possible solution but do not force it.

.NOISE
.NOISE inner_sweep_spec [ V ] pos_node [ VN ] neg_node + [[ INSRC ] in_source ] + [ F frequency ] [SWEEP outer_sweep_spec] Spice Compatible .NOISE V(pos_node [, neg_out_node ]) in_source + DEC|LIN|OCT num_points start stop interval

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This control instructs the simulator to perform a small signal noise analysis. pos_node neg_node in_source inner_sweep_spec outer_sweep_spec Node on circuit at which noise is measured. Node to which outputnode is referenced. Defaults to ground if omitted. Input source (i.e. voltage or current) to which the input noise measurement is referred. See General Sweep Specification on page 168 for syntax. Defines sweep mode. FREQ keyword is optional. If specified, analysis will be repeated according to this specification. See General Sweep Specification on page 168 for syntax. Analysis points are linearly spaced. Analysis points are logarithmically spaced in decades Analysis points are logarithmically spaced in octaves LIN: Total number of points DEC: Number of points per decade OCT: Number of points per octave Start frequency Stop frequency Currently does nothing. Provided for backward compatibility.

LIN DEC OCT num_points

start stop interval Notes

During noise analysis the simulator calculates the total noise measured between pos_node and neg_node at each frequency point. It also calculates and outputs this noise referred back to an input specified by in_source. As for all other analysis modes a DC operating point analysis is carried out first but, unlike AC analysis, the results of this analysis are not made available. The simulator outputs vectors covering the contribution from each noise generating device to the total output noise. The names of these vectors begin with the component reference of the device followed by a suffix to indicate the source of the noise within the device. A listing of the suffixes is given below. It is important to note that it is not the noise being generated by each device that is output but the proportion of that noise that is propagated to the output. It is not necessary to specify a separate AC analysis alongside the noise analysis as it is with SPICE2 and commercial derivatives of SPICE2. The magnitude of any AC independent voltage or current source on the circuit has no effect on the results of a noise analysis. Unlike SPICE and earlier versions of SIMetrix, it is not necessary to specify an AC parameter for the source used for the noise input source. For the first form shown above, the input source is in fact optional. If it is omitted the input referred noise will not be calculated. All noise results are in V/Hz except input noise referred back to a current source which is in A/Hz. In standard SPICE3 the noise values produced for MOS2 and BSIM3 devices are in V2/Hz. For consistency, these have now been changed to V/Hz.

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The original SPICE3 behaviour can be restored by setting the simulator option OldMosNoise (see .OPTIONS on page 195) Device vector name suffixes

Device Type
BJT

Suffix and Description

#rc Noise due to collector resistance #rb Noise due to base resistance #re Noise due to emitter resistance #ic Shot noise in collector #ib Shot noise in base #1overf Flicker (1/f) noise no suffix Total transistor noise #rs Noise due to series resistance #id Shot noise #1overf Flicker (1/f) noise no suffix Total diode noise

Diode

JFET and MOSFETs level 1-3 #rd Noise due to drain resistance and BSIM3 #rs Noise due to source resistance #id Shot noise in drain #1overf Flicker (1/f) noise no suffix Total FET noise Philips MOS9 (all types see #Sfl Flicker (1/f) noise Philips Compact Models on #Sth Drain thermal noise page 104) #Sig Gate thermal noise #Sigth Gate-drain correlated thermal noise no suffix Total FET noise Resistor #therm Resistor thermal noise #1overf Flicker (1/f) noise #noise Total resistor noise no suffix Total switch noise

Voltage controlled switch Creating Noise Info File

Noise analysis generates vectors in the same way as all other swept analyses. Individual vectors may also be tabulated in the list file using the .PRINT control. A noise output file may also be created from the front end. Select the command shell menu Graphs and Data|Create Noise Output File to create a text file with a summary of noise results. Included is a list of the integrated noise output for every device listed in order of magnitude. Select Graphs and Data|View Noise Output File to view the file. Note that this is a front end feature and is not implemented by the simulator. Examples Run noise analysis from 100Hz to 1MHz with 25 points per decade. Calculate noise at node named vout and noise referred back to voltage source vin:
.NOISE V( vout ) vin dec 25 100 1meg

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Decade sweep resistor RSource from 100 to 10K with 25 points per decade. Frequency = 1kHz
.NOISE DEVICE RSource DEC 25 100 10k F=1K

.OP
.OP
This control instructs the simulator to perform a DC operating point analysis. Note that a DC operating point analysis is carried out automatically for transient (unless the UIC parameter is specified), AC, DC, transfer function and noise analyses. DC operating point analysis attempts to find a stable bias point for the circuit. It does this by first applying an initial guess and then uses an iterative algorithm to converge on a solution. If it fails to find a solution by this method the simulator then attempts three further strategies. For the first, a method known as source stepping is employed. For this all voltage and current sources in the circuit are initially set to near zero and the solution found. The sources are then gradually increased until they reach their final value. If this approach fails a second strategy GMIN stepping is invoked. This conditions the solution matrix by increasing the diagonal term such that it is dominant. If large enough, convergence is virtually guaranteed. If successful then the diagonal term is reduced and a further solution sought using the previous solution as a starting point. This procedure is repeated until the diagonal term is returned to its correct value. Increasing the diagonal term is in a way similar, but by no means identical, to placing a small resistance at each node of the circuit. If source stepping fails a final strategy, pseudo transient analysis is invoked. This is the most powerful technique employed and nearly always succeeds. However, it is also the slowest which is why it is left until last. For more information on DC convergence see Convergence and Accuracy on page 228. If the final approach fails then the analysis will abort. IMPORTANT: It is not necessary to include .OP if other analyses are specified. All other analysis modes will perform an operating point anyway so including .OP will simply cause it to be done twice. However, with .NOISE, .TF, .SENS and .PZ the results of the operating point analysis are not output. If the bias point of the circuit is required when running one of these analysis modes, a .OP will be needed. OFF Parameters Some semiconductor devices feature the device parameter OFF. If there are devices in the circuit which specify this parameter, the bias point solution is found in two stages. In stage 1 the devices with OFF specified are treated as if their output terminals are open circuit and the operating point algorithm completes to convergence. In stage 2, The OFF state is then released and the solution restarted but initialised with the results of stage 1.

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The result of this procedure is that OFF devices that are part of latching circuits are induced to be in the OFF state. Note that the OFF parameter only affects circuits that have more than one possible DC solution such as bistables. If the OFF parameter is specified in - say - an amplifier circuit - with a unique solution, the final result will be the same. It will just take a little longer to arrive at it. Nodesets Nodesets work in a similar way to the OFF parameter in that the solution is found in two stages. In the first the nodeset is applied and the solution found. It is then released and convergence continues. Nodeset are an aid to convergence and, like the OFF parameter, can coerce a particular solution if there is more than 1 stable state. See .NODESET on page 190 for details Initial Conditions Initial conditions force a particular voltage at a circuit node during bias point solution. The force is released for any subsequent analysis. See .IC on page 183 for more details. Operating Point Output Info During the operating point analysis, operating point values of every device in the circuit are output to the list file (see page 22). This information is not usually output for other analysis modes unless explicitly requested. The output of operating point information is controlled by three simulator options: NOOPINFO OPINFO If set, the operating point info file is not created for .OP analysis If set, the operating point info file is created for other analyses as well as .OP. (Does not apply to .SENS - operating point information is not available for this mode at all) Sets name of file to receive operating point info. Outputs to list file if this option is not specified.

OPINFOFILE

.OPTIONS
.OPTIONS [ opt1 [=val1]] ...
This control allows the setting of various options specific to the simulator. opt1 val1 Option name. Must be one specified in list below. Option value. Not all options have a value.

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List of simulator options

Option name
ABSTOL

Default value
1p

Description
Units = A The absolute current error tolerance. It is sometimes desirable to increase this for circuits that carry large currents (>1A) to speed the solution and aid convergence. Units = A ABSTOL selectively relaxed to this value if needed to allow transient analysis to continue. Full simulation timing statistics are generated if this is enabled. If enabled, a report about selection of binned models will be output to the list file. See Model Binning on page 43 Units = Coulombs The absolute charge tolerance. Operating point strategy sequence order. See Controlling DC Method Sequence on page 237 for details Unit = m2 Default value for MOSFET AD device parameter. Applies to levels 1-3 and level 49/53. Does not apply to level 8 or Philips MOS9 devices Unit = m2 As DEFAD but for AS parameter Unit = metres As DEFAD but for L parameter As DEFAD but for NRD parameter As DEFAD but for NRS parameter Unit = metres As DEFAD but for PD parameter Unit = metres As DEFAD but for PS parameter Unit = metres As DEFAD but for W parameter Unit = Seconds Minimum digital resolution. Not yet fully supported

ABSTOLMAX

ACCT BINDIAG

false false

CHGTOL DCOPSEQUENCE

1e-14 gmin| source| pta 0

DEFAD

DEFAS DEFL DEFNRD DEFNRS DEFPD DEFPS DEFW DIGMINTIME

0 100 0 0 0 0 100 1pS

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Option name
EXPAND

Default value
false

Description
The netlist with subcircuits expanded is output to the list file if this is specified. Only applies if EXPAND also specified. Specifies a file instead of the list file to receive the expanded netlist

EXPANDFILE

FASTPOINTTOL FASTRELTOL FLUXTOL

1.0 0.001 1e-11

Value for POINTTOL used during Fast transient start. See POINTTOL below. Value for RELTOL used during Fast transient start Unit = V.secs The absolute flux tolerance for inductors. Forces a separate data group to be created for transient analysis operating point data. This happens anyway if tstart>0. Use this option when simulating a large circuit and you wish to make extensive use of schematic bias annotation. See Users Manual Chapter 9 Viewing DC Operating Point Results for more details Unit = Siemens (mhos) The minimum conductance allowed by the program. This has the effect of placing a resistor = 1/GMIN in parallel with every branch of the circuit. Maximum total number of iterations allowed for GMIN stepping operating point algorithm. See Source and GMIN Stepping on page 229 for details. During GMIN stepping the value of GMIN is multiplied by a variable factor at each step. This option is the starting and maximum value of that factor. Iteration limit for each step in GMIN stepping. Increase to 100 for compatibility with SIMetrix 2.0x and earlier. Unit = ICRES Initial condition resistive force. See .IC on page 183 for details

FORCETRANOPGROUP off

GMIN

1e-12

GMINMAXITERS

1000

GMINMULT

10

GMINSTEPITERLIMIT

20

ICRES

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Option name
ITL1 ITL2 ITL4

Default value
100 50 10

Description
DC iteration limit used for initial DC operating point. DC iteration limit used for swept and multi-step analyses. Normal transient timepoint iteration limit. The behaviour of this parameter is slightly different in SIMetrix than other SPICE based simulators. See Convergence and Accuracy on page 228 Upper transient timepoint iteration limit. This is specific to SIMetrix. Unit = Volts Upper threshold for logic inputs. Other comments as for LogicThreshHigh Unit = Volts Lower threshold for logic inputs. Other comments as for LogicThreshHigh Unit = Volts Output voltage for logic high level. Used for & | and ~ operators for arbitrary source. See Arbitrary Source on page 46 for more details Unit = Volts Output voltage for logic low level. Other comments as for LogicThreshHigh If set, components within subcircuits are treated as matched for Monte Carlo analysis. See Monte Carlo Analysis on page 218 . Maximum number of event driven passes allowed at each step. It is not usually necessary to change this value. Maximum number of alternations between analog and event-driven iterations. It is not usually necessary to change this value Maximum integration order. For METHOD=TRAP maximum value is 2. For METHOD=GEAR maximum value is 6. There is rarely any reason to change this value.

ITL7 LOGICHIGH

40 2.2

LOGICLOW

2.1

LOGICTHRESHHIGH

LOGICTHRESHLOW

MATCHEDSUBCIRCUITS

off

MAXEVTITER

0 (sets internal default) 0 (sets internal default) 2

MAXOPALTER

MAXORD

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Option name
MC_ABSOLUTE_RECT

Default value
Off

Description
If set Monte Carlo distribution will be rectangular for absolute tolerances. Otherwise the distribution will be Gaussian. If set Monte Carlo distribution will be rectangular for matched tolerances. Otherwise the distribution will be Gaussian. File name to receive Monte Carlo log. See Log File on page 219 Numerical integration method. Either TRAP (default) or GEAR". More info: See Integration Methods - METHOD option on page 241

MC_MATCH_RECT

Off

MCLOGFILE METHOD

mclog.txt trap

MINBREAK

See notes Unit = Seconds Minimum time between transient analysis breakpoints. A breakpoint is a point in time when an analysis is forced regardless of whether it is required by the timestep selection algorithm. Typically they are set at known turning points such as the start and end of a rising pulse. If two breakpoints are closer than MINBREAK they are merged into one. (there are exceptions to this e.g if the two breakpoints were generated by a single rising edge). Increasing MINBREAK can sometimes help convergence and simulation speed. The default value is MINTIMESTEP*100. (See below for MINTIMESTEP) 1.000001 In GMIN stepping, the step size is multiplied by variable factor at each step. This step is reduced if convergence fails. If it is reduced below this value, the GMIN algorithm will abort and the next DC operating point strategy will be invoked.

MINGMINMULTIPLIER

MINTIMESTEP

1e-9 * Max Unit = Seconds time step Minimum transient time step. Simulation will abort if it reaches this value. See .TRAN on page 213 for value of Max time step

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Option name
MOSGMIN

Default value
GMIN

Description
Value of GMIN used between drain and source of MOSFETs. See MOSFET GMIN Implementation on page 86 Changes the implementation of GMIN for old MOS devices i.e. LEVELs 1-3. When this option is set, GMIN is implemented as a conductance between source and drain. Otherwise two conductances are added between drain and bulk and source and bulk. See MOSFET GMIN Implementation on page 86 Unit = Volts Maximum value allowed for circuit node during iteration. If exceeded, iteration will abort. (This does not usually mean the analysis will abort). Reducing this value can sometime solve floating point exceptions or unexplained singular matrices. Unit = Ohms Driving resistance of nodeset force. See .NODESET on page 190 for details If specified, no Monte Carlo log file will be created. SeeLog File on page 219 for details If specified, no model parameter report will be output to the list file. If specified, the drain induced gate noise model for MOS9 devices will be disabled. See Philips Compact Models on page 104. If specified, only a single pass will be made to resolve the operating point for event driven devices. Switches off creation of operating point info file for .OP analyses. See .OP on page 194 for more details Use GMIN stepping for DC operating point analysis first. (i.e skip normal iteration method)

NEWGMIN

false

NODELIMIT

1e50

NODESETRES

1.0

NOMCLOG

false

NOMOD NOMOS9GATENOISE

false false

NOOPALTER

false

NOOPINFO

Off

NOOPITER

off

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Option name
NORAW

Default value
off

Description
Output transient analysis values at intervals of tstep only. See .TRAN on page 213 Switches off creation of sensitivity analysis data file. Column width used for display of all values in list file and Monte Carlo log file. Minimum value is 8, maximum is 30. Note this value is column width not the number of significant digits. If set SPICE 2 MOS limiting algorithm is used. Value of conductance placed between drain-bulk and source-bulk for BSIM3, BSIM4 and EKV devices. Also applies to LEVEL 1-3 and LEVEL 7 MOSFETs if NEWGMIN parameter is set. See MOSFET GMIN Implementation on page 86 MOS2 and BSIM3 devices return device noise in V2/Hz for SPICE3 and earlier versions of SIMetrix whereas other device's noise is returned in V/ Hz. From release 3 onwards all devices return noise in V/Hz. Setting this option restores to behaviour of earlier versions. If set DC operating point info file is created for all analyses (except .SENS). Normally it is created only for .OP analyses. Specify name of operating point info file. This is OP.TXT by default. Controls expression optimiser. 0=off, 1=on for .FUNC defined expressions, 2=on always. See Optimisation on page 38

NOSENSFILE NUMDGT

Off 10

OLDLIMIT OLDMOSGMIN

Off 0

OLDMOSNOISE

Off

OPINFO

Off

OPINFOFILE OPTIMISE

Off 1

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Option name
PARAMLOG

Default value
Given

Description
Control amount of detail for parameter log in list file. Choices: None: no parameters listed Brief: only parameters specified using an expression are listed Given parameters explicitly specified in the netlist are listed Full all parameters are listed This affects the matrix solution and rarely needs to be altered. Setting this parameter to a high value e.g, 0.99 can sometimes fix convergence problems but may slow down the simulation. Valid values lie between 0 and 1. This affects the matrix solution and rarely needs to be altered. It is the absolute minimum value for a matrix entry to be accepted as a pivot. Unexplained singular matrix errors can sometimes be overcome by lowering this value. (But note that singular matrix errors are usually caused by errors in the circuit such as floating nodes or shorted voltage sources). A factor used to control the extent to which the maximum value attained by a signal is used to control its tolerance. This is new from release 4; set it to zero for pre release 4 behaviour. Increasing this value will speed up the simulation at the expense of precision. See Accuracy and Integration Methods on page 238 If > 0, specifies a time when pseudo transient analysis results will be accepted unconditionally. This is useful when a circuit comes close to convergence during pseudo transient, but doesnt quite make it due to an oscillation. See Pseudo Transient Analysis on page 230

PIVREL

1e-3

PIVTOL

1e-13

POINTTOL

0.001

PTAACCEPTAT

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Option name
PTACONFIG

Default value
0

Description
Integer from 0 to 15 sets internal parameters for pseudo transient algorithm used to find DC operating point. See Pseudo Transient Analysis on page 230 Maximum total number of iterations allowed for pseudo transient algorithm used to find DC operating point. See Pseudo Transient Analysis on page 230 If specified, signal vectors will be output during pseudo transient analysis. This may be used to diagnose a failure. See Pseudo Transient Analysis on page 230 This is the relative tolerance that must be met for each analysis point. Reducing this number will improve accuracy at the expense of simulation time or/and convergence reliability. Simulation results can not be relied upon if its value is increased beyond 0.01. A more detailed discussion is given in Accuracy and Integration Methods on page 238 RELTOL selectively relaxed to this value if needed to allow transient analysis to continue If specified a resistor of the specified value is placed from every node to ground. This can resolve problems with floating nodes. Integer value. If non-zero will be used to initialise random number generator used for Monte Carlo analysis distribution functions. See Seeding the Random Number Generator on page 220 Maximum total number of iterations permitted for source stepping algorithm. Set to zero to disable limit

PTAMAXITERS

20000

PTAOUTPUTVECS

false

RELTOL

0.001

RELTOLMAX

0.01

RSHUNT

Infinite

SEED

SENSFILE SOURCEMAXITERS

SENS.TXT Specify name of sensitivity data file. 1000

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Option name
TEMP

Default value
27

Description
Unit = C Operating temperature of circuit. Note this value can be overridden locally for some devices. You can also use .TEMP for this. Equivalent to ACCT Minimum break point for transmission lines. Works in the same way as MINBREAK but only for break points generated by lossless transmission lines. Default = MINTIMESTEP * 5e-5 Unit = C Temperature at which model parameters are defined. This can be overridden in the model control. This only affects transient analysis. It is a relative value that is used to determine an acceptable value for the local truncation error before an analysis point is accepted. Reducing this value cause the simulator to model the effects of energy storage elements more accurately at the expense of simulation time. See Accuracy and Integration Methods on page 238 Forces compaction of data for lossy transmission lines. This speeds up simulation at the expense of accuracy.

TIMESTATS TLMINBREAK

false See note

TNOM

27

TRTOL

TRYTOCOMPACT

Off

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Option name
VNTOL

Default value
1

Description
Unit = V The absolute voltage error tolerance. Circuits with large voltages present (>100) may benefit from an increase in this value. See Accuracy and Integration Methods on page 238 Unit = V VNTOL selectively relaxed to this value if needed to allow transient analysis to continue. Number of columns used for list file output. This may be set to any reasonable value and not limited to the choice of 80 or 132 as with SPICE2 Define filecontaining wire table used for the digital simulators wire delay. See Wire Delay on page 252

VNTOLMAX

1m

WIDTH

80

WIRETABLE

none

.PARAM
.PARAM parameter_name [=] parameter_value [parameter_name [=] parameter_value]...
Defines a simulation variable for use in an expression. Expressions may be used to define device parameters, to define model parameters, for arbitrary sources and to define variables themselves. See Using Expressions on page 28 for details. parameter_name parameter_value Sequence of alpha-numeric characters. Must begin with a letter or underscore. May not contain spaces. Either: A constant OR An expression enclosed by '{' and '}'. See Using Expressions on page 28 Examples
.PARAM .PARAM .PARAM .PARAM Vthresh = 2.4 Vthresh = {(Vhigh+Vlow)/2} F0 1k Alpha 1 C1 {2*c2} R1 {2/(2*pi*freq*C1*alpha}

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Netlist Order .PARAM controls that resolve to a constant are order independent; they can be placed anywhere in a netlist. They can even be placed after another .PARAM expression that depends on its value (but note this does not apply in subcircuits). .PARAM controls that are defined as an expression that depends on other .PARAMs also defined as an expression must be placed in sequential order. For example, the following is OK:
.PARAM .PARAM .PARAM .PARAM C2 {C1*alpha*alpha/4} C1 1n alpha 1 R1 {2/(2*PI*F0*C2*alpha}

The first .PARAM depends on alpha and C1 which are defined later in netlist. This is OK (as long as it is not in a subcircuit) because alpha and C1 are constants. The fourth .PARAM depends on C2 which is defined as an expression. The definition for must - and does in the above example - come before the definition of R1. The following would yield an error as the definition for C2 comes after the definition of R1:
.PARAM .PARAM .PARAM .PARAM R1 {2/(2*PI*F0*C2*alpha} C1 1n alpha 1 C2 {C1*alpha*alpha/4}

Note that .PARAMs inside subcircuits are local to the subcircuit. This is explained in next section. Subcircuit Parameters Parameters may be declared within sub circuits. E.g
.subckt ADevice n1 n2 n3 n4 .PARAM Vthresh 3.5 ... ... ends

In the above example, in reference to Vthresh within the subcircuit would use the value declared by the .PARAM declared inside the subcircuit. That value would not be available outside the subcircuit definition. Parameters may also be passed to subcircuits. E.g.
X1 1 2 3 4 ADevice : threshold=2.4

or
X1 1 2 3 4 ADevice params: threshold=2.4

Any reference to threshold within the subcircuit definition would use that value. Default values for parameters may also be specified in subcircuit definition:
.subckt ADevice n1 n2 n3 n4 params: threshold=2.4 ...

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.ends

If that subcircuit is called without specifying threshold the default value of 2.4 will be used. Note that it is not compulsory to declare default values. Using .PARAM in Schematics .PARAM controls may be appended to the netlist created by the schematic editor. For information on how to do this, refer to Adding Extra Netlist Lines on page 12. .PARAM in Libraries .PARAM controls may be included in libraries specified using .LIB or by global definitions. SIMetrix will search such libraries for any parameters used in expressions that are not found in the netlist.

.PRINT
.PRINT TRAN|AC|DC|NOISE|TF vector|{expression} ...
Instructs the simulator to output selected simulation data to the list file in tabulated form. Where: vector expression Notes A traditional SPICE2 command, this was not supported by SIMetrix until release 4.0. It is SPICE2 compatible but also supports some additional features: NOISE and TF results may be output as well as TRAN, AC and DC You can put expressions as well as single values enclosed in '{' and '}'. E.g. .PRINT TRAN {vout-q5_c} You can use the SPICE2 style method of accessing single voltages, differential voltages and device currents. These are of the form: Single ended voltage Name of vector to print. May be in SIMetrix native format or traditional SPICE format (see notes below). Arithmetic expression of vectors

funcname(nodename)
Differential voltage

funcname(nodename, nodename)
Device current

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Where: funcname nodename device_name Available functions: Function to be applied. For available list, see below. Node name as specified in the netlist. Name of device for current.

Function name
V V VM VP VR VDB VG I IB IB IC ID IE IG IS IS IM IP

Argument
node name node name node name node name node name node name node name BJT name MOSFET name BJT name MOSFET/JFET name BJT name MOSFET/JFET name MOSFET/JFET name BJT name Two term device Two term device

Analysis mode
Transient AC AC AC AC AC AC TRAN TRAN TRAN TRAN TRAN TRAN TRAN TRAN AC AC

Meaning
Voltage at node Voltage magnitude at node Voltage magnitude at node Voltage phase at node Real voltage at node dbV at node group delay at node Current in device Base current Bulk current Collector current Drain current Emitter current Gate current Source current Substrate current Device current Current phase

two term. device name TRAN

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Function name
IR II IDB IG

Argument
Two term device Two term device Two term device Two term device

Analysis mode
AC AC AC AC

Meaning
Current real part Current imaginary part Current dB Current group delay

.PRINT controls may be placed inside a subcircuit definition in which case the device and node names refer to local devices and nodes. Output will be listed for every instance of the subcircuit. For transient analysis the results are displayed at the interval specified by the time step parameter on the .TRAN control. If this is zero or omitted, it defaults to (tstop-tstart)/ 50. The data is created by interpolation unless the NORAW option (see page 195) is specified in which case a time step is forced at the time step interval. Examples
.PRINT .PRINT .PRINT .PRINT .PRINT TRAN V(VOUT) TRAN VOUT TRAN V(VPos, VNeg) TRAN {Vpos-VNeg} AC VDB(VOUT)

.PZ
.PZ N1 N2 N3 N4 CUR|VOL POL|ZER|PZ
N1, N2 N3, N4 CUR VOL Input nodes Output nodes transfer function is of the type (output voltage)/(input current) transfer function is of the type (output voltage)/(input voltage)

Usually the last parameter would be PZ which instructs the simulator to find both poles and zeros. The alternatives instruct it to find one or the other. This may be used if the simulator aborts because it didn't converge on poles or on zeros, at least it can be instructed to find the other. To view the results of the pole-zero analysis select the command shell menu Graphs and Data|List Pole-zero results. The poles and zeros will be listed in complex form.

.SENS
.SENS V(nodename [,refnodename])| I(sourcename) 209

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This control instructs the simulator to perform a DC sensitivity analysis. In this analysis mode, a DC operating point is first calculated then the linearised sensitivity of the specified circuit voltage or current to every model and device parameter is evaluated. The results are output to a file (SENS.TXT by default but can be changed with SENSFILE option) and they are also placed in a new data group. The latter allows the data to be viewed in the message window (type Display) at the command line and can also be accessed from scripts for further analysis.

.SUBCKT and .ENDS

.SUBCKT subcktname n1 [ n2 ]... + [ [params:] param_name1 [=] param_value1 + [param_name2 [=] param_value2]...]
This control begins a subcircuit definition. subcktname Subcircuit name. This must begin with a letter but may contain any legal ASCII character except any whitespace (space, tab) or ' . ' . The name must be unique i.e. no other subcircuits may have the same name. Node names available externally. Must not be zero. Parameter name and value. This sets default values for parameters used within the subcircuit. These values can be overridden for each subcircuit instance. See Using Expressions on page 28 for more info. Note that it is not compulsory to declare default values for subcircuit parameters.

n1, n2 etc. param_name, param_value

IMPORTANT: Either the params: specifier or the first '=' may be omitted but not both. If both are omitted it becomes impossible for the netlist scanner to tell the difference between parameter names and node names.

.ENDS
Terminates a subcircuit definition. A subcircuit consists of a .subckt control followed by a series of device or model descriptions and terminating in a .ends control. A subcircuit is a circuit that can be called into the main circuit (or indeed another subcircuit) by reference to its name. The .subckt control is used to define the subcircuit while a subcircuit call - an 'X' device - is used to create an instance of that subcircuit. Subcircuits have a number of uses: To repeat a commonly used section of circuit. To hide detail from the main circuit to aid circuit readability. To distribute models of integrated devices such as op-amps.

For a detailed discussion see Subcircuits on page 39

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Subcircuit definitions usually reside in a text file and are read in as libraries. See User's Manual for further details.

.TEMP
.TEMP temperature
This control sets the default simulation temperature. Some devices can override this on a per instance basis. Units are degrees centigrade.

.TF
.TF inner_sweep_spec [ V ] pos_out_node [ VN ] neg_out_node + [[ INSRC ] in_source ] [ F frequency ] [SWEEP outer_sweep_spec ] .TF inner_sweep_spec I source [ INSRC in_source ] + [ F frequency ] [SWEEP outer_sweep_spec ] Spice Compatible: .TF V( pos_out_node [, neg_out_node ]) in_source .TF I (source) [ INSRC ] in_source
This control instructs the simulator to perform a small signal transfer function analysis. pos_out_node neg_out_node in_source inner_sweep_spec outer_sweep_spec Output node. Output reference node. Defaults to ground if omitted for standard SPICE syntax. Name of input source to which input noise will be referred. See General Sweep Specification on page 168 for syntax. Defines sweep mode. If specified, analysis will be repeated according to this specification. See General Sweep Specification on page 168 for syntax. Frequency at which analysis will be performed for nonfrequency sweeps. Default 0. Voltage source to specify output current.

frequency source Notes

The SIMetrix transfer function analysis remains syntax compatible with the SPICE version but is substantially enhanced. The SPICE version performs the analysis at a

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single point with frequency = 0. The SIMetrix implementation performs a swept analysis using the same sweep algorithm used for AC, DC and NOISE. Transfer function analysis is similar to AC analysis in that it performs a swept small signal analysis. However, whereas AC analysis calculates the response at any circuit node from a (usually) single input source, transfer function analysis calculates the individual responses from each source in the circuit to a single specified output node. This allows, for example, the series mode gain, common mode gain and power supply rejection of an amplifier to be measured in one analysis. The same measurements could be performed using AC analysis but several of them would need to be run. Transfer function mode also calculates output impedance or admittance and, if an input source is specified, input impedance. The names of the output vectors will be of the form

Input voltage, output voltage source_name#Vgain

Input voltage, output current source_name#Transconductance Input current, output voltage source_name#Transresistance Input current, output current source_name#Igain
Output impedance for voltage out will be called Zout. For a current output, the output admittance will be calculated and will be named Yout. If an input source is specified the input impedance will be calculated and called Zin. Note that although the syntax for .TF retains compatibility with SPICE and earlier versions of SIMetrix, the output provided is slightly different. Firstly, the data is complex even if F=0 and secondly the names of the output vectors are different as detailed above. Examples SPICE compatible. Outputs results at DC.
.TF V(Vout) Vin

As above but decade sweep from 1k to 100k

.TF FREQ DEC 25 1K 100K V(Vout, 0) Vin

Note that in the above example the '0' in V(Vout, 0) is compulsory. If is omitted, Vin will be assumed as the reference node.

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.TRACE
.TRACE vector_name [vector_name ...] graph_id
Set up a trace. This is graph plot that is updated as the simulation runs. Where vector_name is the name of a net or pin graph_id is an integer between 1 and 999 to specify which graphs traces should use - see explanation below

graph_id is an arbitrary number that makes it possible to direct traces to different graphs. Two traces with the same id will be always be put in the same graph. Traces from subsequent simulations with that id will also go to that graph if it still exists otherwise a new one will be created. To force two traces to go to separate graphs, use different id's. Note that it doesn't matter what the id's value actually is - it could be 1 or 100 - as long as traces that must go to the same graph use the same value. Note that the AutoAxis feature available for normal plotting also works for Traces. So if a current and voltage trace are both directed to the same graph, separate axes will be created for them. Examples .trace v1_p 1 q1#c 1 In the above example a voltage - v1_p - and a current - q1#c - will both be traced on the same graph. As they have different units, the AutoAxis feature will force the curves to two different y axes. .trace v1_p 1 q1#c 2 In this example the voltage and current traces will be directed to different graph sheets. Notes The .TRACE control has now been largely superseded by the .GRAPH control (page 177) which is much more flexible. However, the .TRACE control is still useful for specifying multiple traces on a single line. .GRAPH can only specify one signal at a time.

.TRAN
.TRAN tstop
OR

.TRAN tstep tstop [ tstart [ tmaxstep ]] [ UIC ] + [SNAPSTEP sstart sstop sstep] + [SNAPSHOT slist] + [SNAPMODE=DCOP|SAVESTATE|ALL] + [FAST=fast_start] [RTNSTEP=rtnstep [RTNSTOP=rtnstop] + [RTNSTART=rtnstart] ] [SWEEP sweep_spec ] 213

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This control instructs the simulator to perform a transient analysis. In this mode the simulator computes the behaviour of the circuit over the specified time interval. The circuit's currents and voltages are calculated at discrete time points separated by a variable time step. This time step is adjusted automatically by the simulator according to circuit activity. The circuit may contain any number of time varying voltage and current sources (stimuli) to simulate external signals, test generators etc. tstep This defines the interval for tabulated results specified by the .PRINT control. It also defines the output interval for all data if the NORAW option is specified. If there are no .PRINT controls in the netlist and NORAW is not being used, this can be set to zero or omitted altogether as in form 1 above. If set to zero it defaults to (tstop-tstart)/50 tstep is also used to define default values for pulse and exponential stimuli. Note that if tstep and NORAW are specified a time point is forced at tstep intervals to calculate the output. This differs from other SPICE programs which generate output at tstep by interpolation. tstep does not control the time step used by the simulator. This is controlled automatically according to circuit activity. tstop Stop time. Note that if running in GUI mode, a transient analysis can be restarted from the front end using the RestartTran command. See User's Manual for details. Start time. This is the time at which the storage of transient analysis outputs commences. It is not the time at which the analysis begins; this is always zero. tstart is zero if it is omitted. Maximum time step. The simulator uses the largest time step possible to achieve the required accuracy but will not increase it beyond this value. If not specified it is set to (tstop-tstart)/50 . If specified a DC operating point is not calculated and initial condition specifications are used instead If specified, the simulation will run at reduced accuracy but higher speed for the time specified by this parameter. The reduced accuracy is implemented by altering a number of tolerances and internal parameters. See notes below for more details. If this parameter is specified, Real Time Noise analysis will be enabled. Note that this feature is not available with all versions of the program. rtnstep specifies the step size of the noise generators. See Real Time Noise Analysis on page 216. Specifies time at which real time noise generators are switched on. Specifies time at which real time noise generators are switched off.

tstart

tmaxstep

UIC fast_start

rtnstep

rtnstart rtnstop

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sstart sstop sstep slist Time at which snapshot saving begins. See below for information on snapshots. Time at which snapshot saving stops. See below for information on snapshots Interval between snapshot points. See below for information on snapshots One or more values defining absolute times at which snap shots are saved. See below for information on snapshots Snapshot mode. DCOP: Saves bias point information only. SAVESTATE: Saves state of circuit for subsequent reload for small signal analysis ALL: Both of the above The default is DCOP Fast Start If the FAST parameter is specified, the simulation will begin with a number of tolerances and internal parameters altered to speed up the simulation at the expense of accuracy. Just before the end of the fast start period, these tolerances and parameters will be gradually restored to their normal values. Fast start is an aid for simulating circuits such as switching power supplies and oscillators for which the initial start up period is not of interest but takes a long simulation time. Note that although the fast start interval can run sometimes as much as twice as quickly as normal, the fact that accuracy is impaired can mean that the final steady state reached may not be very accurate. This means that after the fast start period, an additional settling time may be required for full accuracy to be reached. Fast start sets the values of POINTTOL and RELTOL according to the value specified by FASTPOINTTOL and FASTRELTOL respectively. Snapshots This feature allows the state of a simulation to be saved at user specified times during a transient analysis. The states saved can subsequently be reloaded to perform small signal AC analyses. This allows the small signal response of a circuit to be examined at any point during a transient analysis. This is especially useful in situations where a circuit is found to be unstable in a transient run but this instability cannot be reproduced at the operating point usually derived for an AC analysis. The bias point information at the snapshot time may also optionally be saved. This information is output to the list file. To specify snapshot output, specify either the SNAPSHOT or SNAPSTEP keywords with their associated parameters.

DCOP, SAVESTATE, ALL

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To initialise a small signal analysis with snapshot data, you must specify the SNAPSHOT step mode of a multi-step analysis. See Multi Step Analyses on page 170 for details

Real Time Noise Analysis

This is an extension of transient analysis rather than a separate analysis mode. When activated, real time noise sources are added to all noisy devices with a magnitude and frequency distribution calculated using the same equations used for small signal analysis. This allows noise analysis to be performed on sampled data systems and oscillators. To use real time noise analysis, the following parameters may be added to the .TRAN analysis line. RTNstep Source step size in seconds. This will need to be small enough to cover the frequency range of interest. The noise magnitude starts rolling off at about 1/3*stepsize. Default=0 i.e. real time noise analysis disabled. Optional. Time after analysis start at which the noise sources will be enabled. Default = zero Optional. Time after analysis start at which the noise sources will be disabled. Default = stop time.

RTNstart RTNstop

The parameters added to the .TRAN line must be named in the same way as .MODEL parameters are named. Example
.TRAN 0 1m RTNstep=1u RTNstart=500u

Analysis time 1m, RTN step size 1u, real time sources start at 500u. The step size parameter - i.e. the first parameter on the .TRAN line - must be supplied if real time noise parameters are to be included. This is only to comply with the syntax rules not because the step size is needed for any other purpose. In most cases, just set it to zero as in the above example. Test Results To test real time noise and verify it's accuracy we ran a test on a number of circuits which compare AC noise with real time noise. The procedure was to run real time noise analysis 50 times then plot the averaged Fourier spectrum. This test was repeated for different transient run times and step sizes to build a noise spectrum over several decades. The graph below is the result of one such test. This was carried out on the BSIM3 buffer circuit provided in one of the examples except that a value for AF - the flicker noise parameter - was added to the models. As can be seen in the graph below the real time noise results strongly follow the AC noise results. Similar tests were performed on circuits containing each of the major noise generating devices including diodes, BJTs, JFETs, resistors (including its flicker noise parameter) and also the Philips MOS9 and MEXTRAM devices. All showed results similar to below with a close similarity between AC noise and real time noise.

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These tests were performed using a simple script. This script is called rtntest.sxscr and can be found on the installation CD at SCRIPTS\EXAMPLES.

10

2mS RTNstep=2uS 20uS RTNstep=20nS 200n RTNstep=100p

400n AC Noise result 200n

100n

40n

20n

1k

10k

100k

1M

10M

100M

1G

Frequency / Hertz

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Chapter 7 Monte Carlo Analysis

Overview
Monte Carlo analysis is a procedure to assess manufacturing yields by repeating simulation runs with varying applied random variations to component parameters. The technique is very powerful and usually gives a more realistic result than worst-case analysis which varies component values to their extremes in a manner which produces the worst possible result. The implementation of Monte Carlo analysis in SIMetrix has been designed to be quick to set up for simple cases while still providing the required flexibility for more advanced requirements as might be required for integrated circuit design. SIMetrix offers a level of flexibility for tolerance specification that cannot be found in other products including some high priced UNIX based applications. It is possible, for example, for different model parameters to be dependent on a single random variable. This makes it possible to model the fact that a number of model parameters might be dependent on a single physical characteristic, for example, the base width of a bipolar transistor. Of course, lot tolerances are also implemented accounting for the matching of devices in integrated circuits and other multiple components built onto a common substrate. However, in many products, lot tolerances can only be applied to the same type of device. In SIMetrix it is possible to model parametric relationships between different types of device which occur in integrated circuits but which are rarely taken into account. As well as conventional multiple step Monte Carlo analysis, single step Monte Carlo sweeps may also be performed. These are available for the four swept modes, .AC, .DC, .NOISE and .TF. For example, a Monte Carlo analysis of the DC offset voltage of an amplifier can be performed using a single run of .DC using a special sweep mode. This is dramatically faster than the alternative of repeated .OP runs. This type of analysis can also be used to analyse the gain of an amplifier at a single frequency using .AC or .TF or even the noise, again at a single frequency, using .NOISE.

Specifying a Monte Carlo Run

Monte Carlo runs are invoked in the same way as multi-step analyses (see General Sweep Specification on page 168). The basic syntax is:

.analysis_name analysis_parameters SWEEP MONTE num_runs

Where: .analysis_name Dot control for analysis. Either .TRAN, .AC, .DC, .NOISE, .TF

analysis_parameters Specific parameters for that analysis num_runs Number of runs

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Examples Run 10 Monte Carlo runs for 1mS transient analysis
.TRAN 1m SWEEP MONTE 10

100 Runs of a DC Sweep

.DC V1 0 5 0.01 SWEEP MONTE 100

AC sweep of voltage source V5 from -300mV to 300mV. Repeat 50 times

.AC DEVICE=V5 LIN 100 -300m 300m F=100000 SWEEP MONTE 50

Specifying a Single Step Monte Carlo Sweep

Monte Carlo sweep is one of the six modes available to the swept analysis modes, .AC, .DC .NOISE and .TF. The other modes are explained in General Sweep Specification on page 168. The general syntax is:

.analysis_name MONTE num_points analysis_parameters

Where: .analysis_name Dot control for analysis. Either .AC, .DC, .NOISE, .TF

analysis_parameters Specific parameters for that analysis num_points Examples 1000 point Monte Carlo sweep.
.DC MONTE 1000

Number of points in sweep

AC Monte Carlo sweep 100 steps. Frequency = 10K. This is useful if - say - you are interested in the gain of an amplifier at one frequency and it needs to lie within a defined tolerance. Previously you would need to repeat an AC sweep at a single frequency to achieve this which could take a long time especially if the circuit has a difficult to find operating point. The analysis defined by the following line will take very little time even for a large circuit.
.AC MONTE 100 F=10K

Log File
Unless explicitly disabled with the NOMCLOG option, a log file will always be generated for Monte Carlo analyses. It has the default name of MCLOG.TXT but this can be changed with the MCLOGFILE option. Here is an example of an actual output
Run 1: Seed=1226978751 Run 2: Seed=1521158126

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Run 1 Value 5.9185638 283.10907 368.7899a 5.9425623 285.27225 354.1045a 5.8957932 280.37304 359.6985a 5.9020281 280.04731 367.7199a 5.9178142 276.57192 364.6015a 5.9398543 277.08078 362.7751a 5.9281884 276.66227 360.4184a 5.8811702 280.33672 361.0834a 5.9001842 281.41183 358.8014a Run 2 Value (Dev.) 5.8463766 (-0.90887%) 130.81497 (-40.5386%) 219.7988a (-42.1582%) 5.8262401 (-1.25017%) 129.91303 (-40.9486%) 220.1177a (-42.0743%) 5.787891 (-1.90015%) 130.28208 (-40.7809%) 225.8706a (-40.5604%) 5.8132485 (-1.47036%) 129.20488 (-41.2705%) 222.1358a (-41.5432%) 5.8096709 (-1.531% ) 129.93424 (-40.939% ) 222.7107a (-41.3919%) 5.8354342 (-1.09434%) 127.82878 (-41.896% ) 225.9888a (-40.5293%) 5.8421649 (-0.98026%) 129.29449 (-41.2298%) 227.0065a (-40.2614%) 5.8260238 (-1.25383%) 131.98533 (-40.0067%) 218.837a (-42.4113%) 5.8517296 (-0.81814%) 128.02565 (-41.8065%) 221.6128a (-41.6809%)

Device Q10.D1:bv Q10.Q1:bf Q10.Q1:is Q11.D1:bv Q11.Q1:bf Q11.Q1:is Q12.D1:bv Q12.Q1:bf Q12.Q1:is Q13.D1:bv Q13.Q1:bf Q13.Q1:is Q14.D1:bv Q14.Q1:bf Q14.Q1:is Q4.D1:bv Q4.Q1:bf Q4.Q1:is Q7.D1:bv Q7.Q1:bf Q7.Q1:is Q8.D1:bv Q8.Q1:bf Q8.Q1:is Q9.D1:bv Q9.Q1:bf Q9.Q1:is

Nom. 5.9 220 380a 5.9 220 380a 5.9 220 380a 5.9 220 380a 5.9 220 380a 5.9 220 380a 5.9 220 380a 5.9 220 380a 5.9 220 380a

(Dev.) (0.314641%) (28.68594%) (-2.95004%) (0.721395%) (29.66921%) (-6.8146% ) (-713ppm ) (27.44229%) (-5.34249%) (343.74ppm) (27.29423%) (-3.2316% ) (0.301936%) (25.71451%) (-4.05223%) (0.675496%) (25.94581%) (-4.53287%) (0.47777% ) (25.75558%) (-5.15304%) (-0.31915%) (27.42578%) (-4.97804%) (31.215ppm) (27.91447%) (-5.57857%)

The Device column provides the name of the device and its model or instance parameter that is being reported. Q10.D1 is a diode ref D1 inside subcircuit Q1, BV is the model parameter. The Nom column displays the nominal value for that parameter. Two columns are listed for each run. Value is the actual value of the parameter and (Dev.) is the deviation from the nominal. The Seed values displayed for each run at the top are the values used to seed the random number generator. These can be used to set the SEED option in order to repeat a particular random set. See below for more details.

Seeding the Random Number Generator

The random variations are created using a pseudo random number sequence. The sequence can be seeded such that it always produces the same sequence of numbers for a given seed. In Monte Carlo analysis, the random number generator is seeded with a new value at the start of each run and this seed value is displayed in the log file (see above). It is also possible to fix the first seed that is used using the SEED option. This makes it possible to repeat a run. To do this, note the seed value of the run of interest then add the line:

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.OPTIONS SEED=seed_value For example if you wanted to repeat run 2 in the above example you would add this line: .OPTIONS SEED=1521158126 The first run of each Monte Carlo analysis will use the same random values as run 2 above. Note this assumes that only changes in values are made to the circuit. Any topology change will upset the sequence.

Specifying Tolerances
Overview
Tolerances for Monte Carlo analysis may be specified by one of the following methods: 1. 2. 3. Using a distribution function in an expression. Using the device parameters TOL, MATCH and LOT Using a tolerance model

1. above is new to release 4 and is the most general and flexible. 2 and 3 are provided primarily for backward compatibility but may also be more convenient in some circumstances.

Distribution Functions
To specify Monte Carlo tolerance for a model or device parameter, define the parameter using an expression (see Using Expressions on page 28) containing one of the following 12 functions:

Name
GAUSS GAUSSL UNIF UNIFL WC WCL GAUSSE GAUSSEL

Distribution
Gaussian (3-sigma) Gaussian (3-sigma) Uniform Uniform Worst case Worst case Gaussian logarithmic (3sigma) Gaussian logarithmic (3sigma)

Lot?
No Yes No Yes No Yes No Yes

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Name
UNIFE UNIFEL WCE WCEL

Distribution
Uniform logarithmic Uniform logarithmic Worst case logarithmic Worst case logarithmic

Lot?
No Yes No Yes

The logarithmic versions are included for compatibility with release 3.1 and earlier but are nevertheless useful for some parameters which are logarithmic in nature such as the IS parameter for PN junctions. The graphs below show the characteristics of the various distributions. The curves were plotted by performing an actual Monte Carlo run with 10000 steps.
5

WC
4

WCE
3 k 2

0 350

GaussE
300

UnifE
250

Gauss

200

150

Unif

100

50

0 V

0.5

1.5

2 500mV/div

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Examples Apply 50% tolerance to BF parameter of BJT with gaussian distribution.
.MODEL NPN1 NPN IS=1.5e-15 BF={180*GAUSS(0.5)}

Lot Tolerances The lot versions of the functions specify a distribution to be applied to devices whose tolerances track. These functions will return the same random value for all devices that reference the same model. Alternatively, a device can be given a lot value as was required with earlier versions of SIMetrix. Devices must have the same lot value, and also reference the same model, in order to track. This allows, for example, two or more chips using the same process to be simulated together without having to rename the models. Examples Specify 50% uniform lot tolerance and 5% gaussian device tolerance for BF parameter
.MODEL NPN1 NPN IS=1.5E-15 BF={180*GAUSS(0.05)*UNIFL(0.5)}

Here is an abbreviated log file for a run of a circuit using 2 devices referring to the above model:
Device Q1:bf Q2:bf Nom. 180 180 Run 1 Value (Dev.) 93.308486 (-48.162% ) 91.173893 (-49.3478%) Run 3 Value (Dev.) 185.95824 (3.310133%) 190.8509 (6.02828% ) Run 2 Value (Dev.) 241.3287 (34.0715% ) 245.09026 (36.16126%) Run 4 Value (Dev.) 210.46439 (16.92466%) 207.04202 (15.02335%)

Device Q1:bf Q2:bf

Nom. 180 180

For the four runs BF varies from 91 to 245 but the two devices never deviate from each other by more than about 2.7%. Notes The tracking behaviour may not be as expected if the model definition resides within a subcircuit. When a model is defined in a subcircuit, a copy of that model is created for each device that calls the subcircuit. Here is an example:
XQ100 VCC INN Q100_E 0 NPN1 XQ101 VCC INP Q101_E 0 NPN1 .SUBCKT NPN1 1 2 3 SUB Q1 1 2 3 SUB N1 Q2 SUB 1 2 SUB P1 .MODEL N1 NPN IS=1.5E-15 BF={180*GAUSS(0.05)*UNIFL(0.5)} .ENDS

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In the above, XQ100 and XQ101 will not track. Two devices referring to N1 inside the subcircuit definition would track each other but different instances of the subcircuit will not. To make XQ100 and XQ101 track, the definition of N1 should be placed outside the subcircuit. E.g.
XQ100 VCC INN Q100_E 0 NPN1 XQ101 VCC INP Q101_E 0 NPN1 .SUBCKT NPN1 1 2 3 SUB Q1 1 2 3 SUB N1 Q2 SUB 1 2 SUB P1 .ENDS .MODEL N1 NPN IS=1.5E-15 BF={180*GAUSS(0.05)*UNIFL(0.5)}

Arguments to Distribution Functions - the key Value Each of the distribution functions takes 1 or 2 arguments. The first argument is the tolerance while the second is an optional key value. The key is an arbitrary number preferably an integer - which, in effect, names a random variable for which the results of that distribution function will be based. Another call to the same distribution function in the same model and with the same key value, will also be based on the same random variable and return the same value for each Monte Carlo step. The key make it possible to accommodate parameters that tend to track each other possibly because they depend on the same physical characteristic of the device. Example Suppose the BF and TF parameters of a BJJT tend to track each other. That is a 50% increase in BF tends to be accompanied by a 50% increase in TF (there is no physical basis for this; it's just an example). The following model definition would implement this:
.MODEL NPN1 NPN BF={UNIF(0.5,1)*180} TF={1e-11*UNIF(0.5,1)}

For all devices using that model, BF and TF will always have a fixed relationship to each other even though each parameter can vary by +/-50% from one device to the next. Here is the log of a run carried out on a circuit with two of the above devices:
Device Q1:bf Q1:tf Q2:bf Q2:tf Nom. 180 10p 180 10p Run 1 Value 226.52869 12.58493p 179.58993 9.977218p (Dev.) (25.84927%) (25.84927%) (-0.22782%) (-0.22782%) Run 2 Value 117.2733 6.515184p 164.21785 9.123214p (Dev.) (-34.8482%) (-34.8482%) (-8.76786%) (-8.76786%)

Notice that the BF and TF parameters always deviate by exactly the same amount for each device. However, the two devices do not track each other. If this were needed, the lot versions of the functions could be used instead. E.g.
.MODEL NPN1 NPN BF={UNIFL(0.5,1)*180} TF={1e-11*UNIFL(0.5,1)}

This is the log for such an example:

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Run 1 Value 104.57858 5.809921p 104.57858 5.809921p Run 2 Value 93.855425 5.21419p 93.855425 5.21419p

Device Q1:bf Q1:tf Q2:bf Q2:tf

Nom. 180 10p 180 10p

(Dev.) (-41.9008%) (-41.9008%) (-41.9008%) (-41.9008%)

(Dev.) (-47.8581%) (-47.8581%) (-47.8581%) (-47.8581%)

Distribution Functions and .PARAM The key mechanism described above only works for parameters within the same model. If you wish to define a fixed relationship between parameters of different models then you can define a random variable using .PARAM. Using a distribution function in a .PARAM expression in effect creates a global random variable. .PARAM expressions are only evaluated once for each Monte Carlo step so the parameter it defines will be the same value wherever it is used. Note that .PARAM values used for this purpose should be defined at the top level i.e. not in a sub-circuit. If defined in a sub-circuit they will be local to that sub-circuit so each instance of the sub-circuit will use its own random variable.

TOL, MATCH and LOT Device Parameters

These parameters may be used as a simple method of applying tolerances to simple devices such as resistors. The TOL parameter specifies the tolerance of the device's value. E.g.
R1 1 2 1K TOL=0.05

The above resistor will have a tolerance of 5% with a gaussian distribution by default. This can be changed to a uniform distribution by setting including the line:
.OPTIONS MC_ABSOLUTE_RECT

in the netlist. Multiple devices can be made to track by specifying a LOT parameter. Devices with the same LOT name will track. E.g.
R1 1 2 1K TOL=0.05 LOT=RES1 R2 3 4 1k TOL=0.05 LOT=RES1

R1 and R2 in the above will always have the same value. Deviation between tracking devices can be implemented using the MATCH parameter. E.g.
R1 1 2 1K TOL=0.05 LOT=RES1 MATCH=0.001 R2 3 4 1k TOL=0.05 LOT=RES1 MATCH=0.001

R1 and R2 will have a tolerance of 5% but will always match each other to 0.1%. MATCH tolerances are gaussian by default but can be changed to uniform by specifying

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.OPTIONS MC_MATCH_RECT

Distributions are always the logarithmic versions as described in Distribution Functions on page 221 If using device tolerance parameters, note that any absolute tolerance specified must be the same for all devices within the same lot. Any devices with the same lot name but different absolute tolerance will be treated as belonging to a different lot. For example if a circuit has four resistors all with lot name RN1 but two of them have an absolute tolerance of 1% and the other two have an absolute tolerance of 2%, the 1% devices won't be matched to the 2% devices. The 1% devices will however be matched to each other as will the 2% devices. This does not apply to match tolerances. It's perfectly OK to have devices with different match tolerances within the same lot.

Tolerance Models
Overview Tolerance models are an alternative method of applying tolerances to device models to the distribution function method described in an earlier section. The distribution function method is in general more flexible and is recommended for most applications. However, the tolerance model method has some advantages as follows: It is compatible with earlier SIMetrix versions from 2.0 to 3.1 It allows tolerances to be applied to devices without modifying the main model.

Definition The format for a tolerance model:

.MODEL modelname modeltype.tol parameter_list

modelname must be the same name as the normal model for the device while modeltype must be the same type. So for example a tolerance model for a Q2N2222 transistor might be:
.MODEL Q2N2222 npn.tol BF=0.5

This will vary the BF parameter over a +/- 50% range for all BJTs referring to the Q2N2222 model. The above model only specifies one parameter but you can place any parameter specified for that device in a tolerance model. For MOSFETs the level number must be included with the tolerance model otherwise the model will be ignored. Important note Note that tolerances will only be applied to parameters explicitly specified in the base model for the device. Tolerances will not be applied to default values. If the base model for the Q2N2222 device in the above example is:

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.MODEL Q2N2222 npn ( IS=2.48E-13 VAF=73.9 NE=1.2069 + TF=4.00E-10)

The BF parameter in the tolerance model would not be used as it is not specified in the base model. If the base model was modified to:
.MODEL Q2N2222 npn ( IS=2.48E-13 VAF=73.9 NE=1.2069 + TF=4.00E-10) BF=400

Then the BF tolerance would be applied. Matching Devices Using Tolerance Models To match devices with tolerances defined using a tolerance model, specify the LOT parameter on the device line. E.g.
Q1 1 2 3 0 Q2N2222 LOT=lot1 Q2 4 5 6 0 Q2N2222 LOT=lot1 .MODEL Q2N2222 npn.tol BF=0.5

In the above example the BF parameter for Q1 and Q2 will always be the same. To specify a deviation for matched devices requires a match tolerance model definition. This is of the form:

.MODEL modelname modeltype.match parameter_list

modelname must be the same name as the base model for the device while modeltype must be the same type. So for example a matching tolerance model for a Q2N2222 transistor might be:
.MODEL Q2N2222 npn.match BF=0.5

Note that the components will only be matched if they all refer to the same model. Any components with the same lot name but referring to a different model treated as if they belong to a different lot.

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Chapter 8 Convergence and Accuracy

Overview
In transient and DC analyses, an iterative method is used to analyse the circuit. Generally, iterative methods start with an initial guess for the solution to a set of equations and then evaluate the equations with that guess. The result of that evaluation is then used to derive a closer estimate to the final solution. This process is repeated until a solution is found that is within the error tolerance required. SIMetrix and SPICE use a technique known as Newton-Raphson1 iteration which usually converges extremely rapidly. However, there are occasions when this process is either unreasonably slow or fails altogether. Under these circumstances the simulation will abort. SIMetrix offers superior convergence to all other products in its price bracket and possibly all PC based simulators generally. SIMetrix passes 100% of the circuits in the CircuitSim90 benchmark suite compared with about 60% for unmodified SPICE3. This performance has been achieved as a result of the following developments to the simulator core. Automatic pseudo transient analysis algorithm for operating point solution. See below for details. Enhancements to GMIN and source stepping algorithms to use a variable step size. (The standard SPICE3 variants use a fixed step). Junction GMIN DCOP Convergence Method Proprietary enhancements to transient analysis algorithm. Improvements to device models to remove discontinuities.

With these improvements, convergence failure with SIMetrix is extremely rare. However, it is impossible to eliminate this problem altogether and there still remain some circuits which fail. In this chapter we explain some of the causes of non-convergence and some of the strategies SIMetrix uses to prevent it. Also explained is what to do in the rare event that convergence fails.

DC Operating Point
Overview
As explained in DC Operating Point Algorithms on page 235 SIMetrix has four different algorithms at its disposal to solve the DC operating point. For this analysis mode to fail, and assuming the default settings are being used, all four algorithms must fail.

1.

Sir Isaac Newton 1674-1721 and Joseph Raphson 1648-1715. This algorithm has been around somewhat longer than circuit simulators!

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The following sections describe the possible reasons for failure of each mode and what can be done about them. The general procedure is as follows: 1. 2. 3. 4. Check your circuit. Check that all components are the correct way around and have the correct values. Make sure you haven't used 'M' when you meant 'Meg'. Refer to section Source and GMIN Stepping and see if GMIN or source stepping can be made to work. Refer to section Pseudo Transient Analysis to get pseudo transient analysis converging. Contact technical support. We don't officially offer a convergence fixing service and reserve the right to decline help. However, we are always interested in nonconverging circuits and usually we will look at your circuit to see if we can identify the problem.

Source and GMIN Stepping

By default, if these modes fail, SIMetrix will carry on and attempt pseudo transient analysis. It will not do so only if instructed not to using the dcopSequence option (See Controlling DC Method Sequence on page 237). Pseudo transient analysis usually succeeds but sometimes can take a long time so you may prefer to get one of these methods working instead. Also, if pseudo transient analysis fails it is desirable to first see if GMIN or source stepping can be made to work. There are a few options you can set to encourage these modes to converge. These are

Name
GMINSTEPITERLIMIT

Default Set to
20 100

What it does
The number of iterations attempted for each GMIN step

GMINMAXITERS

1000

0 (equivalent to Total number of infinity) iterations allowed for GMIN stepping 0 (equivalent to Total number of infinity) iterations allowed for source stepping

SOURCEMAXITERS

1000

It is only worth changing gminMaxIters or sourceMaxIters if the iteration limit is actually being reached. Often GMIN and source stepping fail to converge before the iteration limit is reached. To find out, select the command shell menu Simulator|Show Statistics. This displays, amongst other things, the number of iterations used for GMIN and/or source stepping. If they exceed 1000 then the iteration limit has been reached. This means that GMIN/source stepping may have succeeded if it had been given a chance.

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Pseudo Transient Analysis

Pseudo transient analysis is the most powerful method known and it is rare for it to fail. It is not however infallible and can go wrong for the following reasons: 1. 2. The transient analysis itself failed to converge. (This is rare) The circuit oscillates

Convergence failure in pseudo transient analysis You will get the error message
Cannot find DC operating point No convergence in pseudo transient analysis

The reasons why this may happen are the same as for transient analysis and are covered in Fixes for Transient Non-convergence on page 234. Circuit oscillation You will see the message
Cannot find DC operating point Iteration limit exceeded in pseudo transient analysis

The circuit can oscillate because: 1. 2. 3. 4. It is designed to i.e. it is or has an oscillator It is supposed to be stable but passes an unstable region during supply ramping It is supposed to be stable but has a fault in its design It is stable but is made unstable by the capacitors added during the pseudo transient analysis

If the circuit is an oscillator If 1. then you must disable the oscillator during the DC solution. You can do this by one of the following methods: 1. 2. Apply an initial condition to a point on the circuit that will break the oscillator's feedback loop. Use the capacitor/inductor PTAVAL parameter to change its value during pseudo transient analysis. This parameter can be applied to a component or components that form part of the oscillator. In the netlist the parameter is applied at the end of the component line. E.g for a capacitor:
C12 N2 N6 1.2n PTAVAL=1

In the above a 1.2n capacitor will take the value of 1 farad during pseudo transient analysis.

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The circuit is not supposed to be an oscillator If the circuit does not have any intentionally unstable elements then diagnosis of the problem is a little harder. Firstly, you need to rule out 4. above as a possible cause. As explained in DC Operating Point Algorithms on page 235, SIMetrix adds its own capacitors to your circuit during pseudo transient analysis in order to overcome potential problems with regenerative action. The problem is that these added capacitors can themselves make a circuit unstable. So the first thing to try is to inhibit the addition of these capacitors. To do this, add the following line to the netlist (See Adding Extra Netlist Lines on page 12 to find out how to add to a schematic).
.OPTIONS PTACONFIG=1

then re-run the simulation. The circuit is not supposed to be an oscillator but it is If this fails, then life gets even more complicated! If it fails with the message
Iteration limit exceeded in pseudo transient analysis

then it is very likely that the circuit is oscillating or entering an unstable region. If a different message is displayed go to The circuit doesn't oscillate but still doesn't converge below. To allow diagnosis of what is happening SIMetrix provides a method of analysing the circuit during the pseudo transient ramp. By default, no data is output during pseudo transient analysis but this can be changed as follows: 1. 2. Set the analysis mode to DC operating point only. Add the simulator option ptaOutputVecs by adding the following line to the netlist: .OPTIONS PTAOUTPUTVECS 3. Now run the simulation for a while or until it stops. You can now probe the circuit in the normal way to see what is oscillating. Once the oscillation has been fixed, you should be able to simulate the circuit successfully. The circuit doesn't oscillate but still doesn't converge As there are no added capacitors, there is a risk that pseudo transient analysis can fail for the same reason that GMIN and source stepping sometimes fail. In this case you will get the message:
No convergence in pseudo transient analysis

If this happens your only recourse is the final desperation measure. This is to repeat the simulation with all valid values of ptaConfig from 2 to 15. (You can skip 7 as this is the default). ptaConfig is a simulator option that controls some of the parameters used in pseudo transient analysis. Most circuits pass for all settings but a few are more selective.

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Accept Pseudo Transient Unconditionally You can specify pseudo transient analysis to be accept unconditionally at some time after it has started. This is often a good soultion to problems caused by circuit oscillation especially if the oscillation is small and unintended. To accept pseud transient unconditionaly, set the option:
.OPTIONS PTAACCEPTAT=time

Specify a time value that is adequate for the circuit state to settle as much as possible.

Junction Initialised Iteration

By default, this is the first method to be tried. If it fails, SIMetrix will then attempt source stepping, GMIN stepping and finally pseudo transient analysis. Usually one of these other methods will succeed and it is not worth spending time getting this method to work. If it does work, however, this is usually the fastest method and this can be put to good use for repetitive runs e.g. Monte Carlo. It can be made to succeed using nodesets (see next section) and with a wisely chosen selection it is possible to speed up repetitive runs. Assuming one of the other methods does complete to a solution, the best way of creating nodesets is by using the SaveRHS command. This is explained in the next section.

Using Nodesets
Nodesets have two uses, one to aid convergence and the other to bias the solution in circuits that have more than one stable state. Initially nodesets work exactly the same way as initial conditions. The nodeset voltage is applied via a 1 Ohm (by default) resistor and the solution is completed to convergence (by any of the methods). The nodeset is then released and the solution repeated. If the nodeset voltage is close to the actual solution the convergence of the second solution should be rapid. With SIMetrix, it is rarely necessary to use nodeset's to find the DC solution of a circuit. They can, however, be useful for speeding up the operating point analysis for circuit that have already been solved. You may wish to do this for a Monte-Carlo analysis, for example. SIMetrix provides a means of creating nodeset's using the SaveRHS command. To make use of this, proceed as follows: 1. 2. Run a DC operating point analysis Save the solution to a file using the SaveRhs command as follows:
SaveRhs /nodeset RHS.TXT

This will save to the file RHS.TXT a .nodeset control specifying the solution at each node.

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3. Paste the contents of RHS.TXT to the netlist. Alternatively, include the file using the .INC control. (See Adding Extra Netlist Lines on page 12 to find out how to add to a schematic).

If you now repeat the DC analysis, you should now find that the solution is very rapid. Depending on the nature of your circuit, you may also find that the solution is found easily even if you modify the circuit. This is not, however, guaranteed.

Transient Analysis
What Causes Non-convergence?
Fundamentally there are four reasons for convergence failure in transient analysis. 1. 2. 3. 4. There is no solution to the circuit within the numerical range of the computer (approx. +/- 10308). One or more device models contains a discontinuity or (less of a problem) a discontinuity in its first derivative. The circuit has a discontinuity caused by undamped regenerative action. The solution matrix is ill-conditioned and the machine does not have sufficient accuracy to solve it to the required tolerance.

1. and 3. above are circuit problems. A trivial example of 1. is a PN junction biased by a large voltage. Without any series resistance, the voltage does not need to be very high for the current in the device to exceed the range of the machine. An example of 3. is a bistable circuit where the device capacitances are not modelled. The action of switching state would theoretically occur in zero time, a situation the simulator cannot be guaranteed to handle. Note also that negative valued components can cause 1. or 3. to occur. 2. is usually a software problem that the user can do little about. However, we are not aware of any discontinuities in the standard devices and have removed the ones we have found in the original SPICE3 code. It is possible to create a device with the arbitrary source that contains discontinuities. If your circuit has any of these devices in it you should check the equations for discontinuous behaviour. In particular the functions SGN() and U() are discontinuous and should be avoided. 4. is probably the most common cause of convergence failure in most other SPICE products but is rare in SIMetrix. This is because we have done an extensive amount of work to eradicate the problem. Nevertheless we still occasionally see circuits that fail. Usually they have one, or more likely, a combination of the following: Very small resistors especially if they are not connected to ground. Very large capacitors especially if they are not connected to ground. Very large inductors especially if they are not connected to ground. Circuit forced to use very small time steps perhaps because of fast rise/fall times. Very large currents/voltages Very high gain loops.

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By very in the above we mean extreme. 1000V is not a very large voltage but 1000MV volts is. 1m is not particularly small but 1p is. If your circuit has any extreme values, try and moderate them. Don't use non-physical values of components if you can avoid it.

Fixes for Transient Non-convergence

1. As with DC operating point, check your circuit. In particular, check that you are not doing anything which might cause numerical difficulties such as forward biasing a zero resistance PN junction with a large zero source impedance voltage source. Do anything that will prevent small time steps being needed. Gross nonlinearities, regenerative loops and high gain loops all require small time-steps if not well damped. It may be that you have left out damping components to simplify the circuit and speed the simulation. It is worth noting that an accurately modelled circuit frequently converges more easily than an idealised circuit. Avoid using unrealistically large capacitors or inductors and unrealistically small resistors if at all possible. You should especially avoid such components if nongrounded. Try setting the PIVREL option to 0.999. If all else fails you can try relaxing some of the tolerances. If your circuit does not have any small (sub-A) currents then set ABSTOL to 1e-9 or 1e-6. You can also increase VNTOL (default 1e-6) to say 1e-3 if your circuit only has large voltages. Increasing RELTOL is the very last thing you should try. In our experience, increasing RELTOL beyond its default value (0.001) is rarely a reliable solution and can make matters worse. Contact technical support. We don't officially offer a convergence fixing service and reserve the right to decline help. However, we are always interested in nonconverging circuits and usually we will look at your circuit to see if we can identify the problem.

2.

3.

4. 5.

6.

DC Sweep
DC sweep is basically a repeated DC operating point and so the issues relating to that mode also apply to DC sweep. However, if you are sweeping a voltage or current source, then an altogether better way of dealing with DC sweep problems is to simulate the DC sweep using transient analysis with a slow ramp. Using transient analysis to perform DC sweep also resolves problems that can occur with circuits that have regions where there is more than one stable state e.g. bistables or schmitt triggers. Consider sweeping the input voltage of a schmitt trigger circuit. When the input voltage is between the lower and upper thresholds, the circuit has two stable states and the DC algorithm could find either of them. As each step in a DC analysis is initialised with the previous step, it will usually find the correct solution but this is not guaranteed. This means that the output could change state even though the input has not passed either threshold. This problem doesn't occur in transient analysis as in this mode the circuit is running as it would in real life.

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DC Operating Point Algorithms

SIMetrix uses five alternative strategies to resolve the DC operating point. These are: 1. 2. 3. 4. 5. Junction initialised iteration. This is our name for the standard algorithm sometimes simply known as DC Iteration. Source stepping. Diag GMIN stepping. Junction GMIN stepping. Pseudo transient analysis.

These are described in the following sections.

Junction Initialised Iteration

This is the standard algorithm and is sometimes known simply as DC iteration. Each semiconductor junction is initialised with a small voltage and iteration then proceeds until convergence (or otherwise). This method often succeeds and is usually the quickest. However, the starting point is only a bit better than an educated guess and can be so far removed from the real solution that it never has a chance of succeeding. (Junction initialised iteration is a name we have coined and you may see it referred to as JI2 elsewhere in this manual and also in messages output by SIMetrix)

Source Stepping
Source stepping. This method - as with all the remaining methods to be described belong to a class of convergence strategies known as continuation methods. These all work by repeating the iterative process while gradually varying some circuit parameter. The circuit parameter is chosen so that at its start value the solution is known or trivial and at its final value the solution is the operating point that is required. In source stepping, all the circuit's power sources are gradually ramped up from zero to their final value. While at zero, the circuit's solution is trivial; all the voltages and currents are zero. At the first step, the supplies might be ramped up to 10% of their maximum and the solution iterates to convergence. Then the supplies are increased and the process is repeated. At each step the solution is initialised with the previous solution which, if the steps are small, will be close to the new solution that is required and convergence will therefore be relative easy to achieve. This method is quite effective and is included in all SPICE based simulators including those derived from SPICE2. However the SPICE versions use a fixed step size, whereas in SIMetrix (since version 2.0), the step size is variable so if a step fails, the step size is reduced and it tries again. However, even with an arbitrarily small step size, this method can fail if the circuit contains some kind of regenerative action. As the supplies are ramped it is possible for the circuit to abruptly switch from one state to another as in a schmitt trigger. Although circuits such as schmitt triggers do give difficulty, even circuits that do not have such elements can also give trouble.

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Diagonal GMIN Stepping

In this method, a large conductance term is added to every diagonal entry of the solution matrix and gradually reduced. This is similar to placing a low value resistor from every node of the circuit to ground but is by no means equivalent. The high conductance term (=low resistance) in the matrix effectively swamps non-linearities and as a result the solution is easy to find. The term is gradually reduced until it is zero. This method is also effective and sometimes works for circuits for which source stepping fails. It is included with all SPICE3 derived simulators but, as with source stepping, the SPICE variants use a fixed step while SIMetrix uses a variable step. GMIN stepping suffers from the same problems as source stepping but not always with the same circuits so it always worth trying both approaches. The received wisdom has always been that GMIN stepping is more effective than source stepping. This has not however been borne out by our own research which has shown the source stepping converges more often and more quickly. For this reason, SIMetrix attempts source stepping before GMIN stepping. This is the reverse of SPICE3 and its derivatives.

Junction GMIN Stepping

The junction GMIN stepping method incrementally steps the conductance across semiconductor junctions. This in effect sweeps the GMIN option parameter. This method is effective for CMOS IC designs as long as GMIN is implemented as a conductance between drain and source. This is not the default configuration for LEVEL 1 to 3 MOSFETs in which GMIN is implemented as two conductances between the drain and bulk and source and bulk. For other MOSFET models such as BSIM3 and EKV, the default GMIN is now between source and drain. For designs containing these devices, Junction GMIN Stepping is the first method attempted after JI2. For circuits that do not contain such devices, this method is not attempted at all.

Pseudo Transient Analysis

This method finds the solution using transient analysis. In SIMetrix, a transient analysis is conducted while ramping up all power sources, in effect simulating the action of switching on the power supplies. This is not the same as source stepping as the latter is a pure DC method with all reactive components set to zero. Because reactive components - i.e. capacitors and inductors - are included in transient analysis, effects such as abrupt changes are damped and occur gradually over a finite time. This eliminates the problem - described above - that the DC continuation methods suffer from. The above assumes, however, that the circuit is well modelled with all reactive elements correctly specified. With integrated circuit design this is usually the case, but for discrete circuits frequently is not. Opamp macro models, for example, consist of many idealised elements that are not always damped by reactive elements. Without such damping, pseudo transient analysis can fail for the same reason as source and GMIN stepping. So, SIMetrix automatically adds additional capacitance to the circuit to prevent this situation from arising.

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The end result is a convergence strategy that nearly always succeeds. However, it is generally the slowest method so in SIMetrix it is, by default, attempted last. Although pseudo transient analysis is very powerful it is not completely infallible. Its Achilles Heel is oscillation. Because a transient analysis is being performed it is possible for the circuit to oscillate. If this happens, pseudo transient analysis can end up going on forever without ever finding a stable solution. In our experience, however, this is actually rare. A number of steps are taken to damp oscillators so that even circuits that are designed to oscillate still succeed with pseudo transient analysis. SIMetrix provides a number of facilities to inhibit circuit oscillation during pseudo transient analysis. These are described in Pseudo Transient Analysis on page 230.

Controlling DC Method Sequence

You may have a circuit that only succeeds with - say - pseudo transient analysis and so attempting the other methods just wastes time. In this situation, you can force the simulator to attempt this method first, or even exclusively. To do this you need to set the two simulator options noOpiter and dcopSequence. noOpiter inhibits the first method (junction initialised iteration) while dcopSequence controls which and what order the remaining methods are attempted. The value of dcopSequence consists of any combination of SOURCE, GMIN, JUNCGMIN and PTA separated by the pipe symbol: '|'. SOURCE, GMIN, JUNCGMIN and PTA refer respectively to source stepping, DIAG GMIN stepping, Junction GMIN stepping and pseudo transient analysis. The order in which these words appear in the value of dcopSequence, determines the order in which the corresponding methods will be attempted. So for example:
.OPTIONS NOOPITER DCOPSEQUENCE=PTA|GMIN

will force pseudo transient analysis to be attempted first followed by GMIN stepping. Junction initialised iteration and source stepping won't be attempted at all.

Singular Matrix Errors

A singular matrix error occurs when the circuit does not have a unique and finite solution. For example, a circuit containing a floating capacitor does not have a unique DC solution as the capacitor can be at any voltage. Also circuits with shorted inductors, voltage sources or a combination of both will fail with this error. If you get this error, you must first check your circuit. The simulator will tell you where the problem is either as a node name or a device name. If you think you circuit is OK then it is possible that the error is occurring because during the course of iterating to a solution, some node voltages or device currents reached very high values and the limited accuracy of the machine made it seem that the matrix was singular. This can happen with junction initialised iteration. If this is the case, try setting the option:
.OPTIONS NOOPITER

This will inhibit this mode and the simulator will start with source stepping. This method, and the others that follow, don't generally suffer from this problem.

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Note that the simulation will abort if a singular matrix is detected in junction initialised iteration. It will not automatically attempt the other methods. This is because, by far the most common reason for singular matrices is circuit error.

Transient Analysis - Time step too small Error

The message:
Timestep too small

is not actually due to non-convergence. It means that, because of the nature of your circuit, to achieve the required accuracy, a time step smaller than the minimum permissible was needed. This can happen if you perform a very long transient analysis on a circuit with relatively short time constants. If you get this message, you can try reducing the minimum time step with the MinTimeStep simulator option. The default value for MinTimeStep is 1e-9*max time step and the max time step defaults to (TstopTstart)/50 where Tstop and Tstart are respectively the stop and start times of the transient analysis. This option can be set in the user interface. See Time Step on page 162 of the Users Manual

Accuracy and Integration Methods

A Simple Approach
The accuracy of the simulation can be a complicated subject. So we will start with simple advice. If you wish to increase the accuracy of a simulation, reduce the value of RELTOL. This defaults to 0.001 so to reduce it to say 1e-5 add the following line to the netlist:
.OPTIONS RELTOL=1e-5

(The setting of RELTOL is supported by the front end. See User's Manual for details.) The simulation will run slower. It might be a lot slower it might be only slightly slower. In very unfortunate circumstances it might not simulate at all and fail with a convergence error. Conversely, you can speed up the simulation by increasing RELTOL, but we don't recommend it. Increasing RELTOL beyond its default value often degrades accuracy to an unacceptable level. To increase speed with a reasonably controlled loss of precision, increase POINTTOL to 0.1 or even 1.0 but no higher.

Iteration Accuracy
For DC and transient modes, the simulator essentially makes an approximation to the true answer. For DC analysis an iterative method is used to solve the non-linear equations which can only find the exact answer if the circuit is linear. The accuracy of the result for non-linear circuits is determined by the number of iterations; accuracy is improved by performing more iterations but obviously this takes longer. In order to

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control the number of iterations that are performed an estimate is made of the error by comparing two successive iterations. When this error falls below a predetermined tolerance, the iteration is deemed to have converged and the simulator moves on the next step or completes the run. Most SPICE simulators use something similar to the following equations to calculate the tolerance: For voltages: TOL = RELTOL * instantaneous_value + VNTOL For currents: TOL = RELTOL * instantaneous_value + ABSTOL "instantaneous_value" is the larger of the current and previous iterations. VNTOL has a default value of 1V so for voltages above 1mV, RELTOL dominates. ABSTOL has a default of 1pA so for currents above 1nA, RELTOL dominates. The above method of calculating tolerance works fine for many circuits using the default values of VNTOL and ABSTOL. However, SPICE was originally designed for integrated circuit design where voltages and currents are always small, so the default values of ABSTOL and VNTOL may not be appropriate for - say - a 100V 20A power supply. Suppose, that such a PSU has a current that rises to 20A at some point in the simulation, but falls away to zero. When at 20A it has a tolerance of 20mA but when it falls to zero the tolerance drops to ABSTOL which is 1pA. In most situations the 1pA tolerance would be absurdly tight and would slow down the simulation. Most other SPICE products recommend increasing ABSTOL and VNTOL for PSU circuits and indeed this is perfectly sound advice. However, In SIMetrix the tolerance equation has been modified to make this unnecessary in most cases. Here is the modified equation: For voltages: TOL = RELTOL * MAX( peak_value * POINTTOL, instantaneous_value ) + VNTOL For currents: TOL = RELTOL * MAX( peak_value * POINTTOL, instantaneous_value ) + ABSTOL peak_value is the magnitude of the largest voltage or current encountered so far for the signal under test. POINTTOL is a new tolerance parameter and has a default value of 0.001. So for the example we gave above, peak_value would be 20 and when instantaneous_value falls to zero the tolerance would be: 0.001 * MAX(20 * 0.001, 0) + 1p = approx. 20A 20A is a much more reasonable tolerance for a signal that reaches 20A. The above method has the advantage that it loosens the tolerance only for signals that actually reach large values. Parts of a circuit that only see small voltages or currents such as the error amplifier of a servo-controlled power supply - would still be simulated with appropriate precision. POINTTOL can be increased to improve simulation speed. It is a more controlled method than increasing RELTOL. POINTTOL can be raised to 0.1 or even 1.0 but definitely no higher than 1.0.

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Time Step Control

The tolerance options mentioned above also affect the time step control algorithm used in transient analysis. In SIMetrix, as with all SPICE based simulators, there are two mechanisms that control the time step. The first - iteration control - reduces the time step by a factor of 8 if convergence to the specified accuracy cannot be achieved after 10 iterations. (10 by default but can be changed with ITL4 option). If convergence is successful, the time step is doubled. As this mechanism is controlled by the success or otherwise of the iteration it is also affected by the same tolerance options described in the above section. The second method used is called LTE time step control. The theory behind this method is beyond the scope of this manual but essentially it controls the accuracy of the numerical integration method used to model reactive devices such as inductors and capacitors. These devices are governed by a differential equation. It is not possible in a non-linear circuit to solve these differential equations exactly so a numerical method is used and this - like the iterative methods used for non-linear devices - is approximate. In the case of numerical integration, the accuracy is determined by the time step. The smaller the time step the greater the accuracy but also the longer the simulation time. The accuracy to which capacitors are simulated is controlled by RELTOL, POINTTOL and two other options namely TRTOL and CHGTOL. The latter is a charge tolerance and has a similar effect to VNTOL and ABSTOL but instead represents the charge in the capacitor. It's default value is 1e-14 which, like ABSTOL and VNTOL is appropriate for integrated circuits but may be too low for PSU circuits with large capacitors. However, the peak detection mechanism controlled by POINTTOL described in the above section also works for the LTE time step control algorithm and it is therefore rarely necessary to alter CHGTOL. TRTOL is a dimensionless value and has a default value of 7. It affects the overall accuracy of the numerical integration without affecting the precision of the iteration. So reducing TRTOL will increase the accuracy with which capacitors and inductors are simulated without affecting the accuracy of the iterative method used to simulate nonlinear elements. However, in order for the simulation of reactive devices to be accurate, the non-linear iteration must also be accurate. So, reducing TRTOL much below unity will result in a longer simulation time but no improvement in precision. Increasing TRTOL to a large value, however, may be appropriate in some circumstances where the accuracy to which reactive devices are simulated is not that important. This may be the case in a circuit where there is an interest in the steady state but not in how it was reached. Inductors are controlled by the same tolerances except CHGTOL is replaced by FLUXTOL. This defaults to 1e-11. The default LTE time step algorithm used in SIMetrix is slightly different to that used by standard SPICE. The standard SPICE variant is also affected by ABSTOL and VNTOL. The SIMetrix algorithm controls the time step more accurately and as a result offers better speed-accuracy performance.

Accuracy of AC analyses
The small-signal analysis modes .AC, .TF and .NOISE do not use approximate methods and their accuracy is limited only by the precision of the processor's floating point unit. Of course the DC operating point that always precedes these analysis modes

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is subject to the limitations described above. Also, the device models used for nonlinear devices are also in themselves approximations. So these modes should not be seen as exact but they are not affected by any of the tolerance option settings.

Summary of Tolerance Options

RELTOL Default = 0.001. This affects all DC and transient simulation modes and specifies the relative accuracy. Reduce this value to improve precision at the expense of simulation speed. We do not recommend increasing this value except perhaps to run a quick test. In any case, you should never use a value larger than 0.01. POINTTOL Proprietary to SIMetrix. Default = 0.001. Can increase to a maximum of 1.0 to improve speed with loss of precision. Reduce to 0 for maximum accuracy but note this may just slow down the simulation without really improving precision where it is needed. ABSTOL Default = 1pA. This is an absolute tolerance for currents and therefore has units of Amps. This basically affects the tolerance for very low values of current. Sometimes worth increasing to resolve convergence problems or improve speed for power circuits. VNTOL Default = 1V. Same as ABSTOL but for voltages. TRTOL Default = 7. This is a relative value and affects how accurately charge storage elements are simulated. Reduce it to increase accuracy of reactive elements but there is no benefit reducing below about 1.0. In circuits where there is more interest in the steady state rather than how to get there, simulation speed can be improved by increasing this value. CHGTOL Default = 1e-14. Minimum tolerance of capacitor charge. Some convergence and speed improvement may be gained by increasing this for circuits with large capacitors. Generally recommended to leave it alone. FLUXTOL Default = 1e-11. Same as CHGTOL except applied to inductors.

Integration Methods - METHOD option

SIMetrix, along with most other SPICE products use three different numerical integration methods to model reactive elements such as capacitors and inductors.

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These are Backward Euler, Trapezoidal Rule and Gear. Backward Euler is used unconditionally at various times during the course of a simulation but at all other times the method used is controlled by the METHOD option (as long as ORDER is set to 2 or higher - see below). The METHOD option can be set to TRAP ( trapezoidal - the default) or GEAR. Gear integration can solve a common problem whereby the solution seems to oscillate slightly. An example is shown below.
1: :q1#b 7 6.5 6 5.5 5 A 4.5 4 3.5 3 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 200nSecs/div 2: tran2:q1#b

Time/Secs

The grey curve was simulated with the default trapezoidal integration method whereas the black used Gear integration. Note that gear integration introduces a slight overshoot. This is a common characteristic. To find out whether such overshoots are a consequence of the integration or are in fact a real circuit characteristic, you should simulate the circuit with much smaller values of RELTOL (see above). It is also suggested that you switch back to trapezoid integration when using tight tolerances; the oscillating effect shown above will vanish if the tolerance is tight enough. Note, you should not use Gear integration if you are simulating strongly resonant circuits such as oscillators. Gear integration introduces a numerical damping effect which will cause resonant circuits to decay more rapidly than they should. For example:

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20

10

-10

-20

-30

20

10

-10

-20

-30 0 Time/Secs 2 4 6 8 10 2Secs/div

The above curves are the result of simulating a simple LC circuit that is completely undamped. The top trace was the result of Gear integration and the bottom, trapezoidal. The bottom curve is correct and agrees with theory. The top curve is inaccurate. If the analysis was done with Gear integration but with a smaller value of RELTOL, the damping effect would be less, so for all methods the result is ultimately accurate if the tolerance is made small enough. But trapezoidal gives accurate results without tight values of RELTOL. ORDER option This defaults to 2 and in general we recommend that it stays that way. Setting it to 1 will force Backward Euler to be used throughout which will degrade precision without any speed improvement. It can be increased up to a value of 6 if METHOD=GEAR but we have not found any circuits where this offers any improvement in either speed or precision.

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Chapter 9 Digital Simulation

Overview
As well as an analog simulator, SIMetrix incorporates an event driven digital simulator tightly coupled to the analog portion. This system can rapidly and accurately simulate mixed signal circuits containing both analog and digital components. Of course, an analog only simulator can simulate a mixed signal circuit using digital models constructed from analog components, but this approach is slow. The advantage of this mixed-mode approach is that it is dramatically faster, typically in the order of 100 times for pure digital circuits. The SIMetrix mixed mode simulator is based on the XSPICE system developed by the Georgia Technical Research Institute. Although based on XSPICE, SIMetrix features many enhancements over the original system. See Enhancements over XSPICE on page 268 for details of these improvements. If you only use digital models supplied in the device library, then you don't need to know much about the digital simulator in order to use it. Just select the devices you need from the parts browser and simulate in the normal way. This chapter describes some of the inner workings of the simulator including how it interfaces to the analog system. More importantly, perhaps, this chapter also describes how you can design your own digital models.

Logic States
The digital simulator is described as 12-state which means that a digital signal can be in 1 of 12 states. These 12 states are combined from 3 levels and 4 strengths as follows:

Logic levels
HIGH LOW UNKNOWN

Strengths
STRONG RESISTIVE HI-IMPEDANCE UNDETERMINED

Logic levels HIGH and LOW are self-explanatory. UNKNOWN means the signal could be either HIGH or LOW but which is not known at this stage. The start up state of a flip-flop is an example of an UNKNOWN state. Strength refers to the driving force behind the signal. STRONG is the highest with HI-IMPEDANCE the lowest. It is used to resolve conflicts when two outputs are connected together. For example consider a LOW-RESISTIVE signal (as possessed by a pull-down resistor) connected to a HIGH-STRONG signal There is a conflict between the two logic levels but as they are different strengths, the stronger wins and therefore the resulting level is HIGH.

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State resolution table

The following table defines how a state is decided when two outputs are connected: 0S 0S 1S XS 0R 1R XR 0Z 1Z XZ 0U 1U XU 0S XS XS 0S 0S 0S 0S 0S 0S 0S XS XS 1S XS 1S XS 1S 1S 1S 1S 1S 1S XS 1S XS XS XS XS XS XS XS XS XS XS XS XS XS XS 0R 0S 1S XS 0R XR XR 0R 0R 0R 0U XU XU 1R 0S 1S XS XR 1R XR 1R 1R 1R XU 1U XU XR 0S 1S XS XR XR XR XR XR XR XU XU XU 0Z 0S 1S XS 0R 1R XR 0Z XZ XZ 0U XU XU 1Z 0S 1S XS 0R 1R XR XZ 1Z XZ XU 1U XU XZ 0S 1S XS 0R 1R XR XZ XZ XZ XU XU XU 0U 0S XS XS 0U XU 1U 0U XU XU 0U XU XU IU XS 1S XS XU 1U XU XU 1U XU XU 1U XU XU XS XS XS XU XU XU XU XU XU XU XU XU

0S = LOW-STRONG 1S = HIGH-STRONG XS = UNKNOWN-STRONG 0R = LOW-RESISTIVE 1R = HIGH-RESISTIVE XR = UNKNOWN-RESISTIVE 0Z = LOW-HI-Z 1Z = HIGH-HI-Z XZ = UNKNOWN-HI-Z 0U = LOW-UNDETERMINED 1U = HIGH-UNDETERMINED XU=UNKNOWN-UNDETERMINED

Analog to Digital Interfaces

At the simulator level, there are two types of node namely analog and digital and they cannot be connected together. At the netlist level it is possible to connect analog components to digital outputs and inputs. When SIMetrix sees an analog component connected to a digital signal, it automatically interconnects them using an interface bridge. It will use an analog-digital bridge to connect an analog signal to a digital input and a digital-analog bridge to connect to a digital output. If you connect an analog component to a signal which connects to both digital inputs and outputs both types of bridge will be used and the digital inputs and outputs will be separated from each other as illustrated in the following diagrams.

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VCC

HC00 D SET Q U3 QN

U4 HC74

RST

VP

X1

TL072

VN

Circuit entered in schematic editor

Analog-digital bridges implicitly connected by simulator
VCC

HC00 D_A U2 U3 A_D U1 RST D SET Q QN

U4 HC74

VP

X1

TL072

VN

Circuit that is actually simulated One problem with the above approach is that the A-D and D-A bridges introduce an additional delay to the signal path which would therefore alter the performance of the digital system even if the analog node does not present any significant load. This is overcome by assigning a negative load to the input of the digital bridge which in effect reduces the delay of the driving gate. In the above example U2 has a negative input load which reduces the delay of U3.

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How A-D Bridges are Selected

When SIMetrix implicitly places an AD bridge in a circuit, it must choose an appropriate model for the bridge. All AD bridges are based on DAC_BRDIGE and ADC_BRIDGE models described in Analog-Digital Interface Bridge, and DigitalAnalog Interface Bridge starting page 153. The model is chosen according to the FAMILY parameter assigned to the digital device to which the bridge is connected. The FAMILY parameter along with the associated OUT_FAMILY and IN_FAMILY parameters are explained more fully in Logic Families on page 247. Basically the FAMILY parameter specifies the logic family to which the device belongs e.g. HC for high speed CMOS. The name of the model used to interconnect digital to analog is always of the form: family_name_dac and to interconnect analog to digital family_name_adc For example if the family name is HC the D-A bridge is called HC_DAC. There is a selection of A-D and D-A bridges in the model library supplied with SIMetrix. (In BRIDGES.LB).

Logic Families
The digital simulator only knows about the 12 logic states described in section Logic States on page 244, It doesn't know anything about threshold voltages or output impedances and consequently cannot directly handle the effects of interconnecting devices from different logic families. It does however feature a mechanism of determining the level of compatibility between families and will raise an error if incompatible devices are interconnected. For example, ECL and high speed CMOS operate at completely different thresholds and cannot be connected except via a special interface gate. SIMetrix knows this so that if you attempt to connect such devices, an error message will be displayed and the simulation will not run. Conversely, it is perfectly OK to drive an LSTTL input from an HC output and SIMetrix will operate normally if you do so. If you drive an HC input from an LSTTL output SIMetrix will issue a warning as, although this may work in practice, it cannot be guaranteed to do so under all circumstances. Another problem arises when connecting inputs from different logic families together. SIMetrix deals with this by treating groups of inputs as if they were all from the same logic family provided they are compatible. This selected logic family is then used to resolve any output-input conflict as described above. It is also used to select an analogdigital interface bridge as described in Analog to Digital Interfaces on page 245 Groups of outputs from different families are dealt with in the same way as inputs described above. SIMetrix knows how to resolve these situations by referring to a set of three tables called the Logic Compatibility Tables. A standard set of tables is built in to the simulator but they can also be redefined. See Logic Compatibility Tables on page 248.

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Logic Family Model Parameters.

There are three model parameters used to specify the logic family to which a device belongs. These are:

Parameter name
IN_FAMILY OUT_FAMILY FAMILY

Description
Family for inputs Family for outputs Family for both inputs and outputs if IN_FAMILY/ OUT_FAMILY not specified

The parameters are text strings. Any name may be used that is defined in the logic compatibility tables but you must not use the underscore character in a family name. The families supported by the internal tables are listed in Supported Logic Families on page 250 The underscore character is used to define a sub-family that has the same characteristics as the main family as far as logic compatibility is concerned but which will call a different interface bridge when connected to an analog node. This is used to define schmitt trigger devices such as the 74HC14. In an all-digital circuit this behaves exactly like a normal inverter with a slightly longer delay. When the input is connected to an analog system an interface bridge with the appropriate hysteresis is called up instead of the normal interface.

Logic Compatibility Tables

As explained in the above section, there are three of these. Each table has a row and column entry for each of the logic families supported. These are: Resolve In-Out table. Decides what to do when an output is connected to an input from a different family. Possible responses are OK, ERR (error - not permissible) and WARN (OK but give warning to user) Resolve In-In table. Decides how to treat the situation when two inputs from dissimilar families are connected. As described above SIMetrix must treat a group of inputs connected together as all belonging to the same logic family for the purpose of deciding an analog interface bridge (see Analog to Digital Interfaces on page 245) and to resolve in-out family conflicts. Possible responses are ROW, COLUMN and ERR. ROW means that the family defining the ROW entry has priority and COLUMN means that the family defining the COLUMN entry has priority. ERR means that it is an error to interconnect these two inputs. You can also enter OK which signifies that the two families are equivalent and it doesn't matter which is chosen. Currently this response is exactly equivalent to ROW. Resolve Out-Out table. Works the same way as the Resolve In-In table but used to define output priorities.

The tables can be redefined by specifying a file containing the new definition. If running in GUI mode a new file can be specified at any time using the ReadLogicCompatibility command (see User's Manual or Script Reference Manual).

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It can also be specified as the configuration setting CompatTable. The format of this file is described in the following section.

Logic Compatibility File Format

For an example of a compatibility table, see the file COMPAT.TXT which you will find in the SCRIPT directory. This file is actually identical to the built-in definitions except for the UNIV family which cannot be redefined. The file format consists of the following sections: 1. 2. 3. 4. Header In-Out resolution table In-In resolution table Out-Out resolution table

Header The names of all the logic families listed in one line. The names must not use the underscore ('_') character. In-Out resolution table: A table with the number of rows and columns equal to the number of logic families listed in the header. The columns represent outputs and the rows inputs. The entry in the table specifies the compatibility between the output and the input when connected to each other. The entry may be one of three values:

Value
OK WARN ERR

Meaning
Fully compatible Not compatible but would usually function. Warn user but allow simulation to continue. Not compatible and would never function. Abort simulation.

In-In resolution table A table with the number of rows and columns equal to the number of logic families listed in the header. Both column and rows represent inputs. The table defines how inputs from different families are treated when they are connected. The entry may be one of four values:

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Value
ROW COL OK ERR

Meaning
Row take precedence Column takes precedence Doesn't matter. (Currently identical to ROW) Incompatible, inputs cannot be connected.

Out-out resolution table A table with the number of rows and columns equal to the number of logic families listed in the header. Both column and rows represent outputs. The table defines how outputs from different families are treated when they are connected. The entry may be one of four values:

Value
ROW COL OK ERR

Meaning
Row take precedence Column takes precedence Doesn't matter. (Currently identical to ROW) Incompatible, outputs cannot be connected.

Supported Logic Families

The following logic families are supported by the internal Logic Compatibility Tables.

Family name

Description

TTL HC HCT FAST LS ALS 4000-5 4000-10 4000-15 ECL10K

TTL - 74 series High speed CMOS - 74HC series TTL compatible High speed CMOS - 74HCT series FAST TTL - 74F series Low power schottky TTL - 74LS series Advanced low power schottky TTL - 74ALS series 4000 series CMOS - 5V operation 4000 series CMOS - 10V operation 4000 series CMOS - 15V operation ECL 10K series

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Family name
ECL10KE AC ACT FORCE5 UNIV

Description
ECL Eclipse series Advanced CMOS - 74AC series TTL compatible Advanced CMOS - 74ACT series Used for 5V VCC rails. Universal family - see below

Universal Logic Family

The internal tables support the concept of a Universal logic family. This is called UNIV and can connect to any logic family without error. This is the default if no FAMILY parameter is supplied.

Internal Tables
The internal tables are documented in the on-line help system. Refer to topic Internal Tables which is listed as a keyword in the index tab.

Load Delay
Overview
The digital simulator includes mechanisms to model the delay introduced when an output is loaded. Two sources of delay are provided for, namely input delay and wire delay. Input delay is determined by the capacitive input while wire delay is an additional delay caused by the capacitance of the interconnection. Both input delay and wire delay are affected by the driving outputs resistance.

Output Resistance
Most devices that have digital outputs have three parameters to define output resistance. Note that the resistance we are referring to here is not an actual analog resistance but a conceptual value that when multiplied by load capacitance provides a delay value. The three output resistance parameters are: out_res, out_res_pos, out_res_neg. out_res_pos and out_res_neg define the output resistance for positive and negative transitions respectively. out_res provides a default value for out_res_pos and out_res_neg.

Input Delay
Most digital inputs include an input_load capacitance parameter. The total input delay is obtained by multiplying the sum of all connected input capacitances by the driving outputs output resistance as described above.

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Wire Delay
Wire delay is derived from the number of connected inputs following a non-linear relationship defined in a look-up table. Defining Look-up Table The wire delay look-up table must be defined in a file containing pairs of values with one pair per line. The first value in the pair is the number of connections and the second is the capacitance. For example:
0 1 2 5 10 0 0 1e-12 10e-12 30e-12

Linear interpolation is used to derive missing values. To specify the wire table used for a simulation, add the line:
.OPTIONS WireTable=filename

where filename is the path of the wire table file.

Digital Model Libraries

Using Third Party Libraries
The SIMetrix digital simulator is based on XSPICE and all the XSPICE digital devices have been implemented. Virtually all of these have been enhanced in a number of ways but all remain backward compatible with the original XSPICE. Consequently any 100% XSPICE compatible digital model will work with SIMetrix.

Arbitrary Logic Block - User Defined Models

Overview
The arbitrary logic block is an internal component that can be defined to perform any logic function. Using a simple descriptive language it is possible to define combinational logic elements, synchronous and asynchronous registers as well as lookup table (ROMs) and arrays (RAMs). Each ALB device is defined as a normal .MODEL control which refers to a separate file containing the logic description. This section is mostly concerned with the descriptive language used in the definition file.

An Example
We start with a simple example. The following is a description of a simple 8 bit synchronous counter. (This definition would be put into a file referred to in a .MODEL

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control. This is described later). A circuit using this model is supplied as an example. See EXAMPLES\ALB_Examples\count.sch
PORT (DELAY = 10n) CountOut out[0:7] ; EDGE (DELAY=5n, WIDTH=8, CLOCK=in[0]) Count ; Count = Count + 1 ; CountOut = count ;

We will go through this line by line. The first line:

PORT (DELAY = 10n) CountOut out[0:7] ;

is a PORT statement and in this case defines the characteristics of an output.

(DELAY = 10n)

says that the output delay is 10nS that is the actual output pins will change state 10nS after the output is assigned.
CountOut

names the output CountOut.

out[0:7]

defines the port as an output and specifies the actual pins used on the device. This specifies the first 8 pins on the output port. There are two sets of pins on an ALB one assigned for inputs and referred to as "in[a:b]" and the other assigned for outputs and referred to as "out[a:b]". The line ends in a semi-colon which terminates the statement. All statements must end in a semi-colon. The next line:
EDGE (DELAY=5n, WIDTH=8, CLOCK=in[0]) Count ;

defines an edge triggered register.

CLOCK=in[0]

specifies the pin used for the clock (it must always be an input pin). This is always positive edge triggered.
DELAY=5n

This is the clock to output delay. (See illustration below)

WIDTH=8

This specifies the width of the register i.e. 8 bits The next line:
Count = Count + 1 ;

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defines the operation to be performed at each clock edge. In this case the value in the register is simply incremented by one. When it reaches 255 it will reset to 0. The final line
CountOut = count ;

defines what appears at the output. This says that the output equals the count register. The following diagram illustrates the internal structure of the counter.
Edge triggered register Delay=5n CLOCK IN D0 D1 D2 D3 D4 D5 D6 D7 Output stage Delay=10n A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7

Reset Count at 200 We will now make a small modification to the counter so that the counter only counts up to 199 before resetting back to zero. Change the line: to:
Count = Count + 1 ; Count = Count==199 ? 0 : Count + 1 ;

This says If the count equals 199 set to zero otherwise increment by one. As before, this will happen on each clock edge. Add an Asynchronous Reset The logic definition language supports the addition of asynchronous controls to synchronous registers. Here we will add an asynchronous reset. The complete definition becomes:
PORT PORT (DELAY = 10n) CountOut Reset out[0:7] ; in[1] ;

EDGE (DELAY=5n, WIDTH=8, CLOCK=in[0]) Count ; Count := !Reset ? 0 ; Count = Count==199 ? 0 : Count + 1 ; CountOut = count ;

To add the reset signal we have to add two lines to the definition. The first:
PORT Reset in[1] ;

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defines the signal pin to be used for the reset and the second:
Count := !Reset ? 0 ;

defines the action to be taken. This is an asynchronous action statement. The '!' means NOT so the line says If Reset is NOT TRUE (i.e. low) set the count to zero otherwise do nothing. Asynchronous action statements are always of the form:

register_name := condition ? action ;

The ':' signifies that the statement is asynchronous and that the action should happen immediately.

Example 2 - A Simple Multiplier

PORT (DELAY=10n) PORT PORT MultOut = in1*in2 ; MultOut out[0:7] ; in1 in[0:3] ; in2 in[4:7] ;

The above defines a simple combinational circuit, that of a 4X4 digital multiplier. The inputs in1 and in2 are treated as 4 bit unsigned values so if both are zero the output will be zero and if both are 1111 (i.e. 15) the result will be 11100001 (i.e. 225). See the circuit EXAMPLES\ALB_Examples\Mult.sch.

Example 3 - A ROM Lookup Table

The following definition is that of a lookup table to define a sine wave:
PORT (DELAY=10n) ROMout out[0:7] ; PORT input in[0:7] ; READONLY (WIDTH=8) ROM[256] = 128, 131, 134, 137, 140, 143, 146, 149, 152, 156, 159, 162, 165, 168, 171, 174, 176, 179, 182, 185, 188, 191, 193, 196, 199, 201, 204, 206, 209, 211, 213, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234, 236, 237, 239, 240, 242, 243, 245, 246, 247, 248, 249, 250, 251, 252, 252, 253, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 254, 254, 253, 252, 252, 251, 250, 249, 248, 247, 246, 245, 243, 242, 240, 239, 237, 236, 234, 232, 230, 228, 226, 224, 222, 220, 218, 216, 213, 211, 209, 206, 204, 201, 199, 196, 193, 191, 188, 185, 182, 179, 176, 174, 171, 168, 165, 162, 159, 156, 152, 149, 146, 143, 140, 137, 134, 131, 128, 124, 121, 118, 115, 112, 109, 106, 103, 99, 96, 93, 90, 87, 84, 81, 79, 76, 73, 70, 67, 64, 62, 59, 56, 54, 51, 49, 46, 44, 42, 39, 37, 35, 33, 31, 29, 27, 25, 23, 21, 19, 18, 16, 15, 13, 12, 10, 9, 8, 7, 6, 5, 4, 3, 3, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15, 16, 18, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 42, 44, 46, 49, 51, 54, 56, 59, 62, 64, 67, 70, 73, 76, 79, 81, 84, 87, 90, 93, 96, 99, 103, 106, 109, 112, 115, 118, 121, 124 ; ROMout = ROM[input] ;

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See the example circuit EXAMPLES\ALB_Examples\SineLookUp.sch

Example 4 - D Type Flip Flop

The following is the definition for the 74X74 Dtype flip flop supplied with the standard SIMetrix model library. This model is somewhat more complicated as it models a number of timing artefacts such as setup time and minimum clock width. Each line below has been annotated to describe its function. Full details are explained in the following sections.
// Input port definitions PORT D in[0] ; // D input PORT CK in[1] ; // Clock PORT SR in[2:3] ; // Set/reset inputs. r bit 3 s bit 2 PORT out // // // // out[0:1] ; // Outputs Q and !Q

Edge triggered register. HOLD is hold time i.e. time after clock edge that data must remain stable. Setup time is implemented by delaying the D input

// MINCLOCK is minimum clock width. // USER[n] references values supplied in the .MODEL control // The final '=2' initialise the register with the value 2 // i.e. Q=0 and Q!=1 EDGE (WIDTH=2, DELAY=USER[4], HOLD=USER[2], MINCLOCK=USER[3], CLOCK=in[1]) DTYPE=2; // COMB defines a combinational register. This is effectively // a delay element. These delay the D input (to implement // setup time) and the set/reset inputs to implement minimum // set and reset times COMB (DELAY=USER[0], WIDTH=1) D_DEL ; COMB (DELAY=USER[1], WIDTH=2) SR_DEL ; // These assign the combinational registers SR_DEL = SR ; D_DEL = D ; // asynchronous action DTYPE := SR_DEL==1||SR_DEL==2 ? // synchronous action DTYPE = D_DEL ? 1 : 2 ; // Both outputs are forced high if S and R are both active // Output will be restored to previous value when one of // S and R becomes inactive out = SR_DEL==0 ? 3 : DTYPE ; (SR_DEL==2 ? 1 : 2) ;

Device Definition - Netlist Entry & .MODEL Parameters

Netlist entry

Axxxx [ in_0 in_1 .. in_n ] [ out_0 out_1 .. out_n ] model_name 256

Chapter 9 Digital Simulation + : parameters

Connection details

Name
in out

Description
Input Output

Flow
in out

Type
d d

Instance parameters

Name
trace_file user Model format

Description
Trace file User device parameters

Type
string real vector

.MODEL model_name d_logic_block parameters

Model parameters

Name
file def out_delay reg_delay setup_time hold_time min_clock trace_file user user_scale input_load

Description
Definition file name Definition Default output delay Default internal register delay Default level triggered setup time Default edge triggered hold time Default minimum clock width Trace log file User defined parameters Input load value (F)

Type Default Limits

string string real real real real real string real none vector 1 1p real none none 1n 1n 0 0 0 none none 1e-12 0- 0- 0- 0- none none 0- none

Vector bounds
n/a n/a n/a n/a n/a n/a n/a n/a none n/a n/a

Scale of user values real

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Name
family in_family out_family out_res min_sink max_source sink_current

Description
Logic family Input logic family Output logic family Digital output resistance Minimum sink current Maximum source current Input sink current

Type Default Limits

string string string real real real real real UNIV UNIV UNIV 100 -0.001 0.001 0 0 none none none 0- none none none none

Vector bounds
n/a n/a n/a n/a n/a n/a n/a n/a

source_current Input source current Notes

Usually the logic block definition would be placed in a file referred in the FILE parameter. Alternatively the definition may be placed directly in the .MODEL control as the value of the DEF parameter. In this case the definition must be enclosed in quotation marks ("). The USER_SCALE parameter scales all values found in the USER parameter.

Language Definition - Overview

The following sections describe the full details of the arbitrary logic block language. All logic definitions are divided into two sections. The first contains the ports and register definitions and the second section consists of the assignment statements. (The first section can be empty in very simple cases).

Language Definition - Constants and Names

Constants follow the usual rules. Any decimal number with optional sign and exponent or engineering suffix is permitted. In addition, numbers in hexadecimal are also allowed. The format is the same as for the 'C' programming language i.e. prefixed with '0X'. E.g.:
0X10 = 10 hex = 16.

Identifiers used for register, port and variable names must begin with an alphabetic character or underscore and consist of alphanumeric characters and underscores.

Language Definition - Ports

Port statements define the inputs and outputs to the logic device. They are of the form

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Chapter 9 Digital Simulation PORT ( DELAY=output_delay) port_name OUT [ pin1| pin1:pin2 ] or PORT port_name IN|OUT [ pin1| pin1:pin2 ]
Ports define a label to a single pin or sequence of pins so that they can be treated as a single entity in the remainder of the logic definition. In the case of outputs they can optionally also define an output delay. (If this is not specified a default output delay defined in the devices .MODEL control is used). port_name Any name to reference the port. Must start with a letter or underscore and consist only of letters numbers and underscores. Names are not case sensitive. Identifies pin or range of pins that port accesses. See next section for more details. Output delay in seconds. When an output port is assigned a value, the actual output is updated after this delay has elapsed (+ any loading delay). You may use engineering units in the normal way. E.g. 10n is 10e-9.

pin1,pin2 output_delay

Relationship between ports, netlist entry and symbol definition The netlist entry for an arbitrary logic block is of the form:

Axxx [ input_node_list ] [ output_node_list ] model_name

The pin numbers in the port statements above, i.e. pin1 and pin2 are the positions within the input_node_list for input ports and output_node_list for output ports. So if the netlist entry is:
A12 [ 1 2 3 4 ] [ A B C D ] ARB1

the port definition:

PORT output OUT[0:3] ;

assigns the label output to the netlist pins A B C and D. If, for example, the value 7 is evaluated and assigned to output, pins A B and C would be set to a logic '1' and pin D would be set to a logic '0'. Pins 1 2 3 & 4 would be used for input ports in a similar way. The netlist entry relates directly to a symbol definition for an arbitrary logic block. When defining a symbol to be used with an ALB you should observe the following rules The first input pin's name and the first output pin's name should both be prefixed with a '['. The last input pin's name and the last output pin's name should both be suffixed with a ']'.

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Use Property/Pin|Edit Pin Order to define the pin order with input pins first then output pins. You should assign a MODEL property with the value 'A'.

Language Definition - Registers and Variables

Registers are the main working elements of the arbitrary logic block. There are four main types. These are: Edge triggered. The value of these change on the rising edge of an assigned clock. Level triggered. The value of these change when an assigned enable is at a logic '1' level. Combinational. The value of these change after a specified delay. Read-only. These are given a fixed value which cannot be changed. These would usually be arranged in indexable arrays to implement a read only memory.

Edge and level triggered registers may be arranged in indexable arrays. Level or edge triggered arrays form a read-write memory or RAM. In addition to registers there are also local variables. These can be assigned a value that can later be used in a register assignment. All registers must be declared. Local variables are declared by simply assigning a value to them. The syntax for register declarations follow: Edge Triggered Register Declaration

EDGE ( CLOCK=input_pin_spec [, DELAY=reg_delay] [, WIDTH=reg_width] [, MINCLOCK=reg_minclock] [, HOLD=reg_hold_time] [, ASYNCDELAY=reg_asyncdelay] [, BITWISE=0|1 ] ) name [[array_size]] [ = initial_condition *[, initial_condition] ] ;
input_pin_spec This specifies which input pin is the clock and must be of the form: IN[n] where n is a pin number. See Relationship between ports, netlist entry and symbol definition on page 259 for details on how pin numbers relate to netlist entries and symbol definitions. Register delay in seconds. This is the delay between the clock rising edge and the register value changing. You can use engineering units in the normal way. Default: REG_DELAY parameter in .MODEL control defines default value. This is turn has a default value of 1nS.

reg_delay

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reg_width reg_minclock Register width in bits. This has a maximum of 32. Default: 32 Minimum clock width. This must be less than or equal to reg_delay. The register value will not update if the clock width is less than this value. Default: MIN_CLOCK parameter in .MODEL control defines default value. This in turn has a default value of 0. Register hold time. This is the time that the input data (i.e. assignment value) must remain stable after the clock edge, for the new value to be accepted. If the BITWISE parameter is set to '1' (which it is by default) the hold time is applied on a bit by bit basis. That is any individual bit in the register that remains stable during the hold period will attain the new value even if other bits violate the hold time. If BITWISE is '0' then if a single bit violates the hold time, the whole register will remain unchanged even if some bits remain stable during the hold period. Setting BITWISE to '0' saves system memory which can be important for large arrays (i.e. RAMs). Default: HOLD_TIME parameter in .MODEL control defines default value. This in turn has a default of 0. Time the register takes to acquire a value set by an asynchronous assignment. This must be less than or equal to reg_delay. Default: reg_delay See reg_hold_time Default: '1' for single registers, '0' for arrays. Register name. If specified, the register is arranged as an addressable array of size array_size. Default: 1 Value assigned to register when simulation starts. Default: 0

reg_hold_time

reg_asysncdelay

BITWISE value name array_size

initial_condition

Notes: To implement register setup time, assign a value to reg_hold_time equal to the sum of the register setup and hold times then delay the input data by a period equal to the setup time. Level Triggered Register Declaration

LEVEL (CLOCK=input_pin_spec [, DELAY=reg_delay] [, WIDTH=reg_width] [, SETUP=reg_setup_time] [, ASYNCDELAY=reg_asyncdelay] [, BITWISE=0|1 ] name [[array_size]] [ = initial_condition *[, initial_condition]] ; 261

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input_pin_spec This specifies which input pin is the enable and must be of the form: IN[n] where n is a pin number. See Relationship between ports, netlist entry and symbol definition on page 259 for details on how pin numbers relate to netlist entries and symbol definitions. Register delay in seconds. If the enable is already high, this is the time taken for the register to acquire new data. Otherwise it is the delay between enable rising edge and the register value changing. You can use engineering units in the normal way. Default: REG_DELAY parameter in .MODEL control defines default value. This is turn has a default value of 1nS. Register width in bits. This has a maximum of 32. Default: 32 Register hold time. This is the time that the input data (i.e. assignment value) must remain stable prior to an enable falling edge, for the new value to be accepted. If the BITWISE parameter is set to '1' (which it is by default) the setup time is applied on a bit by bit basis. That is any individual bit in the register that remains stable during the setup period will attain the new value even if other bits violate the setup time. If BITWISE is '0' then if a single bit violates the setup time, the whole register will remain unchanged even if some bits remain stable during the setup period. Setting BITWISE to '0' saves system memory which can be important for large arrays (i.e. RAMs). Default: SETUP_TIME parameter in .MODEL control defines default value. This in turn has a default of 0. Time the register takes to acquire a value set by an asynchronous assignment. This must be less than or equal to reg_delay. Default: reg_delay See reg_setup_time Default: '1' for single registers, '0' for arrays. Register name. If specified, the register is arranged as an addressable array of size array_size. Default: 1 Value assigned to register when simulation starts. Default: 0

reg_delay

reg_width reg_setup_time

reg_asysncdelay

BITWISE value name array_size

initial_condition

Combinational Register Declaration

COMB ( [, DELAY=reg_delay] [, WIDTH=reg_width] [, BITWISE=0|1 ] ) name [ = initial_condition ] ;

reg_delay Register delay in seconds. You can use engineering units in the normal way. If BITWISE is '1' (the default) this delay is applied

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on a bit by bit basis. If BITWISE is '0' then the delay is applied to the whole register. That is the output will not change until all inputs have remained stable for the delay time. Setting BITWISE to '0' is useful when using combinational registers to implement asynchronous state machines as it eliminates race conditions. Default: REG_DELAY parameter in .MODEL control defines default value. This is turn has a default value of 1nS. reg_width name initial_condition Register width in bits. This has a maximum of 32. Default: 32 Register name. Value assigned to register when simulation starts. Default: 0

Read-only Register Declaration

READONLY ([, WIDTH=reg_width] name[[array_size]] [ = initial_condition *[, initial_condition]] ;

reg_width array_size Register width in bits. This has a maximum of 32. Default: 32 If specified, the register is arranged as an addressable array of size array_size. Default: 1 Register name. Value assigned to register when simulation starts. Default: 0

name initial_condition

Read-only registers are usually arranged as an addressable array. When reading a readonly register, the value returned is the value defined by the initial conditions. As the name implies it is not possible to assign read-only registers.

Language Definition - Assignments

Registers and output ports can be assigned using the assignment operator '='. Assignment values can be constants, input ports, other registers, local variables or expressions of any or all of these. Assignments are of the form:

register | output_port | OUT[pin1:pin2] | OUT[pin1] | local_var = expr ; or clocked_register[index] = expr ;

register output_port pin1, pin2 Combinational, edge triggered or level triggered register name. Output port name Output pin numbers. OUT[pin1:pin2] and OUT[pin1] allow outputs to be assigned with having to declare them in a PORT

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statement. local_var Any name not already used for a port or register. This defines the value for a local variable that can be used in subsequent expressions. A local variable may not be used in an expression that precedes its definition. Local variables, input ports, registers and constant values combined using arithmetic, Boolean, bitwise Boolean, shift, conditional and relational operators. See Expression operators below for detailed documentation on all operators. Edge or level triggered register. Array index. This must be smaller than the array size. Arrays are based at 0. That is the first element is zero and the last is (array length-1).

expr

clocked_register index

Expression operators The following table lists all operators available. These are listed in order of precedence. Precedence determines the order of evaluation. For example in the expression:
var1<var2 && var3<var4

The sub-expressions var1<var2 and var3<var4 are evaluated first and the result of that those evaluations combined using && to yield the final result. This is because < has higher precedence than &&. The precedence can be altered using parentheses in the usual way.

Class
Index Unary Arithmetic multiplicative

Operators
[] +*/%

Description
E.g. var1[4]. Index operator to access array element. Operator to single value e.g. -5 Arithmetic multiply/divide/ modulus treating all values as unsigned integers. % returns remainder after division Arithmetic operation treating all values as unsigned integers Shift-left and shift right. E.g. reg1 << 2 will shift reg1 left by two bits If condition met result is 1 (=TRUE) otherwise result is zero (=FALSE)

Arithmetic additive Shift Relational

+<< >> < > <= >=

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Class
Equality

Operators
== <> !=

Description
== means EQUAL <> and != both mean NOT EQUAL Return 1 when condition met and 0 when condition is not met Performs a Boolean AND bit by bit Performs a Boolean exclusive OR bit by bit Performs a Boolean OR bit by bit Returns 1 if both values are nonzero (TRUE) otherwise returns zero (FALSE) Returns 1 if either value is nonzero (TRUE) otherwise return zero (FALSE) Returns res1 if cond is non-zero (TRUE) otherwise returns res2 Example A<B ? 16 : 0 returns 16 if A is less than B otherwise returns 0

Bitwise AND Bitwise XOR Bitwise OR Logical AND

& ^ | &&

Logical OR

||

Conditional expression

cond ? res1 : res2

Note that the operators and their precedence are a subset of those used in the 'C' programming language with the exception of <>. Controlling Output Enables An output can be set into a high impedance state using a modification to an output port variable. Use the suffix .EN after the output port or port identifier to signify that the result of the expression should control the output enable. E.g. the following is extracted from the 74XX244 definition:
PORT (DELAY=USER[0]) Output out[0:3] ; Output.En = Out_En_Del ? 0 : 0xf ;

Examples
Y = !Enable ? A_Del != B_Del : 1 ;

If Enable is 0 then Y will be the result of A_Del != B_Del otherwise the result will be 1.
Shift = !Par_En_Del ? Par_Data_Del :(Shift<<1) | Ser_Data_Del;

This describes the action of a parallel loadable shift register.

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out[0]= !in[1]&!in[2] | in[1]&!in[2]&in[0] | !in[1]&in[2]&in[0]

An example of referencing inputs and outputs directly without needing PORT statements.

Language Definition - User and Device Values

Sometimes it is convenient to use the logic description to define the functionality of a block but have the timing and other specifications specified separately. This is achieved by USER and DEVICE values. USER values are specified in the .MODEL control while DEVICE values are specified on the device at the netlist (or schematic device) level. The values are referenced in the logic definition in the form:

USER[index] and DEVICE[index]

These can replace any constant value in an expression, register qualifier or port qualifier. (Register and port qualifiers are the values in parentheses after the register/ port keyword. E.g. DELAY, HOLD, SETUP etc.). To set USER values in a .MODEL control, assign the parameter USER. This is a vector parameter, that is it can have any number of values and these must be enclosed in square brackets '[' and ']'. For example:
.MODEL Counter8 d_logic_block file=counter_8.ldf + user=[10n, 5n]

The logic definition to which this model refers - counter_8.ldf - can use USER[0] and USER[1] to refer to the values 10n and 5n respectively. To set DEVICE values in a netlist, the netlist entry for the device must be appended with:
: USER=[ values ]

For example:
A$U3 [clock] [Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7] Counter8 : + USER=[10n, 5n]

The logic definition for this device can use DEVICE[0] and DEVICE[1] to access the USER values in the netlist i.e. 10n and 5n respectively. Always remember to include the colon. This acts as a separator between the device name and any parameters.

Diagnostics: Trace File

In order to debug models, a tracing facility is provided. If the .MODEL TRACE_FILE parameter or instance parameter of the same name is specified, a file will be created which lists the values of all internal registers at each time point.

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The file will usually have a number of lines of the form: Roll back to <time> For example the following is an extract from an actual trace file
5.00022e-05 5.09397e-05 5.09407e-05 Roll back to 5.09397e-05 5.09407e-05 5.09657e-05 2696 2696 2692 9 9 10 2696 2696 2692 0 0 0

5.08599e-05 2696 2692 2692 9 10 10 2696 2692 2692 0 0 0

Roll-back occurs when an analog time step is rejected but the digital simulation has already advanced past the new analog time. In this case the digital simulator has to back-track events. This mechanism is central to the operation of the mixed-mode system and is explained in more detail in Mixed-mode Simulator - How it Works below.

Mixed-mode Simulator - How it Works

Event Driven Digital Simulator
The digital simulator is said to be Event Driven. An event is essentially a change of state e.g. a gate output changing from logic '0' to logic '1'. When an event occurs on an output, all devices with inputs connected to that output are notified of the event and can respond appropriately by generating new events. For example, consider the following circuit fragment.
LOGIC '1'

HC04

HC00

U1 U2

HC02

LOGIC '0'

U3

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U1 receives an event, a rising edge at its input at time = T. U1 has a propagation delay of 5.5nS, so on receipt of the event at its input, U1 posts an event at its output with a time T+5.5nS. At that time this event is received by U2 and U3. U3 does not respond to this event because one of its inputs is permanently at logic '1' so its output will always be low. U2, however, does respond and creates a low-high event at a time delayed by its propagation delay of 6.5nS i.e. T+5.5nS+6.5nS. Any device with an input connected to the output of U2 will process this new event and so the process continues. In addition to the propagation delays described above, there are also additional delays caused by loading effects. Each input has an effective input capacitance and each output a resistance. For each event, an additional delay is added equal to the sum of all capacitances on the node multiplied by the driving output's resistance.

Interfacing to the Analog Simulator

Connections between the analog and digital system are made via special interfaces bridges. (As described in Analog to Digital Interfaces on page 245 these bridges are implicitly included by the simulator and it isn't necessary for the user to wire them in.) The digital to analog interface has an output that looks like - to a first approximation an analog representation of a digital gate. This output changes voltage at a specified rise and fall time when the digital input changes state. More importantly, the analog system is notified when an event occurs at the input to a D-A interface bridge and a timestep is forced at that time. This is known as a breakpoint and is the analog equivalent of an event. The analog system is only notified of events that occur at the input of D-A bridges. It knows nothing of events that are internal to the digital system. Analog to digital interface bridges are much like a comparator. When the analog input passes a threshold, the output state changes appropriately and a digital event is generated. Time Step Control With two simulators running largely independently, something is needed to synchronise the timesteps. Basically the analog system is in control. It tells the digital system to process events up to a certain time, that time being the analog system's next anticipated time point. A problem arises, however in that the next analog timestep is not guaranteed to be accepted. The analog system frequently rejects timesteps either because of slow convergence or because a shorter timestep is needed to maintain the required accuracy. If the analog system has to cut back the timestep to a point prior to the most recent digital event, then the digital system has to back-track. This process is known as roll-back and the need for the digital simulator to be able to perform it substantially increases its complexity. In order to roll-back the digital simulator has to store its past history back to the most recent accepted analog timepoint

Enhancements over XSPICE

Gate delays in XSPICE are stored i.e. like a transmission line not like a real gate. SIMetrix gate delays are inertial so if a pulse shorter than the propagation delay is received, it is swallowed not transmitted. Automatic interface creation. In XSPICE you have to explicitly join digital and analog nodes via interface bridges. In SIMetrix this is done automatically.

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Fan out implemented. The underlying mechanism for load dependent delay was there but none of the models supported it. Static loading effects (as in bipolar logic) was not supported at all. In SIMetrix it is. Input load reflected in analog to digital interfaces. The AD interfaces in XSPICE have infinite input impedance regardless of what the digital output is driving. SIMetrix AD interfaces reflect the digital capacitative and static load at their inputs. Output strength reflected in digital to analog interfaces. The DA interfaces in XSPICE have zero output impedance regardless of what is driving them. SIMetrix DA interfaces reflect the strength of the digital output driving the input. A hi-z logic state will look like a hi-z logic state when transferred to the analog domain. This is not the case with XSPICE. AD interface threshold detection. All AD interfaces switch at a particular input threshold. In the XSPICE system the output switched at the first analog timepoint that exceeded the threshold. This could be a long way passed the threshold if the analog time steps are large. In SIMetrix a mechanism has been implemented that cuts back the time step so that the threshold is hit within a specified time tolerance. Arbitrary logic block device. This allows the definition of any logic device using a simple descriptive language. The language accommodates combinational logic, synchronous and asynchronous registers as well as look up tables (i.e. ROMS) and arrays (i.e. RAMs) Arbitrary analog to digital converter. Up to 32 bits with specified input range and offset, conversion time and maximum conversion rate. Output may be in two's complement or offset binary. Arbitrary digital to analogue converter. Up to 32 bit with specified input range and offset and output slew time. Input may be in two's complement or offset binary. Voltage controlled oscillator (analog in digital out). There was one of these in the original XSPICE code but it suffered a number of problems and was scrapped. The SIMetrix version is all new.

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Chapter 10 SIMetrix vs SPICE

Below is a list of incompatibilities between SIMetrix and SPICE Capacitors SIMetrix: Allows two temperature coefficients of capacitance and two voltage coefficients on device line and model. (TC1, TC2, VC1, VC2). Allows polynomial voltage coefficients. Temperature coefficients not supported. Has capacitor model allowing specification in terms of process parameters. Does not support voltage or temperature coefficients.

SPICE 2 SPICE 3

Inductors SIMetrix SPICE 2 SPICE 3 MOSFETs SIMetrix Supports levels 1, 2 & 3 and new proprietary level 7 designed for vertical devices. Supports specification for L and W as model parameters for compatibility with PSpice. Supports levels 1, 2 & 3 Supports levels 1-6. Levels 4 and 5 are BSIM1 and BSIM2 respectively. Level 6 is a new empirical model Inductance value only Allows polynomial current coefficients. Inductance value only

SPICE 2 SPICE 3

Resistors SIMetrix SPICE 2 SPICE 3 Supports 2 temperature coefficients on device line and in model. Supports 2 temperature coefficients on device line only. Supports 2 temperature coefficients in model only. Also allows specification of resistance in terms of process parameters.

Voltage Controlled Switches SIMetrix Switch specified in terms of model describing on resistance (RON), off resistance (ROFF), turn on voltage (VON) and turn off voltage (VOFF). Resistance between VON and VOFF varies continuously following a cubic law. Switch model is compatible with PSpice Switches not implemented.

SPICE 2

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SPICE 3 Switch specified in terms of on resistance, off resistance, threshold voltage and hysteresis voltage. Device switches abruptly at appropriate voltage.

Additional model parameters have been added to some devices for compatibility with other commercial simulators. Devices affected are: Diodes BJTs JFETs MOSFETs The following devices are implemented in SPICE 3 but are not available with SIMetrix. Current controlled switch Uniform Distributed RC Line Analysis Modes Two analysis modes available in standard SPICE 3 have not been implemented in SIMetrix. Details follow: Distortion analysis. (.DISTO) This has not been implemented primarily because the usefulness of this mode is limited. The analysis only provides 2nd and 3rd harmonics which would is inadequate for the majority of applications. SIMetrix is supplied instead with a comprehensive suite of spectral analysis post processing functions. Fourier analysis (.FOUR). This isn't really an analysis mode at all but a post processing function. SIMetrix is supplied with a script - FOUR - which performs the same action as this analysis mode. In fact it is superior because it can be applied to any signal after the run is complete whereas the standard SPICE .FOUR analysis requires the user to specify the signal in advance of the simulation.

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Index

Index

.ALIAS 173 .DC 174 .ENDF 175 .ENDS 39 .FILE 175 .FUNC 176 .GRAPH 177 .INC 184 .LIB 186 .MODEL 187 .NODESET 190 .OPTIONS 195 .OUT file 22 .PARAM 30, 37, 205 .SUBCKT 39, 210 .SXDAT files 23 .TEMP 211 .TRACE 213

A
ABS (function) 34 ABSTOL (simulator option) 196, 241 ABSTOLMAX (simulator option) 196 AC analysis 171 ACCT (simulator option) 196 ACOS (function) 34 ACOSH (function) 34 ad_converter model 150 adc_bridge model 153 adc_schmitt model 165 Analog-digital converter 150 Analog-digital interface bridge 153 Analog-digital schmitt trigger 165 And gate 110 Arbitrary logic block language definition 252 model 129 Arbitrary source 46 charge devices 47 examples 48 273

Simulator Reference Manual flux devices 47 look-up tables 35 non-linear capacitors and inductors 47 ASIN (function) 34 ASINH (function) 34 ASYNCDELAY - arbitrary logic block keyword 260, 261 ATAN (function) 34 ATAN2 (function) 34 ATANH (function) 34

B
Batch mode 14 B-H curves 73 BINDIAG (simulator option) 196 Bipolar junction transistor 50, 53, 57 BITWISE - arbitrary logic block keyword 260, 261, 262 BJT 50, 53, 57 model parameters 51 BSIM3 84 BSIM4 85 Buffer (digital) 116

C
Capacitor 58 model parameters 60 Capacitor with voltage initial condition 60 CCCS 61 CCVS 62 CHGTOL (simulator option) 196, 241 CLOCK - arbitrary logic block keyword 260, 261 cm_cap model 60 cm_ind model 73 COMB - arbitrary logic block keyword 262 Comments 20 inline 44 Configuration 16 Connection types 27 Constant parameters 30 Controlled digital oscillator 163 Convergence 228 COS (function) 34 COSH (function) 34 Current controlled current source 61 Current controlled switch 271 Current controlled voltage source 62 274

Index Current source 63

D
d_and model 111 d_buffer model 116 d_dff model 114 d_dlatch model 112 d_fdiv model 118 d_inverter model 124 d_jkff model 126 d_nand model 131 d_nor model 132 d_open_c model 133 d_open_e model 134 d_or model 135 d_osc model 164 d_pulldown model 136 d_pullup model 137 d_pulse model 120 d_ram model 138 d_source model 121 d_srff model 139 d_srlatch model 142 d_state model 143 d_tff model 145 d_tristate 147 d_xnor model 148 d_xor model 149 da_converter model 157 dac_bridge model 160 Data file 23 Data names 24 DC analysis 174 DCOPSEQUENCE (simulator option) 196 DDT (function) 34 DEFAD (simulator option) 196 DEFAS (simulator option) 196 DEFL (simulator option) 196 DEFNRD (simulator option) 196 DEFNRS (simulator option) 196 DEFPD (simulator option) 196 DEFPS (simulator option) 196 DEFW (simulator option) 196 Delay load 251 275

Simulator Reference Manual wire 252 DELAY - arbitrary logic block keyword 260, 261, 262 Delay time (pulse source) 98 DEVICE - arbitrary logic block keyword 266 Digital devices 109 delays 110 family parameters 109, 248 input parameters 110 output parameters 109 Digital model libraries 252 Digital pulse 120 Digital signal source 121 Digital simulation 244 analog to digital interfaces 245 logic families 247 logic states 244 Digital-analog converter 157 Digital-analog interface bridge 160 DIGMINTIME (simulator option) 196 Diode 64 model parameters 65, 67 Distortion analysis 271 D-type flip flop 114 D-type latch 112

E
Ebers-Moll 53 EDGE - arbitrary logic block keyword 260 EKV 86 Embedding files in netlist 175 Exclusive NOR gate 148 Exclusive OR gate 149 EXP (function) 34 EXPAND (simulator option) 23, 197 EXPANDFILE (simulator option) 23, 197 Exponential source 102 Expressions 2838 .PARAM 30 circuit variables 29 for arbitrary source 47 for device parameters 29 for model parameters 29 functions 34 operators 31 parameters 30 276

Index syntax 29

F
Fall time pulse source 98 FAMILY (model parameter) 248 FASTPOINTTOL (simulator option) 197 FASTRELTOL (simulator option) 197 Files - embedding in netlist 175 Filter response functions 92 Flicker noise, resistor 88 FLOOR (function) 34 FLUXTOL (simulator option) 197, 241 Fourier analysis 271 Frequency divider 117

G
GaAsFET 68 model parameters 69 Gate-drain capacitance 83 GAUSS (function) 35 GAUSSE (function) 35 GAUSSEL (function) 35 GAUSSL (function) 35 GEAR 199 Gear integration 242 Global nodes 42 GMIN (simulator option) 197 GMIN, MOSFET implementation 86 GMINMAXITERS (simulator option) 197 GMINMULT (simulator option) 197 GMINSTEPITERLIMIT (simulator option) 197 Gummell Poon 50 Gummel-Poon 53

H
HIGH (logic state) 244 HI-IMPEDANCE (logic strength) 244 HOLD - arbitrary logic block keyword 260

I
ICRES (simulator option) 197 IF (function) 34 IFF (function) 34 IGBT 74 IN_FAMILY (model parameter) 248 277

Simulator Reference Manual Inductor 70 saturable 70 with hysteresis 70 Inductor with current initial condition 73 Initial conditions 183 Initial value (pulse source) 98 Integration methods 241 Internal nodes 25 Inverter (digital) 124 ITL1 (simulator option) 198 ITL2 (simulator option) 198 ITL4 (simulator option) 198 ITL7 (simulator option) 198

J
JFET 75 Jiles-Atherton 72 JK flip-flop 125 JUNCAP 104 Junction FET 75 model parameters 76

L
Language 44 Language declaration 19 Laplace block 88 LEVEL - arbitrary logic block keyword 261 LIMIT (function) 34 List file 22 LN (function) 34 Load delay 251 LOG (function) 34 LOG10 (function) 34 Logic compatibility tables 248 Logic families 247 Logic states 244 LOGICHIGH (simulator option) 33, 198 LOGICLOW (simulator option) 33, 198 LOGICTHRESHHIGH (simulator option) 33, 198 LOGICTHRESHLOW (simulator option) 33, 198 Look-up tables 35 Lossy transmission line 77 model parameters 78 LOW (logic state) 244 278

Index

M
MATCHEDSUBCIRCUITS (simulator option) 198 MAX (function) 34 MAXEVTITER (simulator option) 198 MAXOPALTER (simulator option) 198 MAXORD (simulator option) 198 MaxVectorBufferSize (global setting) 17 MC_ABSOLUTE_RECT (simulator option) 199 MC_MATCH_RECT (simulator option) 199 MCLOGFILE (simulator option) 199 METHOD (simulator option) 199, 241 Mextram 106 MIN (function) 34 MINBREAK (simulator option) 199 MINCLOCK - arbitrary logic block keyword 260 MINGMINMULTIPLIER (simulator option) 199 MINTIMESTEP (simulator option) 199 Model parameters analog-digital bridge 154 analog-digital converter 151 arbitrary logic block 130 BJT 51 Buffer 116 capacitor 60 controlled digital oscillator 164 digital initial condition 119 digital pulse 120 digital signal source 122 digital-analog bridge 161 digital-analog converter 158 diode 65, 67 D-type flip-flop 114 D-type latch 112 exclusive NOR gate 148 exclusive OR gate 149 frequency divider 118 gaAsFET 69 inverter 125 JK flip-flop 126 junction FET 76 laplace block 89 lossy transmission line 78 MOSFET 82 NAND gate 131 279

Simulator Reference Manual NOR gate 132 open-collector buffer 133 open-emitter buffer 134 OR gate 135 pulldown resistor 136 pullup resistor 137 resistor 88 schmitt trigger 166 set-reset flip-flop 139 SR latch 142 state machine 143 toggle flip-flop 145 tri-state buffer 147 voltage controlled switch 96 Monte Carlo distribution functions 35 MOS9 104 MOSFET 79 model parameters 80, 82 MOSGMIN (simulator option) 200 Multi step analyses 170 Mutual inductor 103

N
Names, vector 24 Nand gate 131 Netlist 18 NEWGMIN (simulator option) 200 NODELIMIT (simulator option) 200 Nodes, internal 25 NODESETRES (simulator option) 200 Noise analysis creating noise info file 193 real time 216 Noise source 103 NOMCLOG (simulator option) 200 NOMOD (simulator option) 23, 200 NOMOS9GATENOISE (simulator option) 200 Non-GUI mode 14 NOOPALTER (simulator option) 200 NOOPINFO (simulator option) 200 NOOPITER (simulator option) 200 Nor gate 132 NORAW (simulator option) 201 NOSENSFILE (simulator option) 201 280

Index NoStopOnUnknownParam (global setting) 17 NUMDGT (simulator option) 201

O
OLDLIMIT (simulator option) 201 OLDMOSGMIN (simulator option) 201 OLDMOSNOISE (simulator option) 201 Open-collector buffer 133 Open-emitter buffer 134 Operating point analysis output file 195 OPINFO (simulator option) 23, 201 OPINFOFILE (simulator option) 201 OPTIMISE (simulator option) 201 Or gate 135 OUT - arbitrary logic block keyword 263 OUT_FAMILY (model parameter) 248 out_res 251 out_res_neg 251 out_res_pos 251

P
Parameters .PARAM 205 built-in constants 30 in circuits 36 model 205 passing to subcircuits 206 PARAMLOG (simulator option) 23, 202 Period (pulse source) 98 Philips models 104 Piece-wise linear source 99 PIVREL (simulator option) 202 PIVTOL (simulator option) 202 POINTTOL (simulator option) 202, 241 POLY 61, 63 Polynomial specification 62 PORT - arbitrary logic block keyword 258 PSpice 19 PTAACCEPTAT 202 PTACONFIG (simulator option) 203 PTAMAXITERS (simulator option) 203 PTAOUTPUTVECS (simulator option) 203 Pulldown resistor 136 Pullup resistor 137 281

Simulator Reference Manual Pulse (digital) 120 Pulse source 98 Pulse width (pulse source) 98 Pulsed value (pulse source) 98 PWL file source 100 PWR (function) 34 PWRS (function) 34

R
Random access memory 137 READONLY - arbitrary logic block keyword 263 Real time noise analysis 216 RELTOL (simulator option) 203, 241 RELTOLMAX (simulator option) 203 RESISTIVE (logic strength) 244 Resistor 87 model parameters 88 Rise time pulse source 98 RSHUNT (simulator option) 203

S
s_xfer model 89 SDT (function) 34 SearchDefaultTol (global setting) 17 SEED (simulator option) 203 SENSFILE (simulator option) 203 Sensitivity analysis 209 Set-reset flip-flop 138 SETUP - arbitrary logic block keyword 261 SGN (function) 34 SIMULATOR CONTROLS .FILE 101, 175 Simulator controls .AC 171 .ALIAS 173 .DC 174 .ENDF 175 .GRAPH 177 .IC 183 .INC 184 .LIB 186 .MODEL 187 .NODESET 190 .OP 194 282

Index .OPTIONS 195 .PARAM 205 .SENS 209 .SUBCKT 210 .TEMP 211 .TRACE 213 .TRAN 213 SIN (function) 34 Single frequency FM 102 SINH (function) 34 Sinusoidal source 101 Snapshots 215 SOURCEMAXITERS (simulator option) 203 Spectrum (function) 182 SQRT (function) 34 SR latch 141 Star-Hspice 19 State machine (model) 143 States - logic 244 Stimulus exponential source syntax 102 noise source syntax 103 piece wise linear syntax 99 pulse source syntax 98 PWL file source syntax 100 sine source syntax 101 single frequency FM syntax 102 STP (function) 34 STRONG (logic strength) 244 Subcircuits 39 .SUBCKT control 210 calling from a netlist 41 global nodes 42 nesting 42 passing parameters 41

T
Tables, look-up 35 TAN (function) 35 TANH (function) 35 TEMP (simulator option) 204 TempDataDir (global setting) 17 TIMESTATS (simulator option) 204 TLMINBREAK (simulator option) 204 TNOM (simulator option) 204 283

Simulator Reference Manual Toggle flip-flop 144 TotalVectorBufferSize (global setting) 17 Trace file (arbitrary logic block) 266 Transient analysis 213 fast start 215 snapshots 215 Transmission line (lossless) 94 Transmission line (lossy) 77 Tri-state buffer 146 TRTOL (simulator option) 204, 241 TRYTOCOMPACT (simulator option) 204

U
U (function) 35 UIC 214 UNDETERMINED (logic strength) 244 UNIF (function) 35 UNIFE (function) 35 UNIFEL (function) 35 UNIFL (function) 35 Uniform distributed RC line 271 UNIV - universal logic family 251 UNKNOWN (logic state) 244 URAMP (function) 35 USER - arbitrary logic block keyword 266 VBIC 53, 57 VCVS 95 Vector connections 26 Vector names 24 VNTOL (simulator option) 205, 241 VNTOLMAX (simulator option) 205 Voltage controlled current source 95 Voltage controlled switch 95 model parameters 96 Voltage source 97 exponential 102 noise source 103 piece wise linear 99 pulse 98 PWL file 100 sine 101 single frequency FM 102 284

Index

W
WC (function) 35 WCE (function) 35 WCEL (function) 35 WCL (function) 35 WIDTH - arbitrary logic block keyword 260, 261, 262, 263 WIDTH (simulator option) 23, 205 Wire Delay 252 WIRETABLE (simulator option) 205

X
XSPICE devices 109

285