Computer Organization and
Computer Organization and
(SS ZG516)
BITS Pilani
K K Birla Goa Campus
Contd
Reference Books from 24x7 C. Madana Kumar Reddy, Operating Systems Made Easy Laxmi Publications, India, 2009 Nirmala Sharma, Computer Architecture Laxmi Publications, India, 2009
Evaluation Components
Three Evaluation Components
EC1 : Online Quiz (15%) EC2: Mid Semester Test (35%) EC3: Comprehensive Examination (50%)
BITS Pilani
K K Birla Goa Campus
Lecture 1: Introduction
Source: Most of the Slides are based on original slides of William Stallings
Contents
Computer Components Functions Interconnection Structures
Definition of a Computer
Device capable of performing computations and making logical decisions
Is a complex system
Is a programmable device Must be able to process data Must be able to store data Must be able to move data
Computers process data under the control of sets of instructions called computer programs
BITS Pilani, K K Birla Goa Campus
Computer Hardware
Computer Software
System Software
Application Software
Output unit
Outputs information (to screen, to printer, to control other devices)
Memory unit
Rapid access, low capacity, stores input information
Contd
CPU Input ALU Output
CU
Memory
Structure is the way in which components relate to each other Function is the operation of individual components as part of the structure
Function
Functions of Computer:
Data processing Data storage Data movement Control
Operations: Storage
Main Memory
Systems Interconnection
19
BITS Pilani, K K Birla Goa Campus
ALU Registers
CPU
Control unit
20
BITS Pilani, K K Birla Goa Campus
Sequencing logic
Control unit
Control memory
21
BITS Pilani, K K Birla Goa Campus
Contd
Stored-program computers have the following characteristics:
Three hardware systems: A central processing unit (CPU) A main memory system An I/O system The capacity to carry out sequential instruction processing. A single path between the CPU and main memory. This single path is known as the von Neumann bottleneck.
23
BITS Pilani, K K Birla Goa Campus
24
BITS Pilani, K K Birla Goa Campus
Harvard Architecture
Uses separate memory for data and program Example: MIPS processor
What is a program?
A sequence of steps For each step, an arithmetic or logical or data movement operation is done For each operation, a different set of control signals is needed Hardwired program: process of connecting various components in the desired configuration as a form of programming
Data Sequence of arithmetic and Logic functions Results
26
BITS Pilani, K K Birla Goa Campus
Contd
Software program: Uses general purpose configuration of arithmetic and logic functions and instruction interpreter which decodes the instruction codes and generates control signals that drives general purpose hardware.
Instruction Codes
Instruction Interpreter
Control Signals General Purpose Arithmetic and Logic functions
Data
Results
Contd
Hardwired systems are fast but inflexible Using software program general purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals
29
BITS Pilani, K K Birla Goa Campus
Instruction Cycle
Two steps:
Fetch Execute
30
BITS Pilani, K K Birla Goa Campus
Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions
31
BITS Pilani, K K Birla Goa Campus
Execute Cycle
Processor-memory
data transfer between CPU and main memory
Processor-I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations e.g. jump
Combination of above
32
BITS Pilani, K K Birla Goa Campus
Hypothetical Machine
0 Opcode 3 4 Address 15
With 4 bits of opcode we can represent 16 different instructions With 12 bits address we can address 212 = 4096 (4K) memory locations
Hypothetical Machine
Program Counter (PC) = Address of instruction
Instruction Register (IR) = Instruction being executed Accumulator (AC) = Temporary storage
Program statement
Write a program to add the contents of the memory word at address 940H to the contents of the memory word at address 941H and store the result in the location 941H
Program statement
Write a program to add the contents of the memory word at address 940H to the contents of the memory word at address 941H and store the result in the location 941H need 3 instructions:
Load AC from memory address 940H opcode is 0001 1H
Instruction : 1940H
Add to AC from memory address 941H opcode is 0101 5H
Instruction : 5941H
Store AC to memory address 941H opcode is 0010 2H
Instruction : 2941H
37
BITS Pilani, K K Birla Goa Campus
38
BITS Pilani, K K Birla Goa Campus
Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
e.g. memory parity error
39
BITS Pilani, K K Birla Goa Campus
40
BITS Pilani, K K Birla Goa Campus
Interrupt Cycle
Added to instruction cycle Processor checks for interrupt
Indicated by an interrupt signal
42
BITS Pilani, K K Birla Goa Campus
43
BITS Pilani, K K Birla Goa Campus
44
BITS Pilani, K K Birla Goa Campus
45
BITS Pilani, K K Birla Goa Campus
46
BITS Pilani, K K Birla Goa Campus
Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt
47
BITS Pilani, K K Birla Goa Campus
48
BITS Pilani, K K Birla Goa Campus
49
BITS Pilani, K K Birla Goa Campus
50
BITS Pilani, K K Birla Goa Campus