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Data Sheet

The Broadcom(r) BCM4330 single chip device provides for the highest level of integration for a mobile or handheld wireless system. It includes integrated IEEE 802.11(tm) a / b / g and single-stream 802.11n (MAC / baseband / radio), Bluetooth(r) 4. + HS, and FM radio receiver and transmitter. The device includes on-chip 2. GHz and 5 GHz WLAN CMOS power amplifiers that meet the output power requirements of

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Data Sheet

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Preliminary Data Sheet

BCM4330
Single Chip IEEE 802.11 a/b/g/n MAC/Baseband/ Radio with Integrated Bluetooth 4.0 + HS and FM Transceiver
GE N ER A L DE S CR I P TI O N The Broadcom BCM4330 single chip device provides for the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 a/b/g and single-stream 802.11n (MAC/baseband/radio), Bluetooth 4.0 + HS, and FM radio receiver and transmitter. It includes on-chip 2.4 GHz and 5 GHz WLAN CMOS power amplifiers that meet the output power requirements of most handheld systems while permitting an optional external power amplifier for higher output power applications, if required. Utilizing advanced design techniques and process technology to reduce active and idle power, the BCM4330 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for operation directly from a mobile platform battery while maximizing battery life.
VIO

F E A T U RE S The BCM4330 implements the highly sophisticated Enhanced Collaborative Coexistence radio coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative Bluetooth coexistence scheme along with coexistence support for external radios (such as GPS, WiMax, or Ultra Wide-band radio technologies, as well as cellular radios) and a single shared antenna (2.4 GHz antenna for Bluetooth and WLAN). As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. For the WLAN section, two alternative host interface options are included: an SDIO v2.0 interface that can operate in 4b, 1b, or gSPI modes, and an HSIC interface. An independent, high-speed UART is provided for the Bluetooth host interface. Package options include 4.89 mm x 5.33 mm WLBGA and WLCSP, and 6.5 mm x 6.5 mm FCFBGA.

Vbatt

WL_RESETx

BCM4330

WLAN Host I/F

WL_IRQ SDIO*/SPI HSIC CLK_REQ BT_RESETx 5 GHz WLAN Tx 5 GHz WLAN Rx

T/R Switch or FEM

Bluetooth Host I/F

UART I2S/PCM BT_WAKEUP UART_WAKEUP

UART I2S_DO/PCM_OUT (FM Rx) 2.4 GHz WLAN Tx 2.4 GHz WLAN/BT Rx Bluetooth Tx

FM TX/RX Host I/F

I2S_DI/PCM_IN (FM Tx) I2S_WS/PCM_SYNC (FM Rx/Tx) I2S_CK/PCM_CLK (FM Rx/Tx) Analog Audio Out

SP3T Switch

CBF

FM Tx FM Rx

Figure 1: Functional Block Diagram

4330-DS206-R 5300 California Avenue Irvine, CA 92617 Phone: 949-926-5000 Fax: 949-926-5203
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August 17, 2011

BCM4330 Preliminary Data Sheet

Revision History

F E A T U RE S IEEE 802.11x Key Features Single-band 2.4 GHz 802.11 b/g/n or dualband 2.4 GHz and 5 GHz 802.11 a/b/g/n (nonsimultaneous) Single stream 802.11n support for 20 MHz channels provides PHY layer rates up to MCS7 (72 Mbps) for typical upper-layer throughput in excess of 45 Mbps. Integrated CMOS power amplifiers with internal power-detectors and closed-loop power control can deliver greater than 18 dBm of linear output power (in 2.4 GHz band). PAs can be powered directly from VBAT, eliminating the need for a PALDO. Up to 8 RF control signals are available to support optional external PAs for higher output power and LNAs for enhanced sensitivity. Supports a single 2.4 GHz antenna shared between WLAN and Bluetooth. Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN. Internal fractional nPLL allows support for a wide range of reference clock frequencies Supports IEEE 802.15.2 external three-wire coexistence scheme to optimize bandwidth utilization with other co-located wireless technologies such as GPS, WiMax, or UWB Supports standard SDIO v2.0 (50 MHz, 4-bit and 1-bit), and gSPI (48 MHz) host interfaces. Alternative host interface supports HSIC (a USB 2.0 derivative for short-distance, onboard connections). Integrated ARM Cortex-M3 processor and on-chip memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. OneDriver software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as future devices.

F E A T U RE S Bluetooth and FM Key Features Bluetooth Core Specification Version 4.0 + HS compliant with provisions for supporting future specifications Bluetooth Class 1 or Class 2 transmitter operation Supports extended Synchronous Connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets Adaptive Frequency Hopping (AFH) for reducing radio frequency interference Interface support Host Controller Interface (HCI) using a high-speed UART interface and PCM for audio data The FM unit supports HCI for communication, stereo analog input and output Low-power consumption improves battery life of handheld devices FM receiver: 65 MHz to 108 MHz FM bands; supports the European Radio Data Systems (RDS) and the North American Radio Broadcast Data System (RBDS) standards Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound Automatic frequency detection for standard crystal and TCXO values FM transmitter: 65 MHz to 108 MHz bands; supports both RDS and the RBDS standards and programmable output power. General Features Supports battery voltage range from 2.3V to 4.8V supplies with internal switching regulator Programmable dynamic power management 2 Kbit OTP for storing board parameters Package options: - 144 ball FCFBGA (6.5 mm x 6.5 mm, 0.5 mm pitch) - 133 ball WLBGA (4.89 mm x 5.33 mm, 0.4 mm pitch) - 225 bump WLCSP (4.89 mm x 5.33 mm, 0.2 mm pitch) Security: - WPA- and WPA2- (Personal) support for powerful encryption and authentication - AES and TKIP in hardware for faster data encryption and 802.11i compatibility - Reference WLAN subsystem provides Cisco Compatible Extension- (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0) certified - Reference WLAN subsystem provides Wi-Fi Protected Setup (WPS) Worldwide regulatory support: Global products supported with worldwide homologated design

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Revision History
Revision 4330-DS206-R Date 8/17/11 Change Description Updated: Table 51: HSIC Interface Specifications, on page 156. Table 54: Ordering Information, on page 167. Updated: Voltage Regulators on page 25. The introduction of Section 4: Bluetooth + FM Subsystem Overview, on page 37. Figure 8: Startup Signaling Sequence, on page 45. FM Radio on page 65. Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions, on page 104. Table 19: WLAN GPIO Functions and Strapping Options, on page 113. Table 23: I/O States, on page 116. Table 26: ESD Specifications, on page 119. Table 27: Recommended Operating Conditions and DC Characteristics, on page 120. Table 31: FM Transmitter Specifications, on page 127. Table 32: FM Receiver Specifications, on page 129. Table 34: WLAN 2.4 GHz Receiver Performance Specifications, on page 135. Table 35: WLAN 2.4 GHz Transmitter Performance Specifications, on page 138. Table 36: WLAN 5 GHz Receiver Performance Specifications, on page 140. Table 37: WLAN 5 GHz Transmitter Performance Specifications, on page 142. WLAN Current Consumption on page 150. Table 51: HSIC Interface Specifications, on page 157. Figure 49: WLAN = ON, Bluetooth = OFF, on page 161. Broadcom Corporation 5300 California Avenue Irvine, CA 92617 2011 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom, the pulse logo, Connecting everything, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET AS-IS, WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.

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BCM4330 Preliminary Data Sheet

4330-DS200-R

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BCM4330 Preliminary Data Sheet

Table of Contents

SDIO Pin Descriptions ............................................................................................................................72 Generic SPI Mode .........................................................................................................................................74 SPI Protocol............................................................................................................................................75 Command Structure .......................................................................................................................76 Write...............................................................................................................................................76 Write/Read .....................................................................................................................................76 Read ................................................................................................................................................76 Status ..............................................................................................................................................77 gSPI Host-Device Handshake .................................................................................................................79 Boot-Up Sequence .................................................................................................................................79 HSIC Interface ...............................................................................................................................................82

Section 12: Wireless LAN MAC and PHY........................................................................... 83

MAC Features ...............................................................................................................................................83 MAC Description ....................................................................................................................................83 PSM.................................................................................................................................................85 WEP ................................................................................................................................................85 TXE ..................................................................................................................................................86 RXE..................................................................................................................................................86 IFS ...................................................................................................................................................87 TSF ..................................................................................................................................................87 NAV.................................................................................................................................................87 MAC-PHY Interface .........................................................................................................................87 WLAN PHY Description .................................................................................................................................88 PHY Features..........................................................................................................................................88

Section 13: WLAN Radio Subsystem ............................................................................... 91

Receive Path .................................................................................................................................................91 Transmit Path ...............................................................................................................................................91 Calibration ....................................................................................................................................................91

Section 14: Pinout and Signal Descriptions ...................................................................... 93

Signal Assignments .......................................................................................................................................93 WLAN GPIO Signals and Strapping Options .........................................................................................112 Muxed Bluetooth GPIO Signals ............................................................................................................113 I/O States .............................................................................................................................................115

Section 15: DC Characteristics ....................................................................................... 117

Absolute Maximum Ratings .......................................................................................................................117

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BCM4330 Preliminary Data Sheet

Table of Contents

Environmental Ratings ............................................................................................................................... 118 Electrostatic Discharge Specifications .......................................................................................................118 Recommended Operating Conditions and DC Characteristics ..................................................................119

Section 16: Bluetooth RF Specifications......................................................................... 121 Section 17: FM Transmitter Specifications ..................................................................... 126 Section 18: FM Receiver Specifications .......................................................................... 128 Section 19: WLAN RF Specifications............................................................................... 133
Introduction ................................................................................................................................................133 2.4 GHz Band General RF Specifications ....................................................................................................134 WLAN 2.4 GHz Receiver Performance Specifications ................................................................................134 WLAN 2.4 GHz Transmitter Performance Specifications...........................................................................137 WLAN 5 GHz Receiver Performance Specifications ...................................................................................139 WLAN 5 GHz Transmitter Performance Specifications ..............................................................................141 General Spurious Emissions Specifications................................................................................................142

Section 20: Internal Regulator Electrical Specifications.................................................. 143

Core Buck Regulator ...................................................................................................................................143 LDO3p1 .......................................................................................................................................................144 LDO3p3 .......................................................................................................................................................145 CLDO ...........................................................................................................................................................146 LNLDO1 .......................................................................................................................................................147

Section 21: System Power Consumption........................................................................ 148

WLAN Current Consumption ......................................................................................................................149 WLAN Current Consumption 2.4 GHz Operation .............................................................................149 WLAN Current Consumption 5 GHz Operation ................................................................................150 HSIC Interface Current Consumption .........................................................................................................151 Bluetooth and FM Current Consumption ..................................................................................................151

Section 22: Interface Timing and AC Characteristics ...................................................... 152

SDIO/gSPI Timing ........................................................................................................................................152 SDIO Default Mode Timing ..................................................................................................................152 SDIO High-Speed Mode Timing............................................................................................................154 gSPI Signal Timing ................................................................................................................................155 HSIC Interface Specifications......................................................................................................................156 JTAG Timing ................................................................................................................................................157

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BCM4330 Preliminary Data Sheet

Table of Contents

Section 23: Power-Up Sequence and Timing.................................................................. 158

Sequencing of Reset and Regulator Control Signals..................................................................................158 Description of Control Signals..............................................................................................................159 Control Signal Timing Diagrams ...........................................................................................................159

Section 24: Package Information ................................................................................... 162

Package Thermal Characteristics ...............................................................................................................162 Junction Temperature Estimation and PSIJT Versus THETAJC ...................................................................162 Environmental Characteristics ...................................................................................................................162

Section 25: Mechanical Information .............................................................................. 163

WLCSP Package Keep-Out Area .................................................................................................................166

Section 26: Ordering Information .................................................................................. 167

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BCM4330 Preliminary Data Sheet

List of Figures

References
The references in this section may be used in conjunction with this document. Note: Broadcom provides customer access to technical documentation and software through its Customer Support Portal (CSP) and Downloads & Support site (see Technical Support). For Broadcom documents, replace the xx in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document (or Item) Name Broadcom Items
[1] Printed Circuit Board Layout Guidelines and Component Selection for Optimized PMU Performance 4330_4336_AN1xx-R

Number

Source CSP

Technical Support
Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering support representative. In addition, Broadcom provides other product support through its Downloads & Support site (http://www.broadcom.com/support/).

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BCM4330 Preliminary Data Sheet

BCM4330 Overview

Section 1: BCM4330 Overview

Overview
The Broadcom BCM4330 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 a/b/g/n (MAC/baseband/radio), Bluetooth 4.0 + EDR (enhanced data rate), and FM transceiver. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the BCM4330 and their associated external interfaces, which are described in greater detail in the following sections.

BT_REST

BT_REG_ON

WL_ REG_ON

VBAT

FM
Rx Tx Radio Control

POR /System Reset

LDO3P1 LDO3P3 CBUCK CLDO LN LDO BT - PLL Xtal Osc LPO Xtal/ Ext Clk LPO

FM demod, MDX, RDX decode FM stereo OUT DACs FM I/F

CLB (Coexis tence, PMU , etc)

WL - PLL

BT
UART Dig IOs Dbg -UART PCM, I2S RAM

WL
USB20/11 Dev PMU Ctrl SDIO/SPI
JTAG
CORTEX -M3

HSIC SDIO/ SPI

AXI backplane

ROM Intr Ctrl Addr Decoder

WDog mer OTP GPIO UART JTAG Dig IO

RAM ROM

JTAG

CORTEX -M3

Bus Arbiter

PMU Ctrl BLE JTAG -M DMA AHB2APB BT clk/Hopper RX/TX LCU APU Blue RF i/f WDog mer Remap/Pause BT GPIO Modem GPIO s/w mer Tx Shared LNA PA (Int) PA (Int) RADIO 2.4GHz 5GHz 802.11agn (single strm), 2x1STBC Enhanced coexistence i/f Shared LNA control MAC PHY RADIO

BPF

Mobile Phone Usage Model

The BCM4330 incorporates a number of unique features to simplify integration into mobile phone platforms. Its flexible PCM and UART interfaces enable it to transparently connect with the existing circuits. In addition, the TCXO and LPO inputs allow the use of existing handset features to further minimize the size, power, and cost of the complete system. The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or multiple external codec devices. The UART interface supports hardware flow control with tight integration to power control sideband signaling to support the lowest power operation. The TCXO interface accommodates any of the typical reference frequencies used by cell phones. An analog FM receiver interface is available for legacy systems. FM digital interfaces can use either I2S or PCM. The highly linear design of the radio transceiver ensures that the device has the lowest spurious emissions output regardless of the state of operation. It has been fully characterized in the global cellular bands. The transceiver design has excellent blocking (eliminating desensitization of the Bluetooth receiver) and intermodulation performance (distortion of the transmitted signal caused by the mixing of the cellular and Bluetooth transmissions) in the presence of a any cellular transmission (GSM, GPRS, CDMA, WCDMA, or iDEN). Minimal external filtering is required for integration inside the handset. The BCM4330 is designed to provide direct interface with new and existing handset designs as shown in Figure 3.
VIO Vbatt

WL_RESETx

5 GHz WLAN Tx 5 GHz WLAN Rx

T/R Switch or FEM

WLAN Host I/F

WL_IRQ SDIO*/SPI HSIC CLK_REQ BT_RESETx

Bluetooth Host I/F

UART I2S/PCM BT_WAKEUP UART_WAKEUP

2.4 GHz WLAN Tx 2.4 GHz WLAN/BT Rx Bluetooth Tx

SP3T Switch CBF

BCM4330

UART I2S_DO/PCM_OUT (FM Rx)

FM Tx/Rx Host I/F

I2S_DI/PCM_IN (FM Tx) I2S_WS/PCM_SYNC (FM Rx/Tx) I2S_CK/PCM_CLK (FM Rx/Tx) Analog Audio Out

FM Tx FM Rx

Figure 3: Mobile Phone Block System Diagram

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BCM4330 Preliminary Data Sheet

Power Supplies and Power Management

Section 2: Power Supplies and Power Management

Power Supply Topology
One Buck regulator, four LDO regulators, and a Power Management Unit (PMU) are integrated into the BCM4330. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth, WLAN, and FM functions in embedded designs. All regulator inputs and outputs are brought out to pins on the BCM4330. This allows maximum flexibility for the system designer to choose which of the BCM4330 integrated regulators to use. A single host power supply can be used (including VBATT ranging from 2.3V to 4.8V) with all additional voltages being provided by the regulators in the BCM4330. Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators. The CBuck CLDO and LNLDO power up when any of the reset signals are de-asserted. All regulators are powered down only when both resets are asserted. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the digital baseband.

Voltage Regulators
All BCM4330 regulator output voltages are PMU-programmable and have the following nominal ratings. The currents listed below indicate the capabilities of each regulator. See Section 21: System Power Consumption, on page 148 for the actual operating loads. Core Buck switching regulator (CBUCK): 2.3 4.8V in; nominal 1.5V, up to 500 mA out LDO3p1: 2.3 4.8V in; nominal 3.1V, up to 80 mA out LDO3p3: 2.3 4.8 in; nominal 3.3V, up to 80 mA out CLDO (for the core): 1.5V in; nominal 1.2V, up to 150 mA out Low-noise LNLDO1: 1.5V in; nominal 1.2V, up to 300 mA out

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BCM4330 Preliminary Data Sheet

Power Supply Topology

Figure 4 shows the typical power topology.

Internal WLAN PAs WL OTP

(3.3V)

LN LDO1 (1.2V, 300 mA)

WL AFE BT Radio Xtal

LDO3p1
(3.1V, 80 mA)

FM Radio RF Switch Controls BT Class 1 PA Core logic blocks WL Digital CLDO

(1.2V, 150 mA)

LDO3p3 (3.3V, 80 mA)

Vbat 2.34.8V BT_REG_ON WL_REG_ON

(1.5V, 500 mA)

WL OTP (1.2V) BT Digital FM Digital

VIO

WL_VDDIO* and BT_VDDIO*

Notes: * VDDIO, including WL_VDDIO and BT_VDDIO tied together, low state shuts down all PMU, and VDDIO is detected as high by the PMU if it falls within 1.08 3.6V. Shaded areas are internal to the BCM4330

Figure 4: Typical Power Topology

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Not noise sensitive

Core Buck Regulator

Noise sensitive

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BCM4330 Preliminary Data Sheet

Reset Circuits

Reset Circuits
The BCM4330 has three signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 23: Power-Up Sequence and Timing, on page 158. Table 1: Reset Control Signals Signal WL_REG_ON Description This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also ORgated with the BT_REG_ON input to control the internal BCM4330 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. Logic High Level: 1.08V3.6V. 200k pull-down resistor included. This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal BCM4330 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. Logic High Level: 1.08V3.6V. 200k pull-down resistor included. Low asserting reset for the Bluetooth core. This pin has no effect on WLAN and does not control any PMU functions. It must be driven high or low (not left floating).

BT_REG_ON

BT_RST_N

In addition, two other input signals control PMU modes: When EXT_SMPS_REQ is pulled high, it forces CBUCK to stay on, even when the other regulators are shut down by WL_REG_ON or BT_REG_ON. When WLAN and/or Bluetooth are out of reset and EXT_SMPS_REQ is high, then pulling EXT_PWM_REQ high makes CBUCK go into PWM mode, even if internal settings from WLAN and/or Bluetooth are requesting burst mode. During such contention, the request for the higher-power mode wins.

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BCM4330 Preliminary Data Sheet

Frequency References

Section 3: Frequency References

An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. Note: The crystal and TCXO implementations have different power supplies (WRF_XTAL_VDD1P2 for crystal, WRF_TCXO_VDD for TCXO).

Crystal Interface and Clock Generation

The BCM4330 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator including all external components is shown in Figure 5. Consult the reference schematics for the latest configuration.
C WRF_XTAL_OP 12 27 pF

C X Ohms* 12 27 pF * Resistor value determined by crystal drive level. See reference schematics for details. WRF_XTAL_ON

Figure 5: Recommended Oscillator Configuration A fractional-N synthesizer in the BCM4330 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. For SDIO applications the default frequency reference is a 37.4 MHz crystal or TCXO. For HSIC applications, the recommended frequency reference is also 37.4 MHz. The signal characteristics for the crystal interface are listed in Table 2 on page 32. Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. Contact Broadcom for further details.

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BCM4330 Preliminary Data Sheet

TCXO

TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the Phase Noise requirements listed in Table 2 on page 32. When the clock is provided by an external TCXO, there are two possible connection methods, as shown in Figure 6 and Figure 7: 1. If the TCXO is dedicated to driving the BCM4330, it should be connected to the WRF_XTAL_OP pin through an external 1000 pF coupling capacitor, as shown in Figure 6. The internal clock buffer connected to this pin will be turned OFF when the BCM4330 goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P2 pin. 2. For 2.4 GHz operation only, an alternative is to DC-couple the TCXO to the WRF_TCXO_IN pin, as shown in Figure 7. Use this method when the same TCXO is shared with other devices and a change in the input impedance is not acceptable because it may cause a frequency shift that cannot be tolerated by the other device sharing the TCXO. This pin is connected to a clock buffer powered from WRF_TCXO_VDD. If the power supply to this buffer is always on (even in sleep mode), the clock buffer is always on, thereby ensuring a constant input impedance in all states of the device. The maximum current drawn from WRF_TCXO_VDD is approximately 500 A.
1000 pF TCXO NC WRF_XTAL_OP WRF_XTAL_ON WRF_TCXO_IN WRF_TCXO_VDD3P3

Figure 6: Recommended Circuit to Use with an External Dedicated TCXO

To other devices TCXO WRF_TCXO_IN To always present 1.7V to 3.3V supply WRF_TCXO_VDD WRF_XTAL_OP

WRF_XTAL_ON

Figure 7: Recommended Circuit to Use with an External Shared TCXO

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BCM4330 Preliminary Data Sheet

TCXO

Table 2 provides crystal oscillator and external clock requirements and performance information. Table 2: Crystal Oscillator and External Clock Requirements and Performance Crystala Parameter Frequency Crystal load capacitance ESR Drive level Input impedance (WRF_XTAL_OP) Input impedance (WRF_TCXO_IN) WRF_XTAL_OP input voltage (see Figure 6 on page 31) WRF_TCXO_IN Input voltage (see Figure 7 on page 31) Frequency tolerance Initial + over temperature Duty cycle Phase Noisef (802.11b/g) Conditions/Notes External crystal Resistive Capacitive Resistive Capacitive AC-coupled analog signal Min Typ Max External Frequency Referenceb c Min Typ Max 7.5 4 1320 Units pF W pF pF mVp-p

Between 12 MHz and 52 MHzd,e 12 30k 100k 60 200 7.5 30k 30k 400 100k 100k

DC-coupled analog signal

400

3300 mVp-p

Without trimming

20 40

20 60 115 125 130 135 123 133 138 143 120 130 135 140

ppm % dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

Phase Noisef (802.11a)

Phase Noisef (802.11n, 2.4 GHz)

37.4 MHz clock 37.4 MHz clock at 1 kHz offset 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz offset 37.4 MHz clock at 1 MHz offset 37.4 MHz clock at 1 kHz offset 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz offset 37.4 MHz clock at 1 MHz offset 37.4 MHz clock at 1 kHz offset 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz offset 37.4 MHz clock at 1 MHz offset

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BCM4330 Preliminary Data Sheet

TCXO

Table 2: Crystal Oscillator and External Clock Requirements and Performance (Cont.) Crystala Parameter Phase Noise (802.11n, 5 GHz)
f

External Frequency Referenceb c Min Typ Max 128 138 143 148 Units dBc/Hz dBc/Hz dBc/Hz dBc/Hz

Conditions/Notes 37.4 MHz clock at 1 kHz offset 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz offset 37.4 MHz clock at 1 MHz offset

Min

Typ

Max

a. (Crystal) Use WRF_XTAL_OP and WRF_XTAL_ON, internal power to pin WRF_XTAL_VDD1P2. b. (TCXO) See TCXO on page 31 for alternative connection methods. c. For a clock reference other than 37.4 MHz, 20 log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an auto-detected frequency using the LPO clock. e. The frequency step size is approximately 80 Hz resolution. f. If the selected clock has a flat phase noise response above 100 kHz, that is, the phase noise at and above 100 kHz is constant, then subtract 1dB from all 1 kHz, 10 kHz, and 100 kHz values shown. For example, for the 2.4 GHz 802.11b/g values, the phase noise requirements change from 115, 125, and 130 dBc/Hz to 116, 126, and 131 dBc/Hz respectively. Ignore the 1 MHz requirements when the phase noise is flat above 100 kHz.

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BCM4330 Preliminary Data Sheet

Frequency Selection

Frequency Selection
Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard handset reference frequencies of 12, 13, 14.4, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 MHz, but also other frequencies in this range, with approximately 80 Hz resolution. The BCM4330 must have the reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived from the reference frequency. Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. Contact Broadcom for further details. The reference frequency for the BCM4330 may be set in the following ways: Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. Auto-detect any of the standard handset reference frequencies using an external LPO clock. For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard frequencies commonly used, the BCM4330 automatically detects the reference frequency and programs itself to the correct reference frequency. In order for auto frequency detection to work correctly, the BCM4330 must have a valid and stable 32.768 kHz LPO clock that meets the requirements listed in Table 3 on page 35 and is present during power-on reset.

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BCM4330 Preliminary Data Sheet

External 32.768 kHz Low Power Oscillator

The BCM4330 uses a secondary low frequency clock for low power mode timing. A precision external 32.768 kHz clock that meets the specifications listed in Table 3 is required by the BCM4330. Table 3: External 32.768 kHz Sleep Clock Specifications Parameter Nominal input frequency Frequency accuracy Duty cycle Input signal amplitude Signal type Input impedanced Clock jitter (integrated over 300 Hz15 kHz) Clock jitter (during initial start-up) LPO Clock 32.768 200a, b 30 70 2001800c Square-wave or sine-wave >100k <5 <5 <10,000 Units kHz ppm % mV, p-p pF ns ppm

a. If FM RX is used: 150 ppm maximum with frequency error indication, 50 ppm without frequency error indication. b. If FM TX is used: 100 ppm maximum with frequency error indication, 50 ppm without frequency error indication. c. 2001800 mVp-p to avoid additional current consumption and degradation in FM SNR. 3.3 Vp-p maximum. d. When power is applied or switched off.

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Bluetooth Radio
The BCM4330 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the requirements to provide the highest communication link quality of service.

Transmit
The BCM4330 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion, output power amplifier, and RF filtering. The transmitter path also incorporates /4 DQPSK for 2 Mbps and 8 DPSK for 3 Mbps to support EDR. The transmitter section is compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted to provide Bluetooth Class 1 operation.

Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, /4 DQPSK, and 8 DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-synchronization algorithm.

Power Amplifier
The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. The fully integrated PA supports Class 1 and Class 2 output using a temperature-compensated, auto-transformer-based design. This provides a simplified front end that does not require off-chip components for matching and better efficiency. External filtering is required for meeting Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications where the Bluetooth is integrated next to the cellular radio, minimal external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature.

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BCM4330 Preliminary Data Sheet

Bluetooth Radio

Receiver
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation enables the BCM4330 to be used in most applications with no off-chip filtering. For integrated handset operation, where the Bluetooth function is integrated close to the cellular transmitter, minimal external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the BCM4330 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband, so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power.

Local Oscillator Generation

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The BCM4330 uses an internal RF and IF loop filter.

Calibration
The BCM4330 radio transceiver features an automated calibration scheme that is fully self contained in the radio. No user interaction is required during normal operation or during manufacturing to provide the optimal performance. Calibration optimizes the performance of all the major blocks within the radio to optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and heats during normal operation in its environment.

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BCM4330 Preliminary Data Sheet

Bluetooth Baseband Core

Section 5: Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air: Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter.

Bluetooth 4.0 Features

The BBC supports Bluetooth 4.0 features with the following benefits: Dual mode Bluetooth Low Energy (BT and BLE operation). Extended Inquiry Response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode. Encryption Pause Resume (EPR): Enables the use of Bluetooth technology in a much more secure environment. Sniff Subrating (SSR): Optimizes power consumption for low duty cycle asymmetrical data flow, which subsequently extends battery lifetime. Secure Simple Pairing (SSP): Reduces the number of steps for connecting two devices with minimal or no user interaction required. Link Supervision Time Out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link time-out supervision. QoS Enhancements: Changes to data traffic control, which results in better link performance. Audio, human interface design (HID), bulk traffic, SCO and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF) enhancements.

Bluetooth Low Energy

The BCM4330 is forward-compatible with the impending Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls.

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BCM4330 Preliminary Data Sheet

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth Link Controller. Major states: Standby Connection Substates: Page Page Scan Inquiry Inquiry Scan Sniff

Test Mode Support

The BCM4330 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the BCM4330 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include: Fixed frequency carrier wave (unmodulated) transmission Simplifies some type-approval measurements (Japan) Aids in transmitter performance analysis Fixed frequency constant receiver mode Receiver output directed to I/O pin Allows for direct BER measurements using standard RF test equipment Facilitates spurious emissions testing for receive mode Fixed frequency constant transmission Eight-bit fixed pattern or PRBS-9 Enables modulated signal measurements with standard RF test equipment

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BCM4330 Preliminary Data Sheet

Bluetooth Power Management Unit

The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. The power management functions provided by the BCM4330 are: RF Power Management Host Controller Power Management BBC Power Management FM Power Management

RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver. The transceiver then processes the power-down functions accordingly.

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BCM4330 Preliminary Data Sheet

Bluetooth Power Management Unit

Host Controller Power Management

When running in UART mode, the BCM4330 may be configured so that dedicated signals are used for power management hand-shaking between the BCM4330 and the host. The basic power saving functions supported by those hand-shaking signals include the standard Bluetooth defined power savings modes and standby modes of operation. Table 4 describes the power-control hand-shake signals used with the UART interface. Table 4: Power Control Pin Descriptions Signal BT_WAKE Mapped to Pin BT_GPIO_0 Type Description I

Bluetooth device wake-up: Signal from the host to the BCM4330 indicating that the host requires attention. Asserted: Bluetooth device must wake-up or remain awake. Deasserted: Bluetooth device may sleep when sleep criteria are met. The polarity of this signal is software configurable and can be asserted high or low. HOST_WAKE BT_GPIO_1 O Host wake up. Signal from the BCM4330 to the host indicating that the BCM4330 requires attention. Asserted: host device must wake-up or remain awake. Deasserted: host device may sleep when sleep criteria are met. The polarity of this signal is software configurable and can be asserted high or low. BT_CLK_REQ_OUT BT_CLK_REQ_OUT O The BCM4330 asserts BT_CLK_REQ_OUT when the Bluetooth or WLAN systems want the host to turn on the reference clock. The polarity is active-high. Add an external 100 k pull-down resistor to ensure the signal is deasserted when the BCM4330 powers up or resets when VDDIO is present. Note: Pad function Control Register is set to 0 for these pins. See Table 21: GPIO Multiplexing Matrix, on page 113 for details.

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BCM4330 Preliminary Data Sheet

Bluetooth Power Management Unit

Note: Successful operation of the power management hand-shaking signals requires coordination between the BCM4330 firmware and the host software (see Figure 8).

LPO

VDDIO

Host IOs unconfigured Host IOs configured

HostResetX

BT_REG_ON

BTH IOs unconfigured BTH IOs configured Indicates that BTH device is ready.

BT_UART_RTS_N

BT_UART_CTS_N

CLK_REQ_OUT

Tsettle

Driven Pulled

Notes : T1 is the time for host to settle its IOs after a reset. T2 is the time for the BTH device to settle its IOs after a reset and ref clk settling time elapsed. T3 is the time for the BT device to complete initialization and drive BT_UART_RTS_N low. T4 is the setup time for BT_WAKE prior to driving BT_REG_ON high; BT_WAKEUP must be high prior to BT_REG_ON being released. BT_WAKEUP should not be driven low until after configuration has been completed by the host. Tsettle is the time for the ref clk signal from the host to be guaranteed to have settled.

Figure 8: Startup Signaling Sequence

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BCM4330 Preliminary Data Sheet

Bluetooth Power Management Unit

BBC Power Management

The following are low-power operations for the BBC: Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets. Bluetooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the BCM4330 runs on the low-power oscillator and wakes up after a predefined time period. A low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational. When the BCM4330 is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This allows the BCM4330 to effectively be off while keeping the I/O pins powered so they do not draw extra current from any other devices connected to the I/O. During the low-power shut-down state, provided VDDIO remains applied to the BCM4330, all outputs are tri-stated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system and enables the BCM4330 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. Two BCM4330 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the BCM4330 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down.

FM Power Management
The BCM4330 FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC subsystems. The FM subsystem power management scheme operates in conjunction with the Bluetooth RF and BBC subsystems. The FM block does not have a low power state, it is either on or off.

Low-Power Scan
The BCM4330 has an optional low-power scan mode that replaces conventional page/inquiry scans with a proprietary scan scheme. When this mode is activated, it significantly reduces current consumption for page and inquiry scans. The mode will switch to conventional scans if energy in page/inquiry channels with an appropriate activation pattern is detected.

Wideband Speech
The BCM4330 provides support for wideband speech (WBS) using on-chip Smart Audio technology. The BCM4330 can perform subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 kbps rate) transferred over the PCM bus.

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BCM4330 Preliminary Data Sheet

Bluetooth Power Management Unit

Packet Loss Concealment

Packet Loss Concealment (PLC) improves apparent audio quality for systems with marginal link performance. Bluetooth messages are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several ways: Fill in zeros. Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets). Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). These techniques cause distortion and popping in the audio stream. The BCM4330 uses a proprietary waveform extension algorithm to provide dramatic improvement in the audio quality. Figure 9 and Figure 10 show audio waveforms with and without Packet Loss Concealment. Broadcom PLC/BEC algorithms also support wide band speech.

Packet Loss Causes Ramp-Down

Figure 9: CVSD Decoder Output Waveform Without PLC

Figure 10: CVSD Decoder Output Waveform After Applying PLC

Audio Rate-Matching Algorithms

The BCM4330 has an enhanced rate-matching algorithm that uses interpolation algorithms to reduce audio stream jitter that may be present when the rate of audio data coming from the host is not the same as the Bluetooth or FM audio data rates.

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BCM4330 Preliminary Data Sheet

Adaptive Frequency Hopping

Codec Encoding
The BCM4330 can support SBC and mSBC encoding and decoding for wideband speech.

Multiple Simultaneous A2DP Audio Stream

The BCM4330 has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a user to share his or her music (or any audio stream) with a friend.

FM Over Bluetooth
FM Over Bluetooth enables the BCM4330 to stream data from FM over Bluetooth without requiring the host to be awake. This can significantly extend battery life for usage cases where someone is listening to FM radio on a Bluetooth headset.

Burst Buffer Operation

The BCM4330 has a data buffer that can buffer data being sent over the HCI and audio transports, then send the data at an increased rate. This mode of operation allows the host to sleep for the maximum amount of time, dramatically reducing system current consumption.

Adaptive Frequency Hopping

The BCM4330 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop map.

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BCM4330 Preliminary Data Sheet

Advanced Bluetooth/WLAN Coexistence

The BCM4330 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution. These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including applications such as VoWLAN + SCO and Video-over-WLAN + High Fidelity BT Stereo. Support is provided for platforms that share a single antenna between Bluetooth and 802.11g. Dual-antenna applications are also supported. The BCM4330 radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna applications. This is possible only via an integrated solution (shared LNA and joint AGC algorithm). It has superior performance versus implementations that need to arbitrate between Bluetooth and WLAN reception. The BCM4330 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement. The BCM4330 also supports Transmit Power Control on the STA together with standard Bluetooth TPC to limit mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate detection and elimination of interferers (including nonWLAN 2.4 GHz interference). The Bluetooth AFH classification is also enhanced by the WLAN cores channel information.

Fast Connection (Interlaced Page and Inquiry Scans)

Data Formatting
The BCM4330 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the BCM4330 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2s complement data, left justified, and clocked MSB first.

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BCM4330 Preliminary Data Sheet

PCM Interface

Wideband Speech Support

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-bit samples, resulting in a 64 kbps bit rate. The BCM4330 also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus.

Multiplexed Bluetooth and FM Over PCM

In this mode of operation, the BCM4330 multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The format of the data stream consists of three channels: a Bluetooth channel followed by two FM channels (audio left and right). In this mode of operation, the bus data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I2S data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame. To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 11 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration.
1 frame
BT SCO 1 RX BT SCO 2 RX BT SCO 3 RX

PCM_OUT BT SCO 1 TX BT SCO 2 TX BT SCO 3 TX

FM right

FM left

PCM_IN

FM right

FM left

PCM_SYNC PCM_CLK 16 bits per SCO frame Each SCO channel duplicates the data 6 times. Each WBS frame duplicates the data 3 times per frame CLK

16 bits per frame

Figure 11: Functional Multiplex Data Diagram

Burst PCM Mode

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host.

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BCM4330 Preliminary Data Sheet

PCM Interface

PCM Interface Timing

Short Frame Sync, Master Mode
1 2 3

PCM_BCLK

4 PCM_SYNC 8 PCM_OUT 5 6 PCM_IN 7 HIGH IMPEDANCE

Figure 12: PCM Timing Diagram (Short Frame Sync, Master Mode) Table 5: PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Ref No. 1 2 3 4 5 6 7 8 Characteristics PCM bit clock frequency PCM bit clock HIGH PCM bit clock LOW PCM_SYNC delay PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance Minimum Typical 41 41 0 0 8 8 0 Maximum Unit 12 25 25 25 MHz ns ns ns ns ns ns ns

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BCM4330 Preliminary Data Sheet

PCM Interface

Short Frame Sync, Slave Mode

1 2 3

PCM_BCLK 4 5 PCM_SYNC 9 PCM_OUT 6 7 PCM_IN 8 HIGH IMPEDANCE

Figure 13: PCM Timing Diagram (Short Frame Sync, Slave Mode) Table 6: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Ref No. 1 2 3 4 5 6 7 8 9 Characteristics PCM bit clock frequency PCM bit clock HIGH PCM bit clock LOW PCM_SYNC setup PCM_SYNC hold PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance Minimum Typical 41 41 8 8 0 8 8 0 Maximum Unit 12 25 25 MHz ns ns ns ns ns ns ns ns

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BCM4330 Preliminary Data Sheet

PCM Interface

Long Frame Sync, Master Mode

1 2 3

PCM_BCLK

4 PCM_SYNC 8 PCM_OUT 5 6 PCM_IN Bit 0 Bit 1 7 Bit 0 Bit 1 HIGH IMPEDANCE

Figure 14: PCM Timing Diagram (Long Frame Sync, Master Mode) Table 7: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Ref No. 1 2 3 4 5 6 7 8 Characteristics PCM bit clock frequency PCM bit clock HIGH PCM bit clock LOW PCM_SYNC delay PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance Minimum Typical 41 41 0 0 8 8 0 Maximum Unit 12 25 25 25 MHz ns ns ns ns ns ns ns

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BCM4330 Preliminary Data Sheet

PCM Interface

Long Frame Sync, Slave Mode

1 2 3

PCM_BCLK 4 5 PCM_SYNC 9 PCM_OUT 6 7 PCM_IN Bit 0 Bit 1 8 Bit 0 Bit 1 HIGH IMPEDANCE

Figure 15: PCM Timing Diagram (Long Frame Sync, Slave Mode) Table 8: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Ref No. 1 2 3 4 5 6 7 8 9 Characteristics PCM bit clock frequency PCM bit clock HIGH PCM bit clock LOW PCM_SYNC setup PCM_SYNC hold PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance Minimum Typical 41 41 8 8 0 8 8 0 Maximum Unit 12 25 25 MHz ns ns ns ns ns ns ns ns

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BCM4330 Preliminary Data Sheet

PCM Interface

Short Frame Sync, Burst Mode

I2S Interface

Table 13: Timing for I2S Transmitters and Receivers Transmitter Lower LImit Min Clock Period T HIGH tHC LOWtLC HIGH tHC LOW tLC Rise time tRC Transmitter Delay tdtr Hold time thtr Receiver Setup time tsr Hold time thr 0.2Tr 0 6 6 0 0.8T 5 4 Ttr 0.35Ttr 0.35Ttr Max Upper Limit Min Max Receiver Lower Limit Min Tr 0.35Ttr 0.35Ttr Max 0.35Ttr 0.35Ttr Upper Limit Min Max Notes 1 2 2 3 3 4

Master Mode: Clock generated by transmitter or receiver

Slave Mode: Clock accepted by transmitter or receiver 0.35Ttr 0.35Ttr 0.15Ttr

Note: The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. The data setup and hold time must not be less than the specified receiver setup and hold time.

Note: The time periods specified in Figure 19 and Figure 20 are defined by the transmitter speed. The receiver specifications must match transmitter performance.

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BCM4330 Preliminary Data Sheet

I2S Interface

T tRC* tLC > 0.35T tHC > 0.35T VH = 2.0V SCK thtr > 0 totr < 0.8T VL = 0.8V

SD and WS

T = Clock period Ttr = Minimum allowed clock period for transmitter T = Ttr * tRC is only relevant for transmitters in slave mode.

Figure 19: I2S Transmitter Timing

T tLC > 0.35T tHC > 0.35 VH = 2.0V SCK VL = 0.8V

tsr > 0.2T

thr > 0

SD and WS

T = Clock period Tr = Minimum allowed clock period for transmitter T > Tr

Figure 20: I2S Receiver Timing

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BCM4330 Preliminary Data Sheet

FM Transceiver Subsystem

Section 9: FM Transceiver Subsystem

FM Radio
The BCM4330 includes a completely integrated FM radio receiver and transmitter with RDS/RBDS covering all FM bands from 65 MHz to 108 MHz. The transceiver is controlled through commands on the HCI. FM received audio is available as stereo analog output or in digital form through I2S or PCM. The FM audio to be transmitted can be delivered via the I2S or PCM interface. The FM radio is capable of operating from the 32.768 kHz LPO clock.

Digital FM Audio Interfaces

Figure 21: Example Blend/Switch Usage

Figure 22: Example Blend/Switch Separation Soft Mute Improves the user experience by dynamically muting the output audio proportionate to the FM signal C/N. This prevents the user from being assaulted with a blast of static. The mute characteristic is fully programmable to accommodate fine tuning of the output signal level. An example mute characteristic is shown in Figure 23.

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BCM4330 Preliminary Data Sheet

On-Chip MP3 Encoding

Figure 23: Example Soft Mute Characteristic Audio Pause Detect The FM receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when the magnitude of the signal has fallen below the threshold set for a programmable period. This feature can be used to provide alternate frequency jumps during periods of silence to minimize disturbances to the listener. Filtering techniques are used within the audio pause detection block to provide more robust presence-to-silence detection and silence-to-presence detection.

On-Chip MP3 Encoding

In this mode of operation, the device can record the FM audio to MP3, then output the MP3 data over the HCI interface. The feature effectively off loads the MP3 recording processing load from the host and assists in FM time shift applications. This feature can also be used in conjunction with burst mode buffering to provide significant FM system record times.

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BCM4330 Preliminary Data Sheet

RDS/RBDS

RDS/RBDS
The BCM4330 integrates a RDS/RBDS modem and codec, the decoder includes programmable filtering and buffering functions, and the encoder includes the option to encode messages to PS or RT frame format with programmable scrolling in PS mode. The RDS/RBDS data can be read out in receive mode or delivered in transmit mode through the HCI interface. In addition, the RDS/RBDS functionality supports the following: Receive Block decoding, error correction and synchronization Flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and loss of sync. (It is possible to set up the BCM4330 such that synch is achieved when a minimum of two good blocks (error free) are decoded in sequence. The number of good blocks required for sync is programmable.) Storage capability up to 126 blocks of RDS data Full or partial block B match detect and interrupt to host Audio pause detection with programmable parameters Program Identification (PI) code detection and interrupt to host Automatic frequency jump Block E filtering Transmit Support simple block encoding or RT/PS message to frame encoding (RT/PS mode minimizes host communication for improved system power saving) Programmable scroll rate in PS mode 256 bytes of storage for either RT/PS message or simple RDS/RBDS blocks

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BCM4330 Preliminary Data Sheet

WLAN Global Functions

Section 10: WLAN Global Functions

WLAN CPU and Memory Subsystem
The BCM4330 includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for Thumb-2 instruction set. ARM Cortex-M3 delivers 30% more performance gain over ARM7TDMI. At 0.19uW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/uW. It supports integrated sleep modes. ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. ARM Cortex-M3 supports independent buses for Code and Data access (ICode/DCode and System buses). ARM Cortex-M3 supports extensive debug features including real time trace of program execution. On-chip memory for the CPU includes 288 KB SRAM and 512 KB ROM.

One-Time-Programmable Memory
Various hardware configuration parameters may be stored in an internal 2 Kbit one-time-programmable (OTP) memory, which is read by system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC address can be stored, depending on the specific board design. The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. Documentation on the OTP development process is available on the Broadcom customer support portal (http://www.broadcom.com/support).

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BCM4330 Preliminary Data Sheet

GPIO Interface

GPIO Interface
There are seven general purpose I/O (GPIO) pins available on the WLAN section of the BCM4330 that can be used to connect to various external devices. Upon power up and reset, these pins become tri-stated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. An internal pull-up resistor is included on each GPIO. If a GPIO output enable is not asserted, and the corresponding GPIO signal is not being driven externally, the GPIO is read as high.

External Coexistence Interface

An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such as GPS, WiMax, or UWB, to manage wireless medium sharing for optimum performance. The following signals can be enabled by software on the indicated WL_GPIO pins: ERCX_STATUS WL_GPIO1 ERCX_FREQ WL_GPIO2 ERCX_RF_ACTIVE WL_GPIO3 ERCX_TXCONF WL_GPIO4 ERCX_PRISEL WL_GPIO5

UART Interface
One UART interface can be enabled by software as an alternate function on pins WL_GPIO4 and WL_GPIO_3. Provided primarily for debugging during development, this UART enables the BCM4330 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 8 in each direction.

JTAG Interface
The BCM4330 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary debug and characterization test tools during board bringup. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs. Caution! The BCM4330 I/O interface pins are not 3.3V tolerant. All I/O signaling should be limited to 2.9V 3%, 2.5V, 1.8V, or 1.2V, depending on the I/O power supply voltage VDDIO. This applies to the GPIO, External Coexistence, UART, and JTAG signals.

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BCM4330 Preliminary Data Sheet

WLAN Host Interfaces

Section 11: WLAN Host Interfaces

SDIO v2.0
The BCM4330 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps), 4-bit modes (100 Mbps), and high speed 4-bit (50 MHz clocks 200 Mbps). It has the ability to map the interrupt signal onto a GPIO pin. This out-of-band interrupt signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within the WLAN chip is also provided. SDIO mode is enabled using the strapping option pins strap_host_ifc_[3:1] (Table 19: WLAN GPIO Functions and Strapping Options, on page 112). Three functions are supported: Function 0 Standard SDIO function (Max BlockSize/ByteCount = 32B) Function 1 Backplane Function to access the internal System On Chip (SOC) address space (Max BlockSize/ ByteCount = 64B) Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount = 512B)

SDIO Pin Descriptions

Caution! The SDIO interface pins are not 3.3V tolerant. All SDIO signaling should be limited to 2.9V 3%, 2.5V, 1.8V, or 1.2V, depending on the I/O power supply voltage VDDIO.

Table 14: SDIO Pin Description SD 4-Bit Mode DATA0 DATA1 DATA2 DATA3 CLK CMD Data line 0 Data line 1 or Interrupt Data line 2 or Read Wait Data line 3 Clock Command line DATA IRQ RW N/C CLK CMD SD 1-Bit Mode Data line Interrupt Read Wait Not used Clock Command line DO IRQ NC CS SCLK DI gSPI Mode Data output Interrupt Not used Card select Clock Data input

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BCM4330 Preliminary Data Sheet

SDIO v2.0

CLK CMD SD Host DAT[3:0] BCM4330

Figure 24: Signal Connections to SDIO Host (SD 4-Bit Mode)

CLK CMD SD Host DATA IRQ RW BCM4330

Figure 25: Signal Connections to SDIO Host (SD 1-Bit Mode)

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BCM4330 Preliminary Data Sheet

Generic SPI Mode

In addition to the full SDIO mode, the BCM4330 includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include: Supports up to 48 MHz operation Supports fixed delays for responses and data from device Supports alignment to host gSPI frames (16- or 32-bits) Supports up to 2 KB frame size per transfer Supports little endian and big endian configurations Supports configurable active edge for shifting Supports packet transfer through DMA for WLAN gSPI mode is enabled using the strapping option pins strap_host_ifc_[3:1], Table 19: WLAN GPIO Functions and Strapping Options, on page 112.

SCLK DI SD Host DO IRQ CS BCM4330

Figure 26: Signal Connections to SDIO Host (gSPI Mode)

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BCM4330 Preliminary Data Sheet

Figure 27: gSPI Write Protocol

Read Protocol Command 32-bit Little endian Din Dout C3 C2 C1 C0 0000 0000
Fixed Delay

Data xxxx xxxx D3 D2 D1 D0

Data xxxx xxxx D7 D6 D5 D4

16-bit Little endian

Din Dout

C1 C0 0000

C3 C2
Fixed Delay

xxxx D1 D0

xxxx D3 D2

xxxx D5 D4

xxxx D7 D6

0000

32-bit Big endian

Din Dout

C0 C1 C2 C3 0000 0000
Fixed Delay

xxxx xxxx D0 D1 D2 D3

xxxx xxxx D4 D5 D6 D7

16-bit Big endian

Din Dout

C0 C1 0000

C2 C3
Fixed Delay

xxxx D0 D1

xxxx D2 D3

xxxx D4 D5

xxxx D6 D7

0000

Figure 28: gSPI Read Protocol

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BCM4330 Preliminary Data Sheet

Generic SPI Mode

Command Structure
The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 29.
31 C 30 29 A F1 28 F0 27 Ad dres s 17 bits 11 10 P acket length - 11b its *
* 11 h0 = 204 8 by tes

F unction N o: 00 01 10 11

F unc F unc F unc F unc

0 ^W/ 1: Registers and meories belonging to other blocks in the chip (64 bytes max) 1 2 2: DMA channel 1. WLAN packets up to 2048 bytes. 3 D W

A cce ss : 0 F ixed add ress 1 Incremental add res s C ommand : 0 R ead 1 W rite

Figure 29: gSPI Command Structure

Write
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.

Write/Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising clock edge of the clock burst for the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows data to be ready for the first clock edge without relying on asynchronous delays.

Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data and b) the time interval between the command/address is not fixed.

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BCM4330 Preliminary Data Sheet

Generic SPI Mode

Status
The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about any packet errors, protocol errors, information about available packet in the RX queue, etc. The status information helps in reducing the number of interrupts to the host. The statusreporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus timing for read/write transactions with and without status notification are as shown in Figure 30 and Figure 31 on page 78. See Table 15 on page 78 for information on status field details.

Write

cs sclk mosi C31 C31 C30 C30 C1 C1 Command 32 bits C0 C0 D31 D31 D30 D30 D1 D1 Write Data 16*n bits D0 D0

Write-Read

cs sclk mosi miso Command 32 bits Response Delay C31 C31 C30 C30 C0 C0 D31 D31 D30 D30 D1 D1 D0 D0

Read Data 16*n bits

Read

cs sclk mosi miso Command 32 bits Response Delay C31 C31 C30 C30 C0 C0 D31 D31 D30 D30 Read Data 16*n bits D0 D0

Figure 30: gSPI Signal Timing Without Status

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BCM4330 Preliminary Data Sheet

Generic SPI Mode

Write

cs sclk mosi miso Command 32 bits Write Data 16*n bits C31 C31 C1 C1 C0 C0 D31 D31 D1 D1 D0 D0 S31 S31 S1 S1 Status 32 bits S0 S0

Write-Read

cs sclk mosi miso Command 32 bits C31 C31 C0 C0 D31 D31 D1 D1 D0 D0 S31 S31 S0 S0

Read Data 16*n bits

Status 32 bits

Read

cs sclk mosi miso Command 32 bits C31 C31 C0 C0 D31 D31 D1 D1 D0 D0 S31 S31 S0 S0

Read Data 16*n bits

Status 32 bits

Figure 31: gSPI Signal Timing with Status (Response Delay = 0) Table 15: gSPI Status Field Details Bit 0 1 2 3 4 5 6 7 8 9:19 20 21:31 Name Data not available Underflow Overflow F2 interrupt F3 interrupt F2 RX Ready F3 RX Ready Reserved F2 Packet Available F2 Packet Length F3 Packet Available F3 Packet Length Description The requested read data is not available FIFO underflow occurred due to current (F2, F3) read command FIFO overflow occurred due to current (F1, F2, F3) write command F2 channel interrupt F3 channel interrupt F2 FIFO is ready to receive data (FIFO empty) F3 FIFO is ready to receive data (FIFO empty) Packet is available/ready in F2 TX FIFO Length of packet available in F2 FIFO Packet is available/ready in F3 TX FIFO Length of packet available in F3 FIFO

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BCM4330 Preliminary Data Sheet

Generic SPI Mode

gSPI Host-Device Handshake

To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the BCM4330 is ready for data transfer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and then take necessary actions.

Boot-Up Sequence
After power-up, the gSPI host needs to wait 150 ms for the device to be out of reset. For this, the host needs to poll with a read command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wakeup-WLAN bit (F0 reg 0x00 bit 7). The wakeup-WLAN issues a clock request to the PMU. For the first time after power-up, the host needs to wait for the availability of low power clock inside the device. Once that is available, the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chipActive interrupt is issued to the host. This indicates device awake/ready status. See Table 16 for information on gSPI registers. In Table 16, the following notation is used for register access: R: Readable from host and CPU W: Writable from host U: Writable from CPU Table 16: gSPI Registers Address x0000 Register Word length Endianess High speed mode Bit 0 1 4 Access Default R/W/U 0 R/W/U 0 R/W/U 1 Description 0: 16 bit word length 1: 32 bit word length 0: Little Endian 1: Big Endian 0: Normal mode. RX and TX at different edges. 1: High speed mode. RX and TX on same edge (default). 0: Interrupt active polarity is low 1: Interrupt active polarity is high (default) A write of 1 will denote wake-up command from host to device. This will be followed by a F2 Interrupt from gSPI device to host, indicating device awake status. Configurable read response delay in multiples of 8 bits

Interrupt polarity Wake-up

5 7

R/W/U 1 R/W 0

x0001

Response delay

7:0

R/W/U 8h04

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BCM4330 Preliminary Data Sheet

Generic SPI Mode

Table 16: gSPI Registers (Cont.) Address x0002 Register Status enable Interrupt with status Response delay for all Bit 0 1 2 Access Default R/W 1 Description

x0003 x0004

Reserved Interrupt register

x0005

x0006 x0007 x0008 x000B x000C x000D x000E x000F x0010 x0011 x0014 x0017 x0018 x001B

1 2 5 6 7 Interrupt register 5 6 7 Interrupt enable register 15:0 Status register F1 info register 31:0

0: no status sent to host after read/write 1: status sent to host after read/write R/W 0 0: do not interrupt if status is sent 1: interrupt host even if status is sent R/W 0 0: response delay applicable to F1 read only 1: response delay applicable to all function read R/W 0 Requested data not available; Cleared by writing a 1 to this location R 0 F2/F3 FIFO underflow due to last read R 0 F2/F3 FIFO overflow due to last write R 0 F2 packet available R 0 F3 packet available R 0 F1 overflow due to last write R 0 F1 Interrupt R 0 F2 Interrupt R 0 F3 Interrupt R/W/U 16'hE0E7 Particular Interrupt is enabled if a corresponding bit is set R 32'h0000 Same as status bit definitions R R R/U R/U R R/U R/U R R/U R F1 enabled F1 ready for data transfer F1 max packet size F2 enabled F2 ready for data transfer F2 max packet size F3 enabled F3 ready for data transfer F3 max packet size This register contains a predefined pattern, which the host can read and determine if the gSPI interface is working properly. R/W/U 32'h0000 This is a dummy register where the host can 0000 write some pattern and read it back to determine if the gSPI interface is working properly. 1 0 12'h40 1 0 14'h800 1 0 14'h800 32'hFEED BEAD

0 1 13:2 F2 info register 0 1 15:2 F3 info register 0 1 15:2 Test Read only register 31:0 Test R/W register 31:0

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MAC Features
The BCM4330 WLAN media access controller (MAC) supports features specified in the 802.11 base standard, and amended by 802.11n. The salient features are listed below: Transmission and reception of aggregated MPDUs (A-MPDU) Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and multiphase PSMP operation Support for immediate ACK and Block-ACK policies Interframe space timing support, including RIFS Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management Support for coexistence with Bluetooth and other external radios Programmable independent basic service set (IBSS) or infrastructure basic service set functionality Statistics counters for MIB support

MAC Description
The 4329 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 34 on page 84. The following sections provide an overview of the important modules in the MAC.

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BCM4330 Preliminary Data Sheet

MAC Features

Embedded CPU Interface Host Registers, DMA Engines

PMQ

TX-FIFO 32 KB

RX-FIFO 10 KB

PSM

PSM UCODE Memory

IFS Backoff, BTCX WEP WEP, WAPI, TKIP, AES SHM IHR NAV BUS TXE TX A-MPDU RXE RX A-MPDU Shared Memory 6 KB BUS

TSF

EXT- IHR

MAC Features

IFS
The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple backoff engines required to support prioritized access to the medium as specified by WMM. The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a TXOP). The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. When the backoff counters reach 0, the TXE gets notified, so that it may commence frame transmission. In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the PSM. The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer expires the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF is synchronized to the network. The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.

TSF
The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink transmission times used in PSMP.

NAV
The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard. The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames. This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.

MAC-PHY Interface
The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an programming interface, which can be controlled either by the host or the PSM to configure and control the PHY.

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BCM4330 Preliminary Data Sheet

WLAN PHY Description

The BCM4330 WLAN Digital PHY is designed to comply with IEEE 802.11a/b/g/n single stream to provide wireless LAN connectivity supporting data rates from 1 Mbps to 72.2 Mbps for low power, high performance handheld applications. The PHY has been designed to work with interference, radio nonlinearity, and impairments. It incorporates efficient implementations of the filters, FFT and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. The PHY receiver also contains a robust 11b demodulator. The PHY carrier sense has been tuned to provide high-throughput for 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been designed for shared single antenna systems between WL and BT to support simultaneous Rx-Rx.

PHY Features
Supports IEEE 802.11a, 11b, 11g, 11n single stream PHY standards 802.11n single-stream operation in 20 MHz channels Supports Optional Short GI and Green Field modes in Tx and Rx Supports optional space-time block code (STBC) receive of two space-time streams Supports 802.11h/k for worldwide operation Advanced algorithms for low power, enhanced sensitivity, range, and reliability Algorithms to improve performance in presence of Bluetooth Simultaneous Rx-Rx (WL-BT) architecture Automatic gain control scheme for blocking and non blocking application scenario for cellular applications. Closed loop transmit power control Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities On-the-fly channel frequency and transmit power selection Supports per packet Rx antenna diversity Designed to meet FCC and other worldwide regulatory requirements

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BCM4330 Preliminary Data Sheet

WLAN PHY Description

CCK/DSSS Demodulate Filters and Radio Comp Frequency and Timing Synch OFDM Demodulate Viterbi Decoder

Descramble and Deframe

Carrier Sense, AGC, and Rx FSM Radio Control Block Buffers FFT/IFFT MAC Interface

AFE and Radio Tx FSM Common Logic Block

Modulation and Coding

Frame and Scramble

Filters and Radio Comp

PA Comp

Modulate/Spread

COEX

Figure 35: WLAN PHY Block Diagram The PHY is capable of fully calibrating the RF front end to extract the highest performance. On power-up, the PHY performs a full suite of calibration to correct for IQ mismatch and local oscillator leakage. The PHY also performs periodic calibration to compensate for any temperature related drift thus maintaining highperformance over time. A closed loop transmit control algorithm maintains the output power to required level with capability control Tx power on a per packet basis. One of the key feature of the PHY is two space-time stream receive capability. The STBC scheme can obtain diversity gains by using multiple transmit antennas in AP (Access Point) in a fading channel environment, without increasing the complexity at the STA. Details of the STBC receive is shown in the block diagram shown in Figure 36 on page 90.

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BCM4330 Preliminary Data Sheet

WLAN PHY Description

FFT of 2 Symbols

Equalizer

Demod Combine

Demapper

Viterbi

Descramble and Deframe

hold
Transmitter Channel h Weighted Averaging

hnew

hupd

Symbol Memory

Estimate Channel

Figure 36: STBC Receive Block Diagram In STBC mode, symbols are processed in pairs. Equalized output symbols are linearly combined and decoded. Channel estimate is refined on every pair of symbols using the received symbols and reconstructed symbols.

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BCM4330 Preliminary Data Sheet

WLAN Radio Subsystem

Section 13: WLAN Radio Subsystem

The BCM4330 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems (but not both simultaneously). It has been designed to provide lowpower, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Up to eight RF control signals are available to drive the external RF switches and support the addition of optional external power amplifiers and low noise amplifiers for either or both bands. See the reference board schematics for further details.

Receive Path
The BCM4330 has a wide dynamic range, direct conversion receiver. It employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. Control signals are available that can support the use of optional external low noise amplifiers (LNA), which can increase the receive sensitivity by several dB.

Transmit Path
Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5-GHz U-NII bands, respectively. Linear onchip power amplifiers are included, which are capable of delivering high output powers while meeting 802.11a/b/g/n specifications without the need for external PAs. These PAs can be powered directly from VBAT, thereby eliminating the need for a separate PALDO. Closed-loop output power control is completely integrated. Several spare RF control signals are available to support the addition of optional external power amplifiers for either or both bands.

Calibration
The BCM4330 features dynamic on-chip calibration, eliminating process variation across components. This enables the BCM4330 to be used in high-volume applications, because calibration routines are not required during manufacturing testing. These calibration routines are performed periodically in the course of normal radio operation. Examples of this automatic calibration are baseband filter calibration for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip.

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BCM4330 Preliminary Data Sheet

Calibration

WL DAC

WL PA

WL PAD

WL PGA

WL TX G-Mixer

WL TXLPF

WL DAC WL A-PA WL A-PAD WL A-PGA WL TX A-Mixer WL RX A-Mixer WLAN BB WL ADC Voltage Regulators WL TXLPF

WL A-LNA11

WL A-LNA12

WL RXLPF

MUX

WL ADC

SLNA

WL G-LNA12 WL RX G-Mixer WL ATX WL ARX WL GTX WL GRX Gm BT LNA GM

WL RXLPF CLB WL LOGEN WL PLL

Shared XO

BT RX BT TX

BT LOGEN

BT PLL LPO/Ext LPO/RCAL

BT ADC

BT RXLPF

BT LNA Load

BT ADC

BT RX Mixer BT PA

BT RXLPF

BT BB

BT FM

BT DAC

BT TX Mixer

BT TXLPF

Figure 37: Radio Functional Block Diagram

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BCM4330 Preliminary Data Sheet

Pinout and Signal Descriptions

Section 14: Pinout and Signal Descriptions

Signal Assignments
Figure 38 shows the FCFBGA ball map. Figure 39 shows the WLBGA ball map. Figure 40 shows the WLCSP bump map. Table 17 on page 96 contains the WLCSP bump coordinates. Table 18 on page 103 contains the signal description for all packages.
1 A B C D E F G H J K L M 2 3 4

WRF_RFIN_5G WRF_VDDLNA_1P2_5G WRF_LOGEN_A_VDD1P2 WRF_VDD_VCOLDO_IN_1P8 WRF_TCXO_VDD WRF_XTAL_OP WRF_XTAL_ON WL_GPIO_1 HSIC_AVDD12 HSIC_STROBE HSIC_DATA RF_SW_CTRL_5
5

WRF_RFOUT_5G WRF_GNDLNA_5G WRF_LOGEN_A_GND WRF_VDDANA_1P2 WRF_VCO_GND WRF_TCXO_IN WRF_XTAL_GND WL_GPIO_0 WL_VDDC HSIC_AVSS HSIC_RREF RF_SW_CTRL_1
6

WRF_VDDPA_5G WRF_A_TSSI_IN WRF_ANA_GND WRF_VCOLDO_OUT_1P2 WRF_VDDAFE_1P2 WRF_AFE_GND WRF_XTAL_VDD1P2 WL_GPIO_2 WL_GPIO_3 RF_SW_CTRL_7 RF_SW_CTRL_2 RF_SW_CTRL_0
7

WRF_VDDPA_2G WRF_GNDPA_5G WRF_PADRV_VDD WRF_GPIO_OUT WRF_RES_EXT BT_PCM_IN WL_GPIO_4 WL_GPIO_6 VSSC VDDIO_RF RF_SW_CTRL_4 RF_SW_CTRL_6
8

A B C D E F G H J K L M

WRF_RFOUT_2G WRF_GNDPA_2G WRF_PADRV_GND WRF_G_TSSI_IN BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT WL_GPIO_5 VSSC RF_SW_CTRL_3 JTAG_SEL SDIO_DATA_1
9

WRF_RFIN_2G WRF_VDDLNA_1P2_2G WRF_GNDLNA_2G BT_UART_CTS_N BT_UART_RXD BT_UART_RTS_N VSSC WL_VDDC VSSC WL_VDDIO WL_VDDC SDIO_CLK
10

BT_PAVDD3P3 BT_IFVDD1P2 BT_IFVSS BT_CLK_REQ_IN BT_UART_TXD WL_VDDC VSSC LPO BT_VDDIO VDD_ISLAND SDIO_DATA_0 SDIO_CMD
11

BT_RF BT_FEVSS BT_VSS BT_CLK_REQ_POL BT_CLK_REQ_MODE BT_VDDC VSSC BT_I2S_WS BT_VDDC BT_VDDC SDIO_DATA_3 SDIO_DATA_2
12

A B C D E F G H J K L M

BT_LNAVDD1P2 BT_RFVSS BT_VCOVSS BT_PLLVSS FM_VSS BT_GPIO_0 BT_I2S_CLK BT_I2S_DO EXT_SMPS_REQ BT_REG_ON WL_REG_ON VOUT_CLDO

BT_VCOVDD1P2 BT_PLLVDD1P2 FM_VSSAUDIO FM_PLLVSS FM_VDD2P5 BT_RST_N BT_I2S_DI BT_GPIO_5 EXT_PWM_REQ PMU_AVSS VOUT_LNLDO1 VIN_LDO

FM_AOUT1 FM_VDDAUDIO FM_IFVDD1P2 FM_RFVSS FM_VSSVCO BT_TM0 BT_GPIO_4 BT_GPIO_1 VOUT_3P1 SR_VDDBAT2 SR_VLX SR_PVSS

FM_AOUT2 FM_TX FM_RFVDD_1P2 FM_RXN FM_RXP BT_CLK_REQ_OUT BT_GPIO_2 BT_GPIO_3 VOUT_3P3 SR_VDDBAT1 SR_VDDBAT1 SR_VLX

Figure 38: 144-FCFBGA Ball Map (Top View)

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BCM4330 Preliminary Data Sheet

Signal Assignments

12 A
FM_AOUT1

11
BT_ VCOVDD1P2

10
BT_FEVSS

9
BT_RF

4
WRF_VDDPA

2
WRF_ RFOUT_5G

1 A

BT_ WRF_ WRF_RFIN_2G PAVDD3P3 RFOUT_2G

FM_AOUT2

BT_ PLLVDD1P2

BT_RFVSS

BT_RFVDD1P2 BT_IFVDD1P2

WRF_VDDLNA WRF_PA_GND _1P2_2G

WRF_ PA_GND

WRF_PA_GND

WRF_ RFIN_5G

FM_TX

FM_ VSSAUDIO

BT_PLLVSS

BT_VSS

BT_IFVSS

WRF_ GNDLNA_2G

WRF_GND

WRF_PADRV_ WRF_ GND PADRV_VDD

WRF_ ANA_GND

FM_RXN

FM_RXP

FM_ VDDAUDIO

BT_GPIO_1

WL_GPIO_6

BT_ CLK_REQ_IN

BT_ UART_TXD

WL_GPIO_3

WRF_A_ TSSI_IN

WRF_ LOGEN_A _GND

WRF_ WRF_ LOGEN_A_ VDDANA_1P2 VDD1P2

FM_ RFVDD1P2

FM_RXVSS

FM_ VDDPLL1P2

BT_ CLK_REQ_ MODE

BT_VDDC

WL_VDDC BT_UART_RXD WL_VSS_2

WRF_ WRF_RES_EXT GPIO_OUT

WRF_VDD_VC OLDO_IN_1P8

FM_VDD2P5 FM_VSSVCO

FM_PLLVSS

BT_GPIO_0

BT_VSSC

BT_VDDIO

BT_UART_ RTS_N

JTAG_SEL

WRF_ AFE_GND

WRF_ WRF_VCOLDO WRF_ TCXO_VDD _OUT_1P2 VCO_GND

BT_CLK_REQ_ OUT

BT_TM0

BT_RST_N

BT_GPIO_7

BT_I2S_DI

BT_UART_ CTS_N

WL_GPIO_1

WRF_ VDDAFE_1P2

WRF_ TCXO_IN

WRF_ XTAL_OP

BT_GPIO_4

BT_GPIO_2

BT_GPIO_3

BT_GPIO_6

BT_I2S_DO

BT_PCM_CLK WL_GPIO_2

WL_GPIO_0

WRF_ XTAL_VDD 1P2

WRF_ XTAL_GND

WRF_ XTAL_ON

VOUT_3P3

VOUT_3P1

EXT_PWM_ REQ

BT_GPIO_5

WL_GPIO_4

LPO

BT_PCM_IN BT_PCM_OUT

RF_SW_ CTRL_5

RF_SW_ CTRL_6

RF_SW_ CTRL_1

HSIC_RREF

SR_VDDBAT1 SR_VDDBAT2 BT_REG_ON

EXT_SMPS_ REQ

BT_VDDC

WL_VDDC

BT_PCM_ SYNC

RF_SW_ CTRL_0

RF_SW_ CTRL_7

RF_SW_ CTRL_4

WL_VSS_0

WL_VDDC

SR_VDDBAT1

PMU_AVSS

VOUT_ LNLDO1

WL_REG_ON SDIO_DATA_3 SDIO_CMD

WL_GPIO_5

WL_VSS_1

RF_SW_ CTRL_2

VDDIO_RF

HSIC_DATA HSIC_AVDD12

SR_VLX

SR_PVSS

VIN_LDO

VOUT_CLDO SDIO_DATA_1

SDIO_CLK

SDIO_DATA_0 SDIO_DATA_2

RF_SW_ CTRL_3

WL_VDDO

HSIC_STROBE HSIC_AVSS

Figure 39: 133-WLBGA Ball Map (bottom view)

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BCM4330 Preliminary Data Sheet

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions Ball# FCFBGA WLBGA WLAN RF Interface E4 A1 A2 A6 A5 B3 D5 E3 B1 A2 A7 A6 D4 17 19 21 18 20 1 16 WRF_RES_EXT WRF_RFIN_5G WRF_RFOUT_5G WRF_RFIN_2G WRF_RFOUT_2G WRF_A_TSSI_IN WRF_G_TSSI_IN I I O I O I I Connect to external 15 k (1%) to ground WLAN 802.11a internal LNA Rx input WLAN 802.11a internal power amplifier output WLAN 802.11b/g and BT shared LNA RX input WLAN 802.11b/g internal power amplifier output TSSI_11a-band (see reference schematics) TSSI_11g-band (see reference schematics). For the WLBGA package, WRF_GPIO_OUT can be used as an 11gband TSSI input. Programmable RF switch control lines. The control lines are programmable via the driver and NVRAM file. Contact Broadcom for details. Bump# WLCSP Signal Name Type Description

RF Control Lines M3 M2 L3 K5 L4 M1 M4 K3 L10 M9 D1 D3 M10 J11 J12 K5 J2 L4 M4 K3 J4 J3 K4 L10 M9 E1 F2 M10 J11 J12 167 168 169 170 171 172 173 174 103 105 100 102 35 22 91 95 96 97 98 99 RF_SW_CTRL_0 RF_SW_CTRL_1 RF_SW_CTRL_2 RF_SW_CTRL_3 RF_SW_CTRL_4 RF_SW_CTRL_5 RF_SW_CTRL_6 RF_SW_CTRL_7 VOUT_LNLDO1 VOUT_CLDO WRF_VDD_VCOLDO_IN_1P8 WRF_VCOLDO_OUT_1P2 VIN_LDO VOUT_3P1 VOUT_3P3 O O O O O O O O O O I O I O O

Integrated LDOs Output of low noise LNLDO1 Output of core LDO Input to VCOLDO Output of VCOLDO Input supply pin to LDO LDO3p1 output (+3.1V output by default) LDO3p3 output (+3.3V output by default)

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Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA Bump# WLCSP Signal Name SR_VDDBAT1 SR_VDDBAT2 SR_VLX Type Description I I O Buck regulator: Battery Voltage Input Core buck regulator: output to inductor

Integrated Switching Regulators L12, K12 L12, K12 76 80 K11 K11 81 85 L11, M12 M12 86 90 WLAN SDIO Bus Interface L7 M6 177 SDIO_DATA_0 I/O SDIO data line 0 M5 M8 178 SDIO_DATA_1 I/O SDIO data line 1 M8 M5 179 SDIO_DATA_2 I/O SDIO data line 2 L8 L8 180 SDIO_DATA_3 I/O SDIO data line 3 M6 M7 175 SDIO_CLK I SDIO clock M7 L7 176 SDIO_CMD I/O SDIO command line Note: For HSIC mode: Pull WL_GPIO_6 high with a resistor between 4.7 10 k. Pull SDIO_DATA2 high, either directly to VIO or through no more than 10 k. Pull SDIO_DATA1 low either directly to ground or through no more than 10 k. Tie all other SDIO data lines high, either directly to VIO or through a resistor. Ground the SDIO_CLK pin. SDIO_CMD can be left floating. JTAG Interface L5 F5 165 JTAG_SEL TCK TDI TDO TMS I I I I I JTAG selection pin (pulled HIGH by default) These JTAG signals can be enabled by software on pins WL_GPIO[1:5]. TMS WL_GPIO1 TCK WL_GPIO2 TDI WL_GPIO3 TDO WL_GPIO4 TRST_L WL_GPIO5

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BCM4330 Preliminary Data Sheet

Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA HSIC Interface K1 M2 164 HSIC_STROBE I/O HSIC bidirectional data strobe signal. HSIC terminations are built in, external resistors are not needed. On SDIO
designs this pin should not be connected.

Bump# WLCSP Signal Name Type Description

162

HSIC_DATA

I/O

HSIC bidirectional DDR data signal. HSIC terminations are built in, external resistors are not needed. On SDIO
designs this pin should not be connected.

163

HSIC_RREF

HSIC bias pin. Connect to ground via a 49.9 Ohm series resistor. On SDIO
designs this pin should not be connected.

Clocks F1 G1 F2 H7 G1 H1 G3 J7 41 40 36 166 WRF_XTAL_OP WRF_XTAL_ON WRF_TCXO_IN LPO I O I I Crystal oscillator input Crystal oscillator output External TCXO input Input for external low-power clock

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BCM4330 Preliminary Data Sheet

Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA WLAN GPIO D4 E4 15 WRF_GPIO_OUT O Auxiliary RF I/O (see reference schematics). For the WLBGA package, WRF_GPIO_OUT can be used as an 11gband TSSI signal. WLAN general interface pins. These pins are high-impedance on power up and reset. Subsequently, they become inputs or outputs through software control. These pins have programmable pull-up/down. WL_GPIO_0 may be configured by software to function as SDIO_Host_Wake. WL_GPIO[1:5] may be enabled as JTAG signals (seeJTAG Interface on page 71). WL_GPIO[3:4] may be configured by software to function as UART_RX and UART_TX. WL_GPIO[1:5] can be configured as external coexistence interface pins (see External Coexistence Interface on page 71). For HSIC mode pull WL_GPIO_6 high with a resistor between 4.7 10 k. FM analog audio output channel 1 FM analog audio output channel 2 FM radio RF output antenna port FM radio RF antenna port FM radio RF antenna port Bluetooth UART signal input. Serial data input for the HCI UART Interface. Bluetooth UART signal output. Serial data input for the HCI UART Interface. Bluetooth UART REquest to Send. Active-low request-to-send signal for the HCI UART interface. Bluetooth UART Clear to Send. Activelow clear-to-send signal for the HCI UART interface. Bump# WLCSP Signal Name Type Description

H2 H1 H3 J3 G4 H5 H4

H4 G5 H5 D5 J8 L6 D8

185 186 187 188 189 190 191

WL_GPIO_0 WL_GPIO_1 WL_GPIO_2 WL_GPIO_3 WL_GPIO_4 WL_GPIO_5 WL_GPIO_6

I/O I/O I/O I/O I/O I/O I/O

FM Transceiver A11 A12 B12 E12 D12 E6 E7 F6 D6 A12 B12 C12 D11 D12 E6 D6 F6 G6 51 52 43 47 48 136 137 135 134 FM_AOUT1 FM_AOUT2 FM_TX FM_RXP FM_RXN BT_UART_RXD BT_UART_TXD BT_UART_RTS_N BT_UART_CTS_N O O O I I I/O I/O I/O I/O

Bluetooth UART

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BCM4330 Preliminary Data Sheet

Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA Bluetooth Test Mode F11 Bluetooth A8 D7 D8 E8 A9 D7 E9 66 113 116 114 BT_RF BT_CLK_REQ_IN BT_CLK_REQ_POL BT_CLK_REQ_MODE O I I I Bluetooth PA output Reference clock request BT Request clock power on reset External reference clock request mode. Pull this pin high to enable the BT_CLK_REQ_OUT signal to function as a high-asserting enable and disable control for an external TCXO. Pull this pin low if an external BT_CLK_REQ_OUT signal is not required; for example, if a dedicated crystal is used for the BCM4330. In this case, the crystal oscillator circuit is enabled and disabled internally. If enabled by the BT_CLK_REQ_MODE pin, this pin is the Bluetooth clock request output signal. See Table 4: Power Control Pin Descriptions, on page 43 for more information. Bluetooth I2S pins G11 133 132 BT_TM0 BT_TM1 I I Bluetooth test mode pin (no connect) Bluetooth test mode pin (no connect) Bump# WLCSP Signal Name Type Description

F12

G12

118

BT_CLK_REQ_OUT

Bluetooth/FM I2S G9 G10 H8 H9 E5 F4 G5 F5 H8 G7 G8 H7 H6 J6 J5 K6 123 124 126 125 127 128 129 130 BT_I2S_CLK BT_I2S_DI BT_I2S_WS BT_I2S_DO BT_PCM_CLK BT_PCM_IN BT_PCM_OUT BT_PCM_SYNC I I/O I/O I/O I/O I/O I/O I/O

Bluetooth PCM PCM clock, can be master (output) or slave (input) PCM data input PCM data output PCM sync signal, can be master (output) or slave (input)

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BCM4330 Preliminary Data Sheet

Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA Bluetooth GPIO F9 H11 G12 H12 G11 H10 L9 F9 D9 H10 H9 H12 J9 L9 117 115 119 120 121 122 106 BT_GPIO_0 BT_GPIO_1 BT_GPIO_2 BT_GPIO_3 BT_GPIO_4 BT_GPIO_5 WL_REG_ON I/O I/O I/O I/O I/O I/O I Bluetooth general interface pins. These pins are high impedance during powerup and reset. Subsequently, they become inputs or outputs through software control. These pins have programmable pull-ups and pull-downs. See Table 23: I/O States, on page 115 for more information. Bump# WLCSP Signal Name Type Description

Miscellaneous Used by PMU (OR-gated with BT_REG_ON) to power up or power down the internal BCM4330 regulators used by the WLAN section. This pin is also a low-asserting reset for WLAN only (Bluetooth is not affected by this pin). Logic High Level: 1.08V3.6V 200k pull-down resistor included. Used by PMU (OR-gated with WL_REG_ON) to power up or power down internal BCM4330 regulators used by the BT/FM section. Logic High Level: 1.08V3.6V 200k pull-down resistor included. Low asserting reset for Bluetooth/FM only (WLAN is not affected by this pin). Auxiliary PMU control inputs (see Reset Circuits on page 29). These pins have 200k internal pull-down resistors and should be no-connect when not used. Logic High Level: 1.08V3.6V 3.3V Bluetooth internal PA power supply 1.2V Bluetooth power supply 1.2V Bluetooth LNA power supply 1.2V Bluetooth VCO power supply 1.2V Bluetooth IF block power supply 1.2V Bluetooth PLL power supply 1.2V Bluetooth baseband core supply

K10

107 108

BT_REG_ON

F10 J9 J10

G10 K9 J10

131 111 112 109 110

BT_RST_N EXT_SMPS_REQ EXT_PWM_REQ

I I I

Bluetooth Supplies A7 A9 A10 B7 B10 F8, J8, K8 A8 B9 A11 B8 B11 K8, E8 68 67 64 59 61 138 148 BT_PAVDD3P3 BT_RFVDD1P2 BT_LNAVDD1P2 BT_VCOVDD1P2 BT_IFVDD1P2 BT_PLLVDD1P2 BT_VDDC I I I I I I I

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BCM4330 Preliminary Data Sheet

Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA WLAN Supplies A3 A4 C4 B1 A4 C3 33, 34 31, 32 30 28 WRF_VDDPA_5G WRF_VDDPA_2G WRF_VDDPA WRF_PADRV_VDD WRF_VDDLNA_1P2_5G I I I I I VDD power supply (from VBAT) for the internal 11a-band power amplifier VDD power supply (from VBAT) for the internal 11g-band power amplifier VDD power supply (from VBAT) for both internal power amplifiers VDD power supply (from VBAT) supply for the WLAN PA driver 1.2V supply for the 11a-band internal LNA. If the IEEE 802.11a band is not used, tie this supply pin to WRF_VDDLNA_1P2_2G. 1.2V supply for the 11g-band internal LNA 1.2V supply for the crystal oscillator circuit 1.7V to 3.3V supply for the BCM4330 TCXO driver. To maintain a constant load on the WRF_TCXO_IN pin (even when power is removed from the BCM4330), connect this supply pin to a 1.7V to 3.3V supply that is always present. If not used, this pin must be connected to ground (see Section 3: Frequency References, on page 30). 1.2V supply for WLAN PLL 1.2V supply for WLAN AFE 1.2V supply for WLAN ADC/DAC block 1.2V supply for WLAN core Bump# WLCSP Signal Name Type Description

B6 G3 E1

B7 H3 F3

27 38 37

WRF_VDDLNA_1P2_2G WRF_XTAL_VDD1P2 WRF_TCXO_VDD

I I I

C1 E3 D2 F7, H6, J2, L6 C12 C11 E10 B11

D2 G4 D1 E7,K7,K1

29 23, 24 25 26 192204

WRF_LOGEN_A_VDD1P2 WRF_VDDAFE_1P2 WRF_VDDANA_1P2 WL_VDDC

I I I I

FM Transceiver Supplies E12 E10 F12 D10 46 57 54 42 50 FM_RFVDD1P2 FM_IFVDD1P2 FM_VDDPLL1P2 FM_VDD2P5 FM_VDDAUDIO I I I I I 1.2V FM transceiver power supply 1.2V FM IF power supply 1.2V FM PLL power supply FM power supply (nominal 3.1V) FM audio power supply

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BCM4330 Preliminary Data Sheet

Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA J1 K4 K6 J7 Ground C2 B4 B5 C5 B2 C6 C3 E2 F3 G2 C7 C8 B8 C9 B9 D9 D3 B2, B4, B6 C4 C7 C1 F1 F4 H2 K2 L5 E5 C5 C8 C9 A10 B10 C10 F8 8 12 13 10 11 9 7 6 23 14 45 39 58 65 63 60 62 151 159 209 210 211 WRF_LOGEN_A_GND WRF_GNDPA_5G WRF_GNDPA_2G WRF_PA_GND WRF_PADRV_GND WRF_GNDLNA_5G WRF_GNDLNA_2G WRF_ANA_GND WRF_VCO_GND WRF_AFE_GND WRF_XTAL_GND WL_VSS_0 WL_VSS_1 WL_VSS_2 WRF_GND BT_IFVSS BT_VSS BT_FEVSS BT_VCOVSS BT_RFVSS BT_PLLVSS BT_LNAVSS BT_VSSC PACKAGEOPTION_0 PACKAGEOPTION_1 PACKAGEOPTION_2 I I I I I I I I I I I I I I I I I I I I I I I I I I WLAN 11a-band LO ground WLAN 11a-band PA ground WLAN 11g-band PA ground WLAN PA ground WLAN PA driver ground WLAN 11a-band LNA ground WLAN 11g-band LNA ground WLAN ADC/DAC ground WLAN VCO ground WLAN AFE ground WLAN PLL ground WLAN ground L1 L3 M3 F7 Bump# WLCSP 160 182184 205 208 149 150 212 Signal Name HSIC_AVDD12 VDDIO_RF WL_VDDIO BT_VDDIO PACKAGEOPTION_3 Type Description I I/O I I 1.2V HSIC power supply: on SDIO designs this pin should not be connected. RF I/O supply (3.3V) WLAN digital I/O supply (1.2V to 2.5V) BT digital I/O supply (1.2V to 2.5V) Connect to VDD

Miscellaneous Supplies

WLAN RF block ground Bluetooth IF block ground Bluetooth ground Bluetooth ground Bluetooth VCO ground Bluetooth ground Bluetooth PLL ground Bluetooth LNA ground Bluetooth ground Connect to ground

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BCM4330 Preliminary Data Sheet

Signal Assignments

Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.) Ball# FCFBGA WLBGA C10 D11 E11 D10 E9 G6, G7, G8, J4, J5, J6 K2 K10 M11 A1, A2 K7 C11 E11 F11 F10 M1 L11 M11 Bump# WLCSP 53 44 45 49 55 56 161 69 70 71 75 213 225 181 Signal Name FM_VSSAUDIO FM_RXVSS FM_VSSVCO FM_PLLVSS FM_VSS FM_IFVSS VSSC HSIC_AVSS PMU_AVSS SR_PVSS WL_VSS NC VDD_ISLAND Type Description I I I I I I I I I I I N/A I FM audio ground FM receiver ground FM VCO ground FM PLL ground FM ground FM IF block ground Ground HSIC block ground PMU block analog ground Switching regulator ground WLAN ground No connect No connect

No Connect

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BCM4330 Preliminary Data Sheet

Signal Assignments

WLAN GPIO Signals and Strapping Options

The pins listed in Table 19 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 k resistor or less. Note: Refer to the reference board schematics for more information.

Table 19: WLAN GPIO Functions and Strapping Options Pin Name FCFBGA WLBGA WLCSP Pin # Pin # Pin # M8 M5 D8 179 180 181 Default Function X X 0 strap_host_ifc_1 strap_host_ifc_2 strap_host_ifc_3 Description The three pins strap_host_ifc_[3:1] together select the host interface mode: 0XX: SDIO 10X: gSPI 110: normal HSIC 111: bootloader-less HSIC

SDIO_DATA_1 M5 SDIO_DATA_2 M8 WL_GPIO_6 H4

Note: For HSIC mode: Pull WL_GPIO_6 high with a resistor between 4.7 10 k. Pull SDIO_DATA2 high, either directly to VIO or through no more than 10 k. Pull SDIO_DATA1 low, either directly to ground or through no more than 10 k. Tie all other SDIO data lines high, either directly to VIO or through a resistor. Ground the SDIO_CLK pin. SDIO_CMD can be left floating.

Table 20: Strap Options strap_host_ifc_3 WL_GPIO_6 Default states at sampling instant SDIO gSPI HSIC (normal) Bootloader-less HSIC (debug only) 0 0 1 1 1 strap_host_ifc_2 SDIO_DATA_2 Float x 0 1 1 strap_host_ifc_1 SDIO_DATA_1 Float x x 0 1

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BCM4330 Preliminary Data Sheet

Signal Assignments

Muxed Bluetooth GPIO Signals

The Bluetooth GPIO pins (BT_GPIO_0 to BT_GPIO_7) are multiplexed pins and can be programmed to be used as GPIOs or for other Bluetooth interface signals such as I2S. The specific function for a given BT_GPIO_X pin is chosen by programming the Pad Function Control Register for that specific pin. Table 21 shows the possible options for each BT_GPIO_X pin. Note that each BT_GPIO_X pin's Pad Function Control Register Setting is independent (i.e. BT_GPIO_1 can be set to Pad Function 7 at the same time that BT_GPIO_3 is set to PAD Function 0). When the Pad Function Control Register is set to 0 the BT_GPIOs do not have specific functions assigned to them and behave as generic GPIOs. The A_GPIO_X pins described below are multiplexed behind the BCM4330 PCM and I2S interface pins. Table 21: GPIO Multiplexing Matrix Pad Function Control Register Setting Pin Name
BT_UART_CTS_N BT_UART_RTS_N BT_UART_RXD BT_UART_TXD BT_PCM_IN BT_PCM_OUT BT_PCM_SYNC BT_PCM_CLK BT_I2S_DO BT_2S_DI BT_I2S_WS BT_I2S_CLK BT_GPIO_5 BT_GPIO_4 BT_GPIO_3 BT_GPIO_2 BT_GPIO_1 BT_GPIO_0 BT_CLK_REQ_IN

0
UART_CTS_N UART_RTS_N UART_RXD UART_TXD A_GPIO[3] A_GPIO[2] A_GPIO[1] A_GPIO[0] A_GPIO[5] A_GPIO[6] GPIO[7] GPIO[6] GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] A_GPIO[4]

1
PCM_IN PCM_OUT PCM_SYNC PCM_CLK PCM_OUT PCM_IN PCM_SYNC PCM_CLK HCLK LINK_IND

2
PCM_IN PCM_OUT PCM_CLK

3
HCLK LINK_IND HCLK LINK_IND I2S_MSCK I2S_MSDO I2S_MWS

4
INT_LPO I2S_SSDO I2S_SSDI/ MSDI INT_LPO I2S_SSCK I2S_SSDO I2S_SWS I2S_SSDI/ MSDI clk_12p288

5
I2S_MSDO I2S_MWS I2S_MSCK I2S_MSDO I2S_MWS I2S_MSCK

7
A_GPIO[1] A_GPIO[0] GPIO[5] GPIO[4] I2S_SSDI/MSDI I2S_SSDO I2S_SWS I2S_SSCK STATUS TX_CON_FX I2S_SWS I2S_SSCK CLK_REQ RF_ACTIVE A_GPIO[4] A_GPIO[7]

PCM_SYNC HCLK

BT_CLK_REQ_OUT WL/BT_CLK_REQ

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BCM4330 Preliminary Data Sheet

Signal Assignments

The multiplexed GPIO signals are described in Table 22. Table 22: Multiplexed GPIO Signals Pin Name UART_CTS_N UART_RTS_N UART_RXD UART_TXD PCM_IN PCM_OUT PCM_SYNC PCM_CLK GPIO[7:0] A_GPIO[7:0] I2S_MSDO I2S_MWS I2S_MSCK I2S_SSCK I2S_SSDO I2S_SWS I2S_SSDI/MSDI STATUS TX_CON_FX RF_ACTIVE LINK_IND WL/BT_CLK_REQ Type I O I O I O I/O I/O I/O I/O O O O I O I I O I O O O Description Host UART clear to send Device UART request to send Device UART receive data Host UART transmit data PCM data input PCM data output PCM sync signal, can be master (output) or slave (input) PCM clock, can be master (output) or slave (input) General purpose I/O A group general purpose I/O I2S master data output I2S master word select I2S master clock I2S slave clock I2S slave data output I2S slave word select I2S slave/master data input Signals Bluetooth priority status WLAN-BT coexist. Transmission confirmation; permission for BT to transmit WLAN-BT coexist. Asserted (logic high) during local BT RX and TX slots BT receiver/transmitter link indicator WLAN clock request output

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BCM4330 Preliminary Data Sheet

Signal Assignments

I/O States
The following notations are used in Table 23: I: Input signal O: Output signal I/O: Input/Output signal PU = Pulled up PD = Pulled down NoPull = Neither pulled up nor pulled down Table 23: I/O States
Power Downb (BT_REG_ON and WL_REG_ON held low) I; PD (of 200K) I; NoPull I; PD (of 200K) High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull Out of Reset; Before SW Download (BT_RST_N high; xx_REG_ON high) I; PD (of 200K) I; NoPull I; PD (of 200K) I, PD I; PU I; PU I; PU I; PU I; PU I; PU I; NoPull I, PD I, PD I, PD (xx_REG_ON-high and BT_RST_N = 0) and VDDIOs are Power Rail Present I; PD (of 200K) I; NoPull I; PD (of 200K) I, PD I; PU I; PU I; PU I; PU I; PU I; PU I; NoPull I, PD I, PD I, PD BT_VDDIO BT_VDDIO BT_VDDIO BT_VDDIO BT_VDDIO BT_VDDIO WL_VDDIO WL_VDDIO WL_VDDIO BT_VDDIO BT_VDDIO BT_VDDIO

Name WL_REG_ON BT_RST_N BT_REG_ON BT_GPIO 0,1,2,3,4,5 BT_UART_CTS BT_UART_RTS BT_UART_RXD BT_UART_TXD SDIO Datac SDIO CMDc SDIO_CLKc BT_PCM_CLK BT_PCM_IN BT_PCM_OUT

I/O I I I I/O I O I O I/O I/O I I/O I/O I/O

Keepera N Y N Y Y Y Y Y N N N Y Y Y

Active Mode I; PD (pull down can be disabled) I; NoPull I; PD (pull down can be disabled) I/O; PU, PD, NoPull (programmable) I; NoPull O; NoPull I; NoPull O; NoPull I/O; PU I/O; PU I; NoPull I; NoPulld I; NoPulld I; NoPulld

Low Power State/Sleep (all power present) I; PD (pull down can be disabled) I; NoPull I; PD (pull down can be disabled) I/O; PU, PD, NoPull (programmable) I; NoPull O; NoPull I; NoPull O; NoPull I; PU I; PU I; NoPull I; NoPulld I; NoPulld I; NoPulld

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Signal Assignments

Table 23: I/O States (Cont.)

Power Downb (BT_REG_ON and WL_REG_ON held low) High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull High-Z, NoPull Out of Reset; Before SW Download (BT_RST_N high; xx_REG_ON high) I, PD I, PD I, PD I; PD I; PU I; PU I; PU I; NoPull (xx_REG_ON-high and BT_RST_N = 0) and VDDIOs are Power Rail Present I, PD I, PD I, PD I; PD I; PU I; PU I; PU I; NoPull BT_VDDIO BT_VDDIO BT_VDDIO WL_VDDIO WL_VDDIO WL_VDDIO WL_VDDIO WL_VDDIO

Name BT_PCM_SYNC BT_I2S_WS BT_I2S_CLK WL GPIO_0 WL GPIO_1 WL GPIO_2 WL GPIO_3 WL GPIO_4

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I/O I/O I/O I/O I/O I/O I/O I/O I/O

Keepera Y Y Y Y Y Y Y Y

Active Mode I; NoPulld I; NoPull

Low Power State/Sleep (all power present) I; NoPulld I; NoPulle I; NoPulle I/O; PU, PD, NoPull (programmable [Default: PD]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: NoPull]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: PD])

I; NoPulle I/O; PU, PD, NoPull (programmable [Default: PD]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: NoPull]) I/O; PU, PD, NoPull (programmable [Default: PU]) I/O; PU, PD, NoPull (programmable [Default: PD])

WL GPIO_5 WL GPIO_6c

I/O I/O

Y Y

High-Z, NoPull High-Z, NoPull

I; PU I; PD

WL_VDDIO WL_VDDIO

a. N = Pad has no keeper; Y = Pad has a keeper. The keeper is always active except in power down state. If there is no keeper, it is an input, and there is no pull, then the pad should be driven to prevent leakage due to the floating pad (e.g., SDIO_CLK). b. In the power down state (xx_REG_ON = 0), High-Z; noPull: the pad is disabled because power is not supplied. c. Internal pull-up resistors on the SDIO_DATA lines are disabled after the internal power-on reset when the BCM4330 is strapped for HSIC mode. To use the device in HSIC mode: pull WL_GPIO_6 high with a resistor between 4.7 10 k; pull SDIO_DATA2 high, either directly to VIO or through no more than 10 k; pull SDIO_DATA1 low, either directly to ground or through no more than 10 k; tie all other SDIO data lines high, either directly to VIO or through a resistor; and ground the SDIO_CLK pin. SDIO_CMD can be left floating. d. Depending on whether the PCM interface is enabled and the configuration of PCM is in master or slave mode, this can be either output or input. e. The I2S interface is shared with GPIO2, 3, 4, and 5. Up to master or slave mode, it can be either output or input.

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DC Characteristics

Section 15: DC Characteristics

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Absolute Maximum Ratings

Caution! The absolute maximum ratings in Table 24 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 24: Absolute Maximum Ratings Rating Symbol Value Unit

DC supply for VBATT VBATT 0.5 to 6.0 V DC supply for WLAN power amplifier VDDPA 0.5 to 6.0 V DC supply voltage for I/O VDDIO 0.5 to 2.98 V Note: When using a 2.9V 3% supply, a 2.98V to 3.09V range is allowed for a duration not to exceed 1.5 seconds for each power-up cycle. After that, the VDDIO supply for the chip must have a steady state operating condition within the range 2.9V 3%. DC supply voltage for RF VDDRF 0.5 to 1.32 V DC supply voltage for core VDDC 0.5 to 1.32 V DC supply voltage for RF I/Os VDDIO_RF 0.5 to 3.8 V DC input supply voltage for CLDO and LNLDO1 0.5 to 2.1 V WRF_VDD_VCOLDO_IN_1P8 0.5 to 2.75 V WRF_TCXO_VDD 0.5 to 3.63 V Maximum undershoot voltage for I/O Vundershoot 0.5 V Maximum Junction Temperature Tj 125 C

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BCM4330 Preliminary Data Sheet

Environmental Ratings

Environmental Ratings
The environmental ratings are shown in Table 25. Table 25: Environmental Ratings Characteristic Ambient Temperature (TA) Storage Temperature Relative Humidity Value 30 to +85 40 to +125 Less than 60 Less than 85 Units C C % % Conditions/Comments Functional operationa Storage Operation

a. Functionality is guaranteed but specifications require derating at extreme temperatures; see the specification tables for details.

Electrostatic Discharge Specifications

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging. Table 26: ESD Specifications Pin Type Symbol Condition ESD Rating Unit kV

ESD, Handling ESD_HAND_HBM Reference: NQY00083, Section 3.4, Group D9, Table B Machine Model (MM) ESD_HAND_MM CDM ESD_HAND_CDM

Human body model contact discharge per JEDEC 1.5 EID/JESD22-A114 JESD22-A115 Charged device model contact discharge per JEDEC EIA/JESD22-C101 50 200

V V

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BCM4330 Preliminary Data Sheet

Recommended Operating Conditions and DC Characteristics

Caution! Functional operation is not guaranteed outside of the limits shown in Table 27 and operation outside these limits for extended periods can adversely affect long-term reliability of the device.

Table 27: Recommended Operating Conditions and DC Characteristics Value Element Symbol Minimum Typical Maximum Unit DC supply voltage for VBATT VBATT 2.3a 4.8b V a b DC supply for WLAN power amplifier VDDPA 2.3 3.3 4.8 V DC supply voltage for core VDD 1.14 1.2 1.26 V DC supply voltage for RF blocks in chip VDDRF 1.14 1.2 1.26 V c DC supply voltage for RF I/Os VDDIO_RF 3.14 3.3 3.46 V DC supply voltage for I/O VDDIO 1.2 1.8 2.9 3% V Note: When using a 2.9V 3% supply, a 2.98V to 3.09V range is allowed for a duration not to exceed 1.5 seconds for each power-up cycle. After that, the VDDIO supply for the chip must have a steady state operating condition within the range 2.9V 3%. DC supply for HSIC interfaced HSIC_ 1.1 1.2 1.3 V AVDD12 1.08 3.6 V Input High Voltage (WL_REG_ON, BT_REG_ON, VIH EXT_SMS_REQ, EXT_PWM_REQ) Input Low Voltage (WL_REG_ON, BT_REG_ON, VIL 0.4 V EXT_SMS_REQ, EXT_PWM_REQ) Input High Voltage (VDDIO = 1.2V)d,e VIH 0.7 VDDIO V d,e Input Low Voltage (VDDIO = 1.2V) VIL 0.3 VDDIO V d,e Input High Voltage (VDDIO = 1.8V to 2.5V) VIH 0.65 VDDIO V d,e Input Low Voltage (VDDIO = 1.8V to 2.5V) VIL 0.35 VDDIO V d,e Input High Voltage (VDDIO = 2.9V 3%) VIH 0.65 VDDIO V d,e Input Low Voltage (VDDIO = 2.9V 3%) VIL 0.35 VDDIO V Output High Voltage @ 100 A VOH VDDIO 0.1 V (VDDIO = 1.2V) Output High Voltage @ 2 mA VOH VDDIO 0.2 V (VDDIO = 1.2V) Output Low Voltage @ 100 A VOL 0.1 V (VDDIO = 1.2V) Output Low Voltage @ 2 mA VOL 0.2 V (VDDIO = 1.2V) Output High Voltage @ 100 A VOH VDDIO 0.2 V (VDDIO = 1.8V to 2.9V)

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BCM4330 Preliminary Data Sheet

Recommended Operating Conditions and DC Characteristics

Table 27: Recommended Operating Conditions and DC Characteristics (Cont.) Value Element Output High Voltage @ 2 mA (VDDIO = 1.8V to 2.9V) Output Low Voltage @ 100 A (VDDIO = 1.8V to 2.9V) Output Low Voltage @ 2 mA (VDDIO = 1.8V to 2.9V) Input capacitance Symbol VOH VOL VOL CIN Minimum Typical Maximum 0.2 0.45 5 Unit V V V pF VDDIO 0.45

a. The BCM4330 is functional across this range of voltages. Optimal RF performance specified in this Data Sheet, however it is guaranteed only for 3.0V < VBAT < 4.8V. b. The max continuous voltage is 4.8V. Voltages up to 5.5V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. c. VDDIO_RF is generally supplied by the BCM4330 VOUT_3P3 output. d. See Table 51: HSIC Interface Specifications, on page 156 for HSIC STROBE (HSIC_STROBE) and DATA (HSIC_DATA) specifications.

e. Applies to GPIO and SDIO signals.

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BCM4330 Preliminary Data Sheet

Bluetooth RF Specifications

Section 16: Bluetooth RF Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified in Table 25: Environmental Ratings, on page 118 and Table 27: Recommended Operating Conditions and DC Characteristics, on page 119. Typical values apply for the following conditions: Vbatt = 3.6V Ambient temperature +25C

BCM4330
WLAN Tx BT Tx WLAN/BT Rx

RF Switch
(0.5 dB Insertion Loss)

Filter

Antenna Port

Chip Port

RF Port

Figure 41: RF Port Location for Bluetooth Testing

Note: All Bluetooth specifications are measured at the RF port unless otherwise specified.

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Bluetooth RF Specifications

Table 28: Bluetooth Receiver RF Specifications Parameter General Frequency range RX sensitivity GFSK, 0.1% BER, 1 Mbps /4 DQPSK, 0.01% BER, 2 Mbps 8 DPSK, 0.01% BER, 3 Mbps Input IP3 Maximum input at antenna Return loss of BT Rx and Tx pins 50 port Interference Performance1 C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I 3 MHz adjacent channel C/I image channel C/I 1 MHz adjacent to image channel C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I 3 MHz adjacent channel C/I image channel C/I 1 MHz adjacent to image channel C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I 3 MHz adjacent channel C/I Image channel C/I 1 MHz adjacent to image channel GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER /4 DQPSK, 0.1% BER /4 DQPSK, 0.1% BER /4 DQPSK, 0.1% BER 8 DPSK, 0.1% BER /4 DQPSK, 0.1% BER /4 DQPSK, 0.1% BER 8 DPSK, 0.1% BER 8 DPSK, 0.1% BER 8 DPSK, 0.1% BER 8 DPSK, 0.1% BER 8 DPSK, 0.1% BER 8 DPSK, 0.1% BER 11.0 0.0 30.0 40.0 9.0 20.0 13.0 0.0 30.0 40.0 7.0 20.0 21.0 5.0 25.0 33.0 0.0 13.0 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 2402 16 10 93 95 89 9 2480 87.5 87.5 82.5 20 MHz dBm dBm dBm dBm dBm dB Conditions Minimum Typical Maximum Unit

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BCM4330 Preliminary Data Sheet

Bluetooth RF Specifications

Table 28: Bluetooth Receiver RF Specifications (Cont.) Parameter 302000 MHz 20002399 MHz 24983000 MHz 3000 MHz 12.75 GHz 776794 MHz 824849 MHz 824849 MHz 880915 MHz 17101785 MHz 18501910 MHz 18501910 MHz 18501910 MHz 19201980 MHz Spurious Emissions 30 MHz 1 GHz 1 12.75 GHz 851894 MHz 925960 MHz 18051880 MHz 19301990 MHz 21102170 MHz 147 147 147 147 147 62 47 dBm dBm dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz Conditions 0.1% BER 0.1% BER 0.1% BER 0.1% BER CDMA2000 cdmaOne GSM850 E-GSM GSM1800 GSM1900 cdmaOne WCDMA WCDMA Minimum Typical 10.0 27 27 10.0 7 7 7 8 14 15 14 14 15 Maximum Unit dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

Out-of-Band Blocking Performance (CW)

Out-of-Band Blocking Performance, Modulated Interferer 2

1. The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as defined in the version 4.0 specification. 2. Bluetooth reference level for wanted signal at the Bluetooth RF port = 84.5 dBm.

dBuV dBuV dBuV dBuV dB dB dB Hz kHz s s % % dB

dB dBcb

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BCM4330 Preliminary Data Sheet

FM Receiver Specifications

Section 18: FM Receiver Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified inTable 25: Environmental Ratings, on page 118 and Table 27: Recommended Operating Conditions and DC Characteristics, on page 119. Typical values apply for the following conditions: Vbatt = 3.6V Ambient temperature +25C Table 32: FM Receiver Specifications Parameter RF Parameters Operating frequency Sensitivityc Frequencies inclusive 65b FM only, fmod = 1 kHz, f = 22.5 kHz, (S+N)/N 26 dB f = 32 kHz, fmod = 1 kHz, f Pilot = 7.5 kHz. 95% of blocks decoded with no errors, over a sample of 5000 blocks. RDS deviation = 1.2 kHz. f = 32 kHz, fmod=1 kHz, f Pilot = 7.5 kHz. 95% of blocks decoded with no errors, over a sample of 5000 blocks. RDS deviation = 2 kHz. Wanted Signal: RDS sensitivity + 3 dB, 2 kHz RDS deviation. f = 32 kHz, fmod = 1 kHz, f Pilot = 7.5 kHz. Interferer: f = 40 kHz, fmod = 1 kHz. Interferer level for 95% of blocks decoded with no errors, over a sample of 5000 blocks. 200 kHz S + 16 300 kHz S + 25 400 kHz S + 35 f Image frequency 1.1 5 1 19 8.9 13 15 5.6 9 108 3.6 5 11 24 15.9 18 21 11.2 15 MHz V EMF dBV dBV EMF dBV EMF V EMF dBV dBV EMF V EMF dBV Conditionsa Minimum Typical Maximum Units

RDS sensitivityd e

RDS selectivitye

dB dB dB dB

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FM Receiver Specifications

Table 32: FM Receiver Specifications (Cont.) Parameter Receiver adjacent channel selectivityg Conditionsa Minimum Typical Maximum Units dB

Image response, mono

In-band blocking

AM suppression, monoc

Intermediate signal plus noise-to-noise ratio (S+N)/N, stereoc Intermodulation performancec

Measured for 40 dB SNR at the audio S + 16 output. Wanted Signal: 23 dBV EMF (14.1 V EMF) f = 75 kHz, fmod = 1 kHz, f pilot = 7.5 kHz. Interferer: f = 40 kHz, fmod = 1 kHz. At 200 kHz. At 300 kHz and above S + 25 At fWanted 2fIF, depending on LO 25 injection side relative to fWanted. Measured for 40 dB SNR at the audio output. Wanted signal: 66 dBV EMF (2 mV EMF), f = 75 kHz, fmod = 1 kHz. Interferer: f = 40 kHz, fmod = 1 kHz. At fWanted 1 MHz to fWanted + 400 kHz S + 35 in 100 kHz steps. Measured for 40 dB SNR at the audio output. Wanted signal: 23 dBV EMF (14.1 V EMF), f = 75 kHz, fmod = 1 kHz. Interferer: f = 40 kHz, fmod = 1 kHz. Vin = 23 dBV EMF (14.1 V EMF), 40 f = 22.5 kHz, fmod = 1 kHz. AM at 400 Hz with m = 0.3. No A-weighted or any other filtering applied. Vin = 20 dBV EMF (10 V EMF), 45 f = 22.5 kHz, fmod = 1 kHz. BAF = 300 Hz to 15 kHz, A-weighted mono. Vin = 20 dBV EMF (10 V EMF), S + 32 f = 22.5 kHz, fmod = 1 kHz. BAF = 300 Hz to 15 kHz, A-weighted mono. f = 22.5 kHz, fmod = 1 kHz. SNR > 26 dB. 1.5

dB dB

RF Input RF input impedance RF input levelc 111 354 105 55 90 k dBV EMF mV EMF dBV dBm dBm

RF conducted emissions Local oscillator breakthrough measured on the reference port 925960 MHz, 1805 1880 MHz, and 19301990 MHz

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FM Receiver Specifications

Table 32: FM Receiver Specifications (Cont.) Parameter RF blocking levels at the FM antenna input 26 dB SNR. (Assumes presence of an external matching circuit.) Conditionsa 824915 MHz, GSM 200 kHz BW, CDMA 1.2 MHz BW 17101980 MHz, GSM 200 kHz BW, CDMA 1.2 MHz BW, WCDMA 4 MHz BW Minimum Typical Maximum Units 0 5 dBm dBm

Tuning Frequency step Settling time 10 Single frequency switch in any direction to a frequency within the bands 88108 MHz or 7690 MHz. Time measured to within 5 kHz of the final frequency. Total time for an automatic search to sweep from 88108 MHz or 7690 MHz (and reverse direction) assuming no channels found. 14 60 1 60 80 150 kHz s

Sweep time

sec

General Audio Audio output levelh Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz, f pilot = 6.75 kHz. Maximum audio output Vin = 66 dBV EMF(2 mV EMF), leveli f = 100 kHz, fmod = 1 kHz, f pilot = 6.75 kHz. Audio output level Vin = 66 dBV EMF (2 mV EMF), differencej f = 22.5 kHz, fmod = 1 kHz. Left and right AC mute FM input signal fully muted with DAC enabled. Left and right hard mute FM input signal fully muted with DAC
disabled.

12.5 90 0 333 1

dBFS mV rms dBFS mV rms dB dB dB

Soft mute attenuation and start level

Maximum signal plus noise-to-noise ratio (S+N)/N, monoj Maximum signal plus noise-to-noise ratio (S+N)/N, stereoj

Muting is performed dynamically proportional to the FM wanted input signal C/N. The muting characteristic is fully programmable. See Section 9: FM Transceiver Subsystem, on page 64 for more information. Vin = 66 dBV EMF(2 mV EMF), f = 22.5 kHz, fmod = 1 kHz.

60 56

dB dB

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FM Receiver Specifications

Table 32: FM Receiver Specifications (Cont.) Parameter Total harmonic distortion, mono Conditionsa Minimum Typical Maximum Units 0.8 0.8 0.8 1.0 1.5 60 % % % % % dBc

Vin = 66 dBV EMF (2 mV EMF), f = 75 kHz, fmod = 400 Hz. Vin = 66 dBV EMF (2 mV EMF), f = 75 kHz, fmod = 1 kHz. Vin = 66 dBV EMF (2 mV EMF), f = 75 kHz, fmod = 3 kHz. Vin = 66 dBV EMF (2 mV EMF), f = 100 kHz, fmod = 1 kHz. Total harmonic Vin = 66 dBV EMF (2 mV EMF), distortion, stereo f = 67.5 kHz, fmod = 1 kHz, f Pilot = 6.75 kHz, L=R. Audio spurious Vin = 66 dBV EMF (2 mV EMF), productsj f = 22.5 kHz, fmod = 1 kHz, Range from 300 Hz to 15 kHz, with respect to 1 kHz tone. Audio bandwidth, upper Vin = 66 dBV EMF (2 mV EMF), (3 dB point) f = 8 kHz, for 50 s. Audio bandwidth, lower (3 dB point) Audio in-band ripple 100 Hz to 13 kHz, Vin = 66 dBV EMF (2 mV EMF), f = 8 kHz, for 50 s. Deemphasis time With respect to 50 and 75 s constant tolerance RSSI range With 1 dB resolution and 3 dB accuracy at room temperature Pause Detection Audio level at which a pause is detected Audio pause duration Relative to a 1-kHz tone, 22.5 kHz deviation 4 values in 3 dB steps 4 values

15 0.5 3 1.41 3 21 20

20 0.5 5 83 14100 77 12 40

kHz Hz dB % dBV EMF V EMF dBV dB ms

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FM Receiver Specifications

Table 32: FM Receiver Specifications (Cont.) Parameter Stereo Decoder Forced Stereo mode. Vin = 66 dBV EMF (2 mV EMF), f = 67.5 kHz, fmod = 1 kHz, f Pilot = 6.75 kHz, R = 0, L = 1. Mono/stereo blend and Blending and switching is dynamically switching proportional to the FM wanted input signal C/N. The blending and switching characteristics are fully programmable. See Section 9: FM Transceiver Subsystem, on page 64 for more information. Pilot suppression Vin = 66 dBV EMF (2 mV EMF), 46 f = 75 kHz, fmod = 1 kHz. Stereo channel separation 40 dB Conditionsa Minimum Typical Maximum Units

a. The following conditions apply to all relevant tests unless otherwise indicated: Preemphasis and deemphasis of 50 s, R = L for mono, DAC Load > 20 k, BAF = 300 Hz to 15 kHz, A-weighted filtering. b. Contact Broadcom regarding applications that will operate between 65 and 76 MHz. c. Wanted signal: f = 22.5 kHz, fmod = 1 kHz. d. RDS sensitivity numbers are for 87.5 to 108 MHz only. e. Vin = f = 32 kHz, fmod = 1 kHz, f pilot = 7.5 kHz, 95% of blocks decoded with no errors over a sample of 5000 blocks. f. The best tune algorithm is used during normal operation to avoid image interference. g. Wanted Signal: f = 22.5 kHz, fmod = 1 kHz, f pilot = 7.5 kHz. h. Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz, f pilot = 6.75 kHz. i. Vin = 66 dBV EMF (2 mV EMF), f = 100 kHz, fmod = 1 kHz, f pilot = 6.75 kHz. j. Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz.

Figure 42: FM Receiver Circuit

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WLAN RF Specifications

Section 19: WLAN RF Specifications

Introduction
The BCM4330 includes an integrated dual-band direct conversion radio that supports either the 2.4 GHz band or the 5 GHz band. The BCM4330 does not provide simultaneous 2.4 GHz and 5 GHz operation. This section describes the RF characteristics of the 2.4 GHz and 5 GHz portions of the radio. Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified inTable 25: Environmental Ratings, on page 118 and Table 27: Recommended Operating Conditions and DC Characteristics, on page 119. Typical values apply for the following conditions: Vbatt = 3.6V Ambient temperature +25C

BCM4330
WLAN Tx BT Tx WLAN/BT Rx

RF Switch
(0.5 dB Insertion Loss)

Filter

Antenna Port

Chip Port

RF Port

Figure 43: Port Locations

Note: All WLAN specifications are measured at the chip port, unless otherwise specified.

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2.4 GHz Band General RF Specifications

Table 33: 2.4 GHz Band General RF Specifications Item Tx/Rx switch time Rx/Tx switch time Power-up and power-down ramp time Condition Minimum Typical Maximum 5 2 <2 Unit s s s

Including TX ramp down Including TX ramp up DSSS/CCK modulations

WLAN 2.4 GHz Receiver Performance Specifications

Note: The specifications in Table 34 are measured at the chip port, unless otherwise specified.

Table 34: WLAN 2.4 GHz Receiver Performance Specifications Parameter Frequency range RX sensitivity (8% PER for 1024 octet PSDU)a Condition/Notes 1 Mbps DSSS 2 Mbps DSSS 5.5 Mbps DSSS 11 Mbps DSSS 6 Mbps OFDM 9 Mbps OFDM 12 Mbps OFDM 18 Mbps OFDM 24 Mbps OFDM 36 Mbps OFDM 48 Mbps OFDM 54 Mbps OFDM Minimum Typical 2400 96.5 92 90.5 88 89 86 84 75 98 94 92 90 92 90.5 89 88 86 83 78 77 Maximum Unit 2500 MHz dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

RX sensitivity (10% PER for 1000 octet PSDU)a

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WLAN 2.4 GHz Receiver Performance Specifications

Table 34: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical 74 74.5 76.5 80.5 84 86.5 88.5 92 24 25 15 16 18 19 26 26 28.5 45 Maximum Unit dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm

RX sensitivity 20 MHz channel spacing for all MCS rates (10% PER for 4096 octet MCS 7 71.5 PSDU)a,b. Defined for MCS 6 default parameters: GF, 800 ns GI, and non-STBC. MCS 5 MCS 4 79 MCS 3 MCS 2 MCS 1 MCS0 88 Blocking level for 1dB Rx 776794 MHz CDMA2000 sensitivity degradation d 824849 MHz cdmaOne (without external c 824849 MHz GSM850 filtering) 880915 MHz E-GSM 17101785 MHz GSM1800 18501910 MHz GSM1800 18501910 MHz cdmaOne 18501910 MHz WCDMA 19201980 MHz WCDMA 2500-2690 MHz WiMAX 80 In-band static CW jammer Rx PER < 1%, 54 Mbps immunity OFDM, 1000 octet PSDU for: (RxSens + (fc 8 MHz < fcw + 8 MHz) 23 dB < Rxlevel < max input level) Input In-Band IP3a Maximum LNA gain Minimum LNA gain Maximum Receive Level @ 1, 2 Mbps (8% PER, 1024 octets) 3.5 @ 2.4 GHz @ 5.5, 11 Mbps (8% PER, 1024 octets) 9.5 @ 654 Mbps (10% PER, 1024 octets) 9.5 @ MCS07 rates (10% PER, 4095 octets) 9.5 LPF 3 dB Bandwidth 9 Adjacent channel Desired and interfering signal 30 MHz apart rejection-DSSS 1 Mbps DSSS 74 dBm 35 (Difference between interfering and desired 2 Mbps DSSS 74 dBm 35 signal at 8% PER for 1024 octet PSDU with desired Desired and interfering signal 25 MHz apart signal level as specified in 5.5 Mbps DSSS 70 dBm 35 Condition/Notes) 11 Mbps DSSS 70 dBm 35

15.5 1.5

dBm dBm dBm dBm dBm dBm MHz dB dB dB dB

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WLAN 2.4 GHz Receiver Performance Specifications

Table 34: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Adjacent channel rejection-OFDM (Difference between interfering and desired signal (25 MHz apart) at 10% PER for 1024 octet PSDU with desired signal level as specified in Condition/Notes) Adjacent channel rejection MCS0 7 (Difference between interfering and desired signal (25 MHz apart) at 10% PER for 4096 octet PSDU with desired signal level as specified in Condition/Notes) Condition/Notes 6 Mbps OFDM 79 dBm 9 Mbps OFDM 78 dBm 12 Mbps OFDM 76 dBm 18 Mbps OFDM 74 dBm 24 Mbps OFDM 71 dBm 36 Mbps OFDM 67 dBm 48 Mbps OFDM 63 dBm 54 Mbps OFDM 62 dBm MCS7 61 dBm MCS6 62 dBm MCS5 63 dBm MCS4 67 dBm MCS3 71 dBm MCS2 74 dBm MCS1 76 dBm MCS0 79 dBm Range 98 dBm to 30 dBm Range above 30 dBm Zo = 50, across the dynamic range Minimum Typical 16 15 13 11 8 4 0 1 2 1 0 4 8 11 13 16 5 8 10 105 3 11.5 Maximum Unit 5 8 13 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB

Maximum receiver gain Gain control step RSSI accuracye Return loss

a. Derate by 1.5 dB for 30 C to 10C and 55C to 85C. b. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, SGI: 2 dB drop, and STBC: 0.75 dB drop. c. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. d. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to third harmonic signals (3 824 MHz) falling within band.) e. The minimum and maximum values shown have a 95% confidence level.

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WLAN 2.4 GHz Transmitter Performance Specifications

Note: The specifications in Table 35 are measured at the chip port output, unless otherwise specified.

Table 35: WLAN 2.4 GHz Transmitter Performance Specifications Parameter Frequency range Transmitted power in cellular and FM bands (at 21 dBm, >90% duty cycle, 1 Mbps CCK)a Condition/Notes 76 108 MHz 776 794 MHz 869 960 MHz 925 960 MHz 1570 1580 MHz 1805 1880 MHz 1930 1990 MHz 2110 2170 MHz 2.5 to 3.6 GHz 2.5 to 3.6 GHz Harmonic level (at 18 dBm 4.8 5.0 GHz with 100% duty cycle) 7.2 7.5 GHz FM Rx cdmaOne, GSM850 E-GSM GPS GSM1800 GSM1900, cdmaOne, WCDMA WCDMA WIMAX CH1 WIMAX CH13 2nd harmonic 3rd harmonic Minimum Typical 2400 149 127 163 163 150 141 138 Maximum Unit 2500 MHz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/ 1 MHz dBm/ 1 MHz dBm dBm dBm dBm dBm dBm dB

129 115 to 142 113 to 145 10 28

EVM Does Not Exceed Tx power for highest power level setting at 25C, VBATT = 3.6V and spectral mask and EVM complianceb, c 802.11b (DSSS/CCK) OFDM, BPSK OFDM, QPSK OFDM, 16-QAM OFDM, 64-QAM (R = 3/4) OFDM, 64-QAM (R = 5/6) Tx power control dynamic range 9 dB 8 dB 13 dB 19 dB 25 dB 28 dB 19 19 19 17.5 16.5 15.5 10 20.5 20 20 19 18 17

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WLAN 2.4 GHz Transmitter Performance Specifications

Table 35: WLAN 2.4 GHz Transmitter Performance Specifications (Cont.) Parameter Closed-loop Tx power variation PSAT algorithm Tx power variation (Additional back-off due to temperature and voltage by the PSAT algorithm. This is in addition to the closedloop Tx power variation.) Carrier suppression Gain control step Return loss Load pull variation for output power, EVM, and Adjacent Channel Power Ratio (ACPR) Condition/Notes Across full temperature and voltage range. Power accuracy of 1.5 dB for 10 20 dBm and 3 dB for 5 10 dBm. VBATT > 3.6V, 30 to 55C. All rates. VBATT > 3.6V, 85C. All rates. VBATT = 2.7V, 30 to 85C. 18, 12, 9, and 6 Mbps, and all CCK rates. VBATT = 2.7V, 30 to 85C. 54, 48, 36, and 24 Mbps, and all 802.11n rates. VBATT = 2.3V, 30 to 85C. All rates. Zo = 50 2:1 EVM degradation Output power variation ACPR-compliant power level Minimum Typical 15 4 0.25 6 3.5 1.5 15 Maximum Unit 1.5 0 1.5 1 1.5 6 dB dB dB dB dB dB dBc dB dB dB dB dBm

a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. b. Derate by 1.5 dB for 30 C to 10C and 55C to 85C. c. Tx power for Ch 1 and Ch 11 is specified by non-volatile memory parameters.

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WLAN 5 GHz Receiver Performance Specifications

Note: The specifications in Table 36 are measured at the chip port input, unless otherwise specified.

Table 36: WLAN 5 GHz Receiver Performance Specifications Parameter Frequency range RX sensitivity (10% PER for 1000 octet PSDU)a Condition/Notes 6 Mbps OFDM 9 Mbps OFDM 12 Mbps OFDM 18 Mbps OFDM 24 Mbps OFDM 36 Mbps OFDM 48 Mbps OFDM 54 Mbps OFDM HT mode MCS 7 (64 QAM, R = 5/6, 20 MHz channel spacing) Minimum Typical Maximum Unit 4900 86.5 85 84 82 81 78 74 71 68 5845 MHz dBm dBm dBm dBm dBm dBm dBm dBm dBm

RX sensitivity (10% PER for 4096 octet PSDU)a Blocking level for 1 dB Rx 776794 MHz CDMA2000 sensitivity degradation 824849 MHz cdmaOne (without external b 824849 MHz GSM850 filtering) 880915 MHz E-GSM 17101785 MHz GSM1800 18501910 MHz GSM1800 18501910 MHz cdmaOne 18501910 MHz WCDMA 19201980 MHz WCDMA 2500-2690 MHz WiMAX a Input in-band IP3 Maximum LNA gain Minimum LNA gain Maximum receive level @ 6, 9, 12 Mbps @ 5.24 GHz @ 18, 24, 36, 48, 54 Mbps LPF 3 dB bandwidth

9.5 14.5 9

19.5 21.5 10 9.5 13.5 13.5 20.5 20.5 20.5 21 15.5 1.5

dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm MHz

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WLAN 5 GHz Receiver Performance Specifications

Table 36: WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit 16 15 13 11 8 4 0 1 2 32 31 29 27 24 20 16 15 14 5 8 10 100 3 14 5 8 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB

Adjacent channel rejection 6 Mbps OFDM 79 dBm (Difference between 9 Mbps OFDM 78 dBm interfering and desired 76 dBm signal (20 MHz apart) at 12 Mbps OFDM 10% PER for 1000 octet 18 Mbps OFDM 74 dBm PSDU with desired signal 24 Mbps OFDM 71 dBm level as specified in 36 Mbps OFDM 67 dBm Condition/Notes) 48 Mbps OFDM 63 dBm 54 Mbps OFDM 62 dBm 65 Mbps OFDM 61 dBm Alternate adjacent 6 Mbps OFDM 78.5 dBm channel rejection 9 Mbps OFDM 77.5 dBm (Difference between 12 Mbps OFDM 75.5 dBm interfering and desired signal (40 MHz apart) at 18 Mbps OFDM 73.5 dBm 10% PER for 1000c octet 70.5 dBm PSDU with desired signal 24 Mbps OFDM 36 Mbps OFDM 66.5 dBm level as specified in Condition/Notes) 48 Mbps OFDM 62.5 dBm 54 Mbps OFDM 61.5 dBm 65 Mbps OFDM 60.5 dBm Maximum receiver gain Gain control step d RSSI accuracy Range 98 dBm to 30 dBm Range above 30 dBm Return loss Zo = 50

a. Derate by 1.5 dB for 30 C to 10C and 55C to 85C. b. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. c. For 65 Mbps, the size is 4096. d. The minimum and maximum values shown have a 95% confidence level.

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WLAN 5 GHz Transmitter Performance Specifications

Note: The specifications in Table 37 are measured at the chip port, unless otherwise specified.

Table 37: WLAN 5 GHz Transmitter Performance Specifications Parameter Condition/Notes FM Rx cdmaOne, GSM850 E-GSM GPS GSM1800 GSM1900, cdmaOne, WCDMA WCDMA BT/WLAN 2nd harmonic Minimum Typical 4900 162 162 162 162 162 162 162 162 162 31 Maximum Unit 5845 MHz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/MHz

Frequency range Transmitted power in 76 108 MHz cellular and FM bands (at 776 794 MHz 18 dBm)a 869 960 MHz 925 960 MHz 1570 1580 MHz 1805 1880 MHz 1930 1990 MHz 2110 2170 MHz 2400 2483 MHz 9.811.570 GHz

Harmonic level (at 17 dBm) Tx power for highest power level setting at 25C, VBATT = 3.6V and spectral mask and EVM complianceb

EVM Does Not Exceed OFDM, BPSK 8 dB OFDM, 64-QAM 25 dB (R = 3/4) OFDM, 64-QAM 28 dB (R = 5/6) Tx power control dynamic range Tx power control resolution Closed loop Tx power Across full temperature and voltage variation at highest power range level setting Carrier suppression Gain control step Return loss Zo = 50 10 0.5 15 16 15 13 0.25 6 2 dBm dBm dBm dB dB dB dBc dB dB

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General Spurious Emissions Specifications

Table 37: WLAN 5 GHz Transmitter Performance Specifications (Cont.) Parameter Condition/Notes EVM degradation Output power variation ACPR-compliant power level EVM degradation Output power variation ACPR-compliant power level Minimum Typical 3.5 1.5 15 3.5 1.5 15 Maximum Unit dB dB dBm dB dB dBm

Load pull variation for 2:1 output power, EVM, and Adjacent Channel Power Ratio (ACPR) 3:1

a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. b. Derate by 1.5 dB for 30 C to 10C and 55C to 85C.

General Spurious Emissions Specifications

Table 38: General Spurious Emissions Specifications Parameter Frequency range Tx Emissions Condition/Notes 30 MHz < f < 1 GHz RBW = 100 kHz 1 GHz < f < 12.75 GHz RBW = 1 MHz 1.8 GHz < f < 1.9 GHz RBW = 1 MHz 5.15 GHz < f < 5.3 RBW = 1 MHz GHz 30 MHz < f < 1 GHz RBW = 100 kHz 1 GHz < f < 12.75 GHz RBW = 1 MHz 1.8 GHz < f < 1.9 GHz RBW = 1 MHz 5.15 GHz < f < 5.3 RBW = 1 MHz GHz Min 2400 Typ 78 68.5a 96 96 Max 2500 62 47 53 53 63 53 53 53 Unit MHz dBm dBm dBm dBm dBm dBm dBm dBm

General Spurious Emissions

Rx/standby Emissions

a. For frequencies other than 3.2 GHz, the emissions value is 96 dBm. The value presented in table is the result of LO leakage at 3.2 GHz.

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Internal Regulator Electrical Specifications

Section 20: Internal Regulator Electrical Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Functional operation is not guaranteed outside of the specification limits provided in this section.

Core Buck Regulator

Table 39: Core Buck Regulator (CBUCK) Specifications Specification Input supply voltage Input supply voltage ramp-up time PWM mode switching frequency PWM output current PWM load regulationb PWM line regulationb Output voltage range (default = 1.5V) Output voltage accuracyc PWM ripple voltage, static loadd Burst mode ripple voltage, static Peak PWM mode efficiencye Burst mode efficiencye Output current limit External input capacitorf External output capacitorf External output inductorf Notes 04.3V 10 mA to a 500 mA load 10 mA to a 500 mA load Programmable, 33.33 mV steps Measured with a 20 MHz bandwidth limit. <30 mA load current, measured with a 20 MHz bandwidth limit. 200 mA load current 5 mA load current CapESR <4 m at 3.2 MHz, 6.3V, X5R, Ceramic, 0603/0402, 20% CapESR <4 m at 3.2 MHz, 6.3V, X5R, Ceramic, 0603/0402, 20% LQM2MPN2R2NG0 2.2 uH 30% DCR = 110 m 25%, ACR <1. Isat = 1A (based on L-30%) Minimum Typical Maximum Units 2.3 40 2.56 1.2 5 80 70 3.2 1.5 7 90 80 700 4.7 4.7 2.2 4.8a 3.84 500 30 10 1.8 5 20 80 V s MHz mA mV mV V % mVpp mVpp % % mA F F H

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LDO3p1

Table 39: Core Buck Regulator (CBUCK) Specifications Specification Start-up time from power down
g

Notes

Minimum Typical Maximum Units 1400 s

a. The max continuous voltage is 4.8V. Voltages up to 5.5V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. VBAT = 2.7 to 4.8V, inductor DCR <137.5 m c. Includes line/load regulation, VBAT = 2.7 to 4.8V, load 0 to 500 mA, inductor DCR <137.5 m d. Max ripple based on VBAT <4.3V, Vout = 1.5V, Fs = 3.2 MHz, 1.5 uH inductor L >1.05 uH, cap + board totalESR <10 m, Cout > 1.9 F e. VBAT<4.3V, inductor DCR <137.5 m, ACR <1 f. Critical CBuck component see Reference [1] on page 19 for details and required characteristics of external PMU components. g. Start-up time is measured with respect to the rising edge of BT_REG_ON, WL_REG_ON, or EXT_SMPS_REQ.

LDO3p1
Table 40: LDO3p1 Specifications Specification Input supply voltage Output current Output voltage range (default = 3.1V) Output voltage accuracyb Drop-out voltage Quiescent current External output capacitor cd External input capacitorc Start-up time from power down LDO turn-on time Notes Programmable, 100 mV steps Includes line/load regulation At maximum load No load SR_VDDBAT2 pin, ceramic, X5R, 0402, ESR 30200 m, 10%, 10V Chip already powered up Minimum Typical 2.3 2.4 5 3.6 3.1 8 2.2 1 Maximum Units 4.8a 80 3.4 5 200 1400 100 V mA V % mV A F F s s

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BCM4330 Preliminary Data Sheet

LDO3p3

LDO3p3
Table 41: LDO3p3 Specifications Specification Input supply voltage Output current Output voltage range (default = 3.3V) Output voltage accuracyb Drop-out voltage Quiescent current External output capacitorcd External input capacitord Start-up time from power-down LDO turn-on time Notes Minimum Typical 3.6 3.3 8 4.7 1 500 Maximum Units 4.8a 80 3.4 5 200 1000 100 V mA V % mV A F F s s

2.3 Programmable, 100 mV steps 2.4 Includes line/load regulation At maximum load No load SR_VDDBAT2 pin, ceramic, X5R, 0402, ESR 30200 m, 10%, 10V Chip already powered up 5

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BCM4330 Preliminary Data Sheet

CLDO

CLDO
Table 42: CLDO Specifications Specification Notes Minimum Typical 1.425 1.075 1.5 1.25 10 1 40 4.7 1 Maximum Units 2.0 1.325 4 200 150 15 3 V V % mV mA A A dB F F

Input supply voltage, Vin Output voltage Programmable in 25 mV steps (default = 1.25V) Output voltage accuracy Includes line/load regulation Vin > Vo + 0.2V Dropout voltage At maximum load Output current Quiescent current Leakage current through CLDO_pu = 0 output transistor Power supply rejection @1 kHz, Vin >1.5V, (PSR) Cout = 4.7 uF a Output capacitor Ceramic, X5R, 0402, ESR: 30200 m, 10%, 10V a External input capacitor Only use an external input capacitor at VDD_LDO if it is not supplied from the CBUCK output. Ceramic, X5R, 0402, ESR 30200 m, 10%, 10V Start-up time From power-down LDO turn-on time Chip already powered up

1400 180

s s

a. See Reference [1] on page 19 for details and required characteristics of external PMU components.

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BCM4330 Preliminary Data Sheet

LNLDO1

LNLDO1
Table 43: LNLDO1 Specificationsa Specification Input Supply Voltage Output Voltage (default = 1.25V) Output Voltage Accuracyb Output Current Dropout Voltage (at max load) Quiescent Current Leakage Current Output Noise PSR External Output Capacitor Start-up time LDO Turn-on Time Notes Programmable in 25 mV steps @ 30 kHz, 60 mA load @ 1 kHz, Vin >1.5V, Cout = 4.7 F Ceramic, X5R, 0402, ESR 30200 m, 10%, 10V Chip already powered up Minimum Typical 1.425 1.10 1.5 1.25 62 0.1 50 4.7 Maximum Units 2.0 1.35 4 300 200 88 10 60 1400 180 V V % mA mV A A nV/rt Hz dB F s s

a. See Reference [1] on page 19 for details and required characteristics of external PMU components. b. Include line/load regulation, Vin >Vo + 0.2V

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BCM4330 Preliminary Data Sheet

System Power Consumption

Section 21: System Power Consumption

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, these values apply for the conditions specified in Table 27: Recommended Operating Conditions and DC Characteristics, on page 119.

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BCM4330 Preliminary Data Sheet

WLAN Current Consumption

Note: All measurements are with the Bluetooth core in reset (Bluetooth and FM are off) while using the WLAN SDIO interface.

WLAN Current Consumption 2.4 GHz Operation

Table 45 shows the WLAN current consumption during 2.4 GHz operation. Table 44: WLAN Current Consumption (Ivbat + Ivio)2.4 GHz Operation WLAN Mode OFF SLEEPb Power Savec,d RX (Listen)e RX (Active)f,g TX CCK (20.5 dBm @ chip)h,i TX OFDM, 54 Mbps (18 dBm @ chip)h,i TX MCS7 (17.5 dBm @ chip)h,i
a

Typical Ivbat + Ivio Total (VBATT = 3.6V, VDDIO = 1.8V, and TA 25C) 10 180 1.25 52 60 310 250 240

Units A A mA mA mA mA mA mA

a. WL_REG_ON = Low, no VDDIO b. Inter-beacon Sleep c. Beacon Interval = 102.4 ms, DTIM = 1, Beacon duration = 1 ms @1 Mbps. Integrated Sleep + wakeup + Beacon Rx current over 1 DTIM interval. d. In WLAN power save mode, the following blocks are powered down: Crystal oscillator, Baseband PLL, AFE, RF PLL, and the WLAN radio. The above blocks are turned on in the required order with sufficient time for them to settle. This sequencing is done by the PMU controller, which controls the settling time for each of the blocks. It also has information to determine the order in which the blocks should be turned on. The settling times and the dependency order are programmable in the PMU controller. The default CLK settling time is set to 8 ms at power-up. It can be reduced after power-up. Typical dynamic current consumption (at 20C) from VBATT = 3.6V when waking up from doze for beacon reception: Sleep mode: 180 A Turn on XO (~3 4 ms earlier): 3 5 mA Turn on BBPLL (~1 ms earlier): 10 mA Run BB on full clock (~1 ms earlier): 28 mA Turn on RFPLL(~1 ms earlier): 35 mA Turn on Radio Listen (~1 ms earlier): 52 mA Beacon reception: 60 mA Back to sleep mode: 180 A e. Carrier sense (CCA) when no carrier present. f. Carrier sense (CS) detect/packet Rx. g. Applicable to all supported rates. h. Duty cycle is 100%. i. Absolute junction temperature limits are maintained through active thermal monitoring and dynamic Tx duty cycle limiting.

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BCM4330 Preliminary Data Sheet

WLAN Current Consumption

WLAN Current Consumption 5 GHz Operation

Table 45 shows the WLAN current consumption during 5 GHz operation. Table 45: WLAN Current Consumption (Ivbat + Ivio) 5 GHz Operation WLAN Mode OFF SLEEPb Power Savec RX (Listen)d RX (Active)e,f TX OFDM, 54 Mbps (15 dBm @ chip)g,h TX MCS7 (13 dBm @ chip)h,i
a

Typical Ivbat + Ivio Total (VBATT = 3.6V, VDDIO = 1.8V, and TA = 25C) 10 180 1.25 68 75 265 235

Units A A mA mA mA mA mA

a. WL_REG_ON = Low, no VDDIO b. Inter-beacon Sleep c. Beacon Interval = 102.4 ms, DTIM = 1, Beacon duration = 1 ms @1 Mbps. Integrated Sleep + wakeup + Beacon Rx current over 1 DTIM interval. d. Carrier sense (CCA) when no carrier present. e. Carrier sense (CS) detect/packet receive. f. Applicable to all supported rates. g. Duty cycle is 100%. h. Absolute junction temperature limits are maintained through active thermal monitoring and dynamic Tx duty cycle limiting.

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BCM4330 Preliminary Data Sheet

HSIC Interface Current Consumption

The HSIC interface current consumption measurements are shown in Table 46. Table 46: HSIC Interface Current Consumption State Standby Active, Idle Active, Worst case pattern Typical Current in mA (AVDD+DVDD @ 1.2V) 0.012 10.12 18.22

Bluetooth and FM Current Consumption

The Bluetooth and FM current consumption measurements are shown in Table 47. Note: The WLAN core is in reset (WLAN_RST_N = low) for all measurements provided in Table 47.

Note: For FM measurements, the Bluetooth core is in sleep mode. The current consumption numbers are measured based on the typical output power as specified in Table 29 on page 123.

Table 47: Bluetooth and FM Current Consumption Operating Mode Sleep Standard 1.28s Inquiry Scan 3DH5/3DH1 Master 3DH5/3DH1 Slave HV3 + Sniff + Scana P & I Scanb 500 ms Sniff Master 500 ms Sniff Slave DM1/DH1 Master DM3/DH3 Master DM5/DH5 Master FMRX I2S Audio FMRX Analog Audio VBATT (VBATT = 3.6V) Typical 0.14 0.34 24.8 24.8 14.2 529 0.24 0.24 32 40 41 14.7 15.3 VDDIO (VDDIO = 1.8V) Typical 0.15 5 Units mA mA mA mA mA A mA mA mA mA mA mA mA

a. At maximum class 1 TX power, 500 ms sniff, four attempts (slave), P = 1.28s, and I = 2.56s. b. 1.28s page/inquiry scan interval.

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BCM4330 Preliminary Data Sheet

Interface Timing and AC Characteristics

Section 22: Interface T iming and AC Characteristics

SDIO/gSPI Timing
SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 44 and Table 48 on page 153.
fPP tWL tWH

SDIO_CLK

tTHL tISU Input

tTLH tIH

Output tODLY
(max)

tODLY
(min)

Figure 44: SDIO Bus Timing (Default Mode)

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BCM4330 Preliminary Data Sheet

SDIO/gSPI Timing

Table 48: SDIO Bus Timinga Parameters (Default Mode) Parameter Frequency Data Transfer mode Frequency Identification mode Clock low time Clock high time Clock rise time Clock low time Inputs: CMD, DAT (referenced to CLK) Input setup time Input hold time Outputs: CMD, DAT (referenced to CLK) Output delay time Data Transfer mode Output delay time Identification mode tODLY tODLY 0 0 14 50 ns ns tISU tIH 5 5 ns ns Symbol fPP fOD tWL tWH tTLH tTHL Minimum Typical 0 0 10 10 Maximum Unit 25 400 10 10 MHz kHz ns ns ns ns

SDIO CLK (All values are referred to minimum VIH and maximum VILb)

a. Timing is based on CL 40pF load on CMD and Data. b. min(Vih) = 0.7 VDDIO and max(Vil) = 0.2 VDDIO.

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BCM4330 Preliminary Data Sheet

SDIO/gSPI Timing

SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 45 and Table 49.
fPP tWL
50% VDD

tWH

SDIO_CLK tTHL tISU Input tTLH tIH

Output tODLY tOH

Figure 45: SDIO Bus Timing (High-Speed Mode) Table 49: SDIO Bus Timinga Parameters (High-Speed Mode) Parameter Frequency Data Transfer Mode Frequency Identification Mode Clock low time Clock high time Clock rise time Clock low time Inputs: CMD, DAT (referenced to CLK) Input setup Time Input hold Time Outputs: CMD, DAT (referenced to CLK) Output delay time Data Transfer Mode Output hold time Total system capacitance (each line) tODLY tOH CL 2.5 14 40 ns ns pF tISU tIH 6 2 ns ns Symbol fPP fOD tWL tWH tTLH tTHL Minimum Typical 0 0 7 7 Maximum Unit 50 400 3 3 MHz kHz ns ns ns ns

SDIO CLK (all values are referred to minimum VIH and maximum VILb)

a. Timing is based on CL 40pF load on CMD and Data. b. min(Vih) = 0.7 VDDIO and max(Vil) = 0.2 VDDIO.

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BCM4330 Preliminary Data Sheet

SDIO/gSPI Timing

gSPI Signal Timing

The gSPI host and device always use the rising edge of clock to sample data.

T1
T4 T5

SPI_CLK

SPI_DIN
T8 T9

SPI_DOUT (falling edge)

Figure 46: gSPI Timing Table 50: gSPI Timing Parameters Parameter Clock period Clock high/low Symbol T1 T2/T3 Minimum 20.8 (0.45 T1) T4 5.0 5.0 5.0 5.0 7.86 Maximum (0.55 T1) T4 2.5 Units Note ns ns ns ns ns ns ns ns ns Fmax = 48 MHz Setup time, SIMO valid to SPI_CLK active edge Hold time, SPI_CLK active edge to SIMO invalid Setup time, SOMI valid before SPI_CLK rising Hold time, SPI_CLK active edge to SOMI invalid CSX fall to 1st rising edge Last falling edge to CSX high

Clock rise/fall time T4/T5 Input setup time T6 Input hold time T7

Output setup time T8 Output hold time T9 CSX to clocka Clock to CSXa

a. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (i.e., overall words for multiple word transaction)

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BCM4330 Preliminary Data Sheet

HSIC Interface Specifications

Table 51: HSIC Interface Specifications Parameter HSIC supply voltage I/O voltage input low I/O Voltage input high I/O voltage output low I/O voltage output high I/O pad drive strength I/O weak keepers (PU) I/O weak keepers (PD)a I/O input impedance Total capacitive loadb Characteristic trace impedance Circuit board trace length Circuit board trace propagation skewc STROBE frequencyd Slew rate (rise and fall) STROBE and DATAd Receiver data setup time (with respect to STROBE)d Receiver data hold time (with respect to STROBE)d Symbol VDD VIL VIH VOL VOH OD Rku Rkd ZI CL TI TL TS FSTROBE Tslew Ts Tb Minimum 1.1 0.3 0.65 0.75 VDD 40 1 3 45 239.988 0.60 VDD 300 300 Typical 1.2 3.5 35 50 240 1.0 Maximum 1.3 0.35 VDD VDD + 0.3 0.25 VDD 60 14 55 10 15 240.012 1.2 Unit V V V V V k k M pF cm ps MHz V/ns ps ps Comments Controlled output impedance driver 500 ppm Averaged from 30% ~ 70% points Measured at the 50% point Measured at the 50% point

a. The HSIC interface comes up by default with weak bus keepers on both the data and strobe to pull the bus down before discovery. This ensures that the bus does not float during the discovery stage. b. Total Capacitive Load (CL), includes device Input/Output capacitance, and capacitance of a 50 PCB trace with a length of 10 cm. c. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be matched between STROBE and DATA to ensure that the signal timing is within specification limits at the receiver. d. Jitter and duty cycle are not separately specified parameters, they are incorporated into the values in the table above.

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BCM4330 Preliminary Data Sheet

JTAG Timing

JTAG Timing
Table 52: JTAG Timing Characteristics Signal Name TCK TDI TMS TDO JTAG_TRST Period 125 ns 250 ns Output Maximum 100 ns Output Minimum 0 ns Setup 20 ns 20 ns Hold 0 ns 0 ns

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BCM4330 Preliminary Data Sheet

Power-Up Sequence and Timing

Section 23: Power-Up Sequence and T iming

Sequencing of Reset and Regulator Control Signals
The BCM4330 has three signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 47 on page 159, Figure 48 on page 160, Figure 49 on page 160 and Figure 50 on page 161). The timing values indicated are the minimum required values; longer delays are also acceptable. Note: The WL_REG_ON and BT_REG_ON signals are ORed in the BCM4330. The diagrams show both signals going high at the same time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are used (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the BCM4330 regulators. Also note that the reset requirements for the Bluetooth core are also applicable for the FM core. In other words, if FM is to be used, then the Bluetooth core must be enabled. Note: The BCM4330 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the 0.6V threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses. The external reset signals are logically ORed with this POR. So if either the internal POR or one of the external resets is asserted, the device will be in reset. If VDDIO goes LOW, all regulators (including bandgap reference) will be powered OFF immediately, regardless of the status of the WL_REG_ON, BT_REG_ON, and EXT_SMPS_REQ pins.

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BCM4330 Preliminary Data Sheet

Sequencing of Reset and Regulator Control Signals

Description of Control Signals

WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM4330 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. A warm WLAN reset can be initiated by driving WL_REG_ON low for at least 10 microseconds (see Figure 51 on page 161). If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. Logic High Level: 1.08V 3.6V. 200k pull-down resistor included. BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM4330 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. Logic High Level: 1.08V3.6V. 200k pull-down resistor included. BT_RST_N: Low asserting reset for Bluetooth and FM only. This pin has no effect on WLAN and does not control any PMU functions. This pin must be driven high or low (not left floating). In addition, two other input signals control PMU modes: When EXT_SMPS_REQ is pulled high, it forces CBUCK to stay on, even when the other regulators are shut down by WL_REG_ON or BT_REG_ON. When WLAN and/or Bluetooth are out of reset and EXT_SMPS_REQ is high, then pulling EXT_PWM_REQ high makes CBUCK go into PWM mode, even if internal settings from WLAN and/or Bluetooth are requesting burst mode. During such contention, the request for the higher-power mode wins.

Control Signal Timing Diagrams

32.678 kHz Sleep Clock

VBAT

90% of VH

VDDIO ~ 2 Sleep cycles WL_REG_ON

BT_REG_ON

BT_RST_N

Figure 47: WLAN = ON, Bluetooth = ON

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BCM4330 Preliminary Data Sheet

Sequencing of Reset and Regulator Control Signals

32.678 kHz Sleep Clock

VBAT

VDDIO

WL_REG_ON BT_REG_ON BT_RST_N

Figure 48: WLAN = OFF, Bluetooth = OFF

32.678 kHz Sleep Clock

VBAT

90% of VH

VDDIO ~ 2 Sleep cycles WL_REG_ON

BT_REG_ON BT_RST_N

Figure 49: WLAN = ON, Bluetooth = OFF

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BCM4330 Preliminary Data Sheet

Sequencing of Reset and Regulator Control Signals

32.678 kHz Sleep Clock

VBAT

90% of VH

VDDIO ~ 2 Sleep cycles WL_REG_ON

BT_REG_ON

BT_RST_N

Figure 50: WLAN = OFF, Bluetooth = ON

32.678 kHz Sleep Clock

VBAT

90% of VH

VDDIO
10 s min

~ 2 Sleep cycles WL_REG_ON

BT_REG_ON

Figure 51: WLAN Warm Reset

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BCM4330 Preliminary Data Sheet

Package Information

Section 24: Package Information

Package Thermal Characteristics
Table 53: Package Thermal Characteristicsa Characteristic JA (C/W) (value in still air) JB (C/W) JC (C/W) JT (C/W) JB (C/W) Maximum Junction Temperature TJ Maximum Power Dissipation (W) FCFBGA 39.07 12.31 13.03 4.55 19.28 125C 1.43 WLBGA 33.73 2.44 0.61 2.68 11.10 125C 1.43 WLSCP 33.24 2.06 0.69 2.09 10.85 125C 1.43

a. No heat sink, TA = 70C. This is an estimate, based on a 2- or 4-layer PCB that conforms to EIA/JESD51 7 (101.6 mm x 114.3 mm x 1.6 mm) and P = 1.43W continuous dissipation.

Junction Temperature Estimation and PSIJT Versus THETAJC

Package thermal characterization parameter PSIJT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter ThetaJC (JC). The reason for this is that JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is: TJ = TT + P x JT Where: TJ = Junction temperature at steady-state condition (C) TT = Package case top center temperature at steady-state condition (C) P = Device power dissipation (Watts) JT = Package thermal characteristics; no airflow (C/W)

Environmental Characteristics
For environmental characteristics data, see Table 25: Environmental Ratings, on page 118.

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BCM4330 Preliminary Data Sheet

Mechanical Information

Section 25: Mechanical Information

Figure 55 shows the PCB keep-out areas of the BCM4330 WLCSP package. There should not be any metal in the areas indicated in red on the top PCB layer.

Figure 55: WLCSP Package Keep-outs

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BCM4330 Preliminary Data Sheet

Ordering Information

Section 26: Ordering Information

Table 54: Ordering Information Operating Ambient Temp

Part Number BCM4330FB2KFFBG BCM4330FKUBG BCM4330SB2KUBG BCM4330FKWBG BCM4330GKUBG BCM4330XB2KFFBG BCM4330XKUBG BCM4330HB2KUBG BCM4330XKWBG

Package 144 ball FCFBGA (6.5 mm x 6.5 mm, 0.5 mm pitch) 133 ball WLBGA (4.89 mm x 5.33 mm, 0.4 mm pitch) 133 ball WLBGA + BSP (4.89 mm x 5.33 mm, 0.4 mm pitch) 225 bump WLCSP (4.89 mm x 5.33 mm, 0.2 mm pitch) 133 ball WLBGA (4.89 mm x 5.33 mm, 0.4 mm pitch) 144 ball FCFBGA (6.5 mm x 6.5 mm, 0.5 mm pitch) 133 ball WLBGA (4.89 mm x 5.33 mm, 0.4 mm pitch) 133 ball WLBGA + BSP (4.89 mm x 5.33 mm, 0.4 mm pitch) 225 bump WLCSP (4.89 mm x 5.33 mm, 0.2 mm pitch)

Description Single-band WLAN + BT 4.0 + FM RX

30C to +85C Single-band WLAN + BT 4.0 + FM RX 30C to +85C Single-band WLAN + BT 4.0 30C to +85C Single-band WLAN + BT 4.0 + FM RX 30C to +85C Single-band WLAN + BT 4.0 30C to +85C Dual-band WLAN + BT 4.0 + FM 30C to +85C Dual-band WLAN + BT 4.0 + FM 30C to +85C Dual-band WLAN + BT 4.0 + FM 30C to +85C Dual-band WLAN + BT 4.0 + FM 30C to +85C

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BCM4330 Preliminary Data Sheet

Broadcom Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

Phone: 949-926-5000 Fax: 949-926-5203 E-mail: [email protected] Web: www.broadcom.com

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