DEPARTMENT OF ELECTRICAL & ELECTRONIC ENGINEERING BANGLADESH UNIVERSITY OF ENGINEERING & TECHNOLOGY COURSE NO.

: EEE 210 EXPERIMENT NO. 03

Nam !" #$ E%& '(m )#: STUDY OF CASCADED AND FEEDBAC* AMPLIFIER CIRCUITS USING B+T.

OB+ECTIVE
The objective of this experiment is to simulate and observe the characteristics of the following amplifier circuits using BJTs A two-stage cascaded amplifier. Feedbac Amplifiers !oltage-series feedbac amplifier. !oltage-shunt feedbac amplifier. "urrent-series feedbac amplifier. "urrent-shunt feedbac amplifier.

CASCADE AMPLIFIER
Amplifiers are cascaded when the output of the first is the input to the second. The combined gain is

where vi2 = vo1. The total gain is the product of the cascaded amplifier stages. The complication in calculating the gain of cascaded stages is the non-ideal coupling between stages due to loading. Two cascaded CE stages are shown below.

Because the input resistance of the second stage forms a voltage divider with the output resistance of the first stage the total gain is not the product of the individual !separated" stages. The total voltage gain can be calculated in either of two wa#s. $irst wa#% the gain of the first stage is calculated including the loading of ri2. Then the second-stage gain is calculated from the output of the first stage. Because the loading !output divider" was accounted for in the first-stage gain the second-stage gain input &uantit# is the Q2 base voltage vB2 = vo1. 'econd wa#% the first-stage gain is found b# disconnecting the input of the second stage thereb# eliminating output loading. Then the Thevenine&uivalent output of the first stage is connected to the input of the second
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stage and its gain is calculated including the input divider formed b# the first-stage output resistance and second-stage input resistance. (n this case the first-stage gain output &uantit# is the Thevenin-e&uivalent voltage not the actual collector voltage of the stage-connected amplifier. The second wa# includes interstage loading as an input divider in the gain of the second stage while the first wa# includes it as an output divider in the gain of the first stage. B# cascading a CE stage followed b# an emitter-follower !CC" stage a good voltage amplifier results. The CE input resistance is high and CC output resistance is low. The CC contributes no increase in voltage gain but provides a near voltage-source !low resistance" output so that the gain is nearl# independent of load resistance. The high input resistance of the CE stage ma)es the input voltage nearl# independent of input-source resistance. *ultiple CE stages can be cascaded and CC stages inserted between them to reduce attenuation due to inter-stage loading.

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PROCEDURE
Ca,-a. . Am&/("( '

4 -

3cc 123

+1 5..,)

+c1 ,.,) /1

C2 -.u$ /20,12Ce1 -.u$

+, 5..,)

+c2 ,.,) /2 +C, -.u$ /20,12Ce2 -.u$ +6 ,.,)

+s 152
4 -

C1 -.u$ +2 22)

3in 1m3

+e1 2.2)

22)

+e2 2.2)

F(0.0.

C('-1(# "!' Sma// ,(0)a/ a)a/2,(, 1,()0 B+T

$.$.

)raw the circuit shown in Fig. $ in #*pice schematics.

$.&. +ere, !in is variable fre-uenc. A" source /+aving Pa'# Nam of VAC0. *et its amplitude to $ m!, eeping other parameters /e.g. !dc0 to 1ero value. $.'. *elect A" *weep from S #1& A)a/2,(,. *elect sweep from $2 +1 to $ 3+1 /or higher or lower, ensuring that .ou observe both the cut-off fre-uencies0 in )ecade mode, with &2 #ts4decade. $.(. 5un the simulation. $.6. 7bserve the voltage gain /A!8vo4vi0 and phase shift between vo and vi at different fre-uencies. $.9. $.;. :ormali1e the voltage gain A!:8A!4A!max #lot the voltage gain /in dB0 vs. fre-uenc. /f0 <A!dB8&2log$2/A!:0=

$.>. )etermine the -'dB /cut-off0 fre-uencies from the plot. Also note the phase difference between vo and vi at ?'dB fre-uencies. $.%. At mid-band fre-uenc., note the voltage gain /A !0, current gain /A@0, input resistance /5i0 and output resistance /5o0 of the configuration. $.$2. Find the h- parameters of the given "A configuration using the data ta en in step %. $.$$. "ompare the results with that of *ingle-stage amplifier studied in previous simulation. Also compare the gain-bandwidth product /BB0 of single-stage and cascaded amplifiers. /BB8BCDA!, where BC8f+"-fE" F A! 8vo4vi0

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FEEDBAC* AMPLIFIERS
Voltage-Series Feedback

4 3cc -

123

+1 5..,)

+c1 ,.,) /1

C2 -.u$ /20,12Ce1 -.u$ +6 ,.,)

+s 152
41m3

C1 -.u$ +2 22)

3in

+e1 2.2) +f 122

F(0.1.

V!/#a0 3, '( , " .4a-5 am&/("( '

&.$.

)raw the circuit shown in Fig. & in #*pice schematics.

&.&. +ere, !in is variable fre-uenc. A" source /+aving Pa'# Nam of VAC0. *et its amplitude to $ m!, eeping other parameters /e.g. !dc0 to 1ero value. &.'. *elect A" *weep from S #1& A)a/2,(,. *elect sweep from $2 +1 to $ 3+1 /or higher or lower, ensuring that .ou observe both the cut-off fre-uencies0 in )ecade mode, with &2 #ts4decade. &.(. &.6. 5un the simulation. 7bserve the voltage gain /A!8vo4vi0 at different fre-uencies.

&.9. At mid-band fre-uenc., note the voltage gain /A!0, current gain /A@0, input resistance /5i0 and output resistance /5o0 of the configuration. &.;. "ompare the results with that of single stage amplifier /without feedbac 0 studied in previous simulation. +ence, find the desensitivit. /)0 of the amplifier. &.>. !erif. the values measured in step 9, with theoretical values obtained from without feedbac single-stage amplifiers preserved values modified using ). <see theor. for details=

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Current-Series Feedback

4 3cc -

123

+1 5..,)

+c1 ,.,) /1

C2 -.u$ /20,12Ce1 -.u$ +6 ,.,)

+s 152
41m3

C1 -.u$ +2 22)

3in

+e1 2.1) +f 122

F(0.2.

C1'' )#3, '( , " .4a-5 am&/("( '

'.$.

)raw the circuit shown in Fig. & in #*pice schematics.

'.&. +ere, !in is variable fre-uenc. A" source /+aving Pa'# Nam of VAC0. *et its amplitude to $ m!, eeping other parameters /e.g. !dc0 to 1ero value. '.'. *elect A" *weep from S #1& A)a/2,(,. *elect sweep from $2 +1 to $ 3+1 /or higher or lower, ensuring that .ou observe both the cut-off fre-uencies0 in )ecade mode, with &2 #ts4decade. '.(. '.6. 5un the simulation. 7bserve the voltage gain /A!8vo4vi0 at different fre-uencies.

'.9. At mid-band fre-uenc., note the voltage gain /A !0, current gain /A@0, input resistance /5i0 and output resistance /5o0 of the configuration. '.;. "ompare the results with that of single stage amplifier /without feedbac 0 studied in previous simulation. +ence, find the desensitivit. /)0 of the amplifier. '.>. !erif. the values measured in step 9, with theoretical values obtained from without feedbac single-stage amplifiers preserved values modified using ). <see theor. for details=

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Voltage-Shunt Feedback

F(0.3.

V!/#a0 3,$1)# " .4a-5 am&/("( '

(.$.

)raw the circuit shown in Fig. & in #*pice schematics.

(.&. +ere, !in is variable fre-uenc. A" source /+aving Pa'# Nam of VAC0. *et its amplitude to $ m!, eeping other parameters /e.g. !dc0 to 1ero value. (.'. *elect A" *weep from S #1& A)a/2,(,. *elect sweep from $2 +1 to $ 3+1 /or higher or lower, ensuring that .ou observe both the cut-off fre-uencies0 in )ecade mode, with &2 #ts4decade. (.(. (.6. 5un the simulation. 7bserve the voltage gain /A!8vo4vi0 at different fre-uencies.

(.9. At mid-band fre-uenc., note the voltage gain /A !0, current gain /A@0, input resistance /5i0 and output resistance /5o0 of the configuration. (.;. "ompare the results with that of single stage amplifier /without feedbac 0 studied in previous simulation. +ence, find the desensitivit. /)0 of the amplifier. (.>. !erif. the values measured in step 9, with theoretical values obtained from without feedbac single-stage amplifiers preserved values modified using ). <see theor. for details=

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Current-Shunt Feedback

4 -

3cc 123

+1 5..,)

+c1 ,.,) /1

C2 -.u$ /20,12Ce1 -.u$

+, 5..,)

+c2 ,.,) /2 +C, -.u$ /20,12Cf -.u$ +6 ,.,)

+s 152
4 -

C1 -.u$ +2 22)

3in 1m3

+e1 2.2)

22)

+e2 2.2) +f 257

F(0.6.

C1'' )#3,$1)# " .4a-5 am&/("( '

6.$.

)raw the circuit shown in Fig. & in #*pice schematics.

6.&. +ere, !in is variable fre-uenc. A" source /+aving Pa'# Nam of VAC0. *et its amplitude to $ m!, eeping other parameters /e.g. !dc0 to 1ero value. 6.'. *elect A" *weep from S #1& A)a/2,(,. *elect sweep from $2 +1 to $ 3+1 /or higher or lower, ensuring that .ou observe both the cut-off fre-uencies0 in )ecade mode, with &2 #ts4decade. 6.(. 6.6. 5un the simulation. 7bserve the voltage gain /A!8vo4vi0 at different fre-uencies.

6.9. At mid-band fre-uenc., note the voltage gain /A !0, current gain /A@0, input resistance /5i0 and output resistance /5o0 of the configuration. 6.;. "ompare the results with that of single stage amplifier /without feedbac 0 studied in previous simulation. +ence, find the desensitivit. /)0 of the amplifier. 6.>. !erif. the values measured in step 9, with theoretical values obtained from without feedbac single-stage amplifiers preserved values modified using ). <see theor. for details=

Prepared by : Yeasir Arafat, Ahmad Ehteshamul Islam, Shaikh Asif Mahmood

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