Design Ideas
Design Ideas
+
+
VOLTAGE DOUBLER
1N914
V+
IC
2
MAX338
CS
Fi gure 1
Make eight-channel measurements
through an LPT port
J Jayapandian, IGCAR, Tamil Nadu, India
You can obtain eight-channel analog measurements through a PCs LPT port.
Fi gure 2
This front-panel view represents a LabView
Virtual Instrument for an eight-channel ADC.
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
98 edn | June 13, 2002 www.ednmag.com
ideas
design
position of the word; hence, the data re-
ceived through the fourth bit, D3, must
shift left through seven positions to be as-
signed as an 11th bit, and so on. In this
sequence of data structuring, once the
fourth bit (LSB 4) of the 12-bit pattern
appears, it needs no shifting, because it is
an actual D3 bit. The third bit, D2, re-
quires shifting in the right position by
one, and the D1 and D0 bits need right-
shifting by two and three, respectively.
This method of shifting and finally per-
forming a logical-OR operation delivers
the exact 12-bit data pattern from the se-
rial data received through one line of the
parallel port.
D0 through D3 bits in the Data port
(0x378) enable the channel selection. For
each channel selection, the cited se-
quence of acquiring the data and condi-
tioning it provides eight independent
digital readouts. The downloadable Lab-
View Virtual Instrument program (new-
multi_MAX187.vi) is a self-explanatory
graphics program for the data-acquisi-
tion process. In the program, a time de-
lay of 125 sec between SCLK and the se-
rial-data read sets the data-transfer rate
at 4 kHz. This time delay allows the read
cycle to read exactly at the midpoint of
the data bit to avoid improper data reads.
You can reduce the time delay for faster
data acquisition. Figure 2 shows the
front-panel view of the LabView Virtual
Instrument.
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Eliminate thermoelectric EMF
in low-ohm measurements
John Wynne, Analog Devices, Limerick, Ireland
W
hen two different-metal con-
ductors connect together
in a loop and one of the
junctions is at a higher temperature than
the other, an electrical current flows
through the loop. The magnitude of this
current depends on the type of metals in-
volved and the temperature differential
of the junctions. When you open such a
loop, a thermoelectric voltage appears
across the open ends. Again, the phe-
nomenon depends on the type of metals
involved and the temperature differential
of the junctions. The junction of the two
metals forms a thermocouple, so the
thermoelectric voltage is a thermocouple
voltage.
When you try to measure small volt-
ages or low impedances, thermal EMFs
(electromagnetic fields) are likely to
cause errors in the readings. A standard
way that digital-multimeter manufactur-
ers deal with the problem is to initially
take one reading and then to reverse the
excitation and take a second reading. Re-
versing the current excitation through a
low-value resistor or thermocouple junc-
tion reverses the polarity of the desired
signal but does not affect the polarity of
the unwanted EMF voltages. Subse-
quently averaging the two readings elim-
inates the thermoelectric EMFs from the
final result (Reference 1). Figure 1 shows
IC
1
, an AD7719 ADC measuring a low-
value resistor, R
LOW
. The diagram also
shows two thermoelectric EMFs, EMF
1
and EMF
2
, representing summations of
all the thermoelectric EMFs on the way
from and to the ADC and the resistor.
These EMFs would normally cause an er-
ror if you were to take a single measure-
ment of R
LOW
.
However, you can program each of the
AD7719s two current sources, I
EXC1
and
I
EXC2
, to appear at either of the package
pins, I
OUT1
and I
OUT2
. This feature allows
you to reverse the excitation current
EMF
1
EMF
2
R
LOW
Q
1
Q
2
A A
R
REF
ADR420
REFIN1()
A
IN4
A
IN3
A
IN2
A
IN1
I
OUT2
I
OUT1
REFIN1(+)
MULTI-
PLEXER
I
EXC2
I
EXC1
A
VDD
IC
1
BUFFER
AND
PROGRAMMABLE-
GAIN
AMPLIFIER
PHASE 1
CURRENT FLOW
AD7719
AGND
Fi gure 1
In this configuration, the excitation current flows in R
LOW
from top to bottom.
through the low-value resistor. You can
thus take two measurements and
eliminate the effects of EMF
1
and
EMF
2
. To increase the excitation current
and thereby increase the measurement
sensitivity, the two internal 200-A ex-
citation currents appear in parallel with
each other. Thus, a single 400-A current
source makes up the excitation current,
I
EXC
, in this design. Transistors Q
1
and Q
2
steer the excitation current through the
reference resistor, R
REF
, to ensure that the
same polarity reference voltage always
appears, regardless of the excitation-cur-
rent direction. Port pins P1 and P2 (not
shown) of the AD7719 drive the transis-
tors in antiphase mode. A value of 6.8 k
for R
REF
is suitable and ensures a typical
ratiometric reference voltage of 2.5V.
Figures 1 and 2 show the current flow
in each phase of a measurement. During
Phase 1, the excitation current flows out
of I
OUT1
, through R
LOW
, and through R
REF
via Q
2
to ground. During Phase 2, the ex-
citation current flows from I
OUT2
,
through R
LOW
, and through R
REF
via Q
1
to
ground. During Phase 1, V
DIFF(PHASE1)
V
AIN1
V
AIN2
V
EMF1
V
EMF2
(I
EXC
)(R
LOW
).
You now switch the current sources. Dur-
ing Phase 2, V
DIFF(PHASE2)
V
AIN1
V
AIN2
V
EMF1
V
EMF2
(I
EXC
)(R
LOW
). You
now combine the two measurements in
software to cancel the thermoelectric
EMFs: V
DIFF
V
DIFF(PHASE1)
V
DIFF(PHASE2)
(I
EXC
)(R
LOW
).
Finally, you need to turn this ratio-
metric measurement into an absolute
one. You achieve this result by measuring
a known voltage using the unknownra-
tiometric reference voltage. Taking a
reading of this known voltage but with
an unknown reference allows you to in-
fer the unknown reference value and,
hence, the absolute value of V
DIFF
on pins
A
IN1
and A
IN2
. An absolute voltage refer-
ence, such as an ADR420, supplying
2.048V output, provides the known volt-
age. It connects to the second pair of dif-
ferential inputs, A
IN3
and A
IN4
, and into
the main 24-bit ADC channel.
Reference
1. Low Level Measurements, Fifth Edi-
tion, Keithley.
100 edn | June 13, 2002 www.ednmag.com
ideas
design
EMF
1
EMF
2
R
LOW
Q
1
Q
2
A A
R
REF
ADR420
REFIN1()
A
IN4
A
IN3
A
IN2
A
IN1
I
OUT2
I
OUT1
REFIN1(+)
MULTI-
PLEXER
I
EXC2
I
EXC1
A
VDD
IC
1
BUFFER
AND
PROGRAMMABLE-
GAIN
AMPLIFIER
PHASE 2
CURRENT FLOW
AD7719
AGND
Fi gure 2
In this configuration, the excitation current reverses, and flows from the bottom of R
LOW
to the top.
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102 edn | June 13, 2002 www.ednmag.com
ideas
design
Y
ou can use the parallel port of your
PC and a few additional
components to generate a
powerful, easy-to-use arbitrary-wave-
form generator. By using a Visual Basic
program with the circuit in Figure 1, you
can generate any waveform (for example,
sinusoid, triangle, amplitude- or fre-
quency-modulated, or exponential de-
cay) by simply entering its characteristic
equation. For this circuit, the parallel port
connects to four latches (IC
1
, IC
2
, IC
5
, and
IC
6
). IC
5
provides control signals, IC
1
and
IC
6
transfer data to the memory, and IC
2
controls a VFC (voltage-to-frequency)
converter. During the load-waveform op-
eration, the waveform data transfers from
the parallel port via latches IC
1
and IC
6
to
the memory chips IC
7
and IC
10
. The bi-
nary counter, IC
9
, increments the mem-
ory addresses in sequence to allow load-
ing each memory location with a unique
16-bit binary word. Each binary word
corresponds to a waveform data point.
During the load-waveform operation, the
memorys configuration allows writing
information to it (for example, ~OE1,
~WE0).
During the output-waveform opera-
tion, latches IC
1
and IC
6
disconnect from
the bus, and the memory delivers the
stored data (for example, ~OE0,
~WE1). For each accessed location,
one of the binary words stored during the
load-waveform operation transfers to
IC
8
, a DAC7621. This transfer causes the
DAC to deliver one output point in the
waveform. The VFC causes IC
9
to clock
through all possible addresses. IC
11
resets
the counter when the memory sequences
through all possible addresses. When IC
9
resets to zero, the waveform begins to re-
peat itself. Thus, each waveform com-
prises 2048 data points. The number of
points, N, and the clock frequency, C,
control the frequency of the arbitrary
waveform: f
AWG
1/NT
C
, where T
C
is the
period of the clock frequency.
IC
2
, IC
3
, and IC
4
form a circuit that ad-
justs the clock frequency, C, via the par-
Parallel port controls
arbitrary-waveform generator
Art Kay, Texas Instruments Inc, Tucson, AZ
With the aid of some Visual Basic software and a few ICs, a computers parallel port forms an
effective arbitrary-waveform generator.
1
2
2
1D
2D
3D
4D
5D
6D
7D
8D
CK
OC
5
6
9
12
15
16
19
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BIT 8
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 10
BIT 9
BIT 10
BIT 11
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
11
1
3
4
7
8
13
14
17
18
11
1
74HC374N
IC
5
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
74HC374N
IC
6
1D
2D
3D
4D
5D
6D
7D
8D
CK
OC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
9
7
6
5
3
2
4
13
12
14
15
1
IC
9
F
OUT
IC
11
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 10
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
11
1
74HC374N
IC
1
1D
2D
3D
4D
5D
6D
7D
8D
CK
OC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
9
10
11
13
14
15
16
17
8
7
6
5
4
3
2
1
23
22
19
18
20
21
DS122OAB100
IC
7
C
5
,
WE
OE
CE
D0
D1
D2
D3
D4
D5
D6
D7
0.1 F
24
5V
50V, 10%
VCC
GND
CT5
CT6
CT7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
9
10
11
13
14
15
16
17
8
7
6
5
4
3
2
1
23
22
19
18
20
21
DS122OAB100
IC
10
C
9
,
WE
OE
CE
D0
D1
D2
D3
D4
D5
D6
D7
0.1 F
24
12
12
5V
50V, 10%
VCC
GND
CT5
CT6
CT7
IC
11
IC
11
CLK
RST
1 10
IC
11
2
2
3
5
6
11
11
12
10
13
9
8
74HC02N
74HC02N
74HC02N 74HC02N
DB25M
DGND
DGND
DGND
Fi gure 1
(text continued on pg 104)
www.ednmag.com June 13, 2002 | edn 103
Depending on the points stored in memory, the circuit in
Figure 1 can generate virtually any waveform.
Fi gure 2
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 11
2
2
1
1
6
7
5
6
9
10
9
8
7
12
15
16
19
14
13
12
11
20
19
13
15
16
19
3
4
7
8
13
14
17
18
11
1
74HC374N
IC
2
1D
2D
3D
4D
5D
6D
7D
8D
CK
OC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
TLC7226CN
VFC110
IC
3
IC
4
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
A0
A1
WR
VDD
VSS
REF
OUTA
OUTB
OUTC
OUTD
AGND
DGND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
AO
A1
WR
CLR
V
EE
()
V
CC
(+)
GAIN_ADJ
VREF_OUT
OFFSET_ADJ
V
OUT
ACOM
DCOM
DAC7621
IC
8
C
1
, 0.1 F
15V
50V, 10%
C
6
,
R
1
4.99k
0.125W
1%
0.1 F
50V, 10%
C
7
, 0.1 F
C
8
, 0.1 F
50V, 10%
50V, 10%
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
REF_OUT
5V 15V 15V
TP
1
TP
2
DGND
DGND
DGND
AGND
5
5
6
4
V
IN
V
CC
C
3
, 0.1 F
15V
5V
50V, 10%
V
EE
I
IN
C
OS
F
OUT
F
OUT
5V
REF
V
OUT
EN
AGND
GDND
CMPR_IN
NC
IN_COM
DGND
C
4
, 0.1 F
15V
50V, 10%
DGND
DGND
AGND
AGND
DGND
DGND
DGND
REF_OUT
8
3
12
10
11
9
14
2
18
3
4
DGND
CT1
www.ednmag.com
ideas
design
104 edn | June 13, 2002
I
n 1940, William Hewlett and David
Packard launched a product from a
garage. The product was a Wien-
bridge oscillator. It consisted of a single-
pole highpass filter in series with a single-
pole lowpass filter. To keep the gain
constant, the circuit used an incandescent
pilot light to provide AGC (automatic
gain control). As is true for all incandes-
cent bulbs, the pilot light has nonlinear
resistance. When you turn on the circuit,
the cold lamps resistance is low, resulting
in high gain. As the gain increases, the re-
sistance of the warming lamp increases.
Thus, the lamp provides an AGC func-
tion. The circuit has been in use for more
than 60 years and is still in use. The only
problem with the Wien-bridge oscillator
is that below unity gain it does not func-
tion. When working for a telephone com-
pany, I had to develop a 20-Hz, high-volt-
age sine-wave ringer circuit. The circuit
had to be adjustable from 20 to 200V p-
p. The most difficult part was that I had
to adjust the oscillators gain to a value
below unity.
The basic oscillator had to have gain
slightly greater than unity to make the
positive-feedback network oscillate. It
also needed an AGC loop to control the
greater-than-unity gain. So, I added a
third loop around the oscillator and
dubbed it a voltage-controlled, regulat-
ed-output feedback circuit. The end re-
sult (Figure 1) is a simple push-pull cir-
cuit. By adding D
1
, a zener diode, to
another feedback loop, I maintained the
amplitude even when I adjusted the gain
to a value lower than unity. The 5.2V zen-
er diode maintains the gain. The result is
that when the gain falls below unity, the
amplitude tries to decrease but cannot do
so, because the zener-diode voltage pulls
it back up. IC
2
, the LT1056AN amplifier
serves as a driver for the two LEDs, which
alternately turn on and off at the fre-
quency of the oscillator. IC
1
, an
LT1012AN amplifier has very low offset
voltage. IC
3
, a high-voltage TI/Burr-
Brown (www.ti.com) amplifier, produces
the final output of 20 to 200V. The final
resulta major breakthroughis a
Wien-bridge sine-wave oscillator that
you can adjust below unity gain, and the
circuit still maintains its AGC.
Q
2
2N2222
LED
GREEN
LED
GREEN
OSCILLATOR
RUNNING
750
12V
7.5k
270k
IC
2
LT1056-
AN
3
2
7
1
12V
_
+
4
150V
150V
6
12V
4
5
13k
2
7
3
IC
3
3583JM
CASE
1
14k
6
5
1k
HIGH-VOLTAGE
AMPLIFIER
J
1
V
OUT
V
OUT
1
2
_
+
1
12V
7
4
5
IC
1
LT1012-
AN
6
2
3
12V
27k
8
12V
1 F
1 F
1 F
6.8k
6.8k
56k
13k
2k
5.62k
1k
Q
1
2N2222
1N914
1N759A
1N751A
1k
_
+
D
1
Fi gure 1
The Wien-bridge oscillator is reborn
Michael Fisch, Agere Systems, Longmont, CO
This Wien-bridge oscillator is, according to the author, the first oscillator that can function at gains below unity.
Is this the best Design Idea in this
issue? Select at www.ednmag.com.
allel port. The clock rate C controls the
frequency of the arbitrary waveform. The
output frequency of IC
4
, a VFC110 VFC,
is directly proportional to its input volt-
age. With a full-scale input of 10V, the
VFC110 delivers 4 MHz. IC
3
provides a
voltage output of 0 to 10V, thus provid-
ing frequency control from near 0 Hz to
4 MHz. The voltage output of IC
3
re-
ceives its programming via the parallel
port, thus allowing computer control of
the clock rate. Thus, the circuit provides
a frequency range of 7.6 Hz (1/(204864
sec)) to 125 kHz (1/(32250 nsec)).
Figure 2 shows various sample outputs
of the circuit. You can download the
software files associated with this Design
Idea from the Web version of the article
at www.ednmag.com.
Is this the best Design Idea in this
issue? Select at www.ednmag.com.
106 edn | June 13, 2002 www.ednmag.com
ideas
design
T
he transfer gain of optical sensors
spans a 16-to-1 ratio because of vari-
ations in the LED, phototransistor,
ambient temperature, and optical path.
The wide transfer-gain variation compli-
cates output-resistor selection in dc-cou-
pled circuits. You must size the output re-
sistor to prevent high transfer gains from
causing output-stage saturation, but low
transfer gains yield low output-voltage
swings with low-value resistors. You usu-
ally need to make adjustments to match
the dc output voltage to the transfer gain,
and reliable operation requires readjust-
ment under extreme temperature and
dust conditions. The circuit in Figure 1
eliminates the need for adjustments. The
circuit uses dc-coupled feedback to con-
trol the current in the output resistor.
Hence, the output voltage is predictable
and constant.
The op amps input current and the
current in D
3
is negligible, so I
1
I
2
, and
the output voltage is 2.7V when the pho-
totransistor is on (light path unbroken).
The output voltage is 0V when the pho-
totransistor is off (light path broken).
The op amps output-voltage swing ac-
commodates the variation in transfer
gain. This output voltage assumes the val-
ue required to make the LED current
times the transfer gain equal to the pho-
totransistors emitter current. The input-
current equation is as follows:
The range of transfer gain is 80 to 5:
5I
3
/I
2
80. The op amps output-volt-
age range is limited, especially with the
high output-current requirement, thus
the design uses a TLC071 that can source
20 mA at 3.5V in this design:
When the light is blocked, the photo-
transistors emitter current goes to zero.
The input current, I
1
, cant flow into Q
1
because it is off, so the op amp heads for
the positive rail. If the op amps output
stage saturates, the recovery time is un-
predictable, so you insert the zener-diode
combination D
2
and D
3
to prevent satu-
ration. As the op amps output voltage ap-
proaches 3.4V (V
D2
V
D3
), the diodes
clamp the output voltage, thus prevent-
ing saturation. R
3
270 so that it can
supply adequate LED current without in-
curring op-amp saturation. When this
circuit drives a saturated logic circuit, you
should buffer the output with a hystere-
sis gate or a comparator with hysteresis.
Optical sensor needs no tweaking
Ron Mancini, Texas Instruments, Bushnell, FL
_
+
TLC071
5V
I
1
I
2
I
B
R
1
20k
V
REF
3V
R
2
27k
R
3
270
Q
1
V
OUT
D
3
1N4148
D
2
, 2.7V
1N5223
D
1
EESG3
Fi gure 1
The op-amp feedback keeps the phototransistors current constant, so the circuit requires no
adjustments for transfer gain.
Is this the best Design Idea in this
issue? Select at www.ednmag.com. . A 100
k 20
3 5
R
V V
I
1
REF CC
1
. 350
mA 8
7 . 0 5 . 3
I
V V
R
MAX 3
1 D OUTMAX
MAX 3
T
his Design Idea expands on a cir-
cuit in a previous one to configure a
power-outage detector with a flash-
ing alarm (Figure 1, Reference 1). The
circuit plugs into a mains outlet and uses
trickle-charged nickel-cadmium batter-
ies. The green-LED monitors the pres-
ence of line voltage. The BZV55-C4V3
zener diode, D
1
protects the batteries
against overvoltage. Voltage bias from R
6
and the green LED keeps Q
1
off, so the
Q
1
-Q
2
RC oscillator remains off. When a
power outage occurs, capacitor C
2
dis-
charges in approximately 2 to 3 seconds,
and the dc bias disappears. Now supplied
by the batteries, the RC oscillator starts,
and the red LED flashes at a rate of ap-
proximately 2 Hz. R
3
and C
3
set the flash-
ing frequency. You can use an infrared
LED instead of the visible LED. The in-
frared LED couples with an infrared re-
ceiver to provide a convenient remote
alarm.
Reference
1.Terrade, J M, Free-line indicator
stops interruptions, EDN, Dec 7, 2000,
pg 187.
108 edn | June 13, 2002 www.ednmag.com
ideas
design
PL
1
C
1
330 nF
C
2
10 F
R
4
20k
R
3
1M
C
3
0.47 F
R
5
10 TO 47
R
6
1 TO 10k
R
1
220k
R
2
470
1A BRIDGE OR
41N4007
+
Q2N2222A
OR
BC547
Q
2
Q
1
BC327
RED LED
+
+
+
NiCd
BATTERY
3.6V
300 mAH
D
1
BZV55-
C4V3
GREEN LED
Fi gure 1
A green LED indicates normal power-line voltage; a flashing red LED denotes a power outage.
Is this the best Design Idea in this
issue? Select at www.ednmag.com.
Power-line outage flashes red alert
Vasiliy Borodai, Zaporozhje, Ukraine