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Traffic Light Code Explanation

The document describes a traffic light controller module and a VGA controller module. The traffic light controller uses a state machine to control the states and timing of 4 sets of traffic lights. It outputs the color for each set of lights based on the current state. The state transition is controlled by delays between green/yellow and yellow/red. The VGA controller outputs signals to match the resolution of the monitor, which is specified as 800 x 600. It is responsible for the monitor display.

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Ivan Matala
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0% found this document useful (0 votes)
145 views

Traffic Light Code Explanation

The document describes a traffic light controller module and a VGA controller module. The traffic light controller uses a state machine to control the states and timing of 4 sets of traffic lights. It outputs the color for each set of lights based on the current state. The state transition is controlled by delays between green/yellow and yellow/red. The VGA controller outputs signals to match the resolution of the monitor, which is specified as 800 x 600. It is responsible for the monitor display.

Uploaded by

Ivan Matala
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Code Explanation:

The Traffic_Controller is responsible for handling the state machine. There is a single state machine
divided into 2 parts namely: 1.) output 2.) state transition. The output is responsible for outputting what
colors the traffic lights for Traffic light 1, 2, 3 and 4. The state transition is responsible for handling the
sequence of states and is responsible for checking the status of sensors/switches. The delay is
responsible for how long or how short the transition is from red to yellow and yellow to green.

The VGA_Controller is responsible for outputting the necessary signals to the VGA monitor. It uses a set
of values called VGA timings to match specified resolution which is 800 x 600.

module
Traffic_Controller(CLOCK_50,CLEAR,R1,R2,R3,R4,X1,X2,X3,X4,state,next_state,g2ydelay,y2rdelay);

output reg [2:0] R1,R2,R3,R4;
input X1,X2,X3,X4;

input CLOCK_50,CLEAR;

output reg [2:0] state;
output reg [2:0] next_state;

output reg [31:0] g2ydelay;
output reg [31:0] y2rdelay;

parameter RED = 3'b100;
parameter YELLOW = 3'b010;
parameter GREEN = 3'b001;

parameter gg2y = 100_000_000;
parameter yy2r = 100_000_000;

parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
parameter S4 = 3'd4;
parameter S5 = 3'd5;
parameter S6 = 3'd6;
parameter S7 = 3'd7;


initial
begin
state <= S0;
next_state <= S0;
R1 <= GREEN;
R2 <= RED;
R3 <= RED;
R4 <= RED;
g2ydelay <= 0;
y2rdelay <= 0;
end

always@(posedge CLOCK_50)
state <= next_state;

always@(state)
begin
case(state)
S0:
begin
R1 <= GREEN;
R2 <= RED;
R3 <= RED;
R4 <= RED;
end
S1:
begin
R1 <= YELLOW;
R2 <= RED;
R3 <= RED;
R4 <= RED;
end
S2:
begin
R1 <= RED;
R2 <= GREEN;
R3 <= RED;
R4 <= RED;
end
S3:
begin
R1 <= RED;
R2 <= YELLOW;
R3 <= RED;
R4 <= RED;
end
S4:
begin
R1 <= RED;
R2 <= RED;
R3 <= GREEN;
R4 <= RED;
end
S5:
begin
R1 <= RED;
R2 <= RED;
R3 <= YELLOW;
R4 <= RED;
end
S6:
begin
R1 <= RED;
R2 <= RED;
R3 <= RED;
R4 <= GREEN;
end
S7:
begin
R1 <= RED;
R2 <= RED;
R3 <= RED;
R4 <= YELLOW;
end
endcase
end

always@(posedge CLOCK_50)
begin
if(CLEAR)
next_state <= S0;
else
begin
case(state)
S0:
begin
if(g2ydelay == gg2y)
begin
g2ydelay <= 0;
next_state <= S1;
end
else
g2ydelay <= g2ydelay + 1;
end
S1:
begin
if(~X2)
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S4;
end
else
y2rdelay <= y2rdelay + 1;
end
else
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S2;
end
else
y2rdelay <= y2rdelay + 1;
end
end
S2:
begin
if(g2ydelay == gg2y)
begin
g2ydelay <= 0;
next_state <= S3;
end
else
g2ydelay <= g2ydelay + 1;
end
S3:
begin
if(~X3)
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S6;
end
else
y2rdelay <= y2rdelay + 1;
end
else
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S4;
end
else
y2rdelay <= y2rdelay + 1;
end
end
S4:
begin
if(g2ydelay == gg2y)
begin
g2ydelay <= 0;
next_state <= S5;
end
else
g2ydelay <= g2ydelay + 1;
end
S5:
begin
if(~X4)
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S0;
end
else
y2rdelay <= y2rdelay + 1;
end
else
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S6;
end
else
y2rdelay <= y2rdelay + 1;
end
end
S6:
begin
if(g2ydelay == gg2y)
begin
g2ydelay <= 0;
next_state <= S7;
end
else
g2ydelay <= g2ydelay + 1;
end
S7:
begin
if(~X1)
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S2;
end
else
y2rdelay <= y2rdelay + 1;
end
else
begin
if(y2rdelay == yy2r)
begin
y2rdelay <= 0;
next_state <= S0;
end
else
y2rdelay <= y2rdelay + 1;
end
end
default: next_state <= S0;
endcase
end
end
endmodule

Block Diagram Explanation:
The input pins L21,M22,V12,W12,L1,L22 are connected to the Traffic Controller. The Traffic Controller
also outputs the V22,U21,U22,Y22,W21,W22,etc (these are the respective LEDs). The VGA Controller is
responsible for the VSYNC, HSYNC, RGB outputs going to the monitor.

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