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E15 - Fall 2010 - Icarus Verilog Tutorial PDF

Icarus Verilog is a free Verilog simulator that is already installed on classroom PCs. To use it on your own computer, you can download it for Windows or install through MacPorts on Macs. You create a folder to save Verilog files, then compile with iverilog and run the simulation with vvp. GTKWave can view the output waveform file produced. Common errors include missing modules when compiling or files when running the simulation.

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schaltegger
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373 views

E15 - Fall 2010 - Icarus Verilog Tutorial PDF

Icarus Verilog is a free Verilog simulator that is already installed on classroom PCs. To use it on your own computer, you can download it for Windows or install through MacPorts on Macs. You create a folder to save Verilog files, then compile with iverilog and run the simulation with vvp. GTKWave can view the output waveform file produced. Common errors include missing modules when compiling or files when running the simulation.

Uploaded by

schaltegger
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Icarus Verilog

Downloading and installing the software


Icarus Verilog is already installed on the PC's in Hicks 213.
If you want to run it on your home computer, you can download it for Windows here (locally mirrored
from this site).
If you have a Mac, you can install it through MacPorts instead.
Setting up directories and folders
Create a folder for your programs in your Documents folder or on your K: drive. Let's use
K:\verilog\homework5, for example. Save your Verilog files to that folder. You can use notepad or
any other plain text editor to write your Verilog programs.
Here's two example Verilog files, simple.v and simple_tb.v, that you can copy into your directory to
test things out.
simple.v:
module simple(A, B);
input [3:0] A;
output [3:0] B;
// mix up the input bits
assign B = { A[0], A[2], A[1], A[3] };
endmodule
simple_tb.v:
module simple_tb;
reg [3:0] A = 4'b1010;
wire [3:0] B;
initial
begin
$dumpfile("simple.vcd");
$dumpvars(0, s);
$monitor("A is %b, B is %b.", A, B);
#50 A = 4'b1100;
#50 $finish;
end
simple s(A, B);
endmodule
Compiling your Verilog program
You need to compile your Verilog program before you can simulate it. Open up a DOS prompt (run
cmd.exe from the Start menu) and type the following, hitting enter after each line:
K:
cd verilog\homework5
iverilog -o simple.vvp simple.v simple_tb.v
If the compilation went OK, you won't see any output. What this does is create a file called simple.vvp
that we can feed to the simulator.
Running the simulation
To run the simulation, type
vvp simple.vvp
and hit enter. You should see output something like:
VCD info: dumpfile simple.vcd opened for output.
A is 1010, B is 0011.
A is 1100, B is 0101.
Viewing the output
You can use the GTKWave program to view the output. From the DOS prompt, type
gtkwave simple.vcd
to view the results of your simulation.
Troubleshooting
I get the error "Unknown module type: foo" when I run iverilog!
You might have run iverilog without all of the sources needed to define all of the modules. A common
cause is compiling foo_tb.v without also compiling foo.v.
I get the error "foo.vvp: Unable to open input file." when I run vvp!
You might have forgotten to specify -o foo.vvp when you ran iverilog.
The vvp program never stops running!
Is there a $finish statement anywhere in your code? Are you sure it is getting run? You should be able
to type Ctrl + C at the DOS prompt to kill the simulator.
There is no data file produced!
Make sure your test bench includes a $dumpfile statement and a $dumpvars statement.
Typing things at a DOS prompt sucks!
Try using the ModelSim software instead.
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