Substrate Noise in Mixed-Signal

Integrated Circuits

Min Xu
9/6/2001

Center for Integrated Systems

Stanford University
Stanford, CA 94305

Now with Big Bear Networks, Inc.

1591 McCarthy Blvd. Milpitas, CA 95035
 Outline

• Introduction
- Motivation
- Overall picture

• Test Vehicles
• Substrate noise ~ digital circuits (F1)
• Analog circuits ~ substrate noise (F2)
• Impact on the GPS receiver system
• Conclusions

1 C Min Xu, Stanford University

 System on a Chip!

PLL
Amplifier Processor

Mixer
Memory
Filter
I/O
A/D
D/A

Integrating the entire system on a chip has the advantage of low cost, small size,
and low power, but the system is susceptible to performance degradation caused
by substrate noise coupling.

2 C Min Xu, Stanford University

 System on a Chip?

low cost switching

small size noise
low power scaling

System on a chip Two-chip solution

3 C Min Xu, Stanford University

 Reports on Substrate Noise Impact

• Degraded circuit performance

- 8-bit, semiflash pipelined video A/D continued to fail several
specifications after three design fabrication iterations, DNL>+/-1
LSB. (N. K. Verghese, JSSC, March, 1996)

• Forced separation of analog and digital circuits in two chip

- "In the original design, analog and digital functions were
implemented in a single chip, however to reduce digital noise
coupling and improve BER performance it is necessary to use
separate analog and digital test chips." (K. Azadet, ISSCC, 2000)

• Prediction and suggestion

- "The optimal solution to cross-talk is a two-chip solution with the
first chip contains the sensitive analog circuitry and has no
digital." (K. Bult, ISSCC, 1999)

4 C Min Xu, Stanford University

 Overall Picture of Substrate Noise Problem

analog digital
circuit circuit

F2

te
tra
bs
F1

su
Vsub2 propagates (P)
Vsub1

• Vsub1=Vsub2=Vsub for epi process (single node approximation).

• Vsub=F1(digital clock scheme, package)

• Analog circuit performance = F2(Vsub)

• Find F1, F2?

5 C Min Xu, Stanford University

 Approaches of Earlier Research

analog digital
circuit circuit

te
F2

tra
bs
F1

su
Vsub2 propagates (P) Vsub1

equivalent substrate im- substrate noise time do-

pedance main response
process and isola- Vmax
tion techniques,
such as guard
rings
Tsettle

6 C Min Xu, Stanford University

 Approach of this Work
I. Possible Substrate Noise Effects on Analog Circuits

• System function: Y = F2(X+x0+δx, B+δb)

X = dc input, B = bias, x0 = ac input,

δb = bias perturbation, δx = input perturbation

• Expand Y into its Taylor series, retaining only terms as high as

second order. The frequency locations of the terms are

fs, fn, 0, 2fs, 2fn, fs+fn, |fs-fn|

fs = signal frequency, fn = noise frequency,

7 C Min Xu, Stanford University

 Approach of this Work
II. Possible Substrate Noise Effects on a System

Noise tones caused Intermodulation between

by substrate noise signal and substrate noise

|Y(f)|2

signal band

fmin fmax f

Illustration of substrate noise effects in analog circuits. If noise falls into analog sig-
nal band, it will cause SNR reduction; otherwise, the noise in the analog circuit output
can be filtered out.

8 C Min Xu, Stanford University

 Outline
• Introduction
• Test Vehicles
- Analog circuit --- LNA
- Digital circuit emulator
- Substrate noise sensor

• Substrate noise ~ digital circuits (F1)

• Analog circuits ~ substrate noise (F2)
• Impacts on the GPS receiver system
• Conclusions

9 C Min Xu, Stanford University

 Low Noise Amplifier (LNA)*

Outp Outm

Ibias

Vb +
- CMFB

Inp Inm

M1 M2

* D. K. Shaeffer, et al., “A 115-mW, 0.5µm CMOS GPS Receiver with Wide Dynamic-range Active
Filters,” IEEE J. Solid-State Circuits, vol. 33, pp. 2219-2231, Dec. 1998

10 C Min Xu, Stanford University

 Digital Circuit Emulator

sel
clk
digital enb0
amp C0
clock
x1
clk_b mux N+
enb1
ring
x2 2C0
oscillator
N+
sel sel

sel enb5
data_in enb_0 32C0
x 32
enb_1 N+
shift
register enb_5
enb6_1,enb6_2
enb6_1 enb6_3
clk_in 56C0
enb6_2 x56
N+
enb6_3

11 C Min Xu, Stanford University

 Substrate Noise Sensor

clock Vdd=2.5V 50Ω

bias
Vsensor_out

N+ N+ N+ P+

diffusion substrate
capacitor contact
P- P+ channel stop implant

P+ Bulk

12 C Min Xu, Stanford University

 Chip Microdiagram

DIGITAL CIRCUIT
EMULATOR

SENSOR

LNA

13 C Min Xu, Stanford University

 Outline
• Introduction
• Test Vehicles
• Substrate noise ~ digital circuits (F1)
- Substrate noise generated by the digital circuit
emulator
- Generalized model of F1

• Analog circuits ~ substrate noise (F2)

• Impacts on the GPS receiver system
• Conclusions

14 C Min Xu, Stanford University

 Measured Substrate Noise Waveform

An example of the substrate-noise waveform measured

at the substrate noise sensor output

0.02

0.01 tsettle
Vpp
Vout (V)

Vnp
−0.01

−0.02
−100 −50 0 50 100
Time (ns)

Ccouple= 43.52 pF, fclock = 7.1 MHz, trise/fall = 0.9 ns

15 C Min Xu, Stanford University

 Time-Domain Substrate Noise Characteristics

Substrate noise magnitude increases Substrate noise settling time does not
linearly with coupling capacitance change with the coupling capacitance

0.02 0.015

0.01
0.01
Vout (V)

Vout (V)
0.005

0 0

−0.005
−0.01
−0.01
−0.02 −0.015
0 20 40 60 −5 0 5 10
Ccouple (pF) time (ns)

fclock = 7.1 MHz, trise/fall = 0.9 ns sensor output when

Ccouple = 16, 32, 48, 64, 80, 96, 120,
152, 180C0
fclock = 7.1 MHz, trise/fall = 0.9 ns

16 C Min Xu, Stanford University

 Model of Substrate Noise Injection

Vdd
Vdd Lvdd
Lvdd
Rvdd
Rvdd

Mp Rpmos
Vout Cp Cp
Vin
Ccouple Vout Rp
Rp
Ccouple
Rcouple Rcouple
Mn
Vsub(s) Vsub(s)

Zsub_up
Rgnd Rn equivalent to
Cn
Zsub

Lgnd

(a) (b)

17 C Min Xu, Stanford University

 Substrate Noise Caused by a Single Digital
Transition
• In the s domain, substrate noise caused by a single digital
transition is
C couple V dd Z sub – up
V sub – up ( s ) = --------------------------- × --------------------------------------------------------------------------------------
( 1 + t rise s ) ( Z sub – up + L vdd s + R vdd )C s
p
1 + ----------------------------------------------------------------------------
1 + R pC p s

tup = rise time, Ccouple << Cp and Rp << Rpmos

• Substrate noise is a linear function of the Ccouple if trise/fall is a

constant. Therefore substrate noise root function is defined as

1 V dd Z sub – up
V root – u p ( s ) = --------------------------
- × -------------------------------------------------------------------------------------
-
( 1 + t rise s ) ( Z sub – up + L vdd s + R vdd )C s
p
1 + ----------------------------------------------------------------------------
1 + R pC p s

–1
and in time domain as u u p, 1 ( t ) = L ( V root – u p ( s ) )

18 C Min Xu, Stanford University

 Substrate Noise vs. trise/fall
I. Time Domain

In time domain, substrate noise magnitude decreases as trise/fall increases

enb6_1
x8 8C0
enb6_2 N+
digital clock
x 16 16C0
+
enb6_3 N
x 32 32C0
+
N

Only enb6_1 is on, trise/fall = 5.4 ns Three buffers all on, trise/fall= 0.9 ns

5 5
Vout (mV)

0 Vout (mV) 0

−5 −5

−50 0 50 −50 0 50
Time (ns) Time (ns)

19 C Min Xu, Stanford University

 Substrate Noise vs. trise/fall
II. Frequency Domain

In frequency domain, increasing trise/fall reduces high frequency substrate

noise power, but does not reduce low frequency substrate noise power

Only enb6_1 is on, trise/fall = 5.4 ns Three buffers all on, trise/fall= 0.9 ns

−40 −40

Vout (dBm)
Vout (dBm)

−60 −60

−80 −80

−100 −100
500 1000 1500 500 1000 1500
Frequency (MHz) Frequency (MHz)

20 C Min Xu, Stanford University

Analysis of Substrate Noise Spectral Distribution

• In time domain, the total substrate noise is the summation of

substrate noise caused by each digital transition.

• For digital circuits with a periodic switching pattern, the substrate

noise spectra distribution is the Fourier transform of the time
domain substrate noise.

C couple 2 2
S ( f ) = ------------------- U up ( f ) + ( – 1 ) U down ( f ) δ  f – ---
 n n
n = integer
 T   T

C couple 2
S ( f ) ∝ ------------------- ----------------------------- δ  f – ---
 1 n
n = integer
 T  2  T
1 + ( 2πfτ )

21 C Min Xu, Stanford University

 Staggering the Digital Switching
I. Time Domain

In time domain, staggering digital switching reduces substrate noise

magnitude
Normal switching Staggering the digital switching

enb1 enb1
x 48 48C0 x 48 48C0
N+ N+
enb1 enb1
x 48 48C0 x 48 48C0
N+ N+

10 10
5 5
Vout (mV)

0 Vout (mV) 0
−5 −5
−10 −10
−50 −25 0 25 50 −50 −25 0 25 50
Time (ns) Time (ns)

22 C Min Xu, Stanford University

 Staggering the Digital Switching
II. Frequency Domain

In frequency domain, staggering digital switching does not reduce sub-

strate noise in all frequency ranges.
Normal switching Staggering the digital switching

enb1 enb1
x 48 48C0 x 48 48C0
+ +
N N
enb1 enb1
x 48 48C0 x 48 48C0
+ +
N N
−40 −40
Vout (dBm)

Vout (dBm)
−60 −60

−80 −80

−100 −100
50 100 150 200 250 300 50 100 150 200 250 300

Frequency (MHz) Frequency (MHz)

23 C Min Xu, Stanford University

 Outline
• Introduction
• Test Vehicles
• Substrate noise ~ digital circuits (F1)
- Substrate noise generated by the digital circuit
emulator
- Generalized model of F1

• Analog circuits ~ substrate noise (F2)

• Impacts on the GPS receiver system
• Conclusions

24 C Min Xu, Stanford University

 Model of F1 Using Filter Banks (I)

If substrate noise caused by every digital transition is of the same shape

uup,1(t) - substrate noise root function, which describes the substrate noise shape
pup,1(t) - capacitance switching rate functions
coupling capacitance at time τ: pup,1(τ)dτ

substrate noise caused by

the transitions at time t
uup,1(t-τ) x pup,1(τ)dτ
magnitude

Time
τ τ+dτ

substrate noise at time t:

t
v sub, u p, 1 ( t ) = ∫–∞ uu p, 1 ( t – τ ) pu p, 1 ( τ ) dτ
= u u p, 1 ( t ) ⊗ p u p, 1 ( t )

25 C Min Xu, Stanford University

 Model of F1 Using Filter Banks (I)
N types of substrate noise root functions for low-to-high digital transitions
M types of substrate noise root functions for high-to-low digital transitions

uup, 1(t) u u p, 1 ( t ) ⊗ p u p, 1 ( t )
.. .. ..
. . .
uup, N(t) u u p, N ( t ) ⊗ p u p, N ( t )

udown, 1(t) u down, 1 ( t ) ⊗ p down, 1 ( t )

.. .. ..
. (t) . .
udown, M u down, M ( t ) ⊗ p down, M ( t )
Time
t

total substrate noise at time t

N M
v sub ( t ) = ∑ uu p, k ( t ) ⊗ pu p, k ( t ) + ∑ u down, k ( t ) ⊗ p down, k ( t )
k=1 k=1

26 C Min Xu, Stanford University

 Model of F1 Using Filter Banks (II)

pup, 1(t) Uup, 1(f) u u p, 1 ( t ) ⊗ p u p, 1 ( t )

.. .. .. Substrate
. . . noise caused
by low to high
pup, N(t) Uup, N(f) u u p, N ( t ) ⊗ p u p, N ( t ) transition

Vsub(t)
+
pdown, 1(t) Udown, 1(f) u down, 1 ( t ) ⊗ p down, 1 ( t )

.. .. .. Substrate
noise caused
. . . by high to
pdown, M(t) Udown, M(f) u down, M (t) ⊗ p down, M ( t )
low transition

Filter Bank

Digital circuit Substrate noise Substrate noise corresponds

switching scheme root functions to each distinct uup/down,k(t)

27 C Min Xu, Stanford University

 Substrate Noise vs. Digital Switching Pattern (I)

An array of identical inverters, therefore,

there are two types of substrate noise
root functions: N+
uup,1(t): for low-to-high transition,
udown,1(t): for high-to-low tansition
N+
and two capacitance switching rate .. ..
functions: . .
pup,1(t) for low-to-high transition,
pdown,1(t) for high-to-low transition N+

pup, 1(t) Uup, 1(f)

Vsub(t)
Filter-bank model +
pdown, 1(t) Udown, 1(f)

28 C Min Xu, Stanford University

 Substrate Noise vs. Digital Switching Pattern
II. Periodic Switching

If all the buffere inputs are driven by pup, 1(t) Uup, 1(f)
the same clock, the change of digi- Vsub(t)
tal clock duty cycle changes the pdown, 1(t)
+
Udown, 1(f)
filter inputs, thus redistributes sub-
strate noise spectrum.
digital clock cycle=50% digital clock dutycycle=25%

−20 −20

Vout (dBm)
Vout (dBm)

−40 −40

−60 −60

50 100 150 200 250 300 50 100 150 200 250 300
Frequency (MHz) Frequency (MHz)

trise,fall=0.9nsec, fclock=24.8MHz, Ccouple=96Co trise,fall=0.9nsec, fclock=24.8MHz, Ccouple=96Co

29 C Min Xu, Stanford University

 Substrate Noise vs. Digital Switching Pattern
III. Random Switching

pup, 1(t) Uup, 1(f)

If pup(t) and pdown(t) are i.i.d and
wide-sense stationary random pro- Vsub(t)
+
cesses, the substrate noise pdown, 1(t) Udown, 1(f)
spectrum becomes continuous

2 2
S ( f ) = m δ ( f ) ( u up + u down )
2
+ σ  U up ( f ) + U down ( f )  S(f)
2 2
  σ2(|Uup(f)|2+|Udown(f)|2)
where
∞ |Uup(f)|2+|Udown(f)|2
u up = ∫ u ( t ) dt
– ∞ up
∞
u down = ∫–∞ u down ( t ) dt
m = E ( p up ( t ) ) = E ( p down ( t ) )
m2δ(f)(uup+udown)2
2
σ = var ( p up ( t ) ) = var ( p down ( t ) )
f

30 C Min Xu, Stanford University

 Key Issues in Modeling F1

• Use frequency domain approach

Some widely accepted time-domain substrate noise reduction

methods may not be effective, e.g.:
- Staggering the digital switching
- Increasing the digital transition time

• Key factors in the model

- Substrate noise root function
physical characteristics of digital circuitry
- Digital switching scheme
timing characteristics of digital circuitry

31 C Min Xu, Stanford University

 Outline

• Introduction
• Test Vehicles
• Substrate noise ~ digital circuits (F1)
• Analog circuits ~ substrate noise (F2)
• Impacts on the GPS receiver system
• Conclusions

32 C Min Xu, Stanford University

 Measured LNA Outputs

Noise tones appear at the LNA output when the digital circuit
turns on
Digital circuit off Digital circuit on

−40 −40

−60 −60

V(dBm)
V(dBm)

−80 −80

−100 −100
1350 1400 1450 1500 1550 1600 1350 1400 1450 1500 1550 1600
Frequency (MHz) Frequency (MHz)

RF input = -60 dBm, 1.575 GHz

RF input = -60 dBm, 1.575 GHz
Digital circuit operation condition:
fclock= 39.825 MHz, trise/fall= 0.9 ns
Duty cycle= 50%, Ccouple= 32.6 pF

33 C Min Xu, Stanford University

 Measured Substrate Noise Spectrum

Measured substrate noise spectrum at the substrate noise sensor output

−40

−60
V(dBm)

−80

−100
200 400 600 800 1000 1200 1400 1600 1800

Frequency (MHz)

RF input = -60 dBm, 1.575 GHz

Digital circuit operation condition:

fclock= 39.825 MHz, trise/fall= 0.9 ns, Duty cycle= 50%, Ccouple= 32.6 pF

34 C Min Xu, Stanford University

 Analysis of Noise Coupling Mechanism

δxd − differential-mode noise

δxc, δb − common-mode noise
F(X+xd/2+δxd/2+δxc, B+δb)
+ Differential
Output: Y
−
F(X-xd/2-δxd/2+δxc, B+δb)

Y
2 2 2 2
∂F ∂F ∂ F ∂ F ∂ F ∂ F
= xd + δ xd + δ xc x d + xd δb + δ xd δ xc + δ δ
∂x ∂x ∂x
2 ∂ x ∂b x = X ∂x
2 ∂ b ∂ x x = X xd b
x=X x=X
x=X x=X
b = B b = B

fs fn fs+fn, |fs-fn| 0, 2fn

35 C Min Xu, Stanford University

 Noise Coupling Mechanisms for this LNA

• IM noise tones (frf-nfclock) in the LNA output are caused by the

LOW frequency common mode noise.
- Analysis and simulations show that substrate noise is the dominant
common mode noise source.

• Harmonic tones of the digital clock (nfclock) in the LNA output are
caused by the HIGH frequency differential mode noise.
- Caused by the differential mode noise: asymmetry of the board,
package, bonding, chip.

36 C Min Xu, Stanford University

 Effects of Common-mode Noise
I. Identifying IM Noise in the LNA Output

Move RF down 5 MHz, the intermodulation (IM) noise tones

are moved down by 5 MHz.
Measured LNA output
−40
RF input = -60 dBm, 1.575 GHz
−60
V(dBm)

Digital circuit operation condition:

fclock= 39.825 MHz, trise/fall= 0.9 ns
−80 * * * Duty cycle = 50%, Ccouple= 32.6 pF
* *
−100
1350 1400 1450 1500 1550 1600
−40
RF input = -60 dBm, 1.570 GHz
−60
V(dBm)

Digital circuit operation condition:

fclock= 39.825 MHz, trise/fall= 0.9 ns
−80
* * * Duty cycle = 50%, Ccouple= 32.6 pF
* *
−100
1350 1400 1450 1500 1550 1600
Frequency (MHz)

37 C Min Xu, Stanford University

 Effects of Common-mode Noise
I. Identifying IM Noise in the LNA Output (cont’d)

Reduce the RF signal power by 10 dB, the intermodulation (IM) noise

power is reduced by 10dB.
Measured LNA output
−40
RF input = -60 dBm, 1.575 GHz
−60
Digital circuit operation condition:
V(dBm)

* * fclock= 39.825 MHz, trise/fall= 0.9 ns

−80 * * *
Duty cycle = 50%, Ccouple= 61.2 pF

−100
1350 1400 1450 1500 1550 1600
−40
RF input = -70 dBm, 1.575 GHz
−60
V(dBm)

Digital circuit operation condition:

fclock= 39.825 MHz, trise/fall= 0.9 ns
−80
* * Duty cycle = 50%, Ccouple= 61.2 pF
* * *
−100
1350 1400 1450 1500 1550 1600
Frequency (MHz)

38 C Min Xu, Stanford University

 Effects of Common-Mode Noise
II. Model

• Mechanism: perturb the bias condition of the LNA

• Model: single node approximation of the substrate

LNA output
−40

Measured LNA output

−60
V(dBm)

Simulated LNA output

−80
with single node approximation
of the substrate

−100
1350 1400 1450 1500 1550 1600
Frequency (MHz)

39 C Min Xu, Stanford University

 Effects of Common-Mode Noise
III. Experimental Verification
• Theoretical prediction

I M ∝ V sub  2
 ⇒ IM power ∝ C couple
V sub ∝ C couple 

• Measurements

−20 * 119 MHz substrate noise tone

Power (dBm)

measured with the substrate

−40
noise sensor
−60

−80
+ 1.456 GHz IM noise at the LNA
output
−100
2 4 8 16 32
Ccouple (pF)

40 C Min Xu, Stanford University

 Effects of Differential-mode Noise
I. Noise Sources

• Differential-mode noise is caused by mismatch between the two

differential branches that results from

- location difference with regarding to the digital circuit

- bonding mismatch
- on chip inductor pairs dilemma
- mismatch of devices from process variation

41 C Min Xu, Stanford University

 Effects of Differential-Mode Noise
II. Model (difficult)

Differential-mode noise is difficult to model due to its stochastic and dis-

tributed characteristics

• stochastic: process variation

• distributed: important at high frequency

j ( ωt + φ ) jωt
v diff = Ae – Ae ≈ Aφ

2πl 2πlf µε
φ = -------- = ---------------------- analog digital
λ c circuit circuit

F2 F1

te
Example:

tra
f=1.5GHz, l=100µm

bs
l

su
–2 1 2
v diff = 10 A 3

42 C Min Xu, Stanford University

 Effects of Differential-Mode Noise
III. Measurements
• Theoretical prediction

DCN ∝ V sub 
 DCN 1
1  ⇒ power ∝ ------------------------------2
V sub ∝ -------------------------------------------------  ( t rise ⁄ fall )
( 1 + 2πjf t rise ⁄ fall ) 
DCN --- directly coupled noise

• Measurements
−60
1.513 GHz tone at the LNA output

−70 RF input = -60 dBm, 1.575 GHz

V(dBm)

Digital circuit operation condition:

−80 fclock= 39.825 MHz,
Duty cycle = 50%, Ccouple= 19 pF
−90
0.8 1 2 3 4 5 6
trise/fall (ns)

43 C Min Xu, Stanford University

 Outline

• Introduction
• Test Vehicles
• Substrate noise ~ digital circuits (F1)
• Analog circuits ~ substrate noise (F2)
• Impact on the GPS receiver system
• Conclusions

44 C Min Xu, Stanford University

 Bad news

• Substrate noise power (~ −10dBm in this study) is several orders of

magnitude higher than that of the received signal of GPS receiver (−
130dBm)

• To the accuracy of the second order nonlinearity of the LNA, Sub-

strate noise effects can be divided into
- Differential mode noise: couple directly into the LNA output with some
gain factor
- Common mode noise: modulate with differential RF interference and fall
into the GPS signal band.

45 C Min Xu, Stanford University

 GPS Receiver Block Diagram*

Antenna

2.048MHz
1.57542GHz
I[n]

DSP
mixer IF amp IF filter A/D
RF filter LNA

Q[n]
π/2 limiting
amp
LO=1.573GHz

*D. K. Shaeffer, et al., “A 115-mW, 0.5µm CMOS GPS Receiver with Wide Dynamic-range Active
Filters,” IEEE J. Solid-State Circuits, vol. 33, pp. 2219-2231, Dec. 1998

46 C Min Xu, Stanford University

 GPS signal structure*
Thermal noise Floor -175.2dBm/Hz

~-15dB -190.1~-183.1dBm/Hz

direct sequence
spread spectum C/A code

P code

2.046MHz

1.57542GHz
20MHz

*J. J. Spilker, Jr., “GPS Signal Structure and Theoretical Performance,” in B/W. Parkinson and J.J Spilker,
Jr., Eds., Global Positioning System: Theory and Applications, vol. I. American Institute of Aero-
nautics an Astronautics, 1996, pp57-119

47 C Min Xu, Stanford University

 Spread Spectrum System*

Spread spectrumsignal Interferer

Data signal Demodulated
data
Noise

Radio Radio

Spread Trans Spread

spectrum mitter Receiver spectrum
modulator Demodulator

DATA IN DATA OUT

* Olav Berg, Tore Berg, Svein Haavik, Jens Hjelmstad and Reidar Skaug, “Spread Spectrum in Mobile Com-
munication,” The Institution of Electrical Engineers, London, UK, 1998

48 C Min Xu, Stanford University

GPS Signal Spectrum in the Receiver Signal Path

2MHz
1.57542GHz
1.57542GHz

2.046MHz 2.046MHz
2.046MHz

0dB

Antenna -68dB
3.5MHz 10MHz

DSP
LNA
RF filter
LO=1.573GHz

49 C Min Xu, Stanford University

 Good news
• Frequency selective characteristics
- Only low frequency common-mode noise and high frequency differ-
ential-mode noise will actually degrade the performance of the LNA

• Single chip solutions might be possible by

- Careful design of the digital switching scheme
- Modifying the LNA
- Employing system-level techniques, and making full use of the
interference rejecting ability of the spread spectrum GPS signal
structure
=> High order RF filter
=> Adaptive quantizer*
=> Adaptive frequency notch filter*

*J. J. Spilker Jr., and F. D. Natali, “Interference Effects and Mitigation Techniques”, in B/W. Parkinson and
J.J Spilker, Jr., Eds., Global Positioning System: Theory and Applications, vol. I. American Institute
of Aeronautics an Astronautics, 1996, pp717-771.

50 C Min Xu, Stanford University

 Outline

• Introduction
• Test Vehicles
• Substrate noise ~ digital circuits (F1)
• Analog circuits ~ substrate noise (F2)
• Impacts on the GPS receiver system
• Conclusions

51 C Min Xu, Stanford University

 Summary of this Work

• Experimentally and
theoretically studied analog digital
circuit circuit
- F1: substrate noise as a

te
F2

tra
function of digital circuit

bs
characteristics F1

su
- F2: substrate noise Vsub2 propagates (P) Vsub1
effects on analog circuits

• Frequency domain approach and the functional relationships

between the source of substrate noise and its effects provides
insight into substrate noise mitigation.
- Extend the process of substrate noise minimization beyond the
substrate itself to the design of the sensitive analog circuits, the
digital circuits that are the source of the noise, and the system
architecture.

52 C Min Xu, Stanford University

 Design Recommendations
I. From the Analog circuit designing

• Fully differential architecture

• Reduce the differential mode noise effects by

- Symmetric layout, bonding

• Reduce the common mode noise effects by

- Reducing derivatives of system function with respect to the
common mode noise (δxc, δb)

53 C Min Xu, Stanford University

 Design Recommendations
II. From the Digital designing

Depends on the signal band of the mixed-signal system, optimize the substrate noise
spectral distribution, some examples:

1. Narrow band 2. High center frequency

high frequency digital clock increase trise/fall
|power |power
noise signal substrate noise
signal
band band envolope
filter

f f

3. Wide band
Stagger the digital switching, so as to reduce the TOTAL substrate noise
power.

4. Reduce substrate impedance at the directly coupling band, or intermodulation

band by proper substrate contact, bypassing, bonding, packaging.

54 C Min Xu, Stanford University

 Design Recommendations
III. From the System designing

• Employing system-level techniques, and making full use of

interference rejecting ability of the spread spectrum GPS signal
structure
- High order RF filter
- Adaptive quantizer*
- Adaptive frequency notch filter*

*J. J. Spilker Jr., and F. D. Natali, “Interference Effects and Mitigation Techniques”, in B/W. Parkinson and
J.J Spilker, Jr., Eds., Global Positioning System: Theory and Applications, vol. I. American Institute
of Aeronautics an Astronautics, 1996, pp717-771.

55 C Min Xu, Stanford University