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07 AceVerification SystemVerilog Nov2005

This document discusses coverage driven verification using SystemVerilog. It defines functional coverage as assessing that random and focused tests adequately exercise a design. An example is provided of defining a functional coverage point to check that IP and IPX packets are sent in both transmit and receive paths. The key aspects of effective coverage driven verification are outlined as goal definition, tracking progress towards goals, problem solving uncovered issues, using best known methods, and transparency in reporting.

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104 views

07 AceVerification SystemVerilog Nov2005

This document discusses coverage driven verification using SystemVerilog. It defines functional coverage as assessing that random and focused tests adequately exercise a design. An example is provided of defining a functional coverage point to check that IP and IPX packets are sent in both transmit and receive paths. The key aspects of effective coverage driven verification are outlined as goal definition, tracking progress towards goals, problem solving uncovered issues, using best known methods, and transparency in reporting.

Uploaded by

prabhuasb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Cover age Dr i ven Ver i f i c at i on

w i t h Syst emVer i l og
Ace Verification
Func t i onal Cover age
Definition: The functionality required to
be tested to achieve the quality goals
Test Definition is howto exercise
Functional Coverage what needs to be
exercised
Use: To assess that the Random and
Focused tests adequately exercise the
design
Syst emVer i l og Func t i onal -
Cover age Ex ampl e
Example Functional Coverage Definition:
IP and IPX packets are sent in both Txand RX
path of the design
Syst emVer i l og Func t i onal -
Cover age Ex ampl e
cl ass s_packet ;
event pkt _sent ;
enum{I P, I PX, RAW} t yp ;
enum{RX, TX, OTHER} di r ect i on ;
covergroup pkt_sent_cvr @(pkt_sent);
coverpoint typ iff (typ != RAW) ;
coverpoint direction
cross typ, direction {
illegal_bins invalid =
(direction == OTHER);
}
endgroup: pkt_sent_cvr
endcl ass: s_packet
CDV Fl ow Char t
Define Functional
Coverage points
Code the
Coverage points
Run Regressions
Review Results
Refocus efforts to
coverage holes
Loosen Constraints
Enhance environment
Add tests
Preparation
Iterative Process
Random testing
Use existing tools
Why i s t he i ndust r y movi ng t o
Cover age Dr i ven Ver i f i c at i on?
Focused tests are inadequate in delivering
quality designs to fabrication
Random needs to aimed in order to be
effective
Have I covered all of my must-haves?
Do I need to focus the random on additional areas
=> CDV facilitates effective Random
Verification
CDV Addi t i onal benef i t s
Teams define the success criteria for
the verification up-front
The measure of progress is objective
(provided by the tools)
Keys t o ef f ec t i ve CDV
Goal Definition
Tracking
Problem Solving
Best Known Methods
Transparency
Goal Def i ni t i on
Part 1 Project Goal
Part 2 Details
Functional Coverage Goals
Apply VMM methodology
Code in SystemVerilog
Assertions and Checks
Use SystemVerilog Assertions
Enhance with coding styles from VMM
Tr ac k i ng
Use functional coverage as the primary
metric
Track planned vs. executed
Track to 100%
St andar d Pr ogr ess Char t
Functional Verification Progress
0
20
40
60
80
100
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2
0
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2
1
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0
Work Weeks
C
o
v
e
r
a
g
e

P
r
o
g
r
e
s
s
Actual Progress
Expected
Progress
Pr obl em Sol vi ng
Requirements
Clear understanding of problem
Functional Coverage report will show lack of
progress in feature
Cost
Overall impact of the problem on overall
progress
Best Know n Met hods (BKMs)
Use standard interfaces between blocks
OCP, AHB etc.
Use the standard components in VMM
Base classes, Messaging, Interfaces
vmm_env, vmm_channel etc.
Use design paradigms
Scoreboard, Register Mirroring, Test Flow
Etc.
Tr anspar enc y
Motivation
Achieving successful transparency
Build an expect graph up front
Present it at the same time each week
Show progress on individual features
No cover-up
Allow all stake-holders view of progress
How t he k eys w or k t oget her
Clearly defined goals keep people focused
The indicator charts give an objective view on
overall progress (toward 100%)
Verification goal -> Project Goal
The reports identify problems at the root
cause and they get resolved quickly
Using BKMs shortens design time and
reduces the risks of rework
All stake-holders use the transparency to
both boost confidence and preempt problems
Summar y
Coverage Driven Verification
Enables effective Random Verification
Can be used to achieve predictable
schedules
Mor e i nf or mat i on
www.aceverification.com
Coverage Revealed Advanced Training

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