Lab Workbook Direct Memory Access using CDMA

www.xilinx.com/university ZedBoard 4-1

[email protected]
copyright 2013 Xilinx
Direct Memory Access using CDMA
Introduction
In Zynq, multiple interconnections are available between the PS and PL sections with some providing
slower data transfer rate and others faster data transfer rate (performance). The lower performance
interconnections are slave and master types. You have used the PS master to PL slave interconnection in
the previous labs. The PS slave and PL master general purpose interconnections are available for less
performance demanding master IPs residing in the PL section. There are also four higher performance
PS slave to PL master ports available for IPs related to high-performance demanding applications such
as video and image processing. This lab guides you through the process of enabling a high-performance
slave port of the PS, adding an AXI central DMA (CDMA) controller, and performing Direct Memory
Access (DMA) operations between various memories.
Objectives
After completing this lab, you will be able to:
Enable a high-performance (HP) port of the processing system
Add and connect the CDMA controller in the programmable logic
Perform DMA operation between various memories
Procedure
This lab is separated into steps that consist of general overview statements that provide information on
the detailed instructions that follow. Follow these detailed instructions to progress through the lab.
Design Description
In this lab, you will enable the HP port of the PS and add an instance of the Central DMA (CDMA)
controller in the PL. You will also add another instance of an AXI-BRAM controller to access the second
port of the BRAM via the processor. You will connect the interrupt request line from the CDMA to the
input of the GIC of the PS. The following diagram represents the completed design (Figure 1).

Figure 1. Completed Design


Direct Memory Access using CDMA Lab Workbook

ZedBoard 4-2 www.xilinx.com/university
[email protected]
copyright 2013 Xilinx
General Flow for this Lab







Base Design Step 1
1-1. Create the following base design


Figure 1. Base Design

Enable M_AXI_GP1 port in Zynq
BRAM size =64KB (32bit x 16K)
Number of BRAM interface =1
Connect AXI BRAM controller to the M_AXI_GP1 port

Step 1:
Open the
Project
Step 2:
Configure the
Processor to
enable
S_AXI_HP0
Step 3:
Add CDMA
and BRAM
Step 4:
Create the
Wrapper and
Generate the
Bitstream

Step 5:
Generate an
Application in
SDK

Step 6:
Test in
Hardware
Lab Workbook Direct Memory Access using CDMA

www.xilinx.com/university ZedBoard 4-3
[email protected]
copyright 2013 Xilinx



Configure the Processor to Enable S_AXI_HP0 Step 2
2-1. Open the Block Design and enable the S_AXI_HP0 interface
2-1-1. Click Open Block Design in the Flow Navigator pane, and select system.bd to open the block
diagram.
2-1-2. Double-click on the processing_system7_0 instance to open its configuration form.
2-1-3. Select PS-PL Configuration in the Page Navigator window in the left pane, expand HP Slave AXI
Interface on the right, and click on the check-box of the S_AXI HP0 Interface to enable it and
click OK to close the Configuration window.
Add CDMA and BRAM Step 3
3-1. Instantiate the AXI central DMA controller.
3-1-1. Click the Add IP icon and search for Central in the catalog.
3-1-2. Double-click the AXI Central Direct Memory Access to add an instance to the design.
Direct Memory Access using CDMA Lab Workbook

ZedBoard 4-4 www.xilinx.com/university
[email protected]
copyright 2013 Xilinx
3-1-3. Click on Run Connection Automation, and select /processing_system7_1 /S_AXI_HP0.
3-1-4. Click OK to connect to the /axi_cdm_0/m_axi interface.

Figure 2. Connecting AXI Central DMA controller to S_AXI_HP0
Notice that an instance of AXI Interconnect (axi_mem_interconn) is added, S_AXI_HP0 of the
processing_system7_0 is connected to M00_AXI of the axi_mem_intercon, S00_AXI of the
axi_mem_intercon is connected to the m_axi of the axi_cdma_0 instance. Also, m_axi_aclk of
the axi_cdma_0 is connected to the net originating from FCLK_CLK0 of the
processing_system7_0.

Figure 3. Connections between the processor, axi_interconnect, and cdma
3-1-5. Click on Run Connection Automation, and select /axi_cdma_0/s_axi_lite.
3-1-6. Select /processing_system7_0/M_AXI_GP0 using the drop-down button and click OK.

3-2. Instantiate the BRAM Controller and a BRAM.
3-2-1. Click the Add IP icon and search for BRAM in the catalog.
3-2-2. Double-click the AXI BRAM Controller to add another instance to the design. Make connections
like below (Use Run Connection Automation)
Lab Workbook Direct Memory Access using CDMA

www.xilinx.com/university ZedBoard 4-5
[email protected]
copyright 2013 Xilinx


3-3. Turn OFF the SG (scatter gather) feature of the CDMA. Connect the CDMA
interrupt out port to the port of the processor.
3-3-1. Double-click on the axi_cdma_0 instance and uncheck the Enable Scatter Gather option.
3-3-2. Click OK.
3-3-3. Double-click on the processing_system7_0 instance to open its configuration form.
3-3-4. Select Interrupts in the Page Navigator window in the left pane, check Fabric Interrupts box.
3-3-5. Expand Fabric Interrupts > PL-PS Interrupts Ports, and click on the check-box of the IRQ_F2P.

Figure 5. Enabling interrupt
3-3-6. Click OK.
3-3-7. Using wiring tool, connect the cdma_introut to the IRQ_F2P port.
3-4. Using the Address Editor tab, set the BRAM controller size to 64KB.
Validate the design.
3-4-1. Select the Address Editor tab.
3-4-2. Expand the axi_cdma_0> Data section, and change the memory size of axi_bram_ctrl_1 to 64K.
Direct Memory Access using CDMA Lab Workbook

ZedBoard 4-6 www.xilinx.com/university
[email protected]
copyright 2013 Xilinx

Figure 6. Address space
3-4-3. The design should look like as shown below.

Figure 7. The completed design
3-4-4. Select Tools > Validate Design and fix errors if necessary.

Create the wrapper and Generate the Bitstream Step 4
4-1. Create the top-level HDL wrapper.
4-1-1. Select the Design pane, and click on the Sources tab. Expand the Design Sources, right-click the
system.bd and select Create HDL Wrapper.
Lab Workbook Direct Memory Access using CDMA

www.xilinx.com/university ZedBoard 4-7
[email protected]
copyright 2013 Xilinx
4-1-2. Click Copy and Overwrite when the wrapper file, system_wrapper.vhd, is generated and added
to the hierarchy. The wrapper file will be displayed in the Auxiliary pane.
4-1-3. Click on the Generate Bitstream to run the synthesis, implementation, and bit generation
processes.
4-1-4. Click Save to save the project, and Yes to run the processes.
4-1-5. When the bitstream generation process has completed successfully, select the Open
Implemented Design option and click OK.
Generate an Application in the SDK Step 5
5-1. Start the SDK by exporting the implemented design.
5-1-1. Start the SDK by clicking File > Export > Export Hardware for SDK.
The GUI will be displayed. Click on the Launch SDK box to launch the SDK session.
5-1-2. Click OK to export and Yes to overwrite the previous project created by lab3.
5-1-3. Right-click on the standalone_bsp_0 project in the Project Explorer view and select Refresh to
rebuild the project since the hardware has changed (the cdma controller was added)..
5-2. Create an empty application project, named lab4, and import the provided
lab4.c file.
5-2-1. Select File > New >Application Project.
5-2-2. In the Project Name field, enter lab4 as the project name.
5-2-3. Select the Use existing option in the Board Support Package (BSP) field, select
standalone_bsp_0 using the drop-down button, and then click Next.
5-2-4. Select the Empty Application template and click Finish.
The lab4 project will be created in the Project Explorer window of SDK.
5-2-5. Select lab4 in the project view, right-click, and select Import.
5-2-6. Expand the General category and double-click on File System.
5-2-7. Browse to the c:\xup\adv_embedded\sources\lab4 folder.
5-2-8. Select lab4.c and click Finish.
Direct Memory Access using CDMA Lab Workbook

ZedBoard 4-8 www.xilinx.com/university
[email protected]
copyright 2013 Xilinx
Test in Hardware Step 6
6-1. Connect and power up the ZedBoard. Download the bitstream and program
the FPGA.
6-1-1. Connect and power up the ZedBoard.
6-1-2. In SDK, select Xilinx Tools > Program FPGA.
6-1-3. Set the Bitstream location to (check lab4 is selected):
C:\xup\adv_embedded\labs\lab4\lab4.sdk\SDK\SDK_Export\hw_platform_0\system.bit
6-1-4. Click the Program button to program the FPGA.
6-2. Establish serial communication using an external, third party terminal
emulator programs like HyperTerminal, Tera Term. Run the lab4
application from the DDR3 memory.
6-2-1. Start a third party terminal emulator program like HyperTerminal or Tera Term. Select the
appropriate COM port and set the Baud Rate to 115200.
There is a problem with SDK Terminal communicating with the serial driver when an application
needs input. Hence you will have to use an external terminal emulator programs like
HyperTerminal or TeraTerm.
6-2-2. Select the lab4 project in Project Explorer. Right-click and select Run As > Launch on
Hardware (GDB).
Follow the menu in the terminal emulator window and test transfers between various memories.
6-2-3. Select option 4 in the menu to complete the execution or click the Terminate button ( ) on the
Console ribbon bar to terminate the execution if needed.
6-2-4. Close the SDK and Vivado programs by selecting File > Exit in each program.
6-2-5. Turn OFF the power on the board.
Conclusion
This lab led you through adding a CDMA controller to the PS so that you can perform DMA transfers
between various memories. You used the high-performance port so DMA could be done between the
BRAM residing in the PL section and DDR3 connected to the PS. You verified the design functionality by
creating an application and executing it from the DDR3 memory.
.