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Ec 1201digital Electronics

- Propagation delays in combinational logic circuits can cause unwanted glitches or hazards at the outputs. Hazards occur when different logic paths have different delays, causing intermediate output values. - Hazards can be identified using K-maps and eliminated by adding additional implicants or product terms to the logic expression. This ensures only the intended output transitions occur. - While hazards are less important for sequential circuits due to clocking, hazard elimination in combinational circuits requires adding extra logic gates, increasing circuit complexity and costs slightly. Techniques like K-maps help design hazard-free combinational logic.

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Subathra Devi Mourougane
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16 views

Ec 1201digital Electronics

- Propagation delays in combinational logic circuits can cause unwanted glitches or hazards at the outputs. Hazards occur when different logic paths have different delays, causing intermediate output values. - Hazards can be identified using K-maps and eliminated by adding additional implicants or product terms to the logic expression. This ensures only the intended output transitions occur. - While hazards are less important for sequential circuits due to clocking, hazard elimination in combinational circuits requires adding extra logic gates, increasing circuit complexity and costs slightly. Techniques like K-maps help design hazard-free combinational logic.

Uploaded by

Subathra Devi Mourougane
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EC 1201DIGITAL ELECTRONICS

A. Jawahar,
Assistant Professor, ECE Dept.
SSN College of Engineering
Phone: 044 32909855 275 (Extn : 359)
91-9444067484 (cel lphone)
Email: [email protected]
Overview
Minimum sum of products implementation reduces
costs
Propagation delays in circuits can lead to output
glitches
Hazards can be determined from K-map
Technique using K-maps to avoid hazards
Look for neighboring circles
Hazards are less of a concern for sequential circuits.
Combinational outputs settle prior to rising clock edge
Combinational Delay
Logic gates do not produce an output
simultaneously with a change in input.
There is a finite propagation delay through all
gates.
input output
input
output
time
propagation delay
Example of Combinational Hazards
Eg. Q = AB + BD if B & D are 1 then Q should be 1
but because of propagation delays, if B changes
state then Q will become unstable for a short time,
as follows:
A
B
D
Q
(C)
A
D
B
(C)
Q
High
High
glitch
Hazards/Glitches
Hazards/glitches: unwanted switching at the outputs
Occur when different paths through circuit have different propagation
delays
Dangerous if logic causes an action while output is unstable
- May need to guarantee absence of glitches
Usual solutions
1) Wait until signals are stable (by using a clock): preferable (easiest to
design when there is a clock synchronous design)
2) Design hazard-free circuits
1
0 0
1 1
0 0
1 1
0 0
0
1 1
Types of Hazards
Static 1-hazard
Input change causes output to go from 1 to 0 to 1
Static 0-hazard
Input change causes output to go from 0 to 1 to 0
Dynamic hazards
Input change causes a double change
from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0
Hazard Elimination
Hazards like these are best eliminated logically.
The Karnaugh Map of the required function gives
one method.
Covering the hazard causing the transition with a
redundant product term (AD) will eliminate the
hazard. The hazard free Boolean equation is:
Q = AB+BD+AD
00 01 11 10
0 0 0 0 1
1 0 1 1 1
D
AB
AB
BD AD
Static Hazards
Due to a literal and its complement momentarily
taking on the same value
Thru different paths with different delays and reconverging
May cause an output that should have stayed at the
same value to momentarily take on the wrong value
Example
F
A
B
S
S'
F
hazard
static-0 hazard static-1 hazard
A
S
B
S'
B2
A
C
B1
F
hazard
dynamic hazards
B3
A
C
B
F
1
2
3
Dynamic Hazards
Due to the same versions of a literal taking on
opposite values
Thru different paths with different delays and reconverging
May cause an output that was to change value to
change 3 times instead of once
Example:
Hazard Example
Logic gates do not produce an output
simultaneously with a change in input.
There is a finite propagation delay through all gates.
Hazard Removal for Static 0
Locate boundaries between circles
Add an extra circle (product term) to eliminate
hazard
Note: addition of term does not lead to minimum
sum of products implementation.
Hazard Removal Result
Addition of extra AND gate and extra OR gate input
Generally does not slow down circuit
Not as important for sequential circuits
Summary
When inputs change, intermediate values created
Could lead to incorrect circuit behavior
Hazards can be determined from K-map
Technique using K-maps to avoid hazards
Use additional implicants
Hazards not as important for sequential design
Hazard removal requires additional hardware

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