ENGI 3861 Digital Logic

Arithmetic Devices - 1
V. ARITHMETIC DEVICES

(a) Addition and Subtraction

- in binary: addition/subtraction similar to decimal

e.g., addition
! carries
1 1 0 1 1 1
+ 0 1 1 1 0 1


where 1
1 1 1
+ 0 + 1 + 1
1 10 11


no carry carry carry

e.g., subtraction
! borrows
1 1 0 1 1 1
" 0 1 1 1 0 1



where borrow no borrow no borrow



1
1
0 1 1
" 1 " 1 " 0
1 0 1
ENGI 3861 Digital Logic
Arithmetic Devices - 2
What about 011101 " 110111 = negative?

How to represent negative numbers in binary? Many ways!


Signed Magnitude

- use extra bit to represent a sign bit directly

e.g., +45
10
#



"45
10
#




$ leftmost or most significant bit (msb) is sign bit

$ remaining bits are magnitude

- for an n-bit signed-magnitude integer x:

" (2
n"1
" 1) % x % + (2
n"1
" 1)

with 2 representations of zero (+ve and "ve)

ENGI 3861 Digital Logic
Arithmetic Devices - 3
- to add 2 SM values, x and y, to produce z = x + y, a digital circuit
would need to execute the following logical procedure:




















- to subtract, simply change sign of y, so z = x + ("y)

It turns out that this is more complex than necessary if we choose
another representation for negative numbers.


ENGI 3861 Digital Logic
Arithmetic Devices - 4
Twos Complement

Consider n-bit positive binary integer B of value < 2
n"1
:

" B represented as 2
n
" B

but 2
n
" B = (2
n
" 1 " B) + 1
= (11111
2
" B) + 1
= (complement each bit of B) + 1 (*)

- leftmost bit indicates sign (0 $ +ve, 1 $ "ve), but is not a
sign bit as in signed magnitude

Two's complement representation:
+ve integer from 0 to +2
n-1
" 1
$ same as unsigned binary representation with leftmost
bit set to 0
"ve integer from "2
n-1
to "1
$ take 2s complement of +ve representation as per (*)

(a) What is the 10-bit 2s complement representation of +27?




(b) Find the 8-bit 2s complement representation of "106.








ENGI 3861 Digital Logic
Arithmetic Devices - 5
(c) Consider the 6-bit 2s complement representation of a number:

110100
2


What is the signed decimal value of the number?
(This is a "ve number. To determine the magnitude, take 2s
complement.)







(d) Perform the 2s complement operation on the 8-bit 2s
complement representation of +0.







(e) Consider 2s complement representation: 10000000
2


Take the 2s complement of the number and determine the
signed decimal value of the number above.







ENGI 3861 Digital Logic
Arithmetic Devices - 6
- to convert to decimal could use

D =

where b
n-1
b
n-2
b
1
b
0
is 2s complement representation.

e.g., 10010100
2
=

Note range of integers that can be represented by n-bit 2s
complement representation is:

"2
n"1
% D % +2
n"1
" 1

Convince yourself for n = 4!

One's Complement

Consider n-bit positive binary number B of value < 2
n"1
:

" B represented as 2
n
" 1 " B = (11111
2
" B)
= complement each bit of B

e.g., Take one's complement of

01101010
2
(+106) $ ("106)

00000000
2
(0) $ (0)

- positive numbers same as 2s complement and signed magnitude

- zero is either 00000 or 11111

- negation is easier than 2s complement but adder design is more
complex.
ENGI 3861 Digital Logic
Arithmetic Devices - 7
Twos Complement Addition and Subtraction

Consider n = 3

Signed Decimal 2s Complement
" 4 100
" 3 101
" 2 110
" 1 111
0 000
+ 1 001
+ 2 010
+ 3 011

- counting up from " 4 is equivalent to adding 1 in each step and
ignoring carry past MSB

- hence, addition in 2s complement
$ add normally and toss out carry beyond MSB

e.g., 0 0 1 1 0 1 1 1 55
+ 0 1 0 0 0 0 1 1 + 67





1 0 1 0 1 1 1 1 " 81
+ 0 1 1 0 1 0 0 1 + 105





ENGI 3861 Digital Logic
Arithmetic Devices - 8
- overflows can occur if two numbers of same sign are added

e.g.,









$ if sign bit changes & overflow

- subtraction: z = x ! y

subtrahend
minuend

$ negate subtrahend y (i.e., take 2s complement) and add to
minuend x

e.g.,










ENGI 3861 Digital Logic
Arithmetic Devices - 9
- only one addition required if y is complemented bit-by-bit and
then +1 used as carry-in

$ 2s complement is very efficient for addition/subtraction


Ones Complement Addition and Subtraction

- add normally and if there is a carry out of sign, then add +1
(i.e., end-around carry)

e.g.,






- subtraction: complement subtrahend and add


(b) Binary Codes

- numbers, characters, and other data can be represented in n-bit
codewords or symbols

Binary Coded Decimal (BCD)

- represent each decimal digit by 4 bits

0 $ 0000, 1 $ 0001, , 8 $ 1000, 9 $ 1001

so 73
10
$ 01110011

- addition: if binary addition exceeds 9 (1001), add 6 (0110)
ENGI 3861 Digital Logic
Arithmetic Devices - 10

e.g., 73 $ 01110011
+ 18 $ + 00011000











Parity Code

- bit is added to binary representation of data to ensure either
even parity or odd parity

even parity & # ones even
odd parity & # ones odd

- if parity is to be applied to system, one of either even or odd
parity must be chosen and used

e.g., 7 bits of data 1011101

with even parity 11011101

data
parity

with odd parity 01011101

ENGI 3861 Digital Logic
Arithmetic Devices - 11
- parity is used to detect errors when data transmitted through
communications channel or retrieved from memory

e.g., Assume a system is using even parity and the word 11011101
which includes 1 parity bit (the leftmost bit) and 7 data bits
(the rightmost 7 bits) is transmitted through a noisy
communications channel as follows:










$ receiver is expecting a byte with an even parity and yet
the # ones in the received byte is odd & an error must
have occurred in at least one bit

What if errors occur in two bits? An even number of bits? An odd
number of bits?


ENGI 3861 Digital Logic
Arithmetic Devices - 12
ASCII (American Standard Code for Information Interchange)

- 7 bit code to represent numbers, letters, punctuation, etc..
$ 128 symbols in total

e.g., Character ASCII Codeword (hex)
09 3039
AT 4154
ai 6169
} 7D
$ 24
+ 2B
etc.


- very common way to represent and store text

- often add parity bit as 8
th
bit
$ can be used to look for errors in data recovered from
memory or transmitted through communication channel

- 8-bit ASCII codeword + parity # 1 byte
$ convenient data word
$ most computer systems and digital systems with memory
have memory organized in bytes or multiples of bytes
(e.g., 32-bit words common in computers)







ENGI 3861 Digital Logic
Arithmetic Devices - 13
(c) Adders, Subtractors, and ALUs

Adders

How do we add 2 unsigned binary numbers using digital
hardware?

recall process: 1 0 1 1 & each column requires 2 inputs
1 1 0 1 plus carry in to produce
sum bit and carry out

Half Adder: (does not accept carry in)


















XY S C
00
01
10
11
ENGI 3861 Digital Logic
Arithmetic Devices - 14
But what about carry in?

Full Adder: (accepts carry in)













S =

C
OUT
=


(Do it yourself using K-map!)





X Y C
IN
S C
OUT
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
ENGI 3861 Digital Logic
Arithmetic Devices - 15
Ripple Adder X
3
X
2
X
1
X
0
+ Y
3
Y
2
Y
1
Y
0









- iterative circuit $ simple but slow since carry needs to propagate
through all FAs

- could make faster by using 2 level combinational logic but
S
3
= f(X
0
, , X
3
, Y
0
, , Y
3
, C
0
)
& many gates, especially as adder size increases

Carry Lookahead Adder

concept:





ENGI 3861 Digital Logic
Arithmetic Devices - 16
- we say that when stage i produces a carry out (C
i+1
= 1)
independent of C
i
, the carry is generated by:

G
i
= X
i
'Y
i
(not dependent on C
i
)

- when stage i produces a carry out (C
i+1
= 1) because C
i
= 1, we
say that the carry is propagated when:

P
i
= X
i
+ Y
i
(since if X
i
= 1 or Y
i
= 1 produces
C
i+1
= 1 if C
i
= 1)

- so C
1
=

C
2
=

C
3
=

C
4
=



- each equation for C
i
has 3 levels of delay: 1 for P/G and 2 for
equations

- MSI adders such as 74x283 can use 4-bit CLA adder and then
larger adders can use MSI adder as building block in iterative
(i.e., ripple) adder & group ripple adders

$ see Figures 6.87 and 6.89

- generally faster but more and larger gates than ripple adder


ENGI 3861 Digital Logic
Arithmetic Devices - 17
Subtractors (for unsigned binary subtraction)

Full Subtractor

difference D = X " Y " B
IN


B
OUT
# borrow from next bit













D = but also D =

B
OUT
=

- consider K-map for B
OUT
(








& B
OUT
( =
X Y B
IN
D B
OUT

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
0
10 11 01
Y B
IN

00
X




ENGI 3861 Digital Logic
Arithmetic Devices - 18
- compare D / B
OUT
( to S / C
OUT
from full adder

D = S =

B
OUT
( = C
OUT
=

- equations similar with

C
IN
$ B
IN
(, Y $ Y(, and S $ D, C
OUT
$ B
OUT
(

- so can build ripple subtractor using full subtractor similarly to
ripple adder using full adder

- alternatively, can use full adder to replace full subtractor






e.g., 4-bit ripple subtractor








- of course, to do subtraction, X " Y, using signed number
representation such as twos complement, simply need to
convert Y to 2s complement representation and add
ENGI 3861 Digital Logic
Arithmetic Devices - 19
Arithmetic Logic Unit (ALU)

- MSI device to execute word-wise arithmetic or logical operations

e.g., 74x181 4-bit ALU
$ See Table 6.70 and Figure 6.90 in text.

(d) Parity Circuits

- recall 2-input XOR, F = X ) Y

gate truth table

XY F
00 0
01 1
10 1
11 0


SOP circuit NANDs-only circuit












(Can you show?)
ENGI 3861 Digital Logic
Arithmetic Devices - 20
- 3-input XOR, F = X ) Y ) Z

gate truth table

XYZ F
000
001
010
011
100
101
110
111

F = 1 when XYZ have odd number of ones

& F # odd parity and F(# even parity

- 8-bit parity check














ENGI 3861 Digital Logic
Arithmetic Devices - 21
(e) Comparators

Equality Comparator $ compares 2 binary words for equality

- one approach: parallel comparator












- another approach: iterative comparator















IC will be slow since signals need to ripple through cascaded CMP
components
ENGI 3861 Digital Logic
Arithmetic Devices - 22
Magnitude Comparator (An Iterative Design)

- determines if X > Y, when X and Y are 2 n-bit unsigned binary
numbers $ building block is 1-bit magnitude comparator

















ENGI 3861 Digital Logic
Arithmetic Devices - 23
$ 4-bit iterative magnitude comparator
































- parallel 4-bit magnitude comparator design is achievable
$ faster, but larger