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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO. 1, JANUARY/FEBRUARY 1998

The Effect of DC Offset on Current-Operated Relays

Norman T. Stringer, Senior Member, IEEE

Abstract When a fault occurs on a power system, one or

more phases will experience dc offset. This dc component, which
will decay dependent on the L=R time constant of the system,
can produce saturation in the current transformers, as well as
the input current transformers of the protective relays sensing
the fault. In addition, when the fault current is interrupted,
the resulting dc tail can maintain the current above the relays
pickup setting for a time dependent on the current transformer
secondary circuit L=R time constant. This paper discusses this
phenomenon and how it can affect the operation of two types of
current-operated relays.
Index Terms Current-operated relays, current transformer
saturation, dc offset, dc tail, relay performance.
Fig. 1. Simple RL circuit.

I. INTRODUCTION

HE application of protective relays to the power system

requires an accurate representation of the primary fault
current in the secondary of the current transformers [1],
[3]. However, transients that occur upon fault inception and
clearing can affect the performance of current-operated relays.
Among these transients is the dc component of the ac current,
resulting from the instantaneous change in fault current.
Consider the RL circuit shown in Fig. 1. When the switch is
closed, the inductance of the coil will prevent an instantaneous
change in current through the circuit. The voltage across the
coil will then be equal to the impressed EMF as determined by
Kirchhoffs voltage law, or
V. The current across
the resistor will then begin to increase, while the voltage across
the inductor decreases. Therefore, the voltage according to
Kirchhoffs voltage law is
(1)
Solving the first-order differential for

gives

(2)

Paper ICPSD 9723, presented at the 1997 IEEE/IAS Industrial and

Commercial Power Systems Technical Conference, Philadelphia, PA, May
1214, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY
APPLICATIONS by the Power Systems Protection Committee of the IEEE
Industry Applications Society. Manuscript released for publication August
6, 1997.
The author is with Basler Electric Company, Houston, TX 77077 USA (email: [email protected]).
Publisher Item Identifier S 0093-9994(98)01205-5.

Equation (2) can be further defined as

(3)
where
(4)
(5)
and the time constant

is
(6)

In a highly inductive circuit where is much larger than ,

the current is at or near its maximum value when the voltage
is zero. Therefore, if the applied voltage waveform is at or
near zero when switch
is closed, the circuit is required to
provide an instantaneous change in current. To provide this
instantaneous ac current change, a dc current of equal and
opposite magnitude is produced to maintain the total initial
current at zero, as required by (2). The dc component of the
current will decay to zero as a function of the time constant of
the circuit, given by
. The more inductive the circuit,
the longer the decay period. The components of this current
waveform are shown in Fig. 2 [2].
Two specific occurrences in a polyphase power system in
which the phenomenon of the dc component can affect the performance of current operated protective relays are as follows:
1) when a fault occurs causing a severe increase in current
and 2) when a fault current is interrupted causing a severe
decrease in current. Other papers have explored waveform
distortion and its effect on protective relays [6][10]. This
paper considers the specific case of a dc component in the

00939994/98$10.00 1998 IEEE

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31

Fig. 2. Components of an asymmetrical current waveform.

Fig. 3. Equivalent circuit of a current transformer.

ac current and its effects on the operation of time-overcurrent

and breaker failure relays.
II. CURRENT TRANSFORMER PERFORMANCE
The equivalent circuit of a current transformer is shown in
Fig. 3. The resistances
and
are the dc resistance of the
primary and secondary coils of the transformer, respectively.
There is a definite amount of flux that links each coil of the
primary and secondary that does not pass through the core.
This leakage flux is represented by an inductance
in the
primary circuit and
in the secondary.
The resistance
represents the hysteresis and eddycurrent losses within the core due to an ac flux. The inductance
is associated with the magnetization of the core. The
secondary-exciting current
is a function of the secondaryexciting voltage and the secondary-exciting impedance
where

Fig. 4. Secondary-excitation characteristic curves for a typical multiratio

class C current transformer.

The time to saturation is a function of the maximum flux

density of the transformer core. Factors that affect the maximum flux density are the magnitude, duration, and waveform
of the primary fault current, as well as any residual flux in
the transformers core. The maximum flux density capacity
can be reduced as a result of residual magnetism. Therefore,
an increase in flux above the point of saturation will begin
to cripple the secondary output of the current transformer and
produce ratio errors, as shown in Fig. 5. Of major concern
is the dc component of the primary fault current, which
influences buildup of residual core flux [7].
From the simplified equivalent circuit in Fig. 3, the voltage
and current equations are
(8)

(7)
The relationship between these factors, known as the
secondary-excitation characteristic, is shown in Fig. 4. These
curves assume that the voltage developed across the secondary
can drive a current of not more than 20 times the rated through
a secondary burden with no more than 10% ratio correction.
The knee of the characteristic curve is generally considered
the point of saturation where the flux required to produce
the secondary current exceeds the saturation flux density of
the transformer core. Accordingly, ANSI/IEEE defines this
knee point as the intersection of the excitation curve with
a 45 tangent line. However, according to Conner, Wentz,
and Allen [11], the point of saturation occurs significantly
above the knee point of the exciting curve. International
Electrotechnical Commission (IEC) more accurately defines
the point of saturation as the intersection of straight lines
extended from the saturated and nonsaturated portions of the
excitation curve.

(9)
Substituting (9) into (8) and solving for the derivative of
yields
(10)
Equation (10) is the current that the relay will see for an input
current of . Assuming that the primary current is fully offset,
given by
(11)
then, if the transformer saturates due to the primary current,
the secondary current may not have its current zero at the
same time as the primary current. Therefore, when the primary
current is interrupted by a circuit breaker at current zero, the
secondary current may be at a value other than zero, resulting
in a decaying dc current similar to that shown in Fig. 6 [5].

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO. 1, JANUARY/FEBRUARY 1998

Fig. 5. Distortion in secondary current due to dc saturation.

Fig. 6. Waveform resulting from current interruption.

This dc current, or dc tail, will decay as a function of the

time constant of the transformers secondary circuit.
These resultant waveforms, dc offset and dc tail, will have
varying effects on overcurrent relays depending on the specific
application and relay design. These effects will be discussed
in Section III.
III. EFFECTS ON RELAY PERFORMANCE
The effect of asymmetrical current in overcurrent protective
relays, whether from the initial dc offset or the dc tail
resulting from current interruption, can produce undesired
results. Not all applications nor all relays will be affected
by these anomalies; however, each such situation should be
reviewed to maintain the security and dependability of the
protection system and eliminate possible problems.
Time-overcurrent relays are applied in many applications
across the power system from primary feeder protection to
transformer backup protection and fault detectors for breaker
failure schemes. They are generally designed to operate properly under a certain level of current waveform distortion [7].
However, they do not all respond to decaying dc currents
similarly.
Saturation caused by the asymmetrical dc primary current
can severely impede the secondary current output to the relay.
The secondary current will normally reach its peak during the
first half cycle as saturation occurs. During saturation (23
cycles), the secondary output could be near zero. Therefore,
for relays that require more than a half cycle to measure current
magnitude, the secondary output could be less than the pickup
value, effectively increasing the relays setting. After the first
cycle or so, the secondary current would begin to recover as
a result of the decaying dc component, as shown in Fig. 5.
As shown by Elmore, Kramer, and Zocholl [6], some microprocessor relay designs utilize low-pass antialiasing filters
and gain amplifiers, along with digital sampling techniques

to convert the analog current signal into a digital format

for processing. The algorithms used in this process typically
have little response to dc offset. Other microprocessor relay
designs that use rms measurement typically do not have filters.
Therefore, the waveform is sampled a sufficient number of
times to accurately reproduce the signal. The result will include
dc offset.
Negative-sequence overcurrent relays are typically designed
to ignore the positive-sequence component at 60 Hz. Depending on relay design, some relays cease to be negative-sequence
only at frequencies other than 60 Hz. Upon primary current
interruption, the dc tail acts somewhat like a low-frequency ac
current [1]. The negative-sequence relay will not operate on a
balance three-phase fault; however, the dc tail magnitude could
be above the normally low relay pickup settings. Although
this is not crucial, since the fault has already cleared, it could
produce nuisance targets.
DC tail generally affects only those relays that coordinate on
current dropout. In this situation, the dc tail would increase the
time to current dropout, possibly leading to relay misoperation.
The greater the trapped flux in the transformer core and the
greater the inductance in the secondary circuit, the longer will
be the decay time.
Breaker failure relays are an example of this application.
Breaker failure schemes are achieved using fault detectors
in conjunction with timers, or using multifunction solid-state
relays that combine fault detectors and timers into one device.
Both methods approach the protection issue in much the same
manner. Once a fault occurs, if the fault current remains after
a predetermined time, an output will provide tripping of all
remote breakers required to disconnect from the fault. If the
fault current is interrupted before the timer has expired, the
breaker failure relay will reset. Fig. 7 shows the timing logic
for this scheme with both normal operation and failed breaker
condition.
This timing chart indicates the margin necessary between
the point of current interruption and breaker failure output.
Under normal operating conditions, the circuit breaker would
interrupt the fault, allowing the current to fall below the
fault detector dropout before reaching the end of the timing
margin. The timing margin must allow for intermittently
slower breaker operation and system transients, including dc
tail current. If the timing margin is set too short and the dc tail
is significant, the current could remain above the dropout of the
fault detector, resulting in relay operation. Since the dc offset
component only lasts a few cycles, applications with timing
margins set for 20 cycles or higher are typically not affected,
regardless of the relays response to dc offset. However, for
applications that require faster clearing times, the dc offset may
be a factor. This is especially true in applications where the
values are typically large, such as power plants, resulting
in longer decay times.
A comparison of two relays applied in this application are
shown in Fig. 8(a) and (b). These graphs depict the input
current to the relay and the signal within the relay at the point
where a trip decision is made. The same input current was
applied to both relays but are shown in two different time
scales in the figure.

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33

Fig. 7. Typical timing logic for breaker failure protection.

Fig. 8(a) shows the operation of an electromechanical

breaker failure relay. The internal current signal goes high
when the input is applied. When the input current is interrupted
at a zero crossing, the internal signal remains high for an
additional 34.4 ms. This delay is a result of the dc tail
component of the input signal at interruption and must be
considered in the timing margin setting of the breaker failure
relay.
Fig. 8(b) shows the operation of a solid-state breaker failure
relay. This relay, when enabled by the timer, produces an
internal negative-going pulse at each reference crossing of
the input current. When the primary current is interrupted,
the secondary current results in a dc tail decaying toward
zero. Since the current will not cross the reference level, no
additional negative pulses will occur. A negative-going edge
is required from the current detector after timer expiration
to provide an output. If the current crosses the reference
level after the timer has expired, a negative pulse will occur
and the relay will close its output contacts. If the current is
interrupted before the timer expires, no additional pulses will
occur, resulting in instantaneous reset. Therefore, this relay is
not affected by dc offset.

(a)

IV. CONCLUSION
This paper has presented a brief discussion of current
transformer performance and the effect that the dc component
of an asymmetrical fault current will have on select currentoperated protective relays. It has been shown that dc tail,
caused by the instantaneous interruption of input current, can
delay the dropout of the fault-detector function of the relay.
It is also clear from the discussion that the two specific
breaker failure relays react differently under the same input
waveform. If applied in a system requiring fast fault clearing
with minimum time margins, the electromechanical relay could
result in misoperation.
Other relay types may also experience misoperation as a
result of dc offset or dc tail and are considered in the references
given below.
It is the goal of the relay engineer to provide secure and
dependable protection for the power system. Current transformer saturation caused by asymmetrical current, specifically
dc offset and dc tail, can lead to degradation of security

(b)
Fig. 8. (a) Decay time measurement with dc offset on electromechanical
relay. (b) Decay time measurement with dc offset on solid-state relay.

and dependability. Various relays are designed to operate

accurately with some level of current waveform distortion.

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 34, NO. 1, JANUARY/FEBRUARY 1998

However, designs will vary from relay type to relay type

and from manufacturer to manufacturer. In addition, current
transformer designs will vary, leading to inconsistent values
in ratio correction. Each application should be considered to
ensure that the equipment and system performance meets the
need of the user.

[12] J. A. Brogan, G. R. Dalke, and N. T. Stringer, How can current dropout

affect breaker failure timing margins? presented at the 49th Annu.
Texas A&M Protective Relay Conf., College Station, TX, Apr. 1996.
[13] P. Lerley, J. Kanuchok, and M. Ransick, Flexible breaker failure and
protection relaying, Electric Council of New England, Apr. 1996.
[14] N. T. Stringer and D. Waser, An innovative method of providing total
breaker failure protection, IEEE Trans. Ind. Applicat., vol. 32, pp.
10111016, Sept./Oct. 1996.

REFERENCES
[1] J. L. Blackburn, Protective Relaying, Principles and Applications. New
York: Marcel Dekker, 1987.
[2] S. H. Horowitz and A. G. Phadke, Power System Relaying. New York:
Wiley, 1992.
[3] C. R. Mason, The Art and Science of Protective Relaying. New York:
Wiley, 1956.
[4] Requirements for Instrument Transformers, ANSI/IEEE Standard
C57.13, 1978.
[5] IEEE Power System Relay Committee, Summary update of practices on
breaker failure protection, IEEE Trans. Power App. Syst., vol. PAS-101,
pp. 551563, Mar. 1982
[6] W. A. Elmore, C. A. Kramer, S. E. Zocholl, Effect of waveform
distortion on protective relays, IEEE Trans. Ind. Applicat., vol. 29,
pp. 404411, Mar./Apr. 1993.
[7] IEEE Power System Relay Committee, Transient response of current
transformers, IEEE Pub. 76CH11304-4 PWR, Nov./Dec. 1977.
[8] Y. C. Kang, J. K. Park, S. H. Kang, A. T. Johns, and R. K. Aggarwal, An algorithym for compensating secondary currents of current
transformers, IEEE Publication 96 WM 064-6 PWRD, 1996.
[9] D. A. Bradley, C. B. Gray, and D. OKelly, Transient compensation of
current transformers, IEEE Trans. Power App. Syst., vol. PAS-97, pp.
12641271, July/Aug. 1978.
[10] J. G. Andrichak, and J. Cardenas, Global digital bus protection overcomes CT constraints, presented at the 49th Annu. Texas A&M
Protective Relay Conf., College Station, TX, Apr. 1996.
[11] E. C. Wentz and D. W. Allen, Help for the relay engineer in dealing
with transient currents, IEEE Trans. Power App. Syst., vol. PAS-101,
pp. 519525, Mar. 1982.

Norman T. Stringer (M82SM95) received the

B.S. degree in electrical engineering from the University of Texas, Arlington, in 1982 and the M.B.A.
degree in engineering management from the University of Dallas, Dallas, TX, in 1985.
His professional career began with TUElectric,
where he was an Engineer in Power System Protection. After nine years with TUElectric, he served
as a Regional Technical Manager at ASEA Electric,
where he was responsible for applications support of
all transmission and distribution products. In 1989,
he joined Brown & Root USA, Inc., Houston, TX, as a Senior Engineer in
the Engineering Technical Services Group. In 1991, he joined Basler Electric
Company, Houston, TX, as an Applications and Sales Manager for the Utility
Products Division. He is currently the Southwest Regional Sales Manager.
Mr. Stringer is a member of the IEEE Power Engineering and IEEE
Industry Applications Societies. He is actively involved in the Industrial and
Commercial Power Systems (I&CPS) Department of the Industry Applications
Society. He serves on several committees in various capacities, including
Chairman of the I&CPS Awards and Recognition Committee and the Power
System Protection Committee, Chairman of the Medium-Voltage Protection Subcommittee, Protection and Coordination Subcommittee, Chairman of
Chapter 14 and Co-Chairman of Chapter 4, IEEE Standard 242 (Buff Book),
and member of the Refining Subcommittee of the Petroleum and Chemical
Industry Committee. Mr. Stringer is a Registered Professional Engineer in the
State of Texas.