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Design & Analysis of High Speed Low and Area CMOS Based Comparator With Different Architectures

A High Speed CMOS Comparator is proposed to have low area and high speed. It uses the conventional data to form a new data for improvement in design. The comparator is having low offset voltage but cannot reduce to zero due to internal parameters. The circuit designing obtained from Hysteresis effects obviously having positive feedback. The proposed structure is also having strong immune against noise and offset voltage. The required area is reduced as compared to other structure is 2µm. Structures are proposed on nanometer technology. Simulated Circuit exhibited low propagation delay, high speed and low area. These are compared for digital devices to get superior circuits.

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190 views

Design & Analysis of High Speed Low and Area CMOS Based Comparator With Different Architectures

A High Speed CMOS Comparator is proposed to have low area and high speed. It uses the conventional data to form a new data for improvement in design. The comparator is having low offset voltage but cannot reduce to zero due to internal parameters. The circuit designing obtained from Hysteresis effects obviously having positive feedback. The proposed structure is also having strong immune against noise and offset voltage. The required area is reduced as compared to other structure is 2µm. Structures are proposed on nanometer technology. Simulated Circuit exhibited low propagation delay, high speed and low area. These are compared for digital devices to get superior circuits.

Uploaded by

ijeteeditor
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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International Journal of Emerging Technologies and Engineering (IJETE)

Volume 1 Issue 7, August 2014, ISSN 2348 8050

Design & Analysis of High Speed Low and Area CMOS based Comparator
with Different Architectures
Sumit Singh* Parikha Chawla**
*M.Tech Scholar, CBS Group of Institutions, Jhajjar
**Asst. Prof. ECE Deptt.,CBS Group of Institutions, Jhajjar

ABSTRACT
A High Speed CMOS Comparator is proposed to have
low area and high speed. It uses the conventional data
to form a new data for improvement in design. The
comparator is having low offset voltage but cannot
reduce to zero due to internal parameters. The circuit
designing obtained from Hysteresis effects obviously
having positive feedback. The proposed structure is
also having strong immune against noise and offset
voltage.
The required area is reduced as compared to other
structure is 2m. Structures are proposed on
nanometer technology. Simulated Circuit exhibited
low propagation delay, high speed and low area. These
are compared for digital devices to get superior
circuits.

that percent a noisy input from producing false


transitions[7]-[12]. Hysteresis based comparator uses
in digital logic circuit. The circuit can be implemented
using 80nm technology. The above technique is used
in latched comparator & hysteresis comparator[12].

2. SYSTEM STRUCTURE FOR DIFFERENT


COMPARATORS
Hysteresis-Based Comparator
Fig. 2.1 shows the circuit diagram for the model of 3Stage comparator. As we have already seen from the
circuit diagram. It uses a differential self-biased
amplifier with Output driver. It also consists of bias
current source and preamplifier to perform the required
functions[1]-[8].

Keywords:
CMOS,
OFFSET,COMPARA-TOR,
NANOMETER, MOSFET.

1. INTRODUCTION
The basic Cmos Comparator & its schematic symbol
with operation of a voltage comparator are shown in
Fig 1.1. The comparator can be thought of as a
decision making circuit based on input conditions.
fig

Fig 2.1: Circuit Diagram for Hysteresis-Based


Comparator[6].
Performance
Comparator

Fig 1.1: Comparator


where Vp is Non-Inverting input, Vn is Inverted Input
& Vo is output voltage of comparator[3]. It is seen that
the input to a comparator contains a large amount of
noise; the output will be erratic when Vin is near the
trip point. One way to reduce the effect of noise is by
using a comparator with positive feedback. The
positive feedback produces two separate trip points

Analysis

of

Hysteresis-Based

The input voltage is applied to the inverting input.


Because the feedback voltage is aiding the input
voltage, the feedback is positive. A comparator using
positive feedback like this is usually called a Schmitt
trigger. When the comparator is positively saturated, a
positive voltage is feedback to the non-inverting input.
This positive feedback voltage holds the output in the
high state[9].
182

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International Journal of Emerging Technologies and Engineering (IJETE)


Volume 1 Issue 7, August 2014, ISSN 2348 8050

Latched Based Comparator


The basic circuit diagram is shown in fig2.6. A
dynamic latch is defined as the memory unit that stores
the charge on the gate capacitance of the inverter.
Basic operation is based on the 2 phase of the clock.
First phase clock is high & switching transistor closes
& set to certain DC voltage around midpoint of VCC
[1]. In second phase inverter pair amplifies the
imbalance charge into digital voltage level.
Fig 2.2: Comparator responses to a noisy input [9].

Performance
Comparator

Analysis

of

latched-based

The main parameters that affect the performance are:


Kick-Back Noise & Regenerative Time constant of
Latch. Isolation Transistors, preamplifier based design
or Neutralization is some commonly implemented
Techniques used to overcome from Kick-Back Noise.
Regenerative time constant can be reducing by
increasing time constant RC factor by changing gain of
inverter [5].
Fig 2.3: Comparator response to a noisy input when
hysteresis is added [9].

Fig 2.6 shows latched based comparator [2]


The Systematic circuit diagram is shown in fig 2.7.
Designing and simulation of circuit is done in Or CAD
or PSpice from Cadence Design System, Inc.
Fig 2.4: Transient Analysis circuit diagram of
Hysteresis-Based Comparator.

Fig 2.5: Extracted Layout of Hysteresis based


comparator.

Fig 2.7: Systematic diagram of Latched based


Comparator.
183
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International Journal of Emerging Technologies and Engineering (IJETE)


Volume 1 Issue 7, August 2014, ISSN 2348 8050

From the simulation mode we can obtained the


different parameters value like voltage, current, time
delay, area of layout etc.

Fig 3.1: Output Waveform of Comparator and


Decision Circuit

Fig 2.8: Extracted Layout of Latch-based Comparator

The circuit is analysis & the complete waveform is


shown in fig 2.2 above. It is seen from the simulation
result the switching speed is increased & area becomes
low.

3. RESULT ANALYSIS
The simulation result for Hysteresis-Based comparator
is given in Table 1.
PARAMETER
DELAY
SPEED
POWER
DESSIPATION
AREA

VALUE
OBTAINED
0.407ns
9.32GHz
1.99 mW
Fig.3.2: Transient Analysis Waveform
2

189.787m

4. CONCLUSION
It shows that Vir = 153.7ps and Vor = 0.224ns of first
cycle and Vir = 5.630ns and Vir = 5.396ns in second
cycle. The total average delay can be obtained by
taking the difference in time of first and second clock
cycle and divided by 2.
Table 2 Simulation result of Latch-based comparator
PARAMETER
DELAY
SPEED
POWER
DESSIPATION
AREA

VALUE
OBTAINED
0.05485ns
8.81GHz
1.74mW
166.32m2

It shows that Vir = 0.0150ns and Vor = 0.0971ns of


first cycle and Vir = 5.224ns and Vir = 5.50ns in
second cycle. By modification is done as per 90nm
technology.
The circuit has following analysis

The simulation result shows that Time delay in case of


Hysteresis-Based comparator is 0.407nanoseconds
while in case of Latch-based comparator it is
0.05485nanoseconds. The total decrease in time in
latch-based comparator is about 13.40% to that of
hysteresis-based comparator.
Power dissipation is 1.99mW & 1.74mW in hysteresisbased comparator and latch-based comparator
respectively. It is clearly seen from the above result
that total power dissipation is decreased. The total area
of the layout in Latch-based comparator is reduced
upto 12.30% from its counterpart hysteresis-based
comparators case.
References
[1]. Journal on Design of Low power High Speed
CMOS Comparator for A/D Converter Application
by Shubhara Yewale, Radheshyam Gamad, Published
Online April 2012.
[2]. International Journal on Design and Simulation of
a High Speed CMOS Comparator by Smriti
Shubhanand, Dr. H.P. Shukla and A.G. Rao at
184

www.ijete.org

International Journal of Emerging Technologies and Engineering (IJETE)


Volume 1 Issue 7, August 2014, ISSN 2348 8050

National Institute of Electronics and Information


Technology, Gorakhpur.

Bibliography

[3]. P Philip E. Allen and Douglas R. Holberg, CMOS


Analog Circuit Design (oxford University Press, Inc,
USA, 2002), 2nd edition, pp 259-397).
[4]. Noor Aizad, Design and implementation of
comparator for sigma-delta modulator.
[5]. B.Razavi and B.A.Wooley, Design Techniques
for High-Speed High-Resolution Comparators, IEEE
J. Solid-State Circuits, vol. SC-27, pp.1916-1926, Dec
1992.
[6]. Allert H.P. Le, A. Zayegh, and J. Singh,
"Performance analysis of optimized CMOS
comparator," Electronics Letter, vol. 39, pp. 833-835,
May 2003
[7]. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, A
0.35m CMOS Comparator Circuit for High- Speed
ADC Applications, IEEE International Symposium
on Circuits and Systems, pp. 6134-6137, May 2005

Sumit Singh, completed


B.Tech degree in EIC department from Young Man
Christian Association (Y.M.C.A) Institute of
Engineering Faridabad, Haryana, India. Currently
studying at CBS Group of Institutions Fatehpuri,
Jhajjar as an M.Tech scholar in department of
Electronics And Communication. He has published 2
research papers in International Journal of Emerging
Technologies and Engineering. His research area of
interest includes high performance analog and digital
CMOS circuit techniques.

[8]. G. Geelen, "A 6b 1.1GSample/s CMOS A/D


Converter," IEEE International Solid-State Circuits
Conference Electronics Letter, pp. 128-129, 2001.
[9]. P Philip E. Allen and Douglas R. Holberg "
CMOS Analog Circuit Design," Oxford University
Press, Inc, USA, 2nd edition, pp 259-397, 2002.
[10]. HeungJun Jeon, "Low power High Speed Lowoffset fully dynamic CMOS latched Comparator," The
Department of Electrical and Computer Engineering of
Northeastern University, Boston, Massachusetts, 2008.
[11]. Vipul Katyal, Randall L. Geiger and Degang J.
Chen, " Adjustable Hysteresis CMOS Schmitt triggers
" Paper submitted for International Symposium on
Circuits and systems, Seattle, USA, 2008.

Parikha
Chawla,
completed B.E degree in ECE department from Vaish
college of Engineering Rohtak, Haryana, India and
M.Tech degree from GITM Bilaspur, Haryana, India.
Currently working at CBS Group of Institutions
Fatehpuri, Jhajjar as an Assistant Professor in
department of Electronics And Communication. She
has published 3 research papers in international
conference and journal. Her research area of interest
includes Wireless Communication.

[12]. P.Harry " CMOS VLSI design," Pearson,


4edition Chapter 1, pp 1-62, 2010.
[13]. R. J. Baker, H. W. Li, and D. E. Boyce CMOS
Circuit Design, Layout, and Simulation," IEEE Press
Marketing, 1998.

185
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