Term Paper On Intel 80486 Microprocessor

DARPAN DEKIVADIYA

JEMIS JIVANI

09BCE008
Department of Computer Science & Engineering
Institute of Technology
Nirma University
Ahmedabad 382 481
Gujarat, India.
Email: [email protected]

09BCE017
Department of Computer Science & Engineering
Institute of Technology
Nirma University
Ahmedabad 382 481
Gujarat, India.
Email: [email protected]

I.

I NTRODUCTION

1) The 32-bit 80486 is the next evolutionary step up from

the 80386.
2) One of the most obvious feature included in 80486
is a built in math co processor. This coprocessor is
essentially the same as the 80386 but being integrated
on the chip allows it to execute math instruction about
three times as fast as a 80386/387 combination.
3) 80486 is an 8kbyte code and cache
4) To make room for the additional signal, the 80486 is
packed in 168 pin, pin grid array package instead of
132 pin PGA used for the 80386.
5) The 32-bit CPU 80486 from Intel is the first processor
with an inbuilt floating point unit.

Fig. 1.

Intel 80486 Architecture

II.

A RCHITECTURE

1) A 31- A2: Address outputs A31-A2 provide the memory

and I/O with the address during normal operation. During a cache line invalidation A31-A4 are used to drive
the microprocessor.//
2) A20M3: The address bit 20 mask causes the 80486 to
wrap its address around from location 000FFFFFH to
00000000H as in 8086. This provides a memory system
that functions like the 1M byte real memory system in
the 8086 processors.

14) FLUSH: The cache flush input forces the microprocessor

to erase the contents of its 8K byte internal cache.
15) EADS: The external address strobe input is used with
AHOLD to signal that an external address is used to
perform a cache invalidation cycle.
16) FERR: The floating point error output indicates that
the floating point coprocessor has detected an error
condition. It is used to maintain compatibility with
DOS software.

3) ADS: The address data strobe becomes logic zero to

indicate that the address bus contains a valid memory
address.

17) 8 BS: The bus size 8, input causes the 80486 to structure
itself with an 8-bit data bus to access byte-wide memory
and I/O components.

4) AHOLD: The address hold input causes the

microprocessor to place its address bus connections at
their high-impedance state, with the remainder of the
buses staying active. It is often used by another bus
master to gain access for a cache invalidation cycle.

18) 16 BS: The bus size 16, input causes the 80486
to structure itself with a 16-bit data bus to access
word-wide memory and I/O components.

5) BREQ: This bus request output indicates that the 486

has generated an internal bus request.
6) 3 0 BE-BE: Byte enable outputs select a bank of
the memory system when information is transferred
between the microprocessor and its memory and I/O.
The BE3 signal enables D31 - D24, BE2 enables
D23-D16, BE1 enables D15 - D8 and BE0 enables
D7-D0.
7) BOFF: The Back-off input causes the microprocessor
to place its buses at their high impedance state during
the next cycle. The microprocessor remains in the bus
hold state until the BOFF pin is placed at logic 1 level.
8) NMI: The non-mask able interrupt input requests a type
2 interrupt.
9) BRDY: The burst ready input is used to signal the
microprocessor that a burst cycle is complete.
10) KEN: The cache enable input causes the current bus to
be stored in the internal.
11) LOCK: The lock output becomes a logic 0 for any
instruction that is prefixed with the lock prefix.
12) W / R: current bus cycle is either a read or a write.
13) IGNNE: The ignore numeric error input causes the
coprocessor to ignore floating point error and to
continue processing data. The signal does not affect the
state of the FERR pin.

19) PCHK: The parity check output indicates that a parity

error was detected during a read operation on the DP3
- DP0 pin.
20) PLOCK: The pseudo-lock output indicates that current
operation requires more than one bus cycle to perform.
This signal becomes a logic 0 for arithmetic coprocessor
operations that access 64 or 80 bit memory data.
21) PWT: The page write through output indicates the state
of the PWT attribute bit in the page table entry or the
page directory entry.
22) RDY: The ready input indicates that a non-burst bus
cycle is complete. The RDY signal must be returned
or the microprocessor places wait states into its timing
until RDY is asserted.

Fig. 2.

pin diagram of 80486

Flag Registers
1) The extended flag register EFLAG is illustrated in the
figure. The only new flag bit is the AC alignment check,
used to Indicate that the microprocessor has accessed a
word at an odd address or a double word boundary.
2) Efficient software and execution require that data be
stored at Word or double word boundaries.
3) Other common flags between 80486-80386 like
carry flag(CF),parity flag(PF),auxiliary flag(AF),zero
flag(ZF), Sign flag(SF),trap flag(TF),interrupt flag(IF),
direction flag(DF),overflow flag(OF) are set or reset
according to 80486 instruction set and same as 80386.
4) In the common flags six are control flag and three flags
are conditional flags.
5) The 80486 has four control flag register which is same
as in 80386 microprocessor. Five extra bits are added
to the 80486 is :Alignment mask (AM), numeric error
(NE), write protect (WP),cache disable (CD), not-write
through (NW).
6) AM flag is set to 1 when data alignment is check
alignment mask in or set to 0 when alignment mask
out. A double word of the data that is not stored at an
address that is a multiple of four is said to be unaligned.
If an unaligned double word storage location accessed,
two memory bus cycles must be performed. The extra
bus cycle introduce because the data is unaligned
reduce overall system performance so, alignment check
flag are used to identify alignment.
7) CD and NW flags are used to enable and control the
operation of on the on chip cache memory. To enable
the cache memory for the operation, CD must be
cleared to 0.the NW flag enables write through and
cache validation cycles to take place when it is set to 0.

Fig. 3.

flag register of 80486

General Purpose Reg.

Fig. 4.

general purpose register of 80486

Features

Addressing modes
1. Scaled indexed mode
-Content of an index register are multiply by scale factor
that may be added further to get the operand offset.
2. Based scaled indexed mode
-Content of an index register are multiply by scale
factor that may be then added to base register to get the
operand offset.
3.Based scaled indexed mode with displacement
-Content of an index register are multiply by scale
factor and the result is added to a base register and a
displacement to get operand offeset.

Memory System
1) The memory system for the 486 is identical to 386
microprocessor. The 486 contains 4G bytes of memory
beginning at location 00000000H and ending at
FFFFFFFFH.
2) The major change to the memory system is internal
to 486 in the form of 8K byte cache memory, which
speeds the execution of instructions and the acquisition
of data.
3) Another addition is the parity checker/ generator built
into the 80486 microprocessor.

Parity Checker / Generator:

Interrupts
-80486 can handle 256(00 to FFh) hardware interrupts
on its INTR pin. The structure of the interrupt vector
table(IVT) is same as the 8086 and it is handled by
interrupt descriptor table which contain 256 possible
interrupt vectors. Out of 256, 32 are used by Intel and
remaining are free for user.

Parity is often used to determine if data are correctly

read from a memory location. INTEL has incorporated
an internal parity generator / decoder.

Parity is generated by the 80486 during each write cycle.

Parity is generated as even parity and a parity bit is
provided for each byte of memory. The parity check bits
appear on pins DP0-DP3, which are also parity inputs
as well as parity outputs.

These are typically stored in memory during each write

cycle and read from memory during each read cycle.

On a read, the microprocessor checks parity and generates

a parity check error, if it occurs on the PCHK pin. A
parity error causes no change in processing unless the
user applies the PCHK signal to an interrupt input.
Interrupts are often used to signal a parity error in
DS-based computer systems. This is same as 80386,
except the parity bit storage.

Data types
1.Signed/unsigned data type
-8-bit, 16-bit 32-bit signed/unsigned integer are
supported.
2.Floating point data type
-Single precision, double precision extended precision
real data are supported
3.BCD data type
-It supports 8-bit packed and unpacked data
4.String data type
-String of bit, bytes, words and double words are
supported by CPU, each may contain up to 4GHz.
5.ASCII data type
-It is used for representation of characters.
6.Pointer data type
-48-bit pointers containing 32-bit offset at the LSB and
16-bit selector at MSB are supported by CPU.

If parity is not used, Intel recommends that the DP0 DP3 pins be pulled up to +5v.

Cache Memory

The cache memory system stores data used by a program

and also the instructions of the program. The cache is
organized as a 4 way set associative cache with each
location containing 16 bytes or 4 double words of data.

Control register CR0 is used to control the cache with two

new control bits not present in the 80386 microprocessor.

Summary

Reference

1) Thus in sort 80486 is updated version of 80386.

2) It has 8Byte code and cache.

3) It is the processor with inbuilt floating point unit

4) It has tightly coupled pipelining which allows 80486 to
complete an instruction like a simple ALU.
5) It has more no of flag registers then 8086 like AC,
I/Opl, NT, RF VM.
6) It has the same memory system as 80386 have. Which
contains the memory addresses from 00000000H to
FFFFFFFFH.
7) It also has in built parity checker and parity generator
circuit which is used to check that a data read from
memory is correct or not.

The architecture of 80386-80486 microprocessor By Walter A. Treble and Avtar Singh.

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