lacement and Routing is the first phase in VLSI design that describes the physical layout of the

chip. RF Silicon follows perfect-from-root Placement and Routing solution using available tools
that draw on design rules from the foundry as well as the custom designers own experience,
enabling the place-and-route in a custom way.
After the conversion of RTL to Gate-Level netlist(Synthesis) the blocks and the instances are
placed, which is governed by Floor Planning. After Placement, Clock Tree is synthesized
followed by Routing of the signal nets. The following flow chart summarizes the Physical
Design Flow.

[Placement and Routing]

Placement
Placement has become very critical in todays high performance VLSI design. At RF Silicon the
placement strategy is such that the blueprint of the devices of design are placed on chip in an
optimal way to attain minimum chip area.
Key Features

Voltage domains are preferred to be placed on isolated physical islands.

Margins across memories and analog blocks are key to High Placement Utilization.
Placement aware Power Down(to State Retention Power Rated cells) chain stitching.

Automatic level shifter insertion for nets going from SoC to Platform or vice-verse.
Support for MultiMode/ MultiCorner optimization.

Routing
After placing all the devices of design, the devices are connected through routing. Routing is
highly dependent upon placement.At RF Silicon clock routing and synthesis is done before
connecting the devices so that router can utilize low resistance metal paths so as to meet the
clock skew and insertion delay targets.
Objectives of Routing

To determine the necessary wiring, e.g., net topologies and specific routing segments, to
connect these cells while respecting constraints like design rules.
To Optimize routing objectives, e.g., minimizing total wire length and maximizing timing
slack.

Features

Clock tree is build on placed DEF(Design Exchange Format).

Reduction of Dynamic Cells is attained by
o Insertion of clock cells after clock gating cells.
o Smaller size cells.
o Minimizing Local Skew than Global Skew.
o An optimized clock tree reduces Area and Power overhead.

Routing is further divided into

Global Routing
Detailed Routing

Global Routing
It defines the routing regions and generates a tentative route for each net. Each net is assigned to
a set of routing regions. However, it does not specify the actual layout of wires and is not
sensitive to DRV violations.
Detailed Routing
For each routing region (defined during Global Routing), each net passing through that region is
assigned to particular routing tracks. The actual layout of wires is specified. It also tries to fix all
DRV violations in the design.

RF Silicon has been expertise in the synthesis (ASIC design) field from a long time. Gained
expertise in delivering a number of logic and physical synthesized designs as per the client
requirement.As a part of Synthesis(ASIC design flow), RFSilicon also provides solutions to
resolve the problem of skew and insertion delay through clock tree synthesis.The basics of CTS
is to develop the interconnect that connects the system clock into all the cells in the chip that uses
the clock. For CTS, your major concerns are,

Minimizing the clock skew

Optimizing clock buffers to meet skew specifications and
Minimize clock-tree power dissipation

The primary job of CTS tools is to vary routing paths, placement of the clocked cells and clock
buffers to meet maximum skew specifications. When designing a clock tree, we need to consider
performance specifications that are timing-related. Clock-tree timing specifications include clock
latency, skew, and jitter. Non-timing specifications include power dissipation, signal integrity.
Many clock-design issues affect multiple performance parameters; for example, adding clock
buffers to balance clock lines and decrease skew may result in additional clock-tree power
dissipation. Clock skew adds to cycle times, reducing the clock rate at which a chip can operate.
Typically, skew should be 10% or less of a chips clock cycle, meaning that for a 100MHz clock,
skew must be 1ns or less. High-performance designs may require skew to be 5% of the clock
cycle.
Some of the major challenges that CTS engineers deal with during clock tree synthesis includes

Skew minimization. The factors that contribute to clock skew include loading mismatch
at the clocked elements, mismatch in RC delay.
Lots of clock buffers are added, Need to be minimized
To Decrease in Congestion.
Non-clock tree cells may have been moved to non-ideal locations
Can introduce new timing violations, which need to be removed
CTS become more complex in multi voltage designs.

Critical checking to be incorporated during CTS

For a balanced tree without buffers (before CTS), the clock lines capacitance increases
exponentially as you move from the clocked element to the primary clock input.
The extra capacitance results from the wider metal needed to carry current to the
branching segments
extra metal also results in additional chip area to accommodate the extra clock-line width
The. Adding buffers at the branching points of the tree significantly lowers clockinterconnect capacitance, because you can reduce clock-line width toward the root.
Clock Tree Synthesis (CTS) tools should be aware of different power domains and
understand the level shifters to insert them in appropriate places.
Clock tree is routed through level shifters to reach different power domains.
Simultaneous timing analysis and optimization is necessary for multiple voltage domains

Analysis Features

The delays from the root of the clock tree to leaves are almost same.
In order to minimize the clock skew, clock distribution of clock signal across the chip is
there.
Equal rise and fall delays of the clock signal by using clock buffer.
Skew Balance between related FF pairs by local skew.

RF Silicon has already proven its expertise in ASIC design by delivering a number of
multimillion silicon proven designs as per the client requirement. Most of its design is based on
low power where, a good amount of power can be saved by applying various low power
techniques.As a part of ASIC design flow RF Silicon provides solutions to depict a more
accurate timing analysis for both pre and post layout.
Layout development is an integral part of ASIC/VLSI design flow. Layout design is define as the
process of creating an accurate physical representation of an engineering drawing (netlist) that
conforms to constraints imposed by the manufacturing process, the design flow, and the
performance requirements shown to be feasible by simulation.
Let look at the definition in greater detail
Layout design is a process with many steps that should be followed in a logical order for
optimal results
Process:

Design and creation are usually synonymous, and layout design is no exception.
Implementing one schematic in two different technologies usually results in layouts that look
quite different, thus demonstrating the creative nature of the trade. In the same way, a schematic
that will be used in two different regions of the chip may result in two different architectures,
adapted to their geographical location.
Creation:

Accuracy: Although

layout design is a creative process, but final layout must be that it is

equivalent on a transistor-by-transistor basis to the engineering drawing. Redesigning the
configuration of transistors to improve the circuit is not the role of the layout designer unless
you plan to take over (or already have taken over) the circuit design task as well.
Layout design is the art of drawing transistors and wires as they look like in
silicon; thus, the layout can be thought of as the physical representation of the circuit.
Physical representation:

By conforming, we mean meeting the requirements of and not necessarily the

smallest or best design possible. There are many trades-offs to be made in the process of design:
reliability, manufacturability, flexibility, and (perhaps most importantly) time to market, to name
a few. There are minimum requirements that have to be met, but to achieve the optimal design at
the expense of the project schedule is not practical in todays marketplace.
Conform:

These constraints include layout design rules such as

the smallest width a metal track can be, but also many other manufacturability or reliability
guidelines that will improve the overall quality of the layout.
Constraints imposed by the manufacturing process:

GDS integration require following aspects must be address

Design partitioning of very large and diverse blocks. Defining the many interfaces of a
complex chip is a complicated task.
Defining and planning the interface to the outside world. This involves knowledge about
pad and I/O circuitry and the intricacies associated with them.
Planning and implementing critical signals that are routed over the entire chip. This
would include global power supplies and clock signals.
Floor planning techniques and maintenance are of paramount importance here. At the full
chip level the floor plan is critical as a communication tool as well as a layout
implementation tool.
Estimating the chip size is a significant task in itself. Compare the process parameters of
the current project to previous ones. This is one area in which expertise in floor planning
tools can really help.
In the role of a layout leader responsible for a full chip layout, there is also the
requirement to define layout methodologies, task allocation, and scheduling for the entire
team. Also, a layout verification tools is important in ensuring that the team performs
efficiently. Overall, it is the complexity of the task of the full chip layout that makes it
one of the most challenging and interesting roles in layout design.

[GDS Integration Flow]

RF Silicon has already proven its expertise in ASIC design by delivering a number of
multimillion silicon proven designs as per the client requirement. Most of its design is based on
low power where, a good amount of power can be saved by applying various low power
techniques.
As a part of ASIC design flow RFSilicon provides solutions to depict a more accurate timing
analysis for both pre and post layout. Timing analysis is an integral part of ASIC/VLSI design
flow. Static Timing Analysis (STA) is a method of validating the timing performance of a design
by checking all possible paths for timing violations. Presently it is widely adopted in industry for
examine timing violations.

Intend of Static Timing Analysis (STA)

STA Challenges
Critical checking to be incorporated during STA
Analysis Features
Timing Signoff flow

Intend of Static Timing Analysis (STA)Accurate timing analysis is crucial and inevitably
essential for silicon proven design flow. It requires expertise and in-depth knowledge in ASIC
design engineers to analyse and produce precise timing parameters for the design which
enhances the possibility of silicon success rate to Right First time.
STA Challenges
At nano-meter geometries, digital designs exhibit non digital behaviours such as dynamic IR
drop, leakage current and cross-coupling effects that degrade timing and often lead to circuit
failure. In moving to 90nm technologies and below, circuit designers previse that nano-meter
effects will severely impact circuit timing leads to chances of failure in silicon success rate.
Some of the major challenges that STA engineers deal with during timing analysis includes:

Accurate delay calculation of timing signal paths.

Accurate clock timing analysis to determine arrival time at each internal node.
Correctly detecting the false path and multi cycle path.
Critical path analysis.
Hybrid path analysis.

Critical checking to be incorporated during STA

Interconnect delay in proportion of cell delay at DSM technology.

Interconnect delay doesnt track cell delay with variation into process, voltage and
temperature.
Setup checks should be done into on chip variation mode.
Hold failures have been detected at worst PVT corners.
Margins should be built into clock paths for hold analysis.
Clock tree should be deeply analysed, critical to working silicon.
Voltage domains should be properly set on logic designs and level shifter interfaces.
Clock uncertainty should be incorporated into clock frequency.
Derate and margins should be judiciously used to reduce STA corners.
Multi-mode analysis should be used to reduce number of runs.

Analysis Features

Multiple Clocks and clock Frequency.

Multi cycle path timing exceptions.
False path timing exceptions.
Minimum and maximum delay analysis for setup and hold.
Active-high and activelow clock gating checks.