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NET4003 Assign1

This document contains an assignment for a computer systems architecture course. It includes descriptions of new instructions to be added to the miniP computer and questions about expanding the instruction format to support more general purpose registers and a larger address space. It also includes questions about memory sizes, instruction fields, and pseudo-code for instruction phases as well as boolean logic identities.

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Robert Barrett
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232 views

NET4003 Assign1

This document contains an assignment for a computer systems architecture course. It includes descriptions of new instructions to be added to the miniP computer and questions about expanding the instruction format to support more general purpose registers and a larger address space. It also includes questions about memory sizes, instruction fields, and pseudo-code for instruction phases as well as boolean logic identities.

Uploaded by

Robert Barrett
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Carleton University

School of Information Technology


NET 4003 Computer Systems Architecture
Fall 2014
Assignment 1
Last revision: 2014-09-15

1. Consider the following description for the CISC miniP instruction ANM R,x to be added to the miniP
computer described in Unit03 of the class notes:
ANM R,x : ANDs the 16 bit data word at the address x+2 with the specified register R. It then
ANDs the 16 bit word at address x+4 to with the register. It then stores the 16 bit result into the
address x. A copy of the result remains in register R.
e.g. If R contains 010112 and the three consecutive 16 bit words at 3E16,4016,4216 contain FF3716,
13410, 5310, the result after execution of ANM BX, 0x3E is 1111 1111 0011 01112, 2068, 24 in these
locations.
a. Give a pseudo-code description* of the execute phase of the instruction "ANM AX, 0x20".
(Note: we needed a single read from memory during the instruction fetch phase, but more
than one read from memory during the execution phase). Use F0016 as the initial value in R
and example values 61916, 25910, 1FF16. at locations 2016-2516.
b. Show the hex contents of hex locations 20, 21, 22, 23, 24, 25 before and after execution of
the instruction. For this question, assume that miniP is little endian.
c. Allocate opcode 01012 to ANM. Draw the instruction format for the instruction "ANM
BX,0xA5".
* use the micro-architecture level pseudocode as illustrated in the class notes Unit03, slide 14, for
instance.
2. In the miniP design discussed in class, the address space is 80016. Consistent with this, the
instructions that we discussed have only 11 bits available for an operand address. Please refer to
the instruction format outlined on slide 10 of Unit03.
Suppose we want to expand the operand field to allow an address space of 2000016 , and further,
instead of the two general purpose registers AX and BX, we have 16 general purpose registers which
we number 0 to 15 (call them R0-R15). We allow opcodes of 7 bits and the leftmost bit of every
instruction is reserved to indicate indirect addressing of the operand. We will call this bit the star
bit, or * bit.

This gives us the following instruction layout.

OPCODE

31 30

24 23

Operand
20 19

17 16

0 <- bit number

= Unused
Indirect addressing: When the * bit is zero, the operand field of the instruction contains the
address of a memory word containing the operand value to be used in the instruction (as in the class
slides). We call this direct addressing. When the * bit is a 1, indirect addressing is active, and now
the operand field of the instruction contains the address of a memory word containing the address
of another memory word where the operand value can be found. (Another way of saying it: when *
is 0, the operand field contains a pointer to the value. When * is 1, the operand field contains a
pointer to a pointer to the value.)

a. The address space is 2000016 but the instruction format only allows addresses up to 1FFFF16.
Explain.
b. How many KiB of memory does miniP allow if its address space is 800016 ? 2000016 ? How
many bytes is that in base 10? How many KB is that?
c. Assuming that the length of a word in minP is the same as the length of an instruction, how
many bits wide should PC, IR, MAR, MBR, and R0 to R15 be now?
d. Give the microarchitecture-level pseudo-code (as illustrated in the class notes Unit03) for
the Fetch phase of an instruction.
e. Assume that miniP recognizes the opcodes in the class notes Unit03 plus the ANM
instruction from question 1 above. Give microarchitecture-level pseudo-code (as illustrated
in the class notes Unit03) for the execution phase of instructions 0130037816, 8250037816,
83F0037816.
3. You are given a 2 input XOR gate. Show the truth table, Product of Sums (POS) and Sum of Products
(SOP) expressions. Reduce the SOP expression to the POS expression by manipulating it using the
boolean identities in the Unit04 class slides. Show your work and indicate which identity you used at
each step.
4. a. Using truth tables show that (xy) is not the same as x y.
b. Using truth tables show that (x+y) is not the same as x+y
5. Using the truth table approach, show (prove) the "AND version" of de Morgan's rule.

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