Stanley College of Engineering and Technology

for Women

Department of Electronics and Communication

Engineering
Verilog HDL Laboratory Manual
EC 432
Year: 2011 - 2012

Prepared By:

Mr. Charles Daniel Rajendra Assistant Professor

With the help of:

Mr. N. Pradeep Kumar Goud -- Assistant Professor

Mr. A. Sreenivasa Rao Teaching Assistant

EC 432
VERILOG HDL LAB
Instruction
Duration of University Examination
University Examination
Sessional

3 periods per week

3 Hours
50 Marks
25 Marks

Write the Code (using VERILOG), simulate and synthesize

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

Basic logic gates.

Realization of a four variable function.
Arithmetic units(adders, subtractors).
8-bit parallel adder using 4-bit tasks and functions.
Multiplexers, Demultiplexers.
Encoders, Decoders, Priority encoder.
Four-bit Digital Comparator.
Arithmetic Logic Unit with 8 Instructions.
Waveform generators.
Flip-Flops.
Registers/ Counters.
Sequence detector using Mealy and Moore type state machines.

All the programs should be simulated using test benches.

Mini Project:
i)
ii)
iii)
iv)
v)

8 bit CPU.
Generation of different waveforms using DAC.
RTL code for Booths algorithm for signed binary number multiplication.
Development of HDL code to control speed, direction of DC/ Stepper motor.
Development of HDL code for MAC unit and realization of FIR filter.

DEPARTMENT OF ECE - IV/IV SEM-I

EC-432 VERILOG HDL LAB
List of Programs
First Cycle:
1. (a) Implement the logical AND,OR ,NOT ,NAND, NOR, XNOR, XOR gate operation using verilog HDL
dataflow model by simulating using test bench and synthesizing the results
(b) Implement the logical AND, OR , NOT, NAND, NOR, XNOR, XOR gate operation using verilog HDL
gate level model by simulating using test bench and synthesizing the results
2. (a) Implement the function f= (1, 3, 5, 7) using verilog HDL dataflow model by simulating using test
bench and synthesizing the results
(b) Implement the function f= (0, 1, 2, 5, 13, 15) using verilog HDL dataflow and gate level model by
simulating using test bench and synthesizing the results
3. Implement the half adder, full adder, half subtractor, full subtractor circuits using verilog HDL
dataflow and gate level model by simulating using test bench and synthesizing results.
4.(a) Implement the 2:1 multiplexer using verilog HDL dataflow model and simulate the results using test
bench and synthesize the results.
(b) Design the 4:1 multiplexer, 8:1 multiplexer using verilog HDL behavioral model and
using test bench and synthesize the results.

simulate

(c) Design the 4:1 multiplexer using 2:1 multiplexer using verilog HDL structural model
and
simulate using test bench and synthesize the results. (Note: Make use of conditional operator in an
assign statement in 2:1 multiplexer.)
5. Design 1:4 De-multiplexer using behavioral model. Simulate using test bench and synthesize the
results.
6. Design 4*2 Encoder using behavioral model simulate using test bench and synthesize the results.
7. Design 4:1 Multiplexer using Decoder, simulate using test bench and synthesize the result.
8. (a) Implement 1 bit digital comparator using verilog dataflow model . Simulate using test bench and
synthesize the results.
(b) Implement 4bit digital comparator using verilog behavioral model. Simulate and synthesize the
results.

9. Design a circuit that performs various Boolean and arithmetic operations on 4-bit operands.(74381ALU)
Operation
Clear
B-A
A-B
ADD
XOR
OR
AND
Preset

Inputs
s[2]s[1]s[0]
000
001
010
011
100
101
110
111

Outputs
F
0000
B-A
A-B
A+B
A XOR B
A OR B
A AND B
1111

Second Cycle:

10. Implement the 16:1 multiplexer using 4:1 multiplexer using verilog HDL behavioral and structural
model, simulate using test bench code, synthesize the results.
11. Implement 4bit Full adder circuit in verilog HDL, simulate and synthesize the results.
12. Implement 4bit Full subtractor circuit in Verilog HDL, simulate and synthesize the results.
13. Implement the following using behavioral verilog model, simulate using test bench and synthesize
the results.
(b) D flip flop, T flip flop.
(c) JK flip flop.
14. Implement the 4-bit UP/ DOWN counter in Verilog HDL using behavioral model, simulate and
synthesize the results.

ALL THE ABOVE PROGRAMS ARE SIMULATED USING TEST BENCH & IMPLEMENTED USING
FPGA TRAINER

Verilog HDL

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

11.
12.
13.
14.

Title of the program (To be handwritten)

Aim (To be handwritten)
Truth table (To be handwritten)
K-maps - specially for all combinational logic design (To be handwritten)
Boolean expressions or logic expressions from the k-map (To be handwritten)
Block diagram (To be handwritten)
Logic diagram- Gate level (To be handwritten)
Verilog module or verilog code (To be handwritten)
Verilog test fixture or the verilog code for test bench (To be handwritten)
Simulation results
(i)
Image captured through print screen
(ii)
Hand drawn waveforms on the plain page of your program
Synthesis report (To be formatted in word or paint and printed on a A4 size paper)
RTL schematic - .ngr file (To be formatted in word or paint and printed on a A4 size paper)
Technology schematic - .ngc file (To be formatted in word or paint and printed on a A4 size
paper)
Result (To be handwritten)

Specimen example of one program has been provided in the next page of this file.
All the programs should be written in the above order only; any change will cause the reduction in
marks.

Program no: XX
Title: Simulation and synthesis of AND gate using Gate level model
Aim: To simulate and synthesize AND gate using gate level model
Truth table:
Input 1: a
0
0
1
1

Input 2: b
0
1
0
1

K-maps:
For y:
a
b

0
0

Logic expression:
y = a.b
Block diagram:

AND logic
y

Output : y
0
0
0
1

Logic diagram:
a
y
b

Verilog module (.V file):

module module_and(y, a, b);
input a;
input b;
output y;
and a1(y, a, b);
endmodule

Verilog test fixture or the verilog code for test bench:

`timescale 1 ns / 1 ps
module t_and();
reg a, b;
wire y;
module_and(y, a, b);
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule

Simulation results:
(i)

Image captured through print screen

(ii)

Hand drawn waveforms on the plain page of your program

Draw the above waveform on the left page of the verilog module using pencil and scale,
marking the inputs, outputs, time scale properly.

Synthesis report:
The below side headings should be extracted from the complete synthesis report to be attached in
your record
(i)

(ii)
(iii)
(iv)

Synthesis options summary

(a) Source parameters
(b) Target parameters
HDL compilation
Final report
Device utilization summary

(Note: delete the unnecessary spaces)

Example for the above program:
=========================================================================
Synthesis Options Summary
=========================================================================
Source Parameters:
Input File Name
Input Format

: "module_and.prj"
: mixed

Ignore Synthesis Constraint File : NO

Target Parameters:
Output File Name

: "module_and"

Output Format
Target Device

: NGC
: xc3s50-5-pq208

=========================================================================
HDL Compilation
=========================================================================
Compiling verilog file "and2.v" in library work
Module <t_and> compiled
Module <module_and> compiled
No errors in compilation
Analysis of file <"module_and.prj"> succeeded.
10

=========================================================================
Final Report
=========================================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: module_and.ngr
: module_and

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: NO

Design Statistics
# IOs

:3

Cell Usage :
# BELS

:1

:1

LUT2

# IO Buffers
#

IBUF

OBUF

:3
:2
:1

=========================================================================
Device utilization summary:
Selected Device : 3s50pq208-5
Number of Slices:

1 out of 768

Number of 4 input LUTs:

Number of IOs:
Number of bonded IOBs:

0%

1 out of 1536

0%

3 out of 124

2%

11

RTL schematic (.ngr file):

Technology schematic (.ngc file):

12

Result:
The AND gate has been executed, simulated using test bench and synthesized using gate level
model.

13

INDEX
S.No
1.
2.
3.
4.
5.
6.

Program Number/
Title
Design flow for Logic
Circuits
FPGA Design Flow
Introduction to
Verilog
FPGA
Program No:1
Program No:2
Program No:3
Program No:4
Program No:5
Program No:6
Program No:7
Program No:8
Program No:9
Program No:10
Program No:11
Program No:13
Program No:14

Page No
15
16 - 17
18 - 20
21 - 22
23 - 35
36 - 45
46 - 65
66 - 80
81 - 84
85 - 88
89 - 93
94 -100
101 -105
106 - 110
111 116
117 - 122
123 - 132

14

Date of
Execution

Signature of
the Teacher

Marks

DESIGN FLOW FOR LOGIC CIRCUITS:

Design concept

Partition

Design one block

Design one block

Define interconnection between blocks

Functional simulation of complete system

No
Correct
Yes
Physical mapping

Timing simulation

No
Correct

Yes
Implementation

15

FPGA DESIGN FLOW:

PROGRAMMABLE LOGIC DESIGN FLOW:

Design specifications

Design entry
Functional Simulation
(Zero delay)
T
E
S
T

B
E
N
C
H

Target device libraries

RTL model

(Vendor specific)

Gate level simulation

Synthesis Gate level
description using target
library cells

Design Constraints
Area/ Speed

Gate level model

Timing Simulation
(Gate + Interconnect
delays)

Mapping + translation
Gate level model to device
Architecture

Libraries

Target device libraries

(Vendor specific)

Design Constraints
Place & route
Area/ Speed
Placing the design in
device while optimizing it
for speed and area

Programming file generation Bit stream

Download onto FPGA/ CPLD

16

FPGA DESIGN FLOW FOR XILINX:

Entering your design and selecting
hierarchy

Functional simulation of your design

Adding design constraints

Synthesizing and optimizing your design

Evaluating your designs coding
style and system features
Evaluating your design size and
performance

Placing and routing your design

Generating a bitstream

Downloading to the device in-system

debugging

Creating a PROM or JTAG file

17

Timing simulation
of your design

Static timing
analysis

Introduction to Verilog:
Popularity of verilog HDL:
Verilog HDL is a general purpose hardware description language that is easy to learn and easy to use. It
is similar in syntax to the C programming language. Verilog HDL allows different levels of abstraction to
be mixed in the same model. Thus, a designer can define a hardware model in terms of switches, gates,
RTL, or behavioral code. Also, a designer needs to learn only one language for stimulus and hierarchical
design.
All fabrication vendors provide Verilog HDL libraries for postlogic synthesis simulation. Thus, designing a
chip in Verilog HDL allows the widest choice of vendors.

Programming procedure for FPGA and CPLD (Xilinx ISE 9.2i):

1. Click the Project navigator icon on the desktop.
Main window is opened.
2. Go to FILE, open a NEW PROJECT file.
FIRST WINDOW:

In the first text box: enter the name of the project

In the second text box: enter the path of the program
In the third text box: enter the top module type as HDL

Click on Next to proceed

SECOND WINDOW: Select the device and design flow for the project.
In this window following texts are shown. Select the following options present on the right side of the
window.

18

Click on Next, successively for 3 times and then press Finish. After this, user will automatically get in to
Main Window.
In the main window, go to Project menu, select new source. A third window is opened.
THIRD WINDOW: Create a new source

In the first text box: Verilog Module

In the second text box: enter the file name
In the third text box: It will show the same path, whatever user has entered in the first window.

Click on Next to proceed

FOURTH WINDOW: Define verilog source

Enter the above required fields

Click on Next to proceed
Click Finish to get into Main Window.

19

Simulation:

Enter the program

Check the syntax in the process window, clear errors if any, simulate the program using test
bench.

Procedure to Synthesize and Implementation:

Switch on the FPGA trainer board. Connect the board using the JTAG cable and ALS power
supply.
Click on ASSIGN PACKAGE PINS in process window (sub division of USER CONSTRAINTS) and
window will appear, in that assign PIN number corresponding to signal in location text box and
I/O Standard as LVTTL in I/O standard text box.
After assigning package pins click on IMPLEMENT DESIGN in process window.
Click on GENERATE PROGRAMMING FILE in process window.
After generating programming file click on CONFIGURE DEVICE iMPACT.
Click BOUNDARY SCAN MODE.
Bypass the ROM device.
Finally select a *.bit file for FPGA and *.jed file for CPLD and program the device.
Done LED lights up when programming is succeeded in FPGA- Spartan3 only.
Verify the code according to the truth table by giving the inputs and checking the outputs using
LEDs.

Design entry: Write the HDL code using Verilog HDL

Simulation: user verification of the functionality of design using test bench code.
ISE simulator: ISE Simulator provides a complete, full-featured HDL simulator integrated within ISE. HDL
simulation now can be an even more fundamental step within your design flow with the tight
integration of the ISE Simulator within your design environment.
Synthesis: Transforming HDL code into gate level design.
Implementation: Writing the UCF, which describes the pin locking of input and output signals.

20

FPGA:
FPGA stands for Field Programmable Gate Arrays. A FPGA is a programmable logic device that supports
implementation of relatively large logic circuits. FPGAs are quite different from SPLDs and CPLDs
because FPGAs do not contain AND or OR planes.
Instead, FPGAs provide logic blocks for implementation of the required functions. It contains three main
types of resources: logic blocks, I/O blocks for connecting to the pins of the package, and
interconnection wires and switches. The logic blocks are arranged in a two-dimensional array, and the
interconnection wires are organized as horizontal and vertical routing channels between rows and
columns of logic blocks. FPGAs can be used to implement logic circuits of more than a million equivalent
gates in size.
Each logic block in an FPGA typically has a small number of inputs and outputs. The most commonly
used logic block is a look-up table (LUT), which contains storage cells that are used to implement a small
logic function. Each cell is capable of holding a single logic value, either 0 or 1. The stored value is
produced as the output of the storage cell. LUTs of various sizes may be created, where the size is
defined by the number of inputs.
Example: To implement XNOR function using LUT.
Solution: Circuit for a two input LUT is given as:
x1
0/1

0/1
f

0/1

0/1

x2

21

Truth table:
x1
0
0
1
1

x2
0
1
0
1

f
1
0
0
1

f= ~x1. ~x2 + x1.x2

Storage cell contents in the LUT

Explanation: The above look up table has two inputs, x1 and x2, and output, f. we are implementing
with the help of 2:1 Multiplexer. The output function f values are 1001 which are stored in the
memory contents as shown above. Each of these values will appear at the output function line
depending upon the select lines x1 and x2. Note: Here the input values are taken as select lines. we
can also implement the above using 4:1multiplexer. The use of multiplexer depends upon the engineers
choice.

22

Program no: 1 (a)

Title: Implement the logical AND, OR, NOT, NAND, NOR, XNOR, XOR gate operation using Verilog
HDL dataflow model by simulating using test bench and synthesizing the results.
Aim: To implement the logical AND, OR, NOT, NAND, NOR, XNOR, XOR gate operation using
Verilog HDL dataflow model and simulating using test bench and to synthesize the results.

Truth table:
Input 1: a

Input 2: b

0
0
1
1

0
1
0
1

Input: a
0
1

Output:
OR2
0
1
1
1

Output :
AND2
0
0
0
1

Output:
NOT1
1
0

23

Output:
NAND2
1
1
1
0

Output:
NOR2
1
0
0
0

Output:
XOR2
0
1
1
0

Output:
XNOR2
1
0
0
1

K-maps:
For OR2:
a
b

0
0

1
1

For AND2:
a
b

0
0

1
0

For NOR2:
a
b

1
1

0
0

0
0

24

For NAND2:
a
b

1
1

For XOR2:
a
b

0
1

1
0

1
0

For XNOR2:
a
b

0
0

1
0

1
0
1

25

For NOT1:
a

Logic expression:
OR2 = a + b
AND2 = a.b
NOR 2= a+b
NAND2 = a.b
XOR2= a

XNOR2= a a
NOT1=

Block diagram:

ALLGATES logic
a

OR2
AND2
NOR2
NAND2
XOR2
XNOR2

NOT1

26

Logic diagram:
a
OR2
b

a
AND2
b

a
NOR2
b

a
NAND2
b

a
XOR2
b

a
XNOR2
b

27

NOT1

Verilog module:
module allgatesdataflow(and2, or2, not1, nand2, nor2, xor2, xnor2, a, b);
output and2, or2, not1, nand2, nor2, xor2, xnor2;
input a, b;
assign and2 = a & b;
assign or2 = a | b;
assign not1 = ~a;
assign nand2 = (~a | ~b);
assign nor2 = (~a & ~b);
assign xor2= a ^ b;
assign xnor2 = a^~b;
endmodule
Verilog Test fixture:
module allgatestest1_v;
reg a;
reg b;
wire and2;
wire or2;
wire not1;
wire nand2;
wire nor2;
wire xor2;
wire xnor2;
allgatesdataflow uut (.and2(and2),.or2(or2),.not1(not1),.nand2(nand2),.nor2(nor2), .xor2(xor2),
.xnor2(xnor2), a(a), .b(b));
initial begin
#100 $finish;
end
initial begin
#10 a = 0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule

28

Simulation Results:

Synthesis report:
=======================================================================
Synthesis Options Summary
=======================================================================
Source Parameters:
Input File Name
: "allgatesdataflow.prj"
Input Format

: mixed

Ignore Synthesis Constraint File : NO

Target Parameters:
Output File Name
Output Format
Target Device

: "allgatesdataflow"
: NGC
: xc3s50-5-pq208

=========================================================================
HDL Compilation
=========================================================================
Compiling verilog file "allgatesdataflow.v" in library work
Module <allgatesdataflow> compiled
No errors in compilation
Analysis of file <"allgatesdataflow.prj"> succeeded.

29

=========================================================================
Final Report
=========================================================================
Final Results
RTL Top Level Output File Name : allgatesdataflow.ngr
Top Level Output File Name
: allgatesdataflow
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:9
Cell Usage :
# BELS
:7
#
INV
:1
#
LUT2
:6
# IO Buffers
:9
#
IBUF
:2
#
OBUF
:7
=========================================================================
Device utilization summary:
Selected Device : 3s50pq208-5
Number of Slices:
4 out of 768 0%
Number of 4 input LUTs:
7 out of 1536 0%
Number of IOs:
9
Number of bonded IOBs:
9 out of 124 7%

30

RTL schematic:

Technology schematic:

Result: The above following gates have been implemented using xc3s50-FPGA Trainer board, simulated
using test bench and synthesized.
31

Program no: 1 (b)

Title: Implement the logical AND, OR, NOT, NAND, NOR, XNOR, XOR gate operation using Verilog
HDL gate-level model by simulating using test bench and synthesizing the results.
Aim: To implement the logical AND, OR, NOT, NAND, NOR, XNOR, XOR gate operation using
Verilog HDL gate-level model and simulating using test bench and to synthesize the results.
Verilog Module:
module allgatesgatelevel(and2, or2, not1, nand2, nor2, xor2, xnor2, a, b);
output and2, or2, not1, nand2, nor2, xor2, xnor2;
input a, b;
and(and2, a, b);
or(or2, a, b);
not(not1, a);
nand(nand2, a, b);
nor(nor2, a, b);
xor(xor2, a, b);
xnor(xnor2, a, b);
endmodule

32

Verilog test fixture:

module allgatestest2_v;
reg a;
reg b;
wire and2;
wire or2;
wire not1;
wire nand2;
wire nor2;
wire xor2;
wire xnor2;
allgatesgatelevel uut (.and2(and2), .or2(or2), .not1(not1), .nand2(nand2), .nor2(nor2),
.xor2(xor2), .xnor2(xnor2), .a(a),
.b(b));
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule

Simulation Results:

33

Synthesis Report:
=========================================================================
Synthesis Options Summary
=========================================================================
Source Parameters:
Input File Name
: "allgatesgatelevel.prj"
Input Format
: mixed
Ignore Synthesis Constraint File : NO
Target Parameters:
Output File Name
: "allgatesgatelevel"
Output Format
: NGC
Target Device
: xc3s50-5-pq208
=========================================================================
HDL Compilation
=========================================================================
Compiling verilog file "allgatesgatelevel.v" in library work
Module <allgatesgatelevel> compiled
No errors in compilation
Analysis of file <"allgatesgatelevel.prj"> succeeded.
=========================================================================
Final Report
=========================================================================
Final Results :
RTL Top Level Output File Name : allgatesgatelevel.ngr
Top Level Output File Name
: allgatesgatelevel
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:9
Cell Usage :
# BELS
:7
#
INV
:1
#
LUT2
:6
# IO Buffers
:9
#
IBUF
:2
#
OBUF
:7
=========================================================================

34

Device utilization summary:

Selected Device : 3s50pq208-5
Number of Slices:
4 out of 768 0%
Number of 4 input LUTs:
7 out of 1536 0%
Number of IOs:
9
Number of bonded IOBs:
9 out of 124 7%
RTL schematic:

Technology schematic:

Result: The above following gates have been implemented using xc3s50-FPGA Trainer board, simulated
using test bench and synthesized.

35

Program no: 2 (a)

Title: Implement the function f = (1, 3, 5, 7) using Verilog HDL dataflow model by simulating using
test bench and synthesizing the results.
Aim: To implement the function f = (1, 3, 5, 7) using Verilog HDL dataflow model and simulating
using test bench as well as synthesizing the results.
Truth table:
Input 1: a

Input 2: b

Input 3: c

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Output:
f
0
1
0
1
0
1
0
1

K-maps:
b c 00

01

11

10
0

a
1

1
1

Logic Expression:
f = c. c

36

Block Diagram:

FUNCTION 1
a
b

Logic Diagram:

Verilog Module:
module function1(a, b, c, f);
input a;
input b;
input c;
output f;
and (f, c, c);
endmodule

37

Verilog test Fixture:

module function1test_v;
reg a;
reg b;
reg c;
wire f;
function1 uut (.a(a), .b(b), .c(c), .f(f));
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0; c=1;
#10 a=1; b=0; c=0;
#10 a=0; b=1; c=1;
#10 b=0;
end
endmodule

Simulation results:

38

RTL schematic:

Technology schematic:

Result: The above function has been implemented using xc3s50-FPGA trainer and also simulated and
synthesized.

39

Program no: 2 (b)

Title: Implement the function f = (0, 1, 2, 5, 13, 15) using Verilog HDL dataflow and gate level model
by simulating using test bench and synthesizing the results.
Aim: To implement the function f = (0, 1, 2, 5, 13, 15) using Verilog HDL dataflow and gate level
model and simulating using test bench as well as synthesizing the results.
Truth table:
Input 1: a

Input 2: b

Input 3: c

Input 4: d

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

40

Output:
f
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
1

K-Map: For f:
cd

ab

00

01

11

10
1

00
01

11

10

Logic Expression:
f = (~a. ~ b . ~ c) + (~ a. ~ c. d) + (a. b. d)

Block Diagram:

FUNCTION 2

b
c

41

Logic diagram:

~a
~b
~d
~a
~c

d
a
b
d

Verilog Module (gate-level model):

module function2(a, b, c, d, f);
input a,b,c,d;
output f;
wire f1, f2, f3;
and (f1, ~a, ~b, ~d),(f2, ~a, ~c, d),(f3, a, b, d);
or (f, f1, f2, f3);
endmodule

42

Verilog Module (dataflow model):

module function2datatflow(a, b, c, d, f);
input a, b, c, d;
output f;
assign f= (~a & ~b & ~d) | (~a & ~c & d) | (a & b & d);
endmodule
Verilog test Fixture:
module function2test_v;
reg a; reg b; reg c; reg d; wire f;
function2 uut (.a(a), .b(b), .c(c), .d(d), .f(f));
initial begin
#100 $finish;
end
initial begin
#10 a= 0; b=0; c=0; d=0;
#10 d=1;
#10 b=1;
#10 a=1;
#10 c=1;
#10 a=0; b=0; d=0;
#10 d=1;
end
endmodule
Verilog test Fixture:
module function2test_v;
reg a; reg b; reg c; reg d; wire f;
function2datatflow uut (.a(a), .b(b), .c(c), .d(d), .f(f));
initial begin
#100 $finish;
end
initial begin
#10 a= 0; b=0; c=0; d=0;
#10 d=1;
#10 b=1;
#10 a=1;
#10 c=1;
#10 a=0; b=0; d=0;
#10 d=1;
end
endmodule
43

Simulation results:
Gate-level simulation results:

Dataflow simulation results:

RTL schematic:
Gate level model:

Dataflow model:

44

Technology schematic:
Gate level model:

Dataflow model:

Result: The above function has been implemented using xc3s50-FPGA trainer and also simulated and
synthesized.

45

Program no: 3
Title: Implement the Half Adder, Full adder, Half Subtractor, Full Subtractor circuits using Verilog HDL
dataflow and gate-level model by simulating using test bench and synthesizing results.
Aim: To implement the Half Adder, Full Adder, Half Subtractor, Full Subtractor circuits using Verilog
HDL dataflow and gate-level model and simulating the results using test bench and as well as
synthesizing.
Half adder:
Truth table:
Input1: a

Input2: b

0
0
1
1

0
1
0
1

Output1:
Sum
0
1
1
0

K-Maps:
For Sum:

b
a

0
11
11

For Carry:

46

Output2:
Carry
0
0
0
1

Logic expression:
sum = a

carry= a.b

Block diagram:

Half Adder
sum

carry
b

Logic diagram:

a
sum
b

carry

47

Verilog Module ( Half Adder Dataflow model):

module halfadderdataflow(a, b, sum, carry);
input a, b;
output sum, carry;
assign sum= a ^ b;
assign carry= a & b;
endmodule

Verilog Test Fixture:

module halfaddertest2_v;
reg a; reg b; wire sum; wire carry;
halfadderdataflow uut ( .a(a), .b(b), .sum(sum), .carry(carry));
initial begin
#100 $finish;
end
initial beg
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule

Simulation Results:

48

Verilog Module ( Half Adder Gate-level model):

module halfaddergatelevel(a, b, carry, sum);
input a;
input b;
output carry;
output sum;
xor(sum, a, b);
and(carry, a, b);
endmodule
Verilog Test Fixture:
module halfaddertest1_v;
reg a; reg b; wire carry; wire sum;
halfaddergatelevel uut ( .a(a), .b(b), .carry(carry),.sum(sum));
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule

Simulation Result:

49

RTL schematic:

Technology Schematic:

50

Full Adder:
Truth table:
Input1: a

Input2: b

Input3: cin

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Output1:
Sum
0
1
1
0
1
0
0
1

K-Maps:
For sum:
b cin
a

00

01

11

10

For carry:
b cin
a

00

01

11

10

1
0
1

51

Output2:
Carry
0
0
0
1
0
1
1
1

Logic Expressions:
sum=

cin

carry= a.b + b.c + c.a

Logic diagram:

a
b

sum

cin

a
b

carry

c
a

Block diagram:

Full Adder

sum

cin

carry

52

Verilog Module (Full Adder dataflow model):

module fulladderdataflow(a, b, cin, sum, carry);
input a, b, cin;
output sum, carry;
assign sum= a^b^cin;
assign carry= (a&b)|(b& cin)|(cin & a);
endmodule
Verilog Test Fixture:
module fulladdertest1_v;
reg a; reg b; reg cin; wire sum; wire carry;
fulladderdataflow uut (.a(a), .b(b), .cin(cin), .sum(sum), .carry(carry));
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0; cin=0;
#10 a=0; b=0; cin=1;
#10 a=1;
#10 b=1;
end
endmodule

Simulation Results:

53

Verilog Module (Full Adder Gate-level Model):

module fulladdergatelevel(a, b, cin, sum, carry);
input a,b,cin;
output sum, carry;
wire f1, f2, f3;
xor(sum, a, b, cin);
and(f1, a, b);
and(f2, b, cin);
and(f3, cin, a);
or(carry, f1, f2, f3);
endmodule
Verilog Test Fixture:
module test2fulladder_v;
reg a; reg b; reg cin; wire sum; wire carry;
fulladdergatelevel uut (.a(a), .b(b), .cin(cin), .sum(sum), .carry(carry));
initial begin
#100 $finish;
end
initial begin
#10 a=1; b=0; cin=0;
#10 cin=1;
#10 b=1;
#10 a=0;
end
endmodule

Simulation Results:

54

RTL Schematic:

Technology Schematic:

55

Half Subtractor:
Truth Table:
Input1: a

Input2: b

0
0
1
1

0
1
0
1

Output1:
diff
0
1
1
0

K-Maps:
For diff:
b
a

1
1

0
1

For borrow:

b
a

Logic expression:
diff=

borrow= ~a. b

56

Output2:
borrow
0
1
0
0

Block diagram:

a
b

Half
subtractor

diff
borrow

Logic diagram:

a
diff
b

~a
b

borrow

Verilog Module (Half Subtractor Dataflow model):

module halfsubdataflow(a, b, diff, borrow);
input a, b;
output diff, borrow;
assign diff= a^b;
assign borrow= (~a) & b;
endmodule

57

Verilog Test Fixture:

module halfsubtest2_v;
reg a; reg b; wire diff; wire borrow;
halfsubdataflow uut (.a(a), .b(b), .diff(diff), .borrow(borrow));
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule
Simulation Results:

58

Verilog Module (Half Subtractor Gate-Level model):

module halfsubgatelevel(a, b, diff, borrow);
input a, b;
output diff, borrow;
and(borrow, b, ~a);
xor(diff, a, b);
endmodule

Verilog Test Fixture:

module halfsubtest1_v;
reg a; reg b; wire diff; wire borrow;
halfsubgatelevel uut (.a(a), .b(b), .diff(diff), .borrow(borrow));
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule

Simulation Results:

59

RTL Schematic:

Technology Schematic:

60

Full subtractor:
Truth Table:
Input1:a

Input2:b

Input3:bin

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Output1:
diff
0
1
1
0
1
0
0
1

K-Maps:
For diff
b bin
a

00

01

11

10

For borrow:
b bin
00
a

01
1

11
1

0
1
1

61

10
1

Output2:
Borrow
0
1
1
1
0
0
0
1

Logic Expression:
diff= a

bin

borrow= ~a .bin + ~a. b + b. bin

Logic diagram:

62

Block Diagram:

Verilog Module (Full Subtractor dataflow model):

module fullsubtractordataflow(a, b, bin, diff, borrow);
input a, b, bin;
output diff, borrow;
assign diff= a^b^bin;
assign borrow= (~a & bin) | (~a & b) | (b & bin);
endmodule
Verilog Test Fixture:
module fullsubtractortest1_v;
reg a;
reg b;
reg bin;
wire diff;
wire borrow;
fullsubtractordataflow uut (.a(a), .b(b), .bin(bin), .diff(diff), .borrow(borrow));
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0; bin=0;
#10 a=0; b=0; bin=1;
#10 a=1;
#10 b=1;
end
endmodule

63

Simulation Results:

Verilog Module (Full Subtractor Gate-Level model):

module fullsubtractorgatelevel(a, b, bin, diff, borrow);
input a, b, bin;
output diff, borrow;
wire f1, f2, f3;
xor(diff, a, b, bin);
and(f1, ~a, bin), (f2, ~a, b), (f3, b, bin);
or(borrow, f1, f2, f3);
endmodule
Verilog Test Fixture:
module fullsubtractortest2_v;
reg a; reg b; reg bin; wire diff; wire borrow;
fullsubtractorgatelevel uut (
.a(a), .b(b), .bin(bin), .diff(diff), .borrow(borrow)
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=1; bin=0;
#10 a=0; b=0; bin=1;
#10 a=1;
#10 b=1;
end
endmodule

64

);

Simulation Results:

RTL Schematic:

Technology Schematic:

Result: The Half Adder, Full Adder, Half Subtractor, Full Subtractor circuits have been implemented
using xc3s50- FPGA trainer board and simulated using test bench and as well as synthesized.

65

Program no: 4 (a)

Title: Implement the 2:1 multiplexer using verilog HDL dataflow model and simulate the results

using test bench and synthesize the results.

Aim: To implement the 2:1 multiplxer using verilog HDL dataflow model and simulate the results

using test bench and synthesize the results.

2:1 multiplexer:
Block diagram:

2:1 MUX
f

Truth table:
Select line
input:
S
0
1

Output:
f
a
b

a, b are data inputs, it can take the value as 1 or 0. f is the output line, it gives the output as a, b
depending upon the combination of select line.

K-map, logic expression, logic diagram is left as an assignment for the students.

66

Verilog Module:
module mux21df(d, s, f);
input [1:0] d;
input s;
output f;
assign f= d[s];
endmodule

Verilog Test fixture:

module mux21dftest1_v;
reg [1:0] d;
reg s;
wire f;
mux21df uut ( .d(d), s(s), .f(f));
initial begin
#100 $finish;
end
initial begin
assign d[0]= 1'b1;
assign d[1]= 1'b0;
s=0;
#20 s=1;
#20 s=0;
#20 s=1;
end
endmodule
Simulation Results:

67

RTL schematic:

Technology Schematic:

Result: The 2:1 Multiplexer has been implemented using xc3s50-FPGA Trainer board, simulated using
test bench and synthesized.

68

Program no: 4 (b)

Title: Design the 4:1 multiplexer, 8:1 multiplexer using verilog HDL behavioral model and

simulate using test bench and synthesize the results.

Aim: To design the 4:1 multiplexer, 8:1 multiplexer using verilog HDL behavioral model and

simulate using test bench and synthesize the results.

4:1 MUX:
Block diagram:
a[0]

4:1 MUX

a[1]

a[2]
a[3]

s[1]

s[0]

69

Truth table:
Select line input1: s[1]
0
0
1
1

Select line input2: s[2]

0
1
0
1

Output: f
a[0]
a[1]
a[2]
a[3]

[3:0]a are the data inputs, [1:0]s are the select lines input, f is the output line.

PS: K-maps, Logic expression, Logic diagram is left as an assignment for the students.

Verilog Module:
module mux4to1behave(a, s, f);
input [3:0] a;
input [1:0] s;
output reg f;

always@(*)
if (s==2'b00)
f=a[0];
else if(s==2'b01)
f=a[1];
else if(s==2'b10)
f=a[2];
else
f=a[3];
endmodule

70

Verilog test Fixture:

module mux4to1behtest_v;
reg [3:0] a;
reg [1:0] s;
wire f;
mux4to1behave uut (.a(a), .s(s), .f(f));
initial begin
#100 $finish;
end
initial begin
a=4'b1010;
s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
end
endmodule

Simulation Results:

71

RTL schematic:

Technology Schematic:

72

8:1MUX:
Block diagram:
a[0]

8:1 MUX

a[1]
a[2]
a[3]
a[4]

a[5]
a[6]
a[7]

s[2]

s[1]

s[0]

Truth Table:
s[2]
0
0
0
0
1
1
1
1

s[1]
0
0
1
1
0
0
1
1

s[0]
0
1
0
1
0
1
0
1

K-Maps, logic expression, logic diagram are left as an assignment for the students.

73

f
a[0]
a[1]
a[2]
a[3]
a[4]
a[5]
a[6]
a[7]

Verilog Module:
module mux8to1behave(d, s, f);
input [7:0] d;
input [2:0] s;
output reg f;
//behavioural model
always@(*)
if (s==3'b000)
f= d[0];
else if(s==3'b001)
f=d[1];
else if(s==3'b010)
f=d[2];
else if(s==3'b011)
f=d[3];
else if(s==3'b100)
f=d[4];
else if(s==3'b101)
f=d[5];
else if(s==3'b110)
f=d[6];
else
f=d[7];
// end of model
endmodule

74

Verilog test fixture:

module mux8to1test_v;
reg [7:0] d;
reg [2:0] s;
wire f;
mux8to1behave uut (.d(d), .s(s),.f(f));
initial begin
#100 $finish;
end
initial begin
d= 8'b11000110;
s= 3'b000;
#10 s= 3'b001;
#20 s= 3'b110;
#20 s= 3'b111;
end
endmodule

Simulation results:

75

RTL schematic:

Technology Schematic:

Result: The 4:1, 8:1 Multiplexer has been designed using behavioral model, simulated and synthesized.

76

Program no: 4 (c)

Title: Design the 4:1 multiplexer using 2:1 multiplexer using verilog HDL structural model

and simulate using test bench and synthesize the results. (Note: Make use of conditional operator
in an assign statement in 2:1 multiplexer.)
Aim: To design the 4:1 multiplexer using 2:1 multiplexer using verilog HDL structural model

and simulating using test bench and synthesizing the results.

4:1 MUX:
Block diagram:
d[0]

4:1 MUX

d[1]

d[2]
d[3]

s[1]

s[0]

Truth table:
Select line input1: s[1]
0
0
1
1

Select line input2: s[2]

0
1
0
1

[3:0]d are the data inputs, [1:0]s are the select lines input, f is the output line.

77

Output: f
d[0]
d[1]
d[2]
d[3]

2:1 multiplexer:
Block diagram:

w[0]

2:1 MUX
f

w[1]

Truth table:
Select line
input:
S
0
1

Output:
f
w[0]
w[1]

w[0:1] are data inputs, it can take the value as 1 or 0. f is the output line, it gives the output as w[0], w[1]
depending upon the combination of select line input. Complete design of 4:1 Mux using 2:1 Mux is left as
an assignment for the students.

Verilog Module:
module mux41structural(d, s, f);
input [3:0] d;
input [1:0] s;
output f;
wire [1:0] g;
mux2to1 (d[1:0], s[0], g[0]);
mux2to1 (d[3:2], s[0], g[1]);
mux2to1 (g[1:0], s[1], f);
endmodule

78

module mux2to1 (w, s, f);

input [1:0]w;
input s;
output f;
assign f= s? w[1] : w[0];
endmodule

Verilog test fixture:

module mux4to1test3_v;
reg [3:0] d;
reg [1:0] s;
wire f;
mux41structural uut (.d(d),.s(s),.f(f));
initial begin
#100 $finish;
end
initial begin
d= 4'b0101;
#10 s= 2'b00;
#20 s= 2'b01;
#30 s= 2'b10;
#30 s= 2'b11;
end
endmodule

Simulation Results:

79

RTL Schematic:

Technology Schematic:

Result: 4:1 Multiplexer has been design using 2:1 Multiplexer.

80

Program no: 5
Title: Design 1:4 De-multiplexer using behavioral model. Simulate using test bench and

synthesize the results.

Aim: To design 1:4 De-multiplexer using behavioral model. Simulating using test bench and

synthesizing the results.

1:4 DEMUX:
Block diagram:
1:4 Demux
g[0]
a

g[1]
g[2]
g[3]

s[1]

s[0]

Truth table:
Incoming
input: a
a
a
a
a

s[1]

s[0]

g[0]

g[1]

g[2]

g[3]

0
0
1
1

0
1
0
1

1
0
0
0

0
1
0
0

0
0
1
0

0
0
0
1

a is the incoming input at the demultiplexer circuit , [1:0]s are the select lines input whose
combination decides which output data line to be selected i.e. [3:0]g.
PS: K-Maps, Logic expression, Logic diagram are left as an assignment to the students.

81

Verilog Module:
module demux1to4(a, s, g);
input a;
input [1:0] s;
output reg [0:3] g;
always@(*)
case(s)
3: assign g[3]= s[1]& s[0]& a;
2: assign g[2]= s[1]& ~s[0]&a;
1: assign g[1]= ~s[1]& s[0] &a;
0: assign g[0]= ~s[1] & ~s[0] &a;
endcase
endmodule

Verilog Test Fixture:

module demuxtest1_v;
reg a;
reg [1:0] s;
wire [3:0] g;
demux1to4 uut (.a(a), .s(s), .g(g));
initial begin
#100 $finish;
end
initial begin
#10 a=1; s[1]=0; s[0]=0;
#10 a=1; s[1]=0; s[0]=1;
#10 a=1; s[1]=1; s[0]=0;
#10 a=1; s[1]=1; s[0]=1;
end
endmodule

82

Simulation Results:

RTL schematic:

83

Technology schematic:

Result: The 1:4 De- multiplexer has been designed using behavioral model, simulated and synthesized.

84

Program no: 6
Title: Design 42 Encoder using behavioral model simulate using test bench and synthesize the

results.
Aim:

To design 42 Encoder using behavioral model simulating using test bench and

synthesizing the results.

42Encoder:
Block diagram:
a[0]

42Encoder

a[1]

g[0]

a[2]

a[3]

g[1]

En
Truth Table:
En
0
1
1
1
1

a[0]

1
0
0
0

a[1]

0
1
0
0

a[2]
0
0
0
1
0

a[3]
0
0
0
0
1

g[0]
0
0
0
1
1

g[1]
0
0
1
0
1

En is an enable input which controls the encoder circuit, a[3:0] are the data inputs to be encoded
and g[1:0] are the encoded outputs.
PS: K-Maps, Logic expression, logic diagram are left as an assignment for the students.

85

Verilog Module:
module encoder4to2(en, a, g);
input en;
input [0:3] a;
output reg [0:1] g;
always@(*)
begin
if(en==0)
g=2'b00;
else
case(a)
4'b0001: g=2'b00;
4'b0010: g=2'b01;
4'b0100: g=2'b10;
4'b1000: g=2'b11;
endcase
end
endmodule

Verilog test fixture:

module encoder4to2test_v;
reg en;
reg [0:3] a;
wire [0:1] g;
encoder4to2 uut (.en(en), .a(a), .g(g));
initial begin
#100 $finishh;
end
initial begin
en=0; #10 en=1; a[0]=0; a[1]=0; a[2]=0; a[3]=1;
#10 en=1; a[0]=0; a[1]=0; a[2]=1; a[3]=0;
#10 en=1; a[0]=0; a[1]=1; a[2]=0; a[3]=0;
#10 en=1; a[0]=1; a[1]=0; a[2]=0; a[3]=0;
end
endmodule

86

Simulation results:

RTL schematic:

87

Technology schematic:

Result: The 4*2 Encoder has been designed using behavioral model, simulated and synthesized.

88

Program no: 7
Title: Design 4:1 Multiplexer using Decoder, simulate using test bench and synthesize the result.
Aim: To design 4:1 Multiplexer using Decoder, simulating using test bench and synthesizing the

result.
4:1MUX:
Block diagram:
x[0]

4:1 MUX

x[1]

x[2]
x[3]

s[0]

s[1]

Truth table:
Select line input1: s[1]
0
0
1
1

Select line input2: s[2]

0
1
0
1

x[0:3] are the data inputs, s[0:1] are the select lines input, f is the output line.

89

Output: f
x[0]
x[1]
x[2]
x[3]

24Decoder:
Block diagram:
a

24Decoder

y0
y1

y2
y3

Input1: a
0
0
1
1

Input2: b
0
1
0
1

Output1: y0
1
0
0
0

Output2: y1
0
1
0
0

Output3: y2
0
0
1
0

Output4: y3
0
0
0
1

a, b are the encoded data inputs and y0, y1, y2, y3 are the decoded outputs.
Complete design of 4:1Mux using 24Decoder is left as an assignment for the students.

90

Verilog module:
module mux41decoder(x, s, f);
input [0:3] x;
input [0:1] s;
output f;
wire [1:8]g;
decoder24 stage1(s[0],s[1],g[1],g[2],g[3],g[4]);
and2

stage2(x[0], g[1], g[5]);

and2

stage3(x[1], g[2], g[6]);

and2

stage4(x[2], g[3], g[7]);

and2

stage5(x[3], g[4], g[8]);

or4

stage6(g[5], g[6], g[7], g[8], f);

endmodule
module decoder24(a, b, y0, y1, y2, y3);
input a, b;
output y0, y1, y2, y3;
and(y0, ~a, ~b);
and(y1, ~a, b);
and(y2, a, ~b);
and(y3, a, b);
endmodule
module and2(a, b, c);
input a, b;
output c;
and(c, a, b);
endmodule
module or4(a, b, c, d, e);
input a, b, c, d;
output e;
or(e, a, b, c, d);
endmodule

91

Verilog test fixture:

module mux41decodertest_v;
reg [0:3] x;
reg [0:1] s;
wire f;
mux41decoder uut (.x(x), .s(s), .f(f));
initial begin
#100 $finish;
end
initial begin
x= 4'b0101;
s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
end
endmodule
Simulation result:

92

RTL schematic:

Technology schematic:

Result: 4:1 Multiplexer has been design using Decoder. Simulated and Synthesized.
93

Program no: 8(a)

Title: Implement 1 bit digital comparator using verilog dataflow model. Simulate using test

bench and synthesize the results.

Aim: To implement 1 bit digital comparator using verilog dataflow model. Simulating using test

bench and synthesizing the results.

1bit Digital comparator:
Block diagram:

1bit
comparator

a gt b
a lt b

a eq b

Truth table:
Input1: a
0
0
1
1

Input2: b
0
1
0
1

Output1: agtb
0
0
1
0

Output2: altb
0
1
0
0

Output3: aeqb
1
0
0
1

a, b are the one bit inputs and agtb, altb, aeqb are the outputs that stand for a greater
than b, a less than b and a equal to b respectively.

PS: K-maps, Expressions are left as an assignment for the students.

Verilog module:
module onebitcomp(a, b, agtb, altb, aeqb);
input a, b;
output agtb, altb, aeqb;
assign agtb= a & ~b;
assign altb= ~a & b;
assign aeqb= a~^ b;
endmodule

94

Verilog Test fixture:

module onebitcomparatortest_v;
reg a;
reg b;
wire agtb;
wire altb;
wire aeqb;
onebitcomp uut (.a(a), .b(b), .agtb(agtb), .altb(altb), .aeqb(aeqb));
initial begin
#100 $finish;
end
initial begin
a=0;b=0;
#10 a=1;
#10 b=1;
#10 a=0;
end
endmodule
Simulation results:

95

RTL Schematic:

Technology Schematic:

Result: One Bit Comparator is implemented. Simulated and synthesized.

96

Program no: 8(b)

Title: Implement 4bit digital comparator using verilog behavioral model. Simulate and synthesize

the results.
Aim:

To implement 4bit digital comparator using verilog behavioral model. Simulate and

synthesize the results.

4bit digital comparator:
Block diagram:

A [3:0]

4bit
comparator

AeqB
AgtB

B [3:0]

AltB

Verilog module:
module compare4bit(A, B, AeqB, AgtB, AltB);
input [3:0] A, B;
output reg AeqB, AgtB, AltB;
always @(*)
begin
AeqB=0;
AgtB=0;
AltB=0;
if(A==B)
AeqB=1;
else if(A>B)
AgtB=1;
else
AltB=1;
end
endmodule

97

Verilog Test Fixture:

module comparatortest1for4bit_v;
reg [3:0] A;
reg [3:0] B;
wire AeqB;
wire AgtB;
wire AltB;
compare4bit uut (.A(A), .B(B), .AeqB(AeqB), .AgtB(AgtB), .AltB(AltB));
initial begin
#100 $finish;
end
initial begin
A=4'b0000; B=4'b0000;
#10 A=4'b0001; B=4'b1000;
#10 A=4'b0100; B=4'b0001;
#10 A=4'b1000; B=4'b1000;
#10 A=4'b0010; B=4'b0101;
#10 A=4'b0111; B=4'b1111;
#10 A=4'b1111; B=4'b1111;
end
endmodule
Simulation results:

98

RTL Schematic:

99

Technology Schematic:

Result: 4-Bit comparator is implemented. Simulated and synthesized.

100

Program no: 9
Title: Design a circuit that performs various Boolean and arithmetic operations on 4-bit operands.

(74381- ALU).
Aim: To design a circuit that performs various Boolean and arithmetic operations on 4-bit

operands. (74381 - ALU).

74381-ALU operation table:

Operation

Inputs
s[2]s[1]s[0]
000
001
010
011
100
101
110
111

Clear
B-A
A-B
ADD
XOR
OR
AND
Preset

Outputs
F
0000
B-A
A-B
A+B
A XOR B
A OR B
A AND B
1111

A [3:0], B [3:0] are the 4 bit inputs.

Block Diagram:

A [3:0]

74381 - ALU

F[3:0]
B [3:0]

S [2:0]

101

Verilog Module:
module ALU4bit(s, A, B, F);
input [2:0] s;
input [3:0] A, B;
output reg [3:0] F;
always@(s, A, B)
case(s)
0: F= 4'b0000;
1: F= B-A;
2: F= A-B;
3: F= A+B;
4: F= A^B;
5: F=A|B;
6: F=A&B;
7: F= 4'b1111;
endcase
endmodule
verilog text fixture
module ALU4btest_v;
reg [2:0] s;
reg [3:0] A;
reg [3:0] B;
wire [3:0] F;
ALU4bit uut (.s(s),.A(A),.B(B),.F(F));
initial begin
#100 $finish;
end
initial begin
assign A= 4'b1100;
assign B= 4'b0101;
s=0;
#10 s=1;
#10 s=2;
#10 s=3;
#10 s=4;
#10 s=5;
#10 s=6;
#10 s=7;
end
endmodule

102

Simulation results:

103

RTL Schematic:

104

Technology Schematic:

Result: The circuit that performs various Boolean and arithmetic operations has been designed.

105

Program no: 10
Title: Implement the 16:1 multiplexer using 4:1 multiplexer using verilog HDL behavioral and

structural model, simulate using test bench code, synthesize the results.
Aim: To implement the 16:1 multiplexer using 4:1 multiplexer using verilog HDL behavioral

and structural model, simulating using test bench code, synthesizing the results.
Block Diagram: 16:1 MUX
16:1 Multiplexer

a [15:0]

s [3:0]
Truth table: 16:1 MUX
Select line input1:
s[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Select line input2:

s[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Select line input3:

s[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

106

Select line input4:

s[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Output: f
a[0]
a[1]
a[2]
a[3]
a[4]
a[5]
a[6]
a[7]
a[8]
a[9]
a[10]
a[11]
a[12]
a[13]
a[14]
a[15]

Block Diagram: 4:1 MUX:

x[0]

4:1 MUX

x[1]

x[2]
x[3]

y[1]

y[0]

Truth Table: 4:1 MUX

Select line input1: y[1]
0
0
1
1

Select line input2: y[2]

0
1
0
1

Output: z
x[0]
x[1]
x[2]
x[3]

PS: Complete design of 16:1 MUX using 4:1 MUX is left as an assignment for the students.

107

Verilog module:
module mux16to1(a, s, f);
input [15:0] a;
input [3:0] s;
output f;
wire [3:0]g;
mux4to1 (a[3:0],s[1:0],g[0]);
mux4to1 (a[7:4],s[1:0],g[1]);
mux4to1 (a[11:8],s[1:0],g[2]);
mux4to1 (a[15:12],s[1:0],g[3]);
mux4to1 (g[3:0],s[3:2],f);
endmodule
module mux4to1 (x,y,z);
input [3:0]x;
input [1:0]y;
output reg z;
always@(*)
if (y==2'b00)
z=x[0];
else if (y==2'b01)
z=x[1];
else if (y==2'b10)
z=x[2];
else
z=x[3];
endmodule
Verilog test fixture:
module mux16test_v;
reg [15:0] a;
reg [3:0] s;
wire f;
mux16to1 uut ( .a(a), .s(s), .f(f) );
initial begin
#200 $finish;
end
initial begin
a=16'b 1111000011110000;s=4'b0000;
#10 s=4'b0000;
#10 s=4'b0001;
#10 s=4'b0010;
#10 s=4'b0011;
#10 s=4'b0100;
#10 s=4'b0101;
#10 s=4'b0110;
#10 s=4'b0111;
#10 s=4'b1000;
#10 s=4'b1001;
#10 s=4'b1010;
108

#10 s=4'b1011;
#10 s=4'b1100;
#10 s=4'b1101;
#10 s=4'b1110;
#10 s=4'b1111;
end
endmodule
Simulation results:

109

RTL schematic:

Technology schematic:

Result: 16:1 Multiplexer is implemented. Simulated and synthesized.

110

Program no: 11
Title: Implement 4bit Full adder circuit in verilog HDL, simulate and synthesize the results.
Aim: To implement 4bit Full adder circuit in verilog HDL, simulating and synthesizing the

results.
Block Diagram:

x[3:0]
y[3:0]

4-Bit Full
Adder

s[0:3]

cin

cout

Full Adder:
Truth table:
Input1: a

Input2: b

Input3: cin

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

111

Output1:
Sum
0
1
1
0
1
0
0
1

Output2:
Carry
0
0
0
1
0
1
1
1

K-Maps:
For sum:
b cin
a

00

01

11

10

For carry:
b cin
00

01

11

10

1
0
1

Logic Expressions:
sum=

cin

carry= a.b + b.c + c.a

112

Logic diagram:

a
b

sum

cin

a
b

carry

c
a

The complete design of 4-bit full adder is left as an assignment for the students.

113

Verilog Module:
module fulladder4bit(cin, x, y, s, cout, c1,c2,c3);
input cin;
input [3:0] x;
input [3:0] y;
output [3:0] s;
output cout;
inout c1,c2,c3;
fulladd stage0(cin, x[0], y[0], s[0], c1);
fulladd stage1(c1, x[1], y[1], s[1], c2);
fulladd stage2(c2, x[2], y[2], s[2], c3);
fulladd stage3(c3, x[3], y[3], s[3], cout);
endmodule
module fulladd(cinn, x, y, s, coutt);
input cinn, x, y;
output s, coutt;
assign s= x ^ y ^ cinn;
assign coutt= (x & y)|(x & cinn)|(y & cinn);
endmodule
Verilog test fixture:
module fulladderfourbittest_v;
reg cin;
reg [3:0] x;
reg [3:0] y;
wire [3:0] s;
wire cout;
fulladder4bit uut (.cin(cin),.x(x),.y(y),.s(s),.cout(cout));
initial begin
#100 $finish;
end
initial begin
cin=1'b1; x=4'b1101; y=4'b0001;
#20 cin= 1'b0; x=4'b1000; y=4'b0011;
#20 cin= 1'b1; x=4'b1000; y=4'b0011;
#20 cin= 1'b0; x=4'b1100; y=4'b0001;
#20 cin= 1'b1; x=4'b1001; y=4'b1111;
end
endmodule

114

Simulation Results:

RTL Schematic:

115

Technology Schematic:

Result: 4-bit Full Adder is implemented. Simulated and synthesized.

116

Program no: 12
Title Implement 4bit Full subtractor circuit in Verilog HDL, simulate and synthesize the results.
Aim: To implement 4bit Full subtractor circuit in Verilog HDL, simulate and synthesize the

results.
Block Diagram:

a[3:0]

4-Bit Full
Subtractor

d[3:0]

b[3:0]

bout

bin

Full subtractor:
Truth Table:
Input1:a

Input2:b

Input3:bin

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

117

Output1:
diff
0
1
1
0
1
0
0
1

Output2:
Borrow
0
1
1
1
0
0
0
1

K-Maps:
For diff:
b bin
a

00

01

11

10

For borrow:
b bin
00
a

01
1

11
1

10
1

0
1
1

Logic Expression:
diff= a

bin

borrow= ~a .bin + ~a. b + b. bin

118

Logic diagram:

The complete design of 4-bit full Subtractor is left as an assignment for the students.

119

Verilog module:
module fullsub4bit(a, b, bin, bout, d);
input [3:0] a;
input [3:0] b;
input bin;
output bout;
output [3:0] d;
wire [2:0]g;
fullsub (a[0],b[0],bin,g[0],d[0]);
fullsub (a[1],b[1],g[0],g[1],d[1]);
fullsub (a[2],b[2],g[1],g[2],d[2]);
fullsub (a[3],b[3],g[2],bout,d[3]);
endmodule
module fullsub(x,y,z,bar,diff);
input x;
input y;
input z;
output bar;
output diff;
assign diff=x^y^z;
assign bar=(~x&z)|(~x&y)|(y&z);
endmodule

Verilog test fixture:

module fulltest_v;
reg [3:0] a;
reg [3:0] b;
reg bin;
wire bout;
wire [3:0] d;
fullsub4bit uut ( .a(a), .b(b), .bin(bin), .bout(bout), .d(d) );
initial begin
#100 $finish;
end
initial begin
a=4'b 1100;
b=4'b 0001;
bin=0;
end
endmodule

120

Simulation results:

RTL schematic:

121

Technology Schematic:

Result: 4-bit Full Subtractor is implemented. Simulated and synthesized.

122

Program no: 13
Title: Implement the following using behavioral verilog model, simulate using test bench and

synthesize the results.

(a) D flip flop,
(b) T flip flop.
(c) JK flip flop.
Aim: To implement the following Flip-Flops using behavioral verilog model, simulating using

test bench and synthesizing the results.

(a) D flip flop,
(b) T flip flop.
(c) JK flip flop.

D- Flip flop:
Block Diagram:
d

D flip flop

q
clock

resetn
Characteristic Table:
resetn
1

clock

d
x

qn
x

q n+1
0

123

T- Flip flop:
Block Diagram:

T flip flop

q
clk

rst
Characteristic Table:
rst
1

clk

t
x

qn
x

q n+1
0

124

J-K Flip flop: Block diagram:

j

j-k flip flop

k
q

clk
rst

Characteristic Table:
rst

clk

qn

q n+1

125

D flip flop

verilog module:
module d_ff(d, clock, resetn, q);
input d;
input clock;
input resetn;
output reg q;
always @(posedge clock)
if(!resetn)
q<=0;
else
q<=d;
endmodule
verilog test fixture:
module dtest_v;
reg d;
reg clock;
reg resetn;
wire q;
d_ff uut (.d(d), .clock(clock), .resetn(resetn), .q(q));
always
#5 clock=~clock;
initial begin
#100 $finish;
end
initial begin
clock=1; resetn=0; d=1'b0;
#20 resetn=1; d=1'b1;
#20 resetn=0; d=1'b0;
end
endmodule
Simulation results:

126

RTL schematic:

Technology schematic:

127

T flip flop
Verilog module:
module tff(t, clk, rst, q);
input t, clk, rst;
output reg q;
always@(posedge clk)
if(rst == 1)
q=1'b0;
else begin
if(t==1)
q= ~q;
else
q= q;
end
endmodule

Verilog test fixture:

module tfftest_v;
reg t;
reg clk;
reg rst;
wire q;
tff uut ( .t(t), .clk(clk), .rst(rst), .q(q));
always
#5 clk = ~clk;
initial begin
#100 $finish;
end
initial begin
clk= 1; rst = 1; t=0;
#5 t=0;
#10 rst=0; t=1;
#30 t=0;
end
endmodule

128

Simulation results:

RTL schematic:

Technology schematic:

129

JK flip flop:
Verilog module:
module jkff(j, k, clk, rst, q);
input j, k, clk, rst;
output reg q;
always@( posedge clk)
begin
if(rst == 1'b1)
q<= 1'b0;
else
case({j,k})
2'b00: q<=q;
2'b01: q<=1'b0;
2'b10: q<=1'b1;
2'b11: q<= ~q;
endcase
end
endmodule
Verilog testfixture:
module jkfftest1_v;
reg j;
reg k;
reg clk;
reg rst;
wire q;
jkff uut (.j(j),.k(k), .clk(clk), .rst(rst),.q(q));
always
#5 clk = ~clk;
always
#5 rst = ~ rst;
initial begin
#100 $finish;
end
initial begin
rst = 0; j=1; k=0; clk=1;
#5 j=0; k=1;
#5 j=0; k=1;
#5 j=1; k=1;
#5 j=1; k=1;
#5 j=1; k=1;
#5 j=0; k=1;
#5 j=0; k=0;
#5 j=0; k=1;
#5 j=1; k=0;
#5 j=1; k=0;
#5 j=0; k=0;
end
endmodule
130

Simulation results:

RTL Schematic:

Technology schematic:

131

Result: The following flip flops

(a) D flip flop
(b) T flip flop
(c) JK flip flop
have been implemented. Simulated and synthesized.

132

Program no: 14
Title: Implement the 4-bit UP/ DOWN counter in Verilog HDL using behavioral model, simulate

and synthesize the results.

Aim: To implement the 4-bit UP/ DOWN counter in Verilog HDL using behavioral model,

simulating and synthesizing the results.

UP Counter:
reset
0

DOWN Counter:

A
0

reset

q is jumping from 0 state to F state.

133

Verilog Module:
module updowncount(q, reset,s, clk );
output reg [3:0]q;
input reset;
input clk;
input s;
always@(posedge clk)
begin
if(reset==1)
q<=0;
else
case(s)
0: q<=q+1;
1: q<=q-1;
endcase
end
endmodule
Verilog test Fixture:
module updowncounttest_v;
reg reset;
reg s;
reg clk;
wire [3:0] q;
updowncount uut (.q(q),.reset(reset),.s(s),.clk(clk));
always
#5 clk= ~clk;
initial begin
#400 $finish;
end
initial begin
reset=1;clk=1;s=0;
#10 reset=0;
#150 reset=1;
#20 reset=0; s=1;
end
endmodule

134

Simulation Result:

RTL Schematic:

135

Technology Schematic:

Result: The UP/ DOWN counter has been implemented. Simulated and synthesized.

136