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Finite String Pattern Recogniser

This document describes a group project to design a finite state machine pattern recognizer. It includes: - The problem statement of recognizing the pattern "010" while not seeing "100" - The methodology of designing a 6 state FSM with states S0-S6 - The state table and VHDL code implementing the FSM - Simulations showing the FSM recognizes examples inputs correctly

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Aditi Kanjolia
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
241 views

Finite String Pattern Recogniser

This document describes a group project to design a finite state machine pattern recognizer. It includes: - The problem statement of recognizing the pattern "010" while not seeing "100" - The methodology of designing a 6 state FSM with states S0-S6 - The state table and VHDL code implementing the FSM - Simulations showing the FSM recognizes examples inputs correctly

Uploaded by

Aditi Kanjolia
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Indian Institute of Technology, INDORE

EE208 : Digital Systems

COURSE PROJECT :

Finite String Pattern Recognizer


Group No.
Group Members :
Name, Roll No.

1
1. Aditi Kanjolia , 1200202
2. Kanza Naeem, 1200214
3. Himanshu Soni, 1100216

Email ID :

[email protected]

Contents

Problem Statement and Objective____________________________________ 3


Methodology___________________________________________________________ 3
Finite State Machine Design__________________________________________ 4
State Table _____________________________________________________________ 5
VHDL Code_____________________________________________________________ 6
RTL Schematic View of the Design___________________________________ 8
Simulation and Implementaion of few examples____________________ 9
Bibliography__________________________________________________________ 10

Problem Statement and Objective:

A Finite string pattern recognizer has one input (X) and one output (Z). The
Output is asserted whenever the input sequence 010 has been observed, as long
as the sequence 100 has never been seen.

Methodology:

Understanding the problem statement


Sample input/output behaviour:

X: 0 0 1 0 1 0 1 0 0 1 0
Z: 0 0 0 1 0 1 0 1 0 0 0
X: 1 1 0 1 1 0 1 0 0 1 0
Z: 0 0 0 0 0 0 0 1 0 0 0
.

Determine the possible states of machine.


Go for state minimization if possible.

Encode states and outputs into a binary code.


Draw the state diagram and state table.
Make the VHDL code.

Simulate the realization - Verify I/O behaviour of your state diagram to ensure it
matches specification.

Finite State Machine Design:

We will be needed to design a FSM for the problem. A finite-state machine (FSM) , or simply
a state machine, is a mathematical model of computation used to design both computer
programs and sequential logic circuits. It is conceived as an abstract machine that can be in
one of a finite number of states. The machine is in only one state at a time; the state it is in
at any given time is called the current state. It can change from one state to another when
initiated by a triggering event or condition; this is called a transition. A particular FSM is
defined by a list of its states, and the triggering condition for each transition.
For our problem, we need to have six states, marked as S0,S1..and so on. The FSm design
goes as follows.

State Table:
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0

Where- A, B, C = > Current State


A+, B + , C+ => Next state
X=> Input
And Z=> Output.
K- map for outputo/p
ab

ab
ab

ab

cx

X
0
1
0
1
0
1
0
1
0
1
0
1
0
1

cx

1
0

0
0

A+
0
1
0
0
0
1
1
0
1
1
1
0
1
1

cx

cx

X
0

B+
0
0
0
1
1
0
1
1
0
0
1
1
1
1

C+
1
0
1
0
1
0
0
0
1
0
0
0
0
0

O/P
0
0
0
0
1
0
0
0
0
0
0
0
0
0

X
0

Hence, OutputZ = ABCX

VHDL Codeentity GROUP1 is

Port ( clock : in STD_LOGIC;


X: in STD_LOGIC;
Z : out STD_LOGIC);
end GROUP1;

architecture Behavioral of GROUP1 is


type STATE_TYPE is (S0, S1, S2, S3,S4 ,S5 ,S6);
signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
begin

-- Process to hold combinational logic.


COMBIN: process(CURRENT_STATE, X)
begin
case CURRENT_STATE is
when S0 =>
if X = '0' then
Z <= '0';
NEXT_STATE <= S1;
else
Z <= '0';
NEXT_STATE <= S4;
end if;
when S1 =>
if X = '0' then
Z <= '0';
NEXT_STATE <= S1;
else
Z <= '0';
NEXT_STATE <= S2;
end if;
when S2 =>
if X = '0' then
Z <= '1';
NEXT_STATE <= S3;
else
Z <= '0';
NEXT_STATE <= S4;
end if;
when S3 =>
if X = '0' then
Z <= '0';
NEXT_STATE <= S6;

else
Z <= '0';
NEXT_STATE <= S2;
end if;
when S4 =>
if X = '0' then
Z <= '0';
NEXT_STATE <= S5;
else
Z <= '0';
NEXT_STATE <= S4;
end if;
when S5 =>
if X = '0' then
Z <= '0';
NEXT_STATE <= S6;
else
Z <= '0';
NEXT_STATE <= S2;
end if;
when S6 =>
if X = '0' then
Z <= '0';
NEXT_STATE <= S6;
else
Z <= '0';
NEXT_STATE <= S6;
end if;

end case;
end process;
-- Process to hold synchronous elements (flip-flops)
SYNCH: process
Begin
wait until CLOCK'event and CLOCK = '1';
CURRENT_STATE <= NEXT_STATE;
end process;
end Behavioral;

RTL Schematic View of the Design :

Simulation and Implementation of


some examples:
Example 1
Input 1 - 00101010010
Output 1- 0001010000

Example 2Input 2 11011010010


Output 2- 00000001000

Bibliography:

1. Digital Design Moris, Mano


2. Onilne web courses a. http://cseweb.ucsd.edu/~tweng/cse143/VHDLReference/aa.pdf
b. http://www.seas.upenn.edu/~ese171/vhdl/ESE170_Lec17_VHDL.pdf
3. VHDL , Programming By Examples- Douglas L. Perry
4. And, other online web VHDL tutorials.

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