Scribd
Upload
180 views

Lab Report 3 v2

This document summarizes a student's lab report on designing a 7-segment display decoder using Verilog. The experiment had three parts: 1) implementing the decoder with Verilog, 2) adding buffers to display digits on the left or right, 3) using multiplexers to show different values on left and right. The student successfully completed all parts, with the display switching sides and showing different digits as expected. Preparations included creating truth tables and K-maps to derive the logic for each segment.

Uploaded by

Andy Lapian
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
180 views

Lab Report 3 v2

This document summarizes a student's lab report on designing a 7-segment display decoder using Verilog. The experiment had three parts: 1) implementing the decoder with Verilog, 2) adding buffers to display digits on the left or right, 3) using multiplexers to show different values on left and right. The student successfully completed all parts, with the display switching sides and showing different digits as expected. Preparations included creating truth tables and K-maps to derive the logic for each segment.

Uploaded by

Andy Lapian
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 17

Nanyang Technological

University
(School of Computer Engineering)

AY2014/2015
SEMESTER 1

CE/CZ1005: Digital Logic


Experiment 3
Combinational Logic Design with Schematics
And Structural Verilog

Venue: Hardware Lab 3, N4-B1a-05

ANDY PIETER YOSEPH LAPIAN


U1120192D

INTRODUCTION
In Experiment Lab 3, students were conducted the design process and actualized
the logic circuit of 7-segment decoder. The experiment was divided into three
parts, which are

Implementation of 7-Segment Decoder Module using Verilog


Display of Right or Left Digit, and
Right or Left Display with Different Values.

Students were needed to prepare the truth table, K-maps and the Boolean
expressions of the 7-Segment Decoder before doing the experiment, which will
be shown in Preparation chapter.

PREPARATIONS
In this chapter, the truth table and K-maps for every segments are displayed.
Before observing the truth table, we need to know that the binary number are
being labelled X3, X2, X1 and X0 from left to the right sequence, for example
hexadecimal of 5 (0101) would be labelled as:

X3
0

X2
1

X1
0

X0
1

Table 1. Example of Labelling Sequence

Truth Table Section

Table 2. Truth Table of 7-Segment Decoder

K-Maps and Boolean Expressions of Every Segments

EXPERIMENTS AND OBSERVATIONS


Implementation of 7-Segment Decoder Module Using Verilog
In the first part of three-part experiment, students designed the 7-segment
decoder and also the display. Below are the diagram of it.

Figure 1. 7-Segment Decoder and Display

The displays segments are labelled from a to g, which would light up to form a
hexadecimal digits (0-9 and A-F). In order to design the display, students were
needed to write the truth table of every hexadecimal digits for every segment on
the display. The list of truth table are shown in Preparation chapter of this report.
By using the Verilog hardware description language (HDL), student were able to
create and ease the design process. The two files, sevenseg.v and sevenseg.sym
were needed in this experiment, which can be retrieved from NTULearn. I/O ports
were added which consisted of 4 inputs and 7 outputs.

Figure 2. Sevenseg.v with I/O Ports

Student also needed to connect FPGA board with Digilent PmodSSD Peripheral
Module Board, together with the outputs of sseg. The connection was made
based on Table 10.

10

Figure 3. Sseg Logic Output

Table 3. Connection of Logic Output and Display Module

Figure 4. UCF File

After these settings, students need to generate the Programming File (sseg.bit)
and activate it using Adept software. Here is the result of the experiment in first
part.

11

Figure 5. Experiment Result in First Part

The experiment was conducted successfully. By connecting up all the logic


outputs in Verilog (sevenseg.v) and completing the remaining lines in UCF file. All
of 16 digits (0-9, a-f) were able to be shown on the 7-Segment Display.

Display Left or Right Digit


In second part of experiment, we need to create 7-segment display that can
show the digit on left or right. Thus in this part of experiment we need the
addition of buffer to connect the input and output of this logic.

Figure 6. Buffer Addition

In addition to that, we also need to add several lines of logic in the UCF file, to
connect the display with the outputs.

12

Figure 7. Addition of LR input and TGLOUT output

Generate the programming file. Here is the result of the second part of the
experiment.

Figure 8. Result of Experiment in Second Part

The second part was conducted successfully. By pressing the F5 button, we able
to change the display to be shown in left or right without any change in the
value.

Display a Different Value on the Left and Right Digits


In the third part of experiment, we need to display different values of two digits
by pressing the pushbutton. To achieve this, we need to make use of the
multiplexers which were done in Lab Experiment 2. The overall design is shown
in next figure.

13

Figure 9. Third Part of Experiment Design Idea

Thus, in the experiment, the design was made to be this, for sevenseg.v and the
UCF file.

Figure 10. Realization of the Design of Third Part of Experiment

Generate the program from the bit file. Here is the result of the experiment.
14

Figure 11. Result of Third Part of the Experiment

The experiment was conducted successfully. Two different values were able to
show together when changing the left or right digit due to the multiplexers in the
design.

QUESTIONS
Question 1
With the addition of the inverter, the digit would appear in left first, instead of on
the right if we used buffer. By pressing the pushbutton F5, the digit would appear
to the right, instead of on the left if we used the buffer.
Question 2

As shown on the figure, the SW(7:4) are connected from the first (the most top)
to the fourth mux (the most bottom), respectively. The same set-up also has
been done for SW(3:0), respectively. Thus with this set-up, initially, the output
from SW(3:0) would show first and by pressing the pushbutton, the output from
SW(7:4) would show.

DISCUSSION
Experiment 1: Logic Gates and Integrated Circuits
In experiment 1, we able to learn the behaviour of NAND and XOR gates by
observing the oscilloscope. In addition, we also able to build the circuit logic by
15

using bread broad. Full adder logic also had been made in this experiment, which
also have been tested with different inputs to generate various outputs.
Experiment 2: Logic Design in FGPA with Schematic Figure
In Experiment 2 by using Xilinx FPGA design, we able to create full adder module
and also the addition/subtraction of 2s complement. The result was perfect,
which was shown by the correct output for the given inputs that had been given.
Experiment 3: Combinational Logic Design with Schematics and
Structural Verilog
In Experiment 3, the 7-segment decoder was implemented by using schematics
and structural Verilog. The implementation of buffer and multiplexers had
increased the complexity of the experiment, which was shown by the display that
can be switched to left or right with different values.

CONCLUSION
In Experiment 3, the implementation 7-decoder display had been done
successfully without any problems. The K-maps for every segment has been
made prior to experiment in order to generate the correct output from the inputs
which had been given.
In addition, with buffer and multiplexers in the experiment, the complexity of the
experiment had increased. The display able to change on left or right and also
came up with different values which was done by pressing the pushbutton.

REFERENCES
Anonymous. 1005Lab_3.pdf. Retrieved from
www.NTULearn.ntu.edu.sg/DigitalLogic

16

You might also like