RISC?

RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that

utilizes a small, highly-optimized set of instructions, rather than a more specialized set of
instructions often found in other types of architectures.
History
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and
early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed
with a similar philosophy which has become known as RISC. Certain design features have
been characteristic of most RISC processors:

one cycle execution time: RISC processors have a CPI (clock per instruction) of
one cycle. This is due to the optimization of each instruction on the CPU and a
technique called <i.pipelining< i="">;
</i.pipelining<>

pipelining: a techique that allows for simultaneous execution of parts, or stages, of

instructions to more efficiently process instructions;
large number of registers: the RISC design philosophy generally incorporates a
larger number of registers to prevent in large amounts of interactions with
memory

How Pipelining Works

PIpelining, a standard feature in RISC processors, is much like an assembly line. Because
the processor works on different steps of the instruction at the same time, more
instructions can be executed in a shorter period of time.
A useful method of demonstrating this is the laundry analogy. Let's say that there are
four loads of dirty laundry that need to be washed, dried, and folded. We could put the
the first load in the washer for 30 minutes, dry it for 40 minutes, and then take 20
minutes to fold the clothes. Then pick up the second load and wash, dry, and fold, and
repeat for the third and fourth loads. Supposing we started at 6 PM and worked as
efficiently as possible, we would still be doing laundry until midnight.

Source: http://www.ece.arizona.edu/~ece462/Lec03-pipe/
However, a smarter approach to the problem would be to put the second load of dirty
laundry into the washer after the first was already clean and whirling happily in the dryer.
Then, while the first load was being folded, the second load would dry, and a third load
could be added to the pipeline of laundry. Using this method, the laundry would be
finished by 9:30.

Source http://www.ece.arizona.edu/~ece462/Lec03-pipe/
Watch a movie of pipelining in action! (Source: http://www.inf.fhdortmund.de/person/prof/si/risc/intro_to_risc/irt0_index.html)

RISC Pipelines
A RISC processor pipeline operates in much the same way, although the stages in the
pipeline are different. While different processors have different numbers of steps, they
are basically variations of these five, used in the MIPS R3000 processor:
1.
2.
3.
4.
5.

fetch instructions from memory

read registers and decode the instruction
execute the instruction or calculate an address
access an operand in data memory
write the result into a register

If you glance back at the diagram of the laundry pipeline, you'll notice that although the
washer finishes in half an hour, the dryer takes an extra ten minutes, and thus the wet
clothes must wait ten minutes for the dryer to free up. Thus, the length of the pipeline is
dependent on the length of the longest step. Because RISC instructions are simpler than
those used in pre-RISC processors (now called CISC, or Complex Instruction Set
Computer), they are more conducive to pipelining. While CISC instructions varied in
length, RISC instructions are all the same length and can be fetched in a single operation.
Ideally, each of the stages in a RISC processor pipeline should take 1 clock cycle so that
the processor finishes an instruction each clock cycle and averages one cycle per
instruction (CPI).

The simplest way to examine the advantages

and disadvantages of RISC architecture is by
contrasting it with it's predecessor: CISC
(Complex Instruction Set Computers)
architecture.
Multiplying Two Numbers in Memory
On the right is a diagram representing the
storage scheme for a generic computer. The
main memory is divided into locations
numbered from (row) 1: (column) 1 to (row) 6:
(column) 4. The execution unit is responsible
for carrying out all computations. However, the
execution unit can only operate on data that
has been loaded into one of the six registers (A,
B, C, D, E, or F). Let's say we want to find the
product of two numbers - one stored in location
2:3 and another stored in location 5:2 - and
then store the product back in the location 2:3.
The CISC Approach
The primary goal of CISC architecture is to
complete a task in as few lines of assembly as
possible. This is achieved by building processor hardware that is capable of understanding
and executing a series of operations. For this particular task, a CISC processor would
come prepared with a specific instruction (we'll call it "MULT"). When executed, this
instruction loads the two values into separate registers, multiplies the operands in the
execution unit, and then stores the product in the appropriate register. Thus, the entire
task of multiplying two numbers can be completed with one instruction:
MULT 2:3, 5:2
MULT is what is known as a "complex instruction." It operates directly on the computer's
memory banks and does not require the programmer to explicitly call any loading or
storing functions. It closely resembles a command in a higher level language. For
instance, if we let "a" represent the value of 2:3 and "b" represent the value of 5:2, then
this command is identical to the C statement "a = a * b."
One of the primary advantages of this system is that the compiler has to do very little
work to translate a high-level language statement into assembly. Because the length of
the code is relatively short, very little RAM is required to store instructions. The emphasis
is put on building complex instructions directly into the hardware.
The RISC Approach
RISC processors only use simple instructions that can be executed within one clock cycle.
Thus, the "MULT" command described above could be divided into three separate
commands: "LOAD," which moves data from the memory bank to a register, "PROD,"
which finds the product of two operands located within the registers, and "STORE," which
moves data from a register to the memory banks. In order to perform the exact series of
steps described in the CISC approach, a programmer would need to code four lines of
assembly:
LOAD A, 2:3

CISC and RISC Convergence

State of the art processor technology has changed significantly since RISC chips were first
introduced in the early '80s. Because a number of advancements (including the ones
described on this page) are used by both RISC and CISC processors, the lines between
the two architectures have begun to blur. In fact, the two architectures almost seem to
have adopted the strategies of the other. Because processor speeds have increased, CISC
chips are now able to execute more than one instruction within a single clock. This also
allows CISC chips to make use of pipelining. With other technological improvements, it is
now possible to fit many more transistors on a single chip. This gives RISC processors
enough space to incorporate more complicated, CISC-like commands. RISC chips also
make use of more complicated hardware, making use of extra function units for
superscalar execution. All of these factors have led some groups to argue that we are
now in a "post-RISC" era, in which the two styles have become so similar that
distinguishing between them is no longer relevant. However, it should be noted that RISC
chips still retain some important traits. RISC chips stricly utilize uniform, single-cycle
instructions. They also retain the register-to-register, load/store architecture. And despite
their extended instruction sets, RISC chips still have a large number of general purpose
registers.
Simultaneous Multi-Threading
Simultaneous Multi-Threading (SMT) allows multiple threads to be executed at the exact
same time. Threads are series of tasks which are executed alternately by the processor.
Normal thread execution requires threads to be switched on and off the processor as a
single processor dominates the processor for a moment of time. This allows some tasks
that involve waiting (for disk accesses, or network usage) to execute more efficiently.
SMT allows threads to execute at the same time by pulling instructions into the pipeline
from different threads. This way, multiple threads advance in their processes and no one
thread dominates the processor at any given time.
Value Prediction
Value prediction is the prediction of the value that a particular load instruction will
produce. Load values are generally not random, and approximately half of the load
instructions in a program will fetch the same value as they did in a previous execution.
Thus, predicting that the load value will be the same as it was last time speeds up the
processor since it allows the computer to continue without having to wait for the load
memory access. As loads tend to be one of the slowest and most frequently executed
instructions, this improvement makes a significant difference in processor speed.