ANALOG TO DIGITAL CONVERTER (ADC)

Data taken from a physical system normally appear in electrical analog form.
The need arises for a device that converts analog information into digital form. Analog
to digital converters perform the task of converting the naturally occurring analog
signals into digital form.

Vx

unknown analog voltage

V fs

full scale voltage

Input/output relation of an ADC may be given by

n

a 2
i 1

Vx
N
V fs

Vx V fs a1 21 a2 2 2 ... an 2 n

Or

An ADC receives an analog voltage signal

signal by comparing it to a reference voltage,
ADCs represent a positive decimal fraction,
Or

V fs

Vx and

converts it into a digital

. The digital at the output of the

V
N; x
V fs

Vx V fs N

Considering natural binary code and finite no. of bits (say n), then

N a1 21 a2 22 ... an 2 n

Vx ; V fs a1 21 a2 22 ... an 2 n
n

; V fs ai 2 i
i 1

V fs

Here, the full scale range,

fs

2n

n
of the ADC is partitioned into 2 segments, each of width

(where n is the no. of bits) called quantization step (q)

Any analog voltage

Vx V fs

i.e.

V fs
2n

is replaced by a discrete voltage which is an

n
integral multiple of the quantization step i.e. 0, q, 2q,3q, ... , (2 1) q . The maximum

2 N 1
V fs

N
2

possible quantized value of the input voltage is

.
Replacement of an analog voltage by a discrete value can be carried out either
by truncation or by rounding-off.

ANALOG TO DIGITAL CONVERTER (ADC)

Here output changes state at the end of each quantization step (except last
step).
Quantization Error(e) = quantized value Actual value

emax q 1 LSB
e

q
q
V
can be reduced to 2 if an offset voltage of 2 is added to x

Magnitude of max
prior to quantization using truncation.

A large number of Analog to Digital circuits are available. The most commonly
used ADCs are
1. Successive approximation type
2. Integration type (single and dual slope)
3. Counter or servo type
4. Parallel type

SUCCESSIVE APPROXIMATION TYPE ADC

Block Diagram:

A 3-bit successive approximation A/D convertor is shown above.

ADC/NNS

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ANALOG TO DIGITAL CONVERTER (ADC)

The convertor shown above is designed to convert an analog waveform into

binary code (neglecting sign bit).
The convertor consists of:
1. Five D-type flip flops FFA to FFE. These flip flops are connected are connected to
form modulo-5 ring counter. This counters outputs are Q A to QE, only one of
which is at logic 1 at any time. With each successive clock cycle, the logical
level 1 is transferred from A to B to C etc.
2. Flip flops FF1, FF2 and FF3: these are used to register the digital bits, with FF1
corresponds to LSB and FF3 to MSB.
3. Sample and Hold (S/H) amplifier: The sampled value of the analog signal should
be held constant during the sequence of operations. Hence sample & hold
amplifier is used whose switch is operated by Q E.
4. Comparator: Compares the analog input V x and output of the D/A convertor. Its

V V

V V

0 and when
x
0 , comparator output
0 is 0.
output 0 is 1 when x
5. 3-bit D/A convertor: Digital to analog convertor, whose output is used to
compare with the analog input.

6. Summer: To add an offset voltage

1
LSB
2
to reduce the quantization error to

1
LSB
2
.
Operation

The conversion of an analog input voltage into digital value uses a high speed
DAC. The analog output of a high-speed DAC is compared against the analog input
signal. The digital result of the comparison is used to control the contents of a digital
buffer that both drives the DAC and provides the digital output word. The successiveapproximation ADC uses fast control logic which requires only n comparisons for an nbit binary result.

The conversion of an analog input voltage x into its corresponding digital value
by using a 3-bit successive approximation ADC requires five clock intervals. During the
first four clock intervals analog output

V0

of the 3-bit D/A converter is compared with

the analog input x and depending upon the comparators output, the flip flop FF1,
FF2 & FF3 are made set or reset. During the fifth clock interval, digital outputs are
read from FF1, FF2 & FF3 where FF1 gives the LSB and FF3 gives MSB. Sampling of the

unknown voltage x is performed by sample & holds circuit during this fifth clock
periods and the sampled input is held by sample & hold circuit for the next four clock
intervals.
The conversion cycle begins when the output of FFA, i.e.

QA 1

QA 1

. FFA to

QB QC QD QE 0

FFE

forms a modulo-5 ring counter and thus when

, then
. FF3
will set to logic 1 and FF1 & FF2 will be reset to logic 0. This will produce

Q3 1 and Q2 Q1 0

. This

Q3Q2Q1 100

is available as input of the internal D/A

converter which produce a analog voltage

voltage then,

C0

will be

V0

as its output. If

V fs

is the full scale output

V fs

2 . The comparator compares Vx and V0 and comparators output.

C0 1 if Vx V0
0

ADC/NNS

V0

if Vx V0
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ANALOG TO DIGITAL CONVERTER (ADC)

Thus, at the end of first clock interval, comparators output depends upon the
comparison of

Vx and V0

During

the

QA QC QD QE 0

next
. With

clock

interval,

QB 1

while

QB 1 AND
C 1
,
gate G3 is enabled. If 0
,
C0 0

then FF3 is reset (logic 0) and if

, then FF3 is left in the set
state (logic 1). Thus the assigned logic 1 to the most significant
position has been retained or changed to logic 0 will depend upon
the result of comparison of

Vx and V0

i.e. the output of comparator

C0

, during the beginning of the second clock interval. Thus the MSB
of the digital word has been determined to 1 or 0 and the digital word may be 1XX or
0XX as shown in figure 1.
As

Q3Q2Q1

QB 1

, FF2 will set to logic 1 and during the later half of the clock interval,

is presented to the 3-bit D/A converter which gives corresponding analog

voltage

V0' . The comparator compares Vx with V0' and the comparators output will be
C0' 1 if Vx V0

if Vx V0

Thus, at the end of the 2nd clock interval, comparators output

comparison of

C0'

depends upon the

'
0

Vx and V .

During the first half of the 3rd clock interval, depending upon the comparators

C'

output 0 , FF2 i.e. MSB-1 bit retains the set value digital 1 or reset to digital 0 and the
digital word may be 01X or 00X when MSB=0 or 11X or 10X for MSB=1. During
the later half of the clock interval,

Q3Q2Q1

(= 011 or 001 or 111 or 110) has been

presented at the DACs input which converts it into analog voltage

compared with the input analog voltage

Vx

V0'' . This voltage is

and the comparators output will be

C 1 if Vx V0
''
0

if Vx V0

Thus, at the end of the 3rd clock interval, comparators output

comparison of

C0''

depends upon the

''
0

Vx and V .
C ''

During the fourth clock interval, depending upon the comparators output 0 ,
FF3 i.e. MSB-2 bit retains the set value digital 1 or reset to digital 0 and the digital
word may be 000 or 001 when MSB=0 and MSB-1=0 or 010 or 011 for MSB=0
and MSB-1=1 etc.
These sequences of bit testing of successive approximation type ADC is shown
in figure 2.

ADC/NNS

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ANALOG TO DIGITAL CONVERTER (ADC)

During the fifth clock interval, with

GA , GB, and GC

QE 1
Vx

QE 1

and

QA QB QC QD 0

, AND gates

are enabled and the digital output is available.

Also, during this clock interval, sample and hold circuit is made enabled by
to sample the input analog voltage. When

QE 0

, sampled analog input voltage

is held by sample and hold circuit.

Sample and Hold Circuit:

Both the opamp OP1 and OP2 are unity gain non-inverting voltage
amplifier. Switch S is operated i.e. remains closed when
Example:
Encode an analog voltage

Vx 4.9 volts

V fs
2

full

8
1 volt
23

scale

for N 3

into a 3-bit digital word having a full scale range

of 8 volts and offset voltage of 1 2 LSB .

For

QE 1

voltage

V fs 8 volts

quantization

step,

(3-bit converter). The maximum possible quantized value

2 1
7
V fs 8 7 volts

N
8
2
N

of the input voltage is

. Therefore, converters output 000

corresponds to 0 volts and 111 corresponds to 7 volts and LSB 1 volts . Offset voltage
is 1 2 LSB 0.5 volt .
1st clock interval
Here

QA 1

Therefore,

ADC/NNS

and

QB QC QD QE 0

Q3 1; Q2 0 and Q3 0

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ANALOG TO DIGITAL CONVERTER (ADC)

Q3Q2Q1 100

And D/A input =

D/A output =

V0 4 offset voltage 4 (1 2) LSB 4 0.5 3.5 volts

C0 0; Q Vx V0
2nd clock interval
Here

QB 1

Therefore,
As

QB 1

and

QA QC QD QE 0

Q2 1; Q1 0 and Q3 0

and

C0 0

Q3 remains at set state i.e. Q3 1

Q3Q2Q1 110

And D/A input =

D/A output =

V0' 4 offset voltage 4 2 (1 2) LSB 4 2 0.5 5.5 volts

C 0' 1; Q Vx V0
3rd clock interval
Here

QC 1

Therefore,
As

QC 1

and

QA QB QD QE 0

Q3 1; Q1 0 and Q2 0

and

C 0' 1

Q2 will changed to digital '0 ' i.e. Q2 0

And D/A input =

D/A output =

Q3Q2Q1 101

V0' 4 offset voltage 4 1 (1 2) LSB 4 1 0.5 4.5 volts

C 0'' 0; Q Vx V0
4th clock interval
Here
As

QD 1

QD 1

and

and

QA QB QC QE 0

C 0'' 0

Q1 remains at set state i.e. Q1 1

Q3Q2Q1 101
D/A output =

V0' 4 offset voltage 4 1 (1 2) LSB 4 1 0.5 4.5 volts

C 0'' 0; Q Vx V0
5th clock interval
Here

QE 1

Therefore,

and

QA QB QC QD 0

GA , GB and GC

are enable and digital output

Q3Q2 Q1 101

is

available.

ADC/NNS

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ANALOG TO DIGITAL CONVERTER (ADC)

DUAL SLOPE CONVERTER (ADC)

This technique involves comparison of an unknown voltage with a reference

voltage. The unknown voltage
be of opposite polarity.

VX

and reference voltage applied in this circuit must

This process utilized the voltage to time conversion technique twice, first by

X to a function of time and then it is compared

connecting the unknown voltage
with that generated by the precision reference voltage.

X
In integrator the unknown voltage
or known precision voltage R are
applied successively (controlled by digital control circuit). The output of the integrator

is the linearly rising ramp when

is applied after

VX

VX

is applied and linearly decreasing ramp when

VR

is applied.

Comparator compares the output of the integrator with the ground voltage and
thus its output goes high as the conversion process started.
Binary up counter counts the no. of clock pulses when the output of the
comparator is is high.
Digital control circuit gives two types of commands (i) Reset and (ii) Convert.
Working Principle
i)
Before conversion begins, the capacitor is discharged and the counter is reset
to zero count.
ii)
The conversion process is initiated by connecting the input switch through the
analog input. Analog input voltage is then integrated by the integrator. If the
input to the converter is taken from a sample & hold circuit then it can be
assumed to be constant and in addition if it is ensured to be negative then the
output of the integrator will be linearly rising ramp.

v0 (t )
iii)

1
V
( VX ) dt X t

RC 0
RC

Immediately after the conversion process starts, the comparator output goes
high which in turn starts up the up counter. When the
becomes 1, say at time

ADC/NNS

t ta

QN

of flip flop FFN

, it switches the input of the integrator to a fixed

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ANALOG TO DIGITAL CONVERTER (ADC)

VR

reference voltage
given by

by a control circuit. The output of the integrator is then

t

v0 (t )

VX
1
ta
(VR ) dt
RC
RC ta
VX VR (t ta )

RC
RC
t t

b,
Thus the output of the integration is decreasing linearly and at time
becomes zero. This in turn changes the output of the comparator to low state.

V (t t )
VX
ta R b a
RC
RC
V (t t )
VX R b a
ta
0

(tb ta )

VX
ta
VR

t
If f frequency of the clock pulse which is fixed, the time a required for the
counter to set the MSB (
constant

which

corresponds to

ta

depends

QN

) to logical 1, is given by

upon

the

clock

frequency

If M be the no. of pulses counted by the time period

Or

Or

2N
f . Here, ta is

f . 2 N clock pulses
, then

M
(tb ta )
f
VX t a M

VR
f
VX

VR M
.
ta f

VX

VR M
. .f
2n f

Or
Or

(tb ta )

ta

VR
M
2n
VX M
VX

Or
Therefore, the contents of the counter M is directly proportional to the input

voltage X .
Conversion accuracy is not dependent upon resistor and capacitor values and
hence the clock frequency.

ADC/NNS

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