Asst. Prof.

Alkesh M Khatri

MPI Sem- IV

Samarth College of Engineering and Technology

Unit 3 Introduction to 8 bit Microprocessor
Q.1.
Draw and Explain Timing Diagram of Op-Code Fetch Machine
Cycle.
Q.2.
Draw and Explain Timing Diagram of Memory Read Machine
Cycle.
Q.3.
Draw and Explain Timing Diagram of Memory Write Machine
Cycle.
Q.4.
Draw and Explain Timing Diagram of I/O Read and I/O Write
Machine cycle.
Q.5.
Draw and Explain Timing Diagram of LDAX Instruction.
Q.6.
Draw and Explain Timing Diagram of STA 3000H Instruction.
Q.7.
Draw and Explain Timing Diagram of MVI A, 32H Instruction.
Q.8.
Draw and Explain Timing Diagram of IN 00H Instruction.
Q.9.
Draw and Explain Timing Diagram of INR M Instruction.
Q.10.
Draw Timing Diagram of following 1 byte Instruction.
1) ADC M ; 2)ADD M; 3) ANA M; 4) CMP M; 5) MOV R, M; 6) MOV M, R;
7) SBB M; 8) STAX Rp; 9) SUB M; 10) XRA M
Q.11.
Draw Timing Diagram of following 2 byte Instruction.
1) ACI data ; 2)ADI data; 3) ANI data; 4) CMI data; 5) MVI R, data; 6)
ORI data
7) SUI data; 8) XRI data
Q.12.
Draw Timing Diagram of following 3 byte Instruction.
1) JMP addr
Q.13.
Explain Absolute and Partial Decoding with example.
Q.14.
Interface 16k x 8 EPROM memory to 8085. The available
memory chip is 4k x 4. The address should start from 0000H
onwards. Give the details interfacing schematic and address range
for each chip used.
Q.15.
Assume that 16KB memory is to be interfaced to 8085, where
8KB is ROM & 8KB is RAM. The Starting address is 8000H. Use
necessary decoder and giver for mapping.
Q.16.
Describe the Comparison of I.O mapped and Memory Mapped
I/O Interfacing.
Q.17.
Show with the help of Circuit Diagram how to connect one i/p
port and one O/P Port on same address.
Q.18.
What is an O/P port? Explain the design of output port with
example.

Solution of Assignment 3
Q.1.
Draw and Explain Timing Diagram of Op-Code Fetch Machine
Cycle.
Answer:

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Fig. shows the 8085 instruction fetch timing diagram. The

instruction fetch cycle requires either four or six clock periods (T states).
The other m/c cycles that follow OFMC will need three clock cycles.
The purpose of an OF is to read the contents of a memory location
containing the opcode addressed by the program counter and to place it
in the instruction register.

In beginning of state T1, th e8085A puts a low on the IO/ M

line of

the system bus indicating a memory operation the 8085 sets S 1=1 and
S0= 1 on the system bus, indication the memory fetch operation this
status information remains constant for the duration of the m/c cycle.
During T1state, the 16 bit address A 15 - A0, of the memory location
containing the op code is obtained from the program counter pc and
placed in the address and address data latches the higher order 8 bits of
the address appears on the address bus A15 - A0, remains constants until
the end of the state T3 during T4 state the data on the address bus is
unspecified.
The low order 8 bits of the address is placed on the address/data
bus, AD7 - AD0 at the beginning of T1 this data however remains valid only
until the beginning of T2 at which time the addr/data bus is floated (3
states) because this is time multiplexed bus and used on the data bus
during T2 and T3 state. Therefore addr latch enable (ALE) signal issued by
the microprocessor during T1 is used to latch this lower order addr in same
external hardware 8212 on its falling edge the 16 bit addr select a
particular memory location.

RD
During state T2, at the beginning. The
signal goes low
indicating read operation and the opcode to be fetched is placed on the
data bus, AD7 - AD0, by the addressed memory location. The contents of

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

(pc) is incremented be 1 during this state as during T 1 state the pc has

sent the addr to addr bus. The access memory should be fast enough to

RD
output its data before
goes high slower memories can gain more
time by pulling
the READY signal of 8085 LOW this will introduce an integral no of T wait
state between T2 and T3 as long as READY is low on the ring edge of the

RD
control signal in T3, the opcode obtaining from memory is transferred
to the micro process instruction register.
During data T4, the 8085 decodes the instruction and determines
whether to enter state T5 or to enter T1 state of the next m/c cycle from
the operation code the microprocessor determines what other m/c cycles
if any must be execute to complete the instruction cycle state T5 & T6,
when entered, are used for internal microprocessor operation necessitated
by the instruction.
The micro RTL flow for 4 data OFMC is shown below.

OFMC: Status IO/ M =0, S1=1, S0=1

T1: AD7- AD0 (PCL), AD15- AD8 (PCH), ALE=

T2: RD = 0(PC) (PC)+1, AD7- AD0 M (AB)

T3: RD = 1, , INTERNAL REGISTER ( AD7- AD0)

T4: Microprocessor Decodes the Opcode and Decides Whether T 5 AND T6
states are required or next m/c cycle is executed. During T 4-T6 states, T1,
AD7- AD0 = Tri Stated, AD15- AD8= unspecified.
Fig below shows the timing diagram for a 6-state OFMC.

Note: whenever the addr information is sent from the program

counter to the external world during T 1 state, then the pc is incremented
by 1 during the subsequent T2 state so that pc points to the next
subsequent byte. However if the addr information from pc has not been
sent out during the T1 state to the external until then pc will not be
incremented during T2 state.

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Q.2. Draw and Explain Timing Diagram of Memory Read

Machine Cycle.
Answer:
It requires 3 states T1 to T2 the purpose of the memory READ
operation is to read the contents of a memory location addressed by a and
place the data in a microprocessor register by a register pair, the source
of address issued during T1 is not always the program counter but may be
any one of the several other register pairs in the
Microprocessor
depending on the particular instruction of which the m/c cycle is a part.
The 8085 uses m/c cycle MC1 to fetch and decode the instruction. It
then performs the memory read operation in MC2. E.g. in LXIH, Addr.

The IO/ M signal made low to indicate the external world that a
memory reference is required. Then microprocessor made S1=1, S0=0
indicating that memory READ operation is to be performed. During the
8085 places the contents of high byte of the memory address register,
such as that contents of the (PCH) or (H) register on lines A15 - A8 and
the contents of the low byte of the memory address register such as
contents of the (PCL) or (L) reg. On lines AD7 - AD0. The 8085 sets ALE to
HIGH, indicating the beginning of MC-2 AS soon as ALE goes to low, the
8085 latches the low byte of the address lines, since the same lines as
going to be used as data lines.

During T2 state, the RD signal goes LOW indicating a READ

operation. If the addr sent and during T 1 state is from pc, then pc is
incremented by 1 otherwise not the external logic gets the data from the
memory location addressed by the memory address register such as (H,L)
pair and places the data on to data bus AD7 - AD0.

During T2 state, RD signal goes high, this low to high signal

transfer the data from the data bus to internal register such as the
accumulator.

MRMC: status signals IO/ M

=0, S0=0, S1=1

T1: AD7- AD0 (PCL), AD15- AD8 (PCH), ALE=

T2: RD = 0(PC) (PC)+1, AD7- AD0 M (AB)

T3: RD = 1, , INTERNAL REGISTER ( AD7- AD0)

or

T1: AD7- AD0 (PCL), AD15- AD8 (PCH), ALE=

T2: RD = 0 , AD7- AD0 M (AB)

T3: RD = 1, , INTERNAL REGISTER ( AD7- AD0)

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Q.3. Draw and Explain Timing Diagram of Memory Write

Machine Cycle.
Answer:
It also requires only T1 to T3 states the purpose of memory write is to
store the contents of any of the 8085 reg. such as the accumulator into
a memory location addressed by a register pair such as HL.

T1

T2

T3

The 8085
made IO/

M
=0
in
of

the
beginning
T1state to
indicate

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

memory reference operation then it puts S 0=1, S1=0 indicates a

memory write operation.
During T1 state 8085 places the memory address register high byte
such as the contents of the H register on lines A 15- A8 and also places
the MAR low byte such as the contents of the L register on lines AD 7AD0. the 8085sets ALE to HIGH, indicating the beginning of MWRMC. As
soon as ALE goes to low, the 8085 latches the low byte of the address
lines since the same lines are going to be used as data lines. During T 2

state, WR goes low indicating memory write operation It also places

the contents of the internal register say accumulator on data lines AD 7AD0.

During T3 state, WR goes high this low to high transition is used to

transfer the data from the data lines to the memory location address
by MAR such as HL reg. pair.

MWRMC: IO/ M =0, S0=1, S1=0

T1: AD7- AD0 (L), AD15- AD8 (H), ALE=

P (Internal Register)
T2: MR = 0, AD7- AD0

T3: WR = 1, , M(AB) (AD7- AD0)

Q.4. Draw and Explain Timing Diagram of I/O Read and I/O
Write Machine cycle.
Answer:
The I/O read and I/O write machine cycles are similar to the memory
read and Memory write machine cycles, respectively, except that the

IO/ M signal is high for I/O read and I/O write machine cycles.

High IO/ M signal indicates that it is an I/O operation.

Following figure shows the timing diagram of I/O read and I/O write
cycles respectively.

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Q.5. Draw and Explain Timing Diagram of STA 526AH

Instruction.
Answer:
STA means Store Accumulator -The contents of the accumulator is
stored in the specified address(526A).
The opcode of the STA instruction is said to be 32H. It is fetched
from the memory 41FFH(see fig). - OF machine cycle
Then the lower order memory address is read(6A). - Memory Read
Machine Cycle
Read the higher order memory address (52).- Memory Read Machine
Cycle
The combination of both the addresses are considered and the
content from accumulator is written in 526A. - Memory Write Machine
Cycle
Assume the memory address for the instruction and let the content
of accumulator is C7H. So, C7H from accumulator is now stored in
526A.

Q.6. Draw and Explain Timing Diagram

Instruction.
Answer:
Fetching the Opcode DBH from the memory 4125H.
Read the port address C0H from 4126H.

of

IN

C0H

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Read the content of port C0H and send it to the accumulator.

Let the content of port is 5EH.

Q.7. Draw and Explain Timing Diagram of INR M Instruction.

Answer:
Fetching the Opcode 34H from the memory 4105H. (OF cycle)
Let the memory address (M) be 4250H. (MR cycle -To read Memory
address and data)
Let the content of that memory is 12H.
Increment the memory content from 12H to 13H. (MW machine cycle)

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Q.8. Draw and Explain Timing Diagram of MVI B, 43H

Instruction.
Answer:
Fetching the Opcode 06H from the memory 2000H. (OF
machine cycle)
Read (move) the data 43H from memory 2001H. (memory
read)

Asst. Prof. Alkesh M Khatri

Q.9. Draw Timing Diagram of LDAX Instruction.

Answer:

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Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Q.10. Draw Timing Diagram of following 1 byte Instruction.

1) ADC M ; 2)ADD M; 3) ANA M; 4) CMP M; 5) MOV R, M; 6) MOV M, R;
7) SBB M; 8) STAX Rp; 9) SUB M; 10) XRA M
Answer:
1. ADC M

2. ADD M

Asst. Prof. Alkesh M Khatri

3. ANA M

4. CMP M

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Asst. Prof. Alkesh M Khatri

5. MOV R, M

6. MOV M, R

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Asst. Prof. Alkesh M Khatri

7. SBB M

8. STAX Rp

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Asst. Prof. Alkesh M Khatri

9. SUB M

10.

XRA M

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Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Q.11. Draw Timing Diagram of following 2 byte Instruction.

1) ACI data ; 2)ADI data; 3) ANI data; 4) CMI data; 5) MVI R, data; 6)
ORI data
7) SUI data; 8) XRI data
Answer:
1. ACI data

2. ADI data

Asst. Prof. Alkesh M Khatri

3. ANI data

4. CPI data

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Asst. Prof. Alkesh M Khatri

5. MVI R, data

6. ORI, data

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Asst. Prof. Alkesh M Khatri

7. SUI data

8. XRI data

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Asst. Prof. Alkesh M Khatri

MPI Sem- IV

Q.12. Draw Timing Diagram of following 3 byte Instruction.

1) JMP addr
Answer:
1) JMP addr

Q.13. Explain Absolute and Partial Decoding with example.

Answer:

Memories can be interfaced in two ways:

1. Absolute / Complete / full decoding (exhaustive decoding):
IN Absolute decoding technique, all the higher address lines are
decoded to select the memory chip, and memory chip is selected only

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

for the specified logic levels on these higher order address line; no
other logic levels can select the chip.
Figure shows the memory interface with absolute decoding. This
addressing technique is normally used in large memory systems.
Memory Map:
Memor A1 A1 A1 A1 A1 A1
Addre
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
5
4
3
2
1
0
ss
y ICs
Starti
ng
addre
0000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ss of
H
EPRO
M
End
addre
03FF
ss of
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
H
EPRO
M
Starti
ng
2000
Addre 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
H
ss of
RAM
End
addre
23FF
0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1
ss of
H
RAM

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

2. Linear / Partial decoding:

In small systems, hardware for the decoding logic can be eliminated by
using individual high- order address lines to select memory chips. This
referred to as linear decoding.
Figure shows the addressing of RAM with Linear decoding technique.
This technique is also called Partial Decoding.
It reduces cost of decoding circuit, but it has a drawback of multiple
addresses. 9shadow addresses)
Following figure shows the addressing of RAM with lines decoding
technique. A15 address line, is directly connected to the chip select
signal of EPROM and after inversion it is connected to the chip select
signal of RAM. Therefore, when the status of A15 line is 'one' RAM gets
selected.
The status of the other address lines is not considered, since those
address lines are not used for generation of chip select signals.

Memor A1 A1 A1 A1 A1 A1
Addre
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
5
4
3
2
1
0
ss
y ICs
Starti
ng
addre
0000
0 X X X X X 0 0 0 0 0 0 0 0 0 0
ss of
H
EPRO
M

Asst. Prof. Alkesh M Khatri

End
addre
ss of
EPRO
M
Starti
ng
Addre
ss of
RAM
End
addre
ss of
RAM

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03FF
H

8000
H

83FF
H

Q.14. Describe the Comparison of I.O mapped and Memory

Mapped I/O Interfacing.
Sr.
No
.
1
2
3
4

Memory mapped I/O

I/O mapped I/O

IO is treated as memory.

IO is treated IO.

16-bit device address

Data transfer between any generalpurpose register and I/O port.
The memory map (64K) is shared
between I/O device and system
memory

8-bit device address

Data is transfer only between accumulator
and I.O port.
The I/O map is independent of the
memory map; 256 input device and 256.
output device can be connected

Asst. Prof. Alkesh M Khatri

MPI Sem- IV

More hardware is required to decode

16-bit address
Arithmetic or logic operation can be
directly performed with I/O data
Memory Instructions are used.

Less hardware is required to decode 8-bit

address
Arithmetic or logical operation cannot be
directly performed with I/O data
Special Instructions are used like IN, OUT.

Memory control signals are used.

Special control signals are used.

Arithmetic and logic operations can be

performed on data.
Data transfer b/w register and IO.

Arithmetic and logic operations can not be

performed on data.
Data transfer b/w accumulator and IO.

5
6

9
10

Q.15.
Interface 16k x 8 EPROM memory to 8085. The
available memory chip is 4k x 4. The address should start
from 0000H onwards. Give the details interfacing schematic
and address range for each chip used.
Answer:
Q.16.
Show with the help of Circuit Diagram how to connect one i/p
port and one O/P Port on same address.
Q.17.
What is an O/P port? Explain the design of output port with
example.