Lecture 5: Manufacturing

Digital CMOS VLSI Design

Instructor: Prof. Saraju Mohanty
NOTE: The figures, text etc included in slides are borrowed
from various books, websites, authors pages, and other
sources for academic purpose only. The instructor does
not claim any originality.
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Lecture Outline

CMOS Fabrication: High-Level

CMOS Fabrication: Inverter Example
Packaging
Testing

Introduction

Integrated circuits: many transistors on one

chip.
Very Large Scale Integration (VLSI): very
many
Complementary Metal Oxide Semiconductor

Fast, cheap, low power transistors

How to build your own simple CMOS chip

CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
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MOSFET: 3D Perspective
Polysilicon

Aluminum

A Modern CMOS Process

gate-oxide
TiSi2

AlCu
SiO2

Tungsten
poly
p-well

n+

SiO2

n-well

p-epi

p+
p+

Dual-Well Trench-Isolated CMOS Process

Circuit Under Design and Its

Layout
VDD

VDD
M2

M4
Vout

Vin

M1

Vout2

M3

CMOS Fabrication

CMOS transistors are fabricated on silicon

wafer.
Lithography process similar to printing press
is used for the fabrication.
On each step, different materials are
deposited or etched.
Easiest to understand by viewing both top
and cross-section of wafer in a simplified
manufacturing process.

Photo-Lithographic Process
optical
mask
oxidation

photoresist
removal (ashing)

photoresist coating
stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step

spin, rinse, dry

CMOS Process at a Glance

Define active areas
Etch and fill trenches

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

Lithography: Key Idea

Source: A level set method for an

inverse problem arising in
photolithography. Doctoral
Thesis/Dissertation, 2009, 97 pages.

10

Lithography: Wafer Preparation

Source: A level set method for an inverse problem arising in photolithography. Doctoral
Thesis/Dissertation, 2009, 97 pages.

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Lithography: Light Projection

Source: A level set method for an inverse problem arising in photolithography.

Doctoral Thesis/Dissertation, 2009, 97 pages.

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Lithography: Exposing Photoresist

Source: A level set method for an inverse problem arising in photolithography.

Doctoral Thesis/Dissertation, 2009, 97 pages.

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Lithography: Etching the Exposed Area

Source: A level set method for an inverse problem arising in photolithography.

Doctoral Thesis/Dissertation, 2009, 97 pages.

14

Lithography: Implanting/Depositing

Source: A level set method for an inverse problem arising in photolithography.

Doctoral Thesis/Dissertation, 2009, 97 pages.

15

Lithography: End Metallization

Source: A level set method for an inverse problem arising in photolithography.

Doctoral Thesis/Dissertation, 2009, 97 pages.

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Inverter Cross-section
VDD

Typically

use p-type substrate for

nMOS transistors.

A
Requires

n-well for
pMOS transistors.
A

body

GND

GND
Y

of

VDD

SiO2
n+ diffusion

n+

n+

p+

p+
n well

p substrate
nMOS transistor

p+ diffusion
polysilicon
metal1

pMOS transistor

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Well and Substrate Taps

Substrate must is tied to GND and n-well to

VDD
Metal to lightly-doped semiconductor forms
poor connection called Shottky Diode
Heavily doped well
and substrate contacts or
A
V
taps GND
form good ohmic contacts.
Y
2
1
DD

p+

n+

n+

p+

p+

n+

n well
p substrate
substrate tap

well tap

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Inverter Mask Set

Transistors and wires are defined by masks

Cross-section taken along dashed line

GND

VDD
nMOS transistor
substrate tap

pMOS transistor
well tap

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Detailed Mask Views

Six masks

n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal

n well

Polysilicon

n+ Diffusion

p+ Diffusion

Contact

Metal

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Fabrication Steps: Creation of n-well

Objective is to build inverter from the bottom up

First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide)

Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2

n-well : Start with blank p-type silicon wafer

p substrate

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Fabrication Steps: Creation of n-well

n-well: Grow SiO2 on top of Si wafer

900 1200 C with H2O or O2 in oxidation furnace

The oxide is patterned to define n-well.
SiO2

p substrate

n-well: Spin on photoresist

Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2

p substrate

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Fabrication Steps: Creation of n-well

n-well: Expose photoresist through n-well

mask

Allows light to pass through only where the nwell need to be created.
Strip off exposed photoresist

Photoresist
SiO2

p substrate

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Fabrication Steps: Creation of n-well

n-well: Etch oxide with hydrofluoric acid (HF)

Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

n-well: Strip off remaining photoresist

Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
SiO2

p substrate

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Fabrication Steps: Creation of n-well

n-well: using diffusion or ion implantation

Diffusion: Place wafer in furnace with arsenic gas

and heat until As atoms diffuse into exposed Si
Ion Implantation: Blast wafer with beam of As ions
SiO2
n well

n-well: Strip off the remaining oxide using HF

Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate

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Fabrication Steps: Creation of Gates

Gate consists of polysilicon over thin layer of

silicon oxide.
Very thin layer of gate oxide is grown in furnace

< 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

for polysilicon deposition

Place wafer in furnace with Silane gas (SiH4)

Forms many small crystals called polysilicon
Polysilicon is heavily doped to be a good conductor
Polysilicon
Thin gate oxide
n well
p substrate

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Fabrication Steps: Creation of Gates

Use

same lithography process that used to

create n-well to pattern polysilicon using
photoresist and the polysilicon mask.

Polysilicon

Polysilicon
Thin gate oxide
n well
p substrate

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Fabrication Steps: Creation of n+

Transistor active area and well contact are

n+.
N-diffusion forms nMOS source, drain, and
n-well contact
Use oxide and masking to expose where n+
dopants should be diffused or implanted
SiO2
n well
p substrate

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Fabrication Steps: Creation of n+

Pattern oxide with the n-diffusion mask and form

n+ regions.
Self-aligned process where gate blocks diffusion.
Polysilicon is better than metal for self-aligned
gates because it doesnt melt during later
processing.

n+ Diffusion

SiO2
n well
p substrate

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Fabrication Steps: Creation of n+

Historically dopants were diffused

Usually ion implantation today
But regions are still called diffusion
n+

n+

n+
n well

p substrate

Strip off oxide to complete patterning step

n+

n+

n+
n well

p substrate

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Fabrication Steps: Creation of p+

Similar set of steps form p+ diffusion regions

for PMOS source and drain and substrate
contact.
Pattern oxide with the p-diffusion mask and
form p+ regions.
p+ Diffusion

p+

n+

n+

p+

p+

n+

n well
p substrate

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Fabrication Steps:
Creation of Contacts

Now we need to wire together the devices

Cover chip with thick field oxide
Etch oxide where contact cuts are needed
using contact mask.
Contact

Thick field oxide

p+

n+

n+

p+

p+

n+

n well
p substrate

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Fabrication Steps: Metalization

Sputter on aluminum over whole wafer

Pattern to remove excess metal, leaving wires
Metal mask is used during this step.

Metal

Metal
Thick field oxide
p+

n+

n+

p+

p+

n+

n well
p substrate

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Advanced Metallization

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Advanced Metallization

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Bonding Techniques
Wire Bonding

Substrate
Die
Pad

Lead Frame

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Tape-Automated Bonding (TAB)

Sprocket
hole
Film + Pattern

Solder Bump
Die

Test
pads
Lead
frame

Substrate
(b) Die attachment using solder bumps.

Polymer film
(a) Polymer Tape with imprinted
wiring pattern.

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Flip-Chip Bonding
Die
Solder bumps
Interconnect
layers

Substrate

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Package-to-Board Interconnect

(a) Through-Hole Mounting

(b) Surface Mount

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Packaging

Tapeout final layout

Fabrication

6, 8, 12 wafers
Optimized for throughput, not latency (10 weeks!)
Cut into individual dice

Packaging

Bond gold wires from die I/O pads to package

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Packaging Requirements

Electrical: Low parasitics

Mechanical: Reliable and robust
Thermal: Efficient heat removal
Economical: Cheap

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Package Types

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Package Parameters

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Multi-Chip Modules

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Testing

Test that chip operates

Design errors
Manufacturing errors

A single dust particle or wafer defect kills a

die

Yields from 90% to < 10%

Depends on die size, maturity of process
Test each part before shipping to customer

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