ICSP2012 Proceedings

Radar Signal Interception Receiver based on Digital

Channelizer
Zongbo Wang

Lianying Ji

Department of Electronic Engineering

Dalian University of Technology
Dalian, China
[email protected]

School of Information Sciences and Engineering

Graduate University of Chinese Academy of Sciences
Beijing, China
[email protected]
receiver can perform signal detection and measurement tasks in
real time with broadband coverage.

Abstract This paper addresses the concept of digital

channelizer as a promising solution to overcome the real-time
signal detection and analysis challenges for radar signal
interception. By employing digital channelizer after high-speed
ADC, the intercepted broadband signals can be divided into
numbers of sub-channel signals, the signal detection and analysis
tasks can then be performed at lower speed after decimation in
sub-channels. The sub-channel signal detection and parameter
measurement modules are developed to perform signal
processing tasks. A realization example based on multi-FPGA
chips and its test results are presented to consolidate the
proposed signal interception receiver structure.

The structure of the paper is following. Section II gives an

overview of the principle of digital channelizer and its
implementation structure. Section III presents the proposed
signal interception structure in combination with digital
channelizer and other function modules. Section IV gives the
implementation example and test result. The last part is
conclusions and future research visions.
II.

Keywords- channelized receiver; radar signal interception.

I.

INTRODUCTION

Signal interception is one of the most important subjects in

signals and electronic intelligence [1, 2]. In radar signal
interception applications, interception receiver must have
broadband coverage to provide enough spectrum surveillance
capability. High speed analog to digital converter techniques
(ADC) developed over the past several years have led to new
devices with unprecedented performance [3]. With the
availability of high sampling rate chip up to several Giga-Hertz,
intercepted signal can even be digitized at radio frequency (RF),
more conventional analogue signal processing approaches can
be replaced by its counterpart in digital domain.
However, another technical trend can be observed is the
digital signal processor clock frequency is still lagging around
Mega-Hertz, the state-of-the-art FPGA chip from Xilinx still
only supports the processing clock up to 700MHz [4]. How to
process the high speed data stream produced from front-end
ADC by relatively low speed digital signal processor becomes
a challenging task for broadband digital interception receiver.

PRINCIPLE AND STRUCTURE OF DIGITAL CHANNLIZER

A. Digital Channlizer
Digital channelizer, also called digital channelized receiver,
has been first investigated as a branch of multi-rate signal
processing and found its application in telecommunications [5,
6]. The basic principle of digital channelizer is to divide the
digitalized broadband signal into several sub-channels or
subbands by employing a filterbank.
exp( j0 n)

h0 (n)

exp( j1n)

h1 (n)
x ( n)
ADC




hD  2 (n)

To overcome the real-time processing and analysis

challenges for broadband signal interception with high speed
ADC sampling, a signal interception receiver structure based
on digital channelizer is proposed in this paper. By employing
a DFT filterbank in digital domain, the intercepted broadband
signal is divided into numbers of sub-channel signals, the
signal detection and analysis tasks can then be conducted at
lower speed after decimation. In combination with the
optimized sub-band signal detection and parameter
measurement modules, the proposed broadband intercept

y0 (m)

y0 (n)

hD 1 (n)

y1 (n)

y1 (m)
D





exp( jD  2 n)
y N  2 ( n)
exp( jD 1n)
yN 1 (n)

y D  2 ( m)
D

yD 1 (m)
D

Figure 1. Function diagram of digital channelizer

The diagram of digital channelizer is illustrated in Fig.1.

x (n ) represents the discrete output from ADC, the frequency
band of the sampled signal is channelized by
y a filterbank with
0,1,.. , D 1 . Each
filters tap indicated as hi (n ), i 0,1,...,

___________________________________
978-1-4673-2197-6/12/$31.00 2012 IEEE



follow-up functions to form a fully functional interception

receiver include signal detection and parameters measure.

bandpass filters output yi (n ) becomes narrow band signal

with central frequency of:
i

(i

2D 1 2
)
, i
D
4

1,..,
1,. D

The proposed radar signal interception receiver structure

based on digital channelizer is indicated in Fig.3. In
comparison with the conventional interception receiver, the
signal detection and measurement tasks are performed in subchannels instead of the whole covering spectrum. To simply
the description, in signal parameter measurement part, only
frequency measurement module is introduced in this paper,
other signal parameter measurement modules, such as pulse
width and modulation, can be added based on requirement.

(1)

After down-conversion processing with the complex

exponential of exp( j i n)) , maximum D times decimation can
be achieved with alias. The broadband signal has been divided
into multiple sub-channel signals after filtering and decimation.
The output of digital channelizer in Fig.1 can be expressed as:

yi (m)

x(n) * hi (n) exp(

xp(j k n)

n mD

B. Sub-channel Signal Detection

In intercept receiver, signal detection can be a statistic
hypothesis test, or as simple as a fix thresholding. In
channelized receiver, considering sensitivity and keeping low
false alarm rate, a three-step detection scheme is developed for
sub-channel signal detection:

(2)

B. DFT based polyphase implementation structure

Fig.1. indicates the direct structure for digital channelizer.
To increase the computational efficiency, its polyphase
structure using DFT filterbank has been developed to move
forward the decimation operation [7-9]. The DFT
implementation uses DFT to modulate a prototype low-pass
filter to compose a uniform filterbank covering the input
bandwidth, the block diagram of polyphase implementation
structure is illustrated in Fig.2. In comparison with the structure
in Fig.1, most of the channelizer processing has been moved
after decimation, such polyphase structure can dramatically
reduce the calculation burden and makes it suitable for
FPGA/VLSI based implementation. In the implementation
example in Section IV, polyphase structure has been adopted
for system prototyping. The structure in Fig.2 has the same
sub-channel output as expressed in (2) [9].
ADC

x ( n)

h0 (n)

h1 (n)

Z-1

Z-1

hD  2 (n)

hD 1 (n)

D /2

1
2N

N 1

[ y mini (m) ]2 .

(3)

m 0

where y min (m) is the minimum amplitude from all the sub-

DFT
y N  2 ( n)

channel outputs at time m . N is the length of the series of

y min . In comparison with fix threshold, the noise estimation
threshold described in equation (3) uses silent channels as
reference, the noise estimation can then be adaptive with
complicated and unpredictable signal environment.

y1 (m)

y1 (n)

Z-1
D

The noise level for the interception receiver depicted in

Fig.3 after digital channelizer can be estimated using samples
of silent channels from sub-channels output. Silent channel
here means channel without signal present. After sorting all
sub-channels output [y 0 (m ), y1 (m ),..., yD 1 (m ))] at each
sample time m , smallest outputs are noise samples, and their
distributions are related according to noise characteristics. The
adaptive detection threshold based on noise estimation is
defined as:

y0 (m)

y0 (n)









Step 1: noise estimation




y D  2 ( m)

A calculation module indicated as noise estimation in Fig.3)

is developed to perform calculation in equation (3), based on
the amplitude calculation for all sub-channels.

Z-1

yN 1 (n)

yD 1 (m)

Step 2: rabbit ear effect estimation

Radar signals are usually pulse modulated, the pulse
transition edges have wide spectrum energy. When pulse signal
passes digital channelizer, the wide spectrum energy may be
captured by multiple channels and form fake output responses.
Phase-coded signal can also cause the same problem by its
phase discontinuity. Fake outputs can cause false alarms and
affect detection of simultaneous signals in other channels, this
effect is called rabbit ear effect and must be eliminated in subchannel detection [9].

Figure 2. DFT based polyphase channelizer implementation

III.

SIGNAL INTERCEPTION STRUCTURE BASED ON DIGITAL

CHANNLIZER

A. Proposed Structure
Section II introduces the principle of digital channelizer and
its improved polyphase structure. In radar signal interception
applications, digital channelizer can interface with high speed
ADC chip and output rate-reduced sub-channel signals. The



Subband Signal Detection

Digital Channlizer

Noise
Estimation

Amp/Phase
Calculation

Signal Parameter
Measurement

Amp/Phase
Calculation

Sub-channel
output
thresholding

Digital
Channelizer

ADC

Signal
Detection

Instantaneous
Frequency
Measurement

Pulse Descriptor
Word Coding

Pulse Width
Mearement
Amp/Phase
Calculation
Rabbit ear
effect
Estimation

Amp/Phase
Calculation

Figure 3 Radar signal interception receiver structure based on digital channelizer

Using further IFM technique at the output of each channel can

improve the frequency measurement accuracy. The improved
frequency measurement accuracy can also help to solve crosschannel processing and other functions. Most of instantaneous
frequency measurement methods can be applied, in which the
phase difference method is most direct way. Define
r (k, m) and i(k, m) as real part and imaginary part of output of
channel k at time m, the phase of sub-channel output can be
obtained using:

An adaptive and easy-to-implement module called rabbit

ear effect estimation is used to guarantee robust signal
detection, indicated in Fig.3. The motivation is based on the
fact that rabbit ear effects in the adjacent sub-channels have
fixed response function, because this effect is caused by
feeding similar waveform discontinuity into the sub-channel
filters, the responses are the same sinc function if the input is
idea pulse and the filter has idea and narrow frequency
responses [10]. The rabbit ear effect estimation based detection
threshold can be expressed as:

T (k, m)

y(
y(k

1 m)
1,

y(k
2

1,
1 m)

(k, m)

(4)

tan

i(k, m)
r (k, m)

(5)

The instantaneous frequency can be calculated using

instantaneous phase at time m and time m 1 :

where T (k, m ) is the detection threshold for channel k at

time m ,
is the margin to compensate the approximation
error.

f (k, m )

Step 3: signal detection

After obtaining two detection thresholds generated from
noise estimation and rabbit ear effect estimation modules,
the final signal detection is processed in channel detection and
cross channel processing module, indicated in Fig.3. The
threshold comparison is based on the threshold with bigger
amplitude from these two thresholds. The detection module
performs a compensation approach utilizing detection results of
successive multiple samples to achieve better detection results.

(k, m

1)
(k, m )
2 DTS

(6)

where D is decimation factor, and TS is sampling interval of

ADC. Compensating the sub-channel central frequency in
equation (1), the exact frequency of input signal can be
obtained.
D. PDW coding
Final part of the interception receiver is the pulse
descriptor word (PDW) coding to package all detection and
measurement result as the system output.

C. Instantaneous frequency measurement

For detected signal after signal detection, signal parameter
measuremnts can be conducted using signals from one subchannel or multiple sub-channels. Typical singal paramenter
measurements include freqeuncy and pulse width measuremnt.
Following part will focus the instantaneous freqeuncy
measurement (IFM) module with extra consideration of
digital channelizer.

Accuracy improvement using multiple measurement

samples can be also be applied for the receiver proposed here,
however, two factors make the temporal parameter
measurement of channelized receiver different from other
receivers. One is the time resolution reduction caused by
decimation at output of each channel, another is the transient
response which smooth the edge of the pulse. Interpolation
could be adopted to compensate resolution reduction.
Theoretically, the filtered channelized output before decimation
output can be retrieved perfectly using PR filterbank design. In
practice, the retrieved signal is enough for temporal parameter

For channelized receiver, even without any further

processing, we can only use the channel number to determine
the frequency of input signal. The frequency measurement
accuracy is then equal to the bandwidth of each sub-channel.



600MHz. The whole processing is performed in real-time with

processing pipeline delay as less as 2.8 s .

measurement when the interpolation factor is equal to the

decimation factor even with non-PR filterbank.
IV.

V.

SYSTEM IMPLEMENATION AND TESTS

Using the receiver structure shown in Figure.3, the proofof-concept prototyping design is implemented using multi
FPGA chips, the design uses following parameters:
z

Sampling: sampling rate is 1.2Giga samples per

second (SPS) with ADC resolution of 10 bits; input IF
is on second Nyquist region, 600-1200MHz.

Channelizer: Filterbank is 64-channel real-signal DFT

filterbank decimated by 64. The prototype filter is 512
taps, half-overlap design, with 55dB stopband
attenuation. The passband is 9.375MHz, the stopband
is 18.750MHz.

Detection: Noise estimation is based on equation (3)

using two groups of sub-channels, namely the odd and
even numbered sub-channels N equals 1024. Rabbit
ear effect is based on equation (4).

IFM: the phase computation is done using 10 taps

Coordinate Rotation Digital Computer (CORDIC)
algorithm. One step phase difference is used for
instantaneous frequency computation.

PDW coding: 8 PDW coding engine, with real-time

consideration, i.e., the necessary information is
obtained at the leading edge of the pulse.

A receiver structure based on digital channelizer is

proposed for broadband radar signal interception and detection.
In the case of high ADC sampling rate, the processing tasks for
signal detection and parameter measurement are conducted in
sub-channels after digital channelizer, real-time processing can
then be achieved.
In the lab test part of the prototyping design, sinusoidal
signals were used to demonstrate the detection capability and
measurement accuracy. For capturing modulated signals like
LFM and PCM signals, the signal passing channelizer may
cause simultaneous multi-channel outputs, the synthesis
filterbank can be implemented to synthesis the signals from
multi-subchannels. This will be the topic for future work.
Digital channelizer with its polyphase implementation
structure opens the path for broadband real-time signal
processing: the high bandwidth signal can be separated in
spectrum and processed in sub-band. The application of digital
channelizer can even be extended in radar signal processing
like pulse compression and matched filter.
ACKNOWLEDGEMENT
The authors would like to thanks Prof.Meiguo Gao in
Radar Research Lab, Beijing Institute of Technology, Beijing,
China for providing the hardware platform and all colleagues
in RRL for their technical contributions.

The design has been implemented using two customized

high speed digital processing boards. The first board has twochannel high speed ADCs with TS83102GB0 chips from
ATMEL(TM), the second board has multi-FPGA chips array
for signal processing with Virtex-4 SX55 from Xilinx. Two
boards are connected using Low Voltage Differential Signaling
(LVDS) user- defined IO on J4 and J5 connectors of compact
peripheral component interconnect (cPCI) bus. The structure in
Fig.3 is mapped into two FPGAs: the 64-channel digital
channelizer using structure in Fig.2 is implemented in the first
chip and the rest function modules are implemented in another
chip. The processed results after PDW are transferred to host
PC via cPCI bus.

REFERENCES
[1]

W. A. Gardner and C. M. Spooner, "Signal interception: performance

advantages of cyclic-feature detectors," IEEE Transactions on
Communications, vol. 40, pp. 149-159, 1992.
[2] R. G. Wiley, "Electronic intelligence: the interception of radar signals,"
Dedham, MA, Artech House, Inc., 1985, 294 p., vol. 1, 1985.
[3] A. H. Nejadmalayeri, et al., "A 16-fs aperture-jitter photonic ADC: 7.0
ENOB at 40 GHz," Conference on Lasers and Electro-Optics (CLEO),
2011, pp. 1-2.
[4] Xilinx., "7 Series FPGAs Overview," DS108, 2012.
[5] N. Won, "A channelized digital ultrawideband receiver,", IEEE
Transactions on Wireless Communications, vol. 2, pp. 502-510, 2003.
[6] N. Won and F. Lei, "Digital Processing of Single-Carrier Cyclic
Prefixed Frequency Channelized Receiver for Serial Links," IEEE
Transactions on Circuits and Systems II, vol. 57, pp. 353-358, 2010.
[7] Z.Wang, et al., "Design and application of DRFM system based on
digital channelized receiver," 2008 International Conference on Radar,
Adelaide, SA 2008, pp. 375-378.
[8] F. J. Harris, et al., "Digital receivers and transmitters using polyphase
filter banks for wireless communications", IEEE Transactions on
Microwave Theory and Techniques, vol. 51, pp. 1395-1412, 2003.
[9] D. R. Zahirniak, et al., "A hardware-efficient, multirate, digital
channelized receiver architecture," IEEE Transactions on Aerospace and
Electronic Systems, vol. 34, pp. 137-152, 1998.
[10] L. Ji and M. Gao, "Noise variance estimation based on order statistics in
channelized receiver," in 2009 IET International Radar Conference,
Guilin, China, 2009, pp. 1-4.

TABLE I. RECEIVER PERFORMANCE

Function and Index

Test Result

0 dB SNR frequency accuracy

1MHz

Detection sensitivity

-45dBm(input power)

Single-tone dynamic

40dB

Simultaneous signal number

Double-tone dynamic

30dB

Time of Arrival (RMS)

20 ns

Pulse width accuracy(RMS)

82 ns

Processing delay

2.8 us

CONCLUSIONS

Table I shows the testing result in lab environment. The

detection sensitivity is -45dBm covering the bandwidth of