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Junctionless FET

Junctionless FET

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335 views3 pages

Junctionless FET

Junctionless FET

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msiregar_38
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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584

IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 5, MAY 2013

Junctionless Tunnel Field Effect Transistor


Bahniman Ghosh and Mohammad Waseem Akram
Abstract In this letter, a double-gate junctionless tunnel field
effect transistor (JL-TFET) is proposed and investigated. The
JL-TFET is a Si-channel heavily n-type-doped junctionless field
effect transistor (JLFET), which uses two isolated gates (ControlGate, P-Gate) with two different metal work-functions to behave
like a tunnel field effect transistor (TFET). In this structure, the
advantages of JLFET and TFET are combined together. The
simulation results of JL-TFET with high-k dielectric material
(TiO2) of 20-nm gate length shows excellent characteristics with
high ION /IOFF ratio ( 6 108 ), a point subthreshold slope (SS)
of 38 mV/decade, and an average SS of 70 mV/decade at
room temperature, which indicates that JL-TFET is a promising
candidate for a switching performance.
Index Terms High-k dielectric material, junctionless field
effect transistor (JLFET), subthreshold slope (SS), tunnel field
effect transistor (TFET).

I. I NTRODUCTION

HE conventional metal oxide semiconductor field effect


transistor (MOSFET) is based on the presence of two
pn junctions at the interface of source-to-channel and drainto-channel regions. As the devices are scaled down further, the
requirement of large doping-concentration gradient and careful
fabrication of these junctions becomes too stringent to achieve
a low-thermal budget. Realizing this kind of metallurgical
junction, beyond 32-nm nodes for a MOSFET, has become
extremely challenging due to the requirement of an ultrasharp
doping profile [1]. Because of such stringent demands, the
scaling of MOSFET will soon reach its fundamental limits.
Based on Lilienfelds first transistor architecture [2], very
recently, a transistor has been proposed and successfully fabricated and named junctionless field effect transistor (JLFET)
[3], [4], and it does not have any metallurgical junction. Unlike
a MOSFET, for a JLFET channel, the doping concentration
and type are equal to those in the source and drain. Since this
device has no concentration gradient in the lateral direction of
the conduction layer, it does not have any pn junction. Also,
as this device does not require any metallurgical junction, it
should be simpler to fabricate, have better electrical properties,
and less variability than MOSFET [3][5]. Although the
JLFET shows better electrical properties and less variability
than MOSFET, its subthreshold slope (SS) is still limited as
in a MOSFET [4]. Because of a low power demand, over the
last few decades, alternative transistors have been proposed to

Manuscript received February 4, 2013; revised March 9, 2013; accepted


March 16, 2013. Date of current version April 22, 2013. The review of this
letter was arranged by Editor X. Zhou.
B. Ghosh is with the Microelectronics Research Center, University of Texas
at Austin, Austin, TX 78758 USA.
M. W. Akram is with the Department of Electrical Engineering,
Indian Institute of Technology Kanpur, Kanpur 208016, India (e-mail:
[email protected]).
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2013.2253752

Fig. 1. Schematical representation of the JL-TFET, the length and thickness


are as mentioned in the 2-D structure. The width of device equals to 1 m.
Work function (CG) = 4.3 eV, Work function (PG) = 5.93 eV.

achieve lower SS (< 60 mV/decade at room temperature). The


most commonly reported alternative transistors are tunnel field
effect transistor (TFET) [6][7] and impact ionization metal
oxide semiconductor (IMOS) transistors [8][9]. In this letter,
we proposed and examined a new TFET structure (namely JLTFET), which gives the advantages of both JLFET and TFET
combined together.
II. D EVICE S TRUCTURE AND O PERATION
Fig. 1 shows the proposed double-gate junctionless tunnel
field effect transistor (JL-TFET) structure along with the
lengths and thicknesses of different layers used in simulation.
The simulated JL-TFET is a Si-channel heavily n-type-doped
(1 1019 cm3 ) JLFET with a 20-nm channel length,
source/drain extension length of 20 nm, silicon film thickness
of 5 nm, 2-nm gate oxide thickness, and 5 nm of isolation
in between Control-Gate (CG) and P-Gate (PG), which works
as an isolation between the gates and also as a spacer. The
double-gate technology is used to provide better controllability
over the channel. All simulations are carried out using a
2-D device simulator, Silvaco Atlas, of version 5.15.32.R.
We use a nonlocal band-to-band tunneling (BTBT) model
available in Silvaco Atlas [10], and this model has been
used in the literature to predict the performance of TFET
[7]. The nonlocal BTBT model is used in the simulation
to take into account a tunneling along the lateral direction.
Band-gap narrowing (BGN) model is also enabled due to
high doping concentration in the channel. The gate leakage
current model is not included, with the assumption of high-k
metal gate stack. ShockleyReadHall (SRH) recombination
model is also included because of a presence of high impurity
atom in the channel and also consideration of an interface
trap (or defect) effect [10]. The quantum confinement effect
and interface trap effect on BTBT in TFETs are also enabled,
by inclusion of quantum confinement (QC) model given by
Hansch [10], [11], and trap-assisted tunneling (TAT) model
given by Schenk [10], [12].

0741-3106/$31.00 2013 IEEE

20

OFF State Concentration Profile

1.0

Electron
Hole

18
16

10

Valence Band Energy (eV)


Conduction Band Energy (eV)

0.5

14
12

OFF State Energy Band Diagram

0.0

Drain

Channel

Source

-0.5

Drain

Channel

-3

22

Source

8
-1.0

6
4

-1.5

2
0

-2.0

-2
0.01

0.02

0.03

0.04

0.05

0.06

Distance along x-direction (m)

(a)

0.07

0.01

0.02

0.03

0.04

0.05

0.06

585

Concentration (cm ) in Log10 Scale

-3

Concentration (cm ) in Log10 Scale

GHOSH AND AKRAM: JUNCTIONLESS TUNNEL FIELD EFFECT TRANSISTOR

0.07

Distance along x-direction (m)

(b)

22
20

ON State Concentration Profile

1.0

ON State Energy Band Diagram


Valence Band Energy (eV)
Conduction Band Energy (eV)

18
0.5

Electron
Hole

16
14

0.0

12
10
8

Drain

Channel

-0.5

Source

-1.0

6
4

-1.5

2
0

Drain

Channel

Source

-2.0

-2
0.01

0.02

0.03

0.04

0.05

0.06

Distance along x-direction (m)

(a)

0.07

0.01

0.02

0.03

0.04

0.05

0.06

0.07

Distance along x-direction (m)

(b)

Fig. 2.
(a) OFF-state electron and hole concentration of JL-TFET.
(b) Energy band diagram of JL-TFET in the OFF state. OFF state (VDS = 1 V,
VCGS = 0 V).

Fig. 3. (a) ON-state electron and hole concentration of JL-TFET. (b) Energy
band diagram of JL-TFET in the ON state. ON state (VDS = 1 V, VCGS = 1 V).

The simulated device structure is a lateral n-type JLFET,


which uses the two isolated gates (Control-Gate, P-Gate) of
two different metal work-functions, to make the layer beneath
the gates intrinsic and p-type.
To make the layers beneath Control-Gate and P-Gate intrinsic and p-type, respectively, we have varied the metal workfunction from 4.3 to 5.1 eV and 5.5 to 5.93 eV, respectively.
The highest value of work function, i.e., 5.93 eV, corresponds
to the metal platinum (Pt) [13]. In the proposed device structure, the work functions of 4.3 and 5.93 eV for Control-Gate
and P-Gate give the best result in terms of SS and ION /IOFF values. However, JL-TFET with different silicon channel length,
thickness, doping concentration, and source/drain extension
length would have different combination of work function
for Control-Gate and P-Gate to get the optimized results of
the required performance parameters. The basic idea applied
here is to convert the (N+ N+ N+ ) drain, channel and source
of JLFET into a (N+ -I-P+ ) structure without any physical
doping.

of the source to the conduction band of the channel. Hence,


significant amount of current flows because of the quantumtunneling mechanism. Like in a TFET, we apply gate voltage
only on the Control-Gate (the gate above the intrinsic region
of the device) to turn on the device. The voltage of ControlGate (CG) is varied from 0 to 1 V for turning the device ON.
Either in an OFF state or ON state, P-Gate terminal is kept at
zero bias.
It has been shown that the use of high-k dielectric gate
material for TFETs improves the ON current and also SS
[7]. Although the use of high-k dielectrics gives advantages
in device characteristics, however, when high-k dielectric
material is directly put in contact with silicon channel, it can
lead to defects at the dielectric/semiconductor interface. The
effect of interface defects is also taken into consideration for
the simulation of TFETs. Here in the proposed structure, we
have considered different dielectric materials (such as TiO2 (r
= 80), La2O3 (r = 30), HfO2 (r = 25), Al2O3 (r = 9),
Si3N4 (r = 7), SiO2 (r =3.9)), and the dielectric constants
of different materials are taken from [14]. The subthreshold
characteristic of the proposed device with high-k dielectric
materials is shown in Fig. 4(a); here the QC model is not
included. It is clear from figure that the material with higher
dielectric constant gives a higher ON current and also improved
SS. The improved ION and SS are observed, because of a
higher gate coupling offered by high-k dielectric gate material
of higher dielectric constant value ranging from 3.9 to 80,
keeping the physical thickness of gate oxide fixed and equal
to 2 nm. The point SS is measured as the inverse of maximum
slope of the log of the drain current versus gate voltage [3],
[7], [10]. The average SS is measured as used in [7]. The
ON current (I ON ) and OFF current (I OFF ) are measured at the
supply voltages of (V D S = 1V, VC G S = 1 V) and (V D S = 1V,
VC G S = 0V), respectively. The highest ON current of 36
A/m is achieved for a high-k dielectric material of TiO2.
Very low OFF current (<51014 A/ m) is also observed
for all considered high-k dielectric materials. Fig. 4(b) shows
the SS and ION /IOFF ratio for the different high-k dielectric
materials.
Point SS of 38 mV/decade, average SS of 70 mV/decade
and ION /IOFF ratio of 6 108 is observed for a dielectric
material of TiO2. The high-k dielectric materials, with lower
dielectric constant values (such as La2O3, HfO2) than that
of TiO2, also show improved point SS of 43 mV/decade,

III. R ESULTS AND D ISCUSSIONS


Fig. 2(a) shows the electron and hole concentration profile in
the OFF state, from the concentration profile it is observed that
the device looks like an N+ -I-P+ -doped device structure. The
OFF -state energy-band diagram is shown in Fig. 2(b); in this
case, the probability of the tunneling of electrons is negligible,
since the tunneling barrier in between the source and channel
is very large, so the OFF-state current flows only because of an
N+ -I-P+ diode leakage. The device is turned on, by applying
a gate voltage on the Control-Gate, which narrows the barrier
between the source and channel of the device. The ON-state
electron and hole concentration profile is shown in Fig. 3(a).
From the figure, we observe that on applying a gate voltage
on the Control-Gate, the electron concentration of the device
layer beneath this gate increases and becomes almost an ntype region. This results in narrowing of the barrier between
the source and channel of the device.
For a TFET, it is found that the ON current (ION ) increases
exponentially with decrease in the tunneling barrier width [7].
Fig. 3(b) shows the ON-state energy band diagram, in which
we observe that the tunneling barrier between source and
channel of the device has lowered significantly, so there is a
high probability of tunneling of electrons from a valence band

586

IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 5, MAY 2013

figure, we observe that the QC effect does not become very


prominent in the measurement of I D versus. VG S curve. The
inclusion of TAT model increases the IOFF as compared to
the case without the use of TAT model. Further improvement
of different performance parameters could be obtained using
IIIV compound semiconductor channel material, gate work
function engineering, etc.
IV. C ONCLUSION
(a)

(b)

Fig. 4. (a) Subthreshold characteristics of JL-TFET for different dielectric


constant values from 3.9 to 80 at VDS = 1 V. (b) Subthreshold Slope
and ION /IOFF ratio of JL-TFET for different dielectric constant values
from 3.9 to 80.

In this letter, we proposed and discussed the basic static


operation of JL-TFET in which there is no pn junction and
which gives the combined advantages of conventional TFET
and JLFET. The high-k dielectric gate material for JL-TFETs
is used to improve the ON current and SS. The proposed device
structure exhibits excellent ON OFF characteristics based on
our simulations. It seems to be a very promising device for
sub-22-nm nodes.
R EFERENCES

(a)

(b)

Fig. 5. (a) I D versus VGS curve of JL-TFET using TiO2 as gate dielectric
for different isolation thicknesses (in between the Control-Gate and P-Gate) at
VDS = 1 V. (b) I D versus VGS curve of JL-TFET and CM-TFET using TiO2
as gate dielectric with or without inclusion of different model at VDS = 1 V.

average SS of 87 mV/decade and ION /IOFF ratio of


3.5 108 (for La2O3), point SS of 45 mV/decade,
average SS of 91 mV/decade, and ION /IOFF ratio of
3.0 108 (for HfO2) respectively. The values of performance parameters (ION , IOFF , SS and ION /IOFF ) obtained for
the proposed device structure are similar to those observed
in TFETs [15] of the same channel length. Fig. 5(a) shows
the impact of the thickness of isolation layer on the I D VG S
characteristics. It is observed that the reduction in isolation
thickness layer improves the ION and SS; however, it would
also increase the intergate capacitance, which in turn increases
the power dissipation. Improved ION is observed because of
narrowing of the barrier between the source and channel of the
device. Fig. 5(b) shows the I D versus VG S curve for JL-TFET
and conventional TFET (CM-TFET) with the same device
parameters with or without inclusion of different model. It
is observed that the performance parameter of the JL-TFET
almost matches that of CM-TFET. The advantages of JL-TFET
is that it would be simpler to fabricate and would be less
prone to variability and short channel effect (SCE) than the
CM-TFET, since this device does not require any metallurgical
junction. The disadvantage of JL-TFET is that it would require
an extra layer of gate deposition for the P-Gate layer and also
an extra isolation layer between the Control-Gate and P-Gate.
Moreover, its parasitic capacitances also increase. From the

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