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EEE312 EEE282 Lab4 Spring2015 PDF

This experiment analyzes and compares resistor loaded NMOS and BJT inverter circuits. It involves calculating DC operating points and voltage transfer characteristics, simulating timing performance and power dissipation in LTSpice, and measuring circuits constructed with CA3046 and CD4007 ICs. Key results include higher noise margins and slower switching for the BJT circuit compared to NMOS. Power dissipation is also higher for BJTs due to their lower current drive capability. Replacing the base resistors with a lower value improves the NMOS circuit performance.

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130 views

EEE312 EEE282 Lab4 Spring2015 PDF

This experiment analyzes and compares resistor loaded NMOS and BJT inverter circuits. It involves calculating DC operating points and voltage transfer characteristics, simulating timing performance and power dissipation in LTSpice, and measuring circuits constructed with CA3046 and CD4007 ICs. Key results include higher noise margins and slower switching for the BJT circuit compared to NMOS. Power dissipation is also higher for BJTs due to their lower current drive capability. Replacing the base resistors with a lower value improves the NMOS circuit performance.

Uploaded by

vognar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment 4.

NMOS and BJT Inverting Circuits


I. INTRODUCTION
1. Objectives
In this experiment, the characteristics of the resistor loaded NMOS and BJT (RTL) inverter
circuits will be analyzed and compared.
II. PRELIMINARY WORK
1. Read Chapter 1 and sections 4.1 and 4.2 of Digital Integrated Circuits by T.A. Demassa
and Z. Ciccone, and Chapter 6 of Microelectronic Circuit Design by R. Jaeger and T.
Blalock.
2. Consider the following Resistor Loaded BJT and NMOS circuits. The circuits consist of two
back to back inverters, which together make up a buffer.
VDD = 5 V

VCC = 5 V
R1

R1

R2

VOUT1

VOUT1
VIN

RB1
10 k

VOUT2

RB2
Q1

R2

10 k

Q2

20 pF

M1

M2

VIN

(a)

VOUT2
20 pF

(b)

Figure 4.1. Resistor loaded (a) BJT, (b) NMOS.


You may use the following parameters for CD4007 NMOS transistor in your calculations
if needed:
Vt = 1.2 V ; k*W/L = 0.7 mA/V2 ; = 0.004 V-1 ; = 1.9V0.5
CA3046 BJT parameters were provided in the previous labs.
a) Calculate the critical VIN, VOUT1, VOUT2 DC points for both circuits with i. R1=R2=1
k and ii. R1=R2=10 k, and sketch the VTC curves of VOUT1 vs VIN and VOUT2 vs
VIN on the same plot. Label all critical points in your plots. Provide high and low
noise margins for VOUT2 in each case.

Explain the difference between BJT and NMOS results in a few sentences.

Also comment on the differences between VOUT1 and VOUT2 results for both BJT
and NMOS circuit.
b) Calculate the total average power dissipation of both circuits with i. R1=R2=1
k, and ii. R1=R2=10 k. Assume VIN is a square wave switching at 100 kHz.
Ignore the loading due to the transistor parasitic capacitances.

Explain the difference between BJT and NMOS results in a few sentences.

c) Simulate the DC performance of both circuits with LTSPICE using CA3046 BJT
and CD4007 MOSFET models (see APPENDIX), and obtain VTC curves for VOUT1
vs VIN and VOUT2 vs VIN with i. R1=R2=1 k and ii. R1=R2=10 k. When
simulating the NMOS transistor, you can use the nmos model in the LTSPICE

METU-NCC

EEE 312/EEE 282 Digital Electronics Laboratory


library and add the properties of CD4007, as you have done before for the
BJTs.

Comment on the differences between VOUT1 and VOUT2 timing performance for
both BJT and NMOS circuit.
d) Simulate the total power dissipation of both circuits in LTSPICE with i. R1=R2=1
k and ii. R1=R2=10 k given the input is a 100 kHz square wave.
e) Simulate the AC performance of both circuits in LTSPICE using 100 kHz input
square waveform, and use the results to measure tf, tr, tPHL, tPLH for both VOUT1
and VOUT2 at i. R1=R2=1 k and ii. R1=R2=10 k. Answer the following
questions qualitatively (not quantitatively) by providing an explanation:

1. Do you observe any problems? Explain the meaning of your results.


2. Do you think that the rise time of the circuit depends on the magnitude of

the supply voltage, VDD?


3. Does the rise time depend on the values of the drain resistor and the
capacitance at the output?
4. Does the rise time increase or decrease, if a resistor is connected in parallel
to the capacitance at the output?
5. What are the parameters likely to determine the fall time?
f)

Can you estimate the capacitive loading on VOUT1 compared to the final load
of 20 pF for the NMOS?

g) Comment on your overall results from (a) to (d). What do you think would be

the difference in applications of the Resistor Loaded BJT vs. NMOS circuits?

h) Fill in Table 4.1 below with the results from (a) to (d). Explain differences
between your hand analysis in (a), and simulations in (b). If a parameter
cannot be measured, enter N/A. Submit your LTSPICE schematics and
clearly labeled simulation waveforms. Measurement rows in the table will be
filled in the laboratory.
i)

Finally replace the 10 k at the base of the BJTs in Fig. 4.1(a) with 100 . How
do your simulation results in part (e) change? Can you explain?

III. EXPERIMENT
i) Use the pin diagrams in Figure 4.2 to construct your circuits in Figure 4.1 with CA3046
and CD4007 IC components.

(a)

(b)

Figure 4.2. IC pin diagram for a) CA3046 BJT array, (b) CD4007 MOSFET array chips.
Experiment 4

METU-NCC

EEE 312/EEE 282 Digital Electronics Laboratory


Table 4.1. Calculated, Simulated, and Measured Results for BJT and NMOS
circuits

Parameter
VIL
(V)
VIH
(V)
VOUT1 VOL
(V)
VOUT1 VOH
(V)
VOUT2 VOL
(V)
VOUT2 VOH
(V)
Power Diss.
(mW)
VOUT1 tr
(ns)
VOUT1 tf
(ns)
VOUT1 tPHL
(ns)
VOUT1 tPLH
(ns)
VOUT2 tr
(ns)
VOUT2 tf
(ns)
VOUT2 tPHL
(ns)
VOUT2 tPLH
(ns)

ii)

Method

Resistor
Resistor Loaded
Loaded BJT
NMOS
R1=R2 R1=R2 R1=R2 R1=R2=
= 1 k =10 k = 1 k 10 k

Hand Calculation
LTSPICE Simulation
Measurement (in lab)
Hand Calculation
LTSPICE Simulation
Measurement (in lab)
Hand Calculation
LTSPICE Simulation
Measurement (in lab)
Hand Calculation
LTSPICE Simulation
Measurement (in lab)
Hand Calculation
LTSPICE Simulation
Measurement (in lab)
Hand Calculation
LTSPICE Simulation
Measurement (in lab)
Hand Calculation
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)
LTSPICE Simulation
Measurement (in lab)

Configure HP VEE and measure the voltage transfer characteristics of both resistor
loaded BJT and NMOS circuits with two different resistor values. Complete the related
measurement sections of Table 4.1.

Experiment 4

METU-NCC

EEE 312/EEE 282 Digital Electronics Laboratory

iii) Use the function generator to generate a 100 kHz square wave as the input waveform
to the circuits. Measure the power dissipation for both circuits. Also measure the
timing parameters using the oscilloscope. Fill in the rest of Table 4.1.
iv) Demonstrate your result to the lab instructor for each of the circuits after you are
done.
v)

(BONUS) Set-up the following circuit, and similarly obtain the VTC and timing
waveforms as above.

Demonstrate your results, and explain the following in qualitative terms to


your TA based on your measurements:
1. What is the advantage of the NMOS pull-up compared to the resistor. Which region
of operation is this pull-up NMOS in?
2. Why is the NMOS pull-down duplicated in the circuit, what advantage does this
provide?

IC LIST FOR EXPERIMENT 4

Experiment 4

CD4007

MOSFET Array

CA3046

BJT Array

1k, 10k

Resistors

20 pF

Capacitors

METU-NCC

EEE 312/EEE 282 Digital Electronics Laboratory

APPENDIX: LTSPICE device models


.model CA3046 NPN (IS=10.0E-15 XTI=3.000E+00 EG=1.110E+00 VAF=1.00E+02
+ VAR=1.000E+02 BF=145.7E+00 ISE=114.286E-15 NE=1.480E+00
+ IKF=46.700E-03 XTB=0.000E+00 BR=.1000E+00 ISC=10.005E-15
+ NC=2.000E+00 IKR=10.00E-03 RC=10.000E+00 CJC=991.71E-15
+ MJC=0.333E-00 VJC=0.7500E-00 FC=5.000E-01 CJE=1.02E-12
+ MJE=.336E-00 VJE=0.750E-00 TR=10.000E-09 TF=277.01E-12
+ ITF=1.750E-00 XTF=309.38E+00 VTF=16.37E+00 PTF=0.000E+00
+ RE=0.0E+00 RB=0.00E+00)
.model CD4007nMOS NMOS (LEVEL=1 VTo=1.2 Kp=.9m LAMBDA=0.004)

Experiment 4

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