Manufacturing Challenges and

their Implications on Design

Phi
Phiroze
P
Parakh,
kh Ph
Ph.D
D

45nm/32nm Design Challenges

MANUFACTURING
VARIATIONS

PROCESS & DESIGN VARIATIONS

LOW POWER
LARGE DESIGNS

P
PRE-TAPE
EOUT

The Evolution of Signoff

130nm

90nm

DRC

DRC
C
Critical
Feature
Analysis

65nm
DRC
C
Critical
Feature
Analysis
Critical Area
Analysis
Lith f i dl
Litho-friendly
Design

45nm
DRC
C
Critical
Feature
Analysis
Critical Area
Analysis
Lith f i dl
Litho-friendly
Design
Litho-aware Silicon
Modeling

32nm

Variability vs. Yield, Cause vs. Effect

Variability: spread in process/layout parameters and is

inherently caused by the litho-process

Yield: measure of success-rate in fabrication process

Yield-failure:
Yi
ld f il
li iti
limiting
case off variability.
i bilit
The effect of a high- event!

P&R, RET and Fabrication

P&R

timing

place

opt

route

clock

GDS2
RET: Backend

Litho model
Parametric Variations
Defect densities
FAB: Tapeout
Design rules

OPC

CAA

LFD

Mask Layers
yield

wafer

models

logic

Corners
Gate delays
RC/m
Design rules

How does robust optimization address variability?

low Vth

fast RC

Typical optimization
centered around nominal
process

Fab & Test Universe

high Vth
slow RC

Robust optimization
p
seeks to cover larger
g process
p
conditions

Taxonomy

Variability

Systematic
y

Parametric (process)
Spatial
p
((wafer/die))
Proximity (local position)

Dynamic

Temperature/Voltage
N.B.T.I
Electro-migration

Random

Particle Defects
I
Implant
l t
L.E.R

What can be addressed by P&R?

Example Systematic Parametric Variation: PV-Bands

The bands
represent a
range of
simulations
across Dose,
Dose
Defocus, and
Mask-Bias

M3
V23

M2

Drawn != Actual

Calibre
Olympus
LFD

Understanding Lithography is the first step

Mask

Wafer

NA: sin()

Resist

Critical_dimension = 1 * / Numerical_Aperture

How is sub- possible?

= 193nm; sin() 1 CD 193nm

CD = k1 * /NA
1.35

1.35

NA can be > 1 if we use immersion lithography

water
1 31
t = 1.31
1.2

0.92

0.85

NA
Take advantage of the mask-spectrum
Partially coherent imaging
1
0.62Off-axis illumination
Annular light sources
0.48

0.44

0.35

0.24

Improve the mask via OPC

90nm

65nm

45nm

32nm

22nm

Optics: Initial Source of Variability

Mask

Resist

Wafer

1.1 E0

0.9 E0

Exposure Latitude

Mask Bias

(CDimage) limits (E0)

Focus
(DOF) limited by (CDimage)

(CDimage) limits (CDmask)

The variance of CDimage, Exposure, Masks and Focus are coupled

Parametric Variability in Lithography

space

Fat M1

Variability is a measure of the change in the image

over changes in Dose, Focus and Mask-Bias

Variability through Timing Corners

Inverter driving 25m of M2

250

200

Delay (ps
s)

150ps
150

Weak: High-Vt
100

Weak: Low-Vt

50

20ps

Strong: High-Vt
Strong: Low-Vt

0
C1

C2

C3

C4

C5

C6

C7

C8

C9 C10 C11 C12 C13 C14 C15 C16 C17

Corners

1 2 0C
1.2v,
0C, b
bestt RC

0 9 125C
0.9v,
125C, worstt RC

Each corner is a full chip timing tighten the range

Robust P&R for DFM

place

Timing aware

opt

route

clock

logic

Multi-corner analysis

Metal Fill
Fast DRC
Wire Spreading
p
g
Double Via Ins.

Litho Errors
Advanced Rules
CAA / Yield
CMP Maps

Mentor Olympus DB

Litho aware

Litho analysis

CAA

LFD

OPC

CMP

Variability

Systematic
y

Parametric (process)
Spatial
p
((wafer/die))
Proximity (local position)

Dynamic

Temperature/Voltage
N.B.T.I
Electro-migration

Random

Particle Defects
I
Implant
l t
L.E.R

Systematic vs. Parametric

80nm

65nm

Actual Shape Can be Simulated

85nm?
120nm?

Systematic Drawn - Actual

Parametric (Actual)

69nm?
60nm?
64nm?

Can we account for Drawn Shapes in Routing?

Metal Pinching (Min-Width)

M2 bridge with
litho error
Pinched (but still ok)
PV-band violation
OPC: nominal case
Rather than make
OPC solve for all
Process windows,
we could make the
M2 jog wider

Density based width variation

40nm

20nm variation!
60nm

Modeled in
RC extraction

Double vias can be a double edged sword

80nm

39nm

43nm

Increased contact reliability Decreased metal reliability

Locality != adjacency

Space allows
the other side
to compensate
Symmetry
suggests this
should be an
error

M3
min-width
i
idth
violation

Robust repair of Litho-Errors

Aggressor
Zones
Expand
to fix error

Victim

Rotate (if possible)

Use a fine grid to resolve violation

Systematic vs. Parametric

80nm

65nm

Actual Shape Can be Simulated

85nm?
120nm?

Systematic Drawn - Actual

Parametric (Actual)

69nm?
60nm?
64nm?

Can we account for Drawn Shapes in Timing?

OCV Margins Fudge-factor

OCV Margin factor of ~20%

This factor masks
Location based variation
L/Weff variation
IR-drop etc..

Robust OCV model each factor

Systematic Density-based Variation for a Timer

65nm

High density

Opticall diameter

45nm
32nm

High cell density increased (Leff)

Proximity(Density) Based OCV

Low density

Parasitic Variation and Chemical Mechanical Polishing

Wire thickness (Clateral) is a function of layer, density and width
The dielectric between layers will also vary (Csubstrate)

Per layer
y CMP variation M3 could be worse than M2!
Metal fill makes density consistent
Calibre CMP

Taxonomy

Variability

Systematic
y

Parametric (process)
Spatial
p
((wafer/die))
Proximity (local position)

Dynamic

Temperature/Voltage
N.B.T.I
Electro-migration

Random

Particle Defects
I
Implant
l t (Vth)
L.E.R

Dynamic Variation
Time/state dependent
Eg: Negative Bias Temp Instability (NBTI)
max Vth
When will we reach max Vth?

125
log(Vthh)

25
log(t)

Lifetime

A comprehensive model of PMOS NBTI degradation, M. Alam.

A K map + ttargett conditions

diti
are needed
d d
Also supports delay dependence on IR-drop

Taxonomy

Variability

Systematic
y

Parametric (process)
Spatial
p
((wafer/die))
Proximity (local position)

Dynamic

Temperature/Voltage
N.B.T.I
Electro-migration

Random

Particle Defects
I
Implant
l t (Vth)
L.E.R

Random variation along timing-path

(Vth) = K WL

Due to variation in number and distribution of dopant

p
atoms in the channel
l i
logic_path_depth:
th d th 5

0.78v

0.58v
clock_path_depth: 2

Different distribution!
Same number of atoms

(logic): (Vth)*5
(clock): (Vth)*2

Randomeven
dopant induced
voltage
lowering and fluctuations,
Asenov.
On clock trees,
a threshold
small
difference
in Asen
path-depth
matters.

Random Fault: Critical Area Analysis

C.A =

P(r) A(r) dr
0

CAA: How is A(r) to be determined?

Shorts:
PV-Bands 3 possible A(r)
Opens:
PV-Bands 3 possible A(r)

Conservative: Inner band for opens and Outer band for shorts

Improving CAA score

C.A =

P(r) A(r) dr

Tough to spread!

Improve A(r) by wire-spreading or wire-sizing

Easier

Random Fault: Pattern collapse

M1 mask
y
x

Etch

y
x

High aspect ratio, without side support!

Pattern collapse

Capillary effect

s
w

Youngs Modulus
used to determine
snapping point

Potential For Collapse?

Has Support
pp

Too short

Long
Unsupported
Imbalanced

Well balanced

Wire-spreading prevent collapse

Conclusion

Variability

Systematic
y

Parametric (process)
Spatial
p
((wafer/die))
Proximity (local position)

Dynamic

Temperature/Voltage
N.B.T.I
Electro-migration

Random

Particle Defects
I
Implant
l t
L.E.R

Proper models are key to addressing variability

Acknowledgements

Andres Torres
Alex Volkov
Shankar Krishnamoorthy

Resolution lower-bound

2
Pitch: 1
< /NA
1 /NA

The lens is a low pass filter!

It will suppress frequencies below CD-11

Image
Image

Interference

Incident plane wave

n*

(n+)*

Diffraction

Incident plane wave

Constructive: n*
Destructive: (n+)*

Sub- stressed by need for increased control

7.1
6

3 (nm
m)

4.8

47
4.7

43
4.3
4

3.8

3.8
3

34
3.4

1.9

Vias

1.3

Uniform wires

2.1
2.1
1.7

2006

Non-uniform wires

24
2.4
2.6

2005

3.4

2007

2008

2009

2010

Variance is larger due to non-uniformity

Contacts vs. Metal

Is this Double Via

needed?
Shift the wire &
rotate the via?

M3 pinch

CAA on 45nm design

Metal 2
Metal 3
Metal 4
Stripes due to power lines

O.C.V: Systematic variation for a Timer

outside
Spherical aberration Focus

inside

Resist Coating, CMP Planarity Etch Thickness

outside > inside

Chips inside have less variation they sort into faster bins!
L
Location
ti
Based
B
d OCV

CAA: How is P(r) determined?

Inline Particle Detectors shine a laser

on the wafer and detect scattered light
Scattering intensity is proportional to
particle size