LAB ASSIGNMENT 3:EE

705- VLSI DESIGN LAB

Describing a Finite State Machine(FSM)

INDRANIL CHAKRABORTY

ROLL-143070072

ELECTRICAL ENGINEERING
MICROELECTRONICS

DATE 06th February , 2015

IIT BOMBAY

Describing an FSM

Characteristics:
Input symbol set: {p,q}
Output symbol set: {M, N}
The machine outputs M if the input sequence seen thus far (including the
current input) is of the form ppp..pqqq..q, where the number of input ps
and number of qs are both even numbers.

Description:
The FSM should detect the sequence ppp..pqqq..q, where the number of input ps
and number of qs are both even numbers. The minimum detectable sequence is ppqq.
So, we need the following states: (starting state), p,pp,ppq,ppqq. We also need a state
where the FSM will end up in case of invalid sequences. We call that state dead.
Whenever there is a break in the build up to the required sequence, we send the FSM to
the dead state. The dead state can only be recovered using a reset signal.
The states and transitions:
a) State This is the starting state. On receiving input p, it moves to state p but on
receiving input q, it moves to state dead as its an invalid input stream.
b) State p- On receiving input p, it moves to state pp but on receiving input q, it
moves to state dead, as pq is an invalid stream.
c) State pp- On receiving input pp, it moves to state p but on receiving input q, it
moves to state ppq.
d) State ppq - On receiving input ppq, it moves to state p but on receiving input
dead, as it becomes an invalid stream, but on receiving q, it moves to state ppqq,
e) State ppqq - On receiving input p, it moves to state dead but on receiving input
q, it moves to state ppq.
f) State dead This is the state where the system ends up when an invalid input stream
occurs. On receiving input p or q, it remains in the dead state. Only a reset input
can move the system away from this state to state .
The outputs:
a) M When a valid input stream occurs ppppqqqq., output M occurs. Only a
transition from ppq to ppqq, will produce this output M. This will signify a
successful detection.
b) N In case of any other input stream, unsuccessful detection is signified by output
N.

State Diagram:
p/N
p/N

p/N

p
q/N

reset/N

q/N

pp

p/N

ppq

q/N

q/M

q/N
dead
reset/N

ppqq
p/N
p,q/N

State Transition Table:

Current State

X=p
p
pp
p
dead
dead
dead

Next State
X= q
dead
dead
ppq
ppqq
ppq
dead

X= Reset

X=p
N
N
N
N
N
N

Output
X= q
N
N
N
M
N
N

X= Reset

N
p
N
pp
N
ppq
N
Ppqq
N
dead
N
VHDL organization of DUT:
i)
Package Definition: We define a package in order to introduce new data types - i)
fsm_state ii)input_symbol, iii) output_symbol and the fsm component.
-----------------------------------------------------------package FsmPackage is --Package definition
type fsm_state is (s_phi, s_p, s_pp, s_ppq, s_ppqq,s_dead); -States defined
type input_symbol is (reset, p,q); --Inputs defined
type output_symbol is (M,N); --Outputs defined
component exp_fsm is --Component defined specifying input and
output ports and clock
port (X: in input_symbol;
Y: out output_symbol;
clk: in bit);
end component;
end FsmPackage;
-------------------------------------------------------------

ii)

Architecture and Process: We define a signal state, of type fsm_state which would
denote the current state. Signals denoting next state(nstate), present state(pstate) and
variable denoting the output(vY) is defined.
------------------------------------------------------------architecture fsm_behave of exp_fsm is
signal pstate: fsm_state; --Signal to store Present State
signal nstate: fsm_state; --Signal to store Next State
begin
FSM: process(X,pstate)
variable vY: output_symbol; --Variable to store output-------------------------------------------------------------

The start of the FSM process is stated by assigning current state to next state and N to Y.
------------------------------------------------------------nstate <= pstate;
vY := N;

-------------------------------------------------------------

Now using case command, we have realized the state transition table. For example, if the
current state is (s_phi), then on receiving input p, it moves to state p(s_p), or on
receiving input q, it moves to state dead (s_dead), else it stays in state . In case of
same state transition, there is no need to assign new state.
------------------------------------------------------------case pstate is
when s_phi =>
if(X = p) then
nstate <= s_p;
elsif(X =q) then
nstate <= s_dead;
else
nstate <= s_phi;
end if;

-------------------------------------------------------------

In this way, all the cases of the state transition table has been specified.
And when there is a correct sequence detected, output variable vY is assigned M.
At the end of case sequence, we apply vY to the output signal
------------------------------------------------------------if(X = reset) then
Y <= N;
else
Y <= vY;
end if;
end process FSM;

-------------------------------------------------------------

State transitions happen on the event of a clock, specifically a rising edge. So, we define
a process which causes the state transitions when rising edge of clock arrives.

------------------------------------------------------------STATE_TRAN: process
begin
wait until clk'event and clk = '1';

report ht & input_symbol'image(X) & ht & ht &

fsm_state'image(pstate) & ht & ht & fsm_state'image(nstate) & ht & ht &
output_symbol'image(Y); --reporting format
pstate <= nstate;

end process STATE_TRAN;

-------------------------------------------------------------

VHDL organization of Testbench

We need to write a testbench using a sequence such that
i)
Every state is visited at least once.
ii)
Every transition is taken at least once.
Let us traverse the state diagram. The transitions are numbered for reference.

Let the reset transitions from each state be named as reset , reset p, reset pp and so on.
Number

Symbol

Current State

Next state

Transition
completed

0
1
2
3
4
5

reset
p
p
p
q
reset

p
pp
p
dead

p
pp
p
dead

Reset (0)
1
2
3
6
8

Expected
output
stream
N
N
N
N
N
N

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

p
p
q
p
reset
p
p
q
q
q
q
p
p
q
reset
q
reset
p
reset
p
p
reset
p
p
q
reset
p
p
q
q
reset

p
pp
ppq
dead

p
pp
ppq
ppqq
ppq
ppqq
dead
dead
dead

dead

p
pp

p
pp
ppq

p
pp
ppq
ppqq

p
pp
ppq
dead

p
pp
ppq
ppqq
ppq
ppqq
dead
dead
dead

dead

p
pp

p
pp
ppq

p
pp
ppq
ppqq

1
2
4
5
8
1
2
4
10
11
10
9
12
13
8
7
8
1
Reset p
1
2
Reset pp
1
2
4
Reset ppq
1
2
4
10
Reset ppqq

N
N
N
N
N
N
N
N
M
N
M
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
M
N

So, that stream reset, pppq,reset,ppqq,reset,ppqqqqppq,reset,p,reset,pp,reset,ppq,reset,ppqq,reset covers

all possible transitions and states.
The expected output stream is NNNNNNNNNNNNNNMNMNNNNNNNNNNNNNNNNNNMN
To be noted that, this is not an exhaustive test and might not be able to show all the problems in the FSM.
For an exhaustive test, it is advised to test each combination of input string of length N(N=number of
states). However for more than 2 input symbols, this may become a lengthy procedure.
The testbench includes the library we have defined and the architecture behave is defined over the entity
Testbench. We use an array of Input_symbol and an array of Output_Symbol to incorporate the input
string and match the output.
----------------------------------------------------------------type InputVector is array (natural range <>) of input_symbol;
type OutputVector is array (natural range <>) of output_symbol;

constant input_trace: InputVector(0 to 36) := (0 => reset, 1 => p, 2 => p,

3 => p, 4 => q, 5 => reset, 6 => p, 7 => p, 8 => q, 9=> p, 10=> reset, 11=>
p, 12=> p, 13=> q, 14=> q, 15=> q, 16=> q, 17=> p, 18=>p, 19=> q, 20=> reset,
21=>q , 22=> reset,23=> p, 24=> reset, 25=> p, 26=> p, 27=> reset, 28=> p,
29=> p, 30=>q,31=> reset, 32=> p, 33=> p, 34=> q, 35=>q,36=> reset ); --Input
sequence
constant output_trace: OutputVector(0 to 36) := (0 => N, 1 => N, 2 => N,
3 => N, 4 => N, 5 => N, 6 => N, 7 => N, 8 => N, 9=> N, 10=> N, 11=> N, 12=>
N, 13=> N, 14=> M, 15=> N, 16=> M, 17=> N, 18=> N, 19=> N, 20=> N, 21=> N,
22=> N,23=> N, 24=> N, 25=> N, 26=> N, 27=> N, 28=> N, 29=> N, 30=>N,31=> N,
32=> N, 33=> N, 34=> N, 35=>M,36=> N ); --Corresponding expected output
Sequence
----------------------------------------------------------------

We define the clock of period 10 ns, with 50% duty cycle using the following process:
--------------------------------------------------------------SIM: process --Process to generate clock
begin
if end_of_sim = false then --Apply Clock
clk<='0';
wait for 5 ns;
clk<='1';
wait for 5 ns;
else
wait;
end if;
end process SIM;
-------------------------------------------------------------

The end_of_sim is a shared variable defined to stop the vhdl program when the test input stream ends. It
is assigned a default value false so that the clock generation starts. However in the next process, it is set
to true when the input stream ends.
And for the 16 input symbols, we match the expected output with the output produced by our FSM at
each rising edge of the clock.

--------------------------------------------------------------ESIM: process --Process to apply input

begin
report "Input" & ht & " Current State" & ht & "
Next State"
& ht & "
Output"; --Reporting format
for I in 0 to 36 loop
X <= input_trace(I); --X is loaded with the input sequence
wait for 1 ns; --wait for output to be produced by FSM
assert (Y = output_trace(I)) report --Match produced output
with expected output
"output-mismatch"
severity error;

wait until clk = '1'; --Wait for rising edge of clock

end loop;
wait for 5 ns;
assert false report "test successful" severity note;
end_of_sim := true;
wait;
end process ESIM;
---------------------------------------------------------------

Points to Note:
We have applied the input synchronously with the clock. However, a special characteristic of
Mealy machine is that the output changes asynchronously whenever input changes. We have not
shown that characteristic in this experiment.

Reporting of output:
We report all the transitions that takes place during the processing of the input stream using the
following piece of code:
-------------------------------------------------------------------------------

report ht & input_symbol'image(X) & ht & ht & fsm_state'image(pstate) &

ht & ht & fsm_state'image(nstate) & ht & ht & output_symbol'image(Y);
-------------------------------------------------------------------------------

Here, pstate stores the present state, nstate stores the next state, X and Y are the input and output
symbols.

Sample output:

WAVE:

ZOOMED TO SHOW DIFFERENT STATES:

ZOOM1(0-90ns):

ZOOM2(90ns-180ns)

ZOOM3(180ns-270ns)

ZOOM4(270ns-360ns)