5.

1 Data-Transfer Instructions

8088/8086 MICROPROCESSOR
PROGRAMMING INTEGER
INSTRUCTIONS AND
COMPUTATIONS

The MOVE Instruction

The move (MOV) instruction is used to transfer a byte or a word
of data from a source operand to a destination operand.
Mnemonic

Meaning

Format

Operation

Flags affected

MOV

Move

MOV D, S

(S) (D)

None

e.g.

MOV DX, CS
MOV [SUM], AX

611 37100 Lecture 05-4

8088/8086 MICROPROCESSOR
PROGRAMMING INTEGER
INSTRUCTIONS AND COMPUTATIONS

The MOVE Instruction

Note that the MOV instruction cannot transfer data directly
between external memory.

5.1 Data-Transfer Instructions

5.2 Arithmetic Instructions
5.3 Logic Instructions
5.4 Shift Instructions
5.5 Rotate Instructions

611 37100 Lecture 05-2

5.1 Data-Transfer Instructions

Destination

5.1 Data-Transfer Instructions

Source

Memory

Accumulator

Accumulator

Memory

Register

Register

Register

Memory

Memory

Register

Register

Immediate

Memory

Immediate

Seg-reg

Reg16

Seg-reg

Mem16

Reg16

Seg-reg

Memory

Seg-reg

Allowed operands for MOV instruction

611 37100 Lecture 05-5

5.1 Data-Transfer Instructions

The MOVE Instruction

The data-transfer functions provide the ability to

move data either between its internal registers or

between an internal register and a storage location in
memory.
The data-transfer functions include
MOV (Move byte or word)
XCHG (Exchange byte or word)
XLAT (Translate byte)
LEA (Load effective address)
LDS (Load data segment)
LES (Load extra segment)
611 37100 Lecture 05-3

MOV DX, CS
0100
0100
0200

XXXX

IP
CS
DS
SS
ES
AX
BX
CX
DX

Address Memory
Content
01100
01101
01102

8C
CA
XX

02000
02001

XX
XX

Instruction

MOV DX, CS
Next instruction

SP
BP
SI
DI

8088/8086 MPU
Before execution
611 37100 Lecture 05-6

5.1 Data-Transfer Instructions

5.1 Data-Transfer Instructions

The MOVE Instruction

The XCHG Instruction

MOV DX, CS
0102
0100
0200

0100

IP
CS
DS
SS
ES
AX
BX
CX
DX

Address Memory
Content
01100
01101
01102

02000
02001

8C
CA
XX

Instruction

MOV DX, CS

The exchange (XCHG) instruction can be used to swap data

between two general-purpose registers or between a generalpurpose register and a storage location in memory.

Next instruction

XX
XX

Mnemonic

Meaning

Format

Operation

Flags affected

XCHG

Exchange

XCHG D, S

(D) (S)

None

e.g.

XCHG AX, DX
Destination

SP
BP
SI
DI

8088/8086 MPU
After execution
611 37100 Lecture 05-7

Source

Accumulator

Reg16

Memory

Register

Register

Register

Register

Memory

Allowed operands for XCHG instruction

611 37100 Lecture 05-10

5.1 Data-Transfer Instructions

5.1 Data-Transfer Instructions

EXAMPLE

EXAMPLE

What is the effect of executing the instruction

MOV CX, [SOURCE_MEM]
Where SOURCE_MEM equal to 2016 is a memory location offset
relative to the current data segment starting at 1A00016.

What is the result of executing the following instruction?

XCHG [SUM], BX
Where SUM = 123416, (DS)=120016

Solution:
((DS)0+2016) (CL)
((DS)0+2016+116) (CH)
Therefore CL is loaded with the contents held at memory address
1A00016 + 2016 = 1A02016
and CH is loaded with the contents of memory address
1A00016 + 2016 +116 = 1A02116

611 37100 Lecture 05-8

5.1 Data-Transfer Instructions

Solution:
((DS)0+SUM) (BX)
PA = 1200016 + 123416=1323416
Execution of the instruction performs the following 16-bit swap:
(1323416) (BL)
(1323516) (BH)
So we get (BX) = 00FF16
(SUM) = 11AA16

5.1 Data-Transfer Instructions

The XCHG Instruction

EXAMPLE

XCHG [SUM], BX

Use the DEBUG the verify the previous example.

Solution:

0101
1100
1200

11

AA

IP
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI

8088/8086 MPU

611 37100 Lecture 05-9

611 37100 Lecture 05-11

Before execution
611 37100 Lecture 05-12

Address Memory
Content
11101
11102
11103
11104
11105

87
1E
34
12
XX

12000
12001
.
.
.
.
13234
13235

XX
XX

FF
00

Instruction

XCHG [SUM],BX

Next instruction

Variable SUM

5.1 Data-Transfer Instructions

5.1 Data-Transfer Instructions

The XCHG Instruction

The XLAT Instruction

XCHG [SUM], BX
0105
1100
1200

00

FF

IP
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI

8088/8086 MPU
After execution
611 37100 Lecture 05-13

Address Memory
Content
11101
11102
11103
11104
11105

12000
12001
.
.
.
.
13234
13235

87
1E
34
12
XX

Instruction

XCHG [SUM],BX

Next instruction

Mnemonic

Meaning

Format

Operation

Flags affected

XLAT

Translate

XLAT

((AL)+(BX)+(DS)0) (AL)

None

e.g.

XX
XX

AA
11

The translate (XLAT) instruction is used to simplify

implementation of the lookup-table operation. Execution of the
XLAT replaces the contents of AL by the contents of the
accessed lookup-table location.

PA = (DS)0 + (BX) + (AL)

= 0300016 + 010016 + 0D16 = 0310D16
(0310D16) (AL)

Variable SUM

611 37100 Lecture 05-16

5.1 Data-Transfer Instructions

5.1 Data-Transfer Instructions

EXAMPLE

The LEA, LDS, and LES Instructions

Use the DEBUG program to verify the previous example.

Solution:

The LEA, LDS, LES instructions provide the ability to manipulate

memory addresses by loading either a 16-bit offset address into
a general-purpose register or a register together with a segment
address into either DS or ES.
Mnemonic

Meaning

LEA

Load effective address

LEA Reg16, EA

EA (Reg16)

None

LDS

Load register and DS

LDS Reg16, Mem32

(Mem32) (Reg16)
(Mem32+2) (DS)

None

LES

Load register and ES

LES Reg16,Mem32

(Mem32) (Reg16)
(Mem32+2) (ES)

None

e.g.

611 37100 Lecture 05-14

5.1 Data-Transfer Instructions

Format

Operation

Flags affected

LEA SI, [DI+BX+5H]

611 37100 Lecture 05-17

5.1 Data-Transfer Instructions

The LEA, LDS, and LES Instructions

EXAMPLE

LDS SI, [200H]

Use the DEBUG program to verify the previous example.

Solution:

0100
1100
1200

IP
CS
DS
SS
ES
AX
BX
CX
DX

XXXX

SP
BP
SI
DI

Address Memory
Content
11100
11101
11102
11103
11104

C5
36
00
02
XX

12000
12001
.
.
12200
12201
12202
12203

XX
XX

Instruction

LDS SI, [200H]

Next instruction

20
00
00
13

8088/8086 MPU

611 37100 Lecture 05-15

Before execution
611 37100 Lecture 05-18

5.1 Data-Transfer Instructions

5.2 Arithmetic Instructions

The LEA, LDS, and LES Instructions

The arithmetic instructions include

LDS SI, [200H]

0104

IP

1100
1300

CS
DS
SS
ES
AX
BX
CX
DX

0020

SP
BP
SI
DI

8088/8086 MPU

Address Memory
Content
11100
11101
11102
11103
11104

C5
36
00
02
XX

12000
12001
.
.
12200
12201
12202
12203
.
.
13000
13001

XX
XX

Instruction

LDS SI, [200H]

Next instruction

20
00
00
13

XX
XX

After execution
611 37100 Lecture 05-19

New data
segment

5.1 Data-Transfer Instructions

Addition
Subtraction
Multiplication
Division

Data formats
Unsigned binary bytes
Signed binary bytes
Unsigned binary words
Signed binary words
Unpacked decimal bytes
Packed decimal bytes
ASCII numbers

611 37100 Lecture 05-22

5.2 Arithmetic Instructions

ADDITION

EXAMPLE
Verify the following instruction using DEBUG program.
LDS SI, [200H]

ADD

Add byte or word

ADC

Add byte or word with carry

INC

Increment byte or word by 1

AAA

ASCII adjust for addition

DAA

Decimal adjust for addition

SUB

Subtract byte or word

SBB

Subtract byte or word with borrow

SUBTRACTION

DEC

Decrement byte or word by 1

NEG

Negate byte or word

AAS

ASCII adjust for subtraction

DAS

Decimal adjust for subtraction

MUL

Multiply byte or word unsigned

IMUL

Integer multiply byte or word

AAM

ASCII adjust for multiply

DIV

Divide byte or word unsigned

IDIV

Integer divide byte or word

MULTIPLICATION

DIVISION

611 37100 Lecture 05-20

5.1 Data-Transfer Instructions

AAD

ASCII adjust for division

CBW

Convert byte to word

CWD

Convert word to doubleword

611 37100 Lecture 05-23

5.2 Arithmetic Instructions

Addition Instructions: ADD, ADC, INC, AAA, DAA

EXAMPLE
Initializing the internal registers of the 8088 from a table in
memory.

Solution:
MOV AX, [INIT_TABLE]
MOV SS, AX
LDS SI, [INIT_TABLE+02H]
LES DI, [INIT_TABLE+06H]
MOV AX, [INIT_TABLE+0AH]
MOV BX, [INIT_TABLE+0CH]
MOV CX, [INIT_TABLE+0EH]
MOV DX, [INIT_TABLE+10H]

611 37100 Lecture 05-21

Mnemonic

Meaning

Format

Operation

Flags affected

ADD

Addition

ADD D, S

(S) +(D)(D)
Carry (CF)

OF, SF, ZF, AF, PF, CF

ADC

Add with carry

ADC D, S

(S) +(D)+(CF)(D)
Carry (CF)

OF, SF, ZF, AF, PF, CF

INC

Increment by 1

INC D

(D) +1(D)

OF, SF, ZF, AF, PF

AAA

ASCII adjust
for addition

AAA

AF, CF
OF, SF, ZF, PF undefined

DAA

Decimal adjust
for addition

DAA

SF, ZF, AF, PF, CF,

OF undefined

611 37100 Lecture 05-24

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

Addition Instructions: ADD, ADC, INC, AAA, DAA

Addition Instructions: ADD, ADC, INC, AAA, DAA

ADD AX, BX

Destination

Source

0102

Register

Register

Register

Memory

Memory

Register

Register

Immediate

Reg16

Memory

Immediate

Reg8

1100
1200

CS
DS
SS
ES

1BBC
0ABC

AX
BX
CX
DX

Destination

Memory

Accumulator Immediate
Allowed operands for ADD and
ADC instructions

IP

Address Memory
Content
11100
11101
11102

03
C3
XX

12000
12001

XX
XX

Instruction

ADD AX, BX
Next instruction

SP
BP
SI
DI

Allowed operands
for INC instruction

8088/8086 MPU

611 37100 Lecture 05-25

After execution
611 37100 Lecture 05-28

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

EXAMPLE

EXAMPLE

Assume that the AX and BX registers contain 110016 and

0ABC16, respectively. What is the result of executing the instruction
ADD AX, BX?

Solution:

Verify the previous example using DEBUG program.

Solution:
(BX)+(AX)= 0ABC16 + 110016=1BBC16
The sum ends up in destination register AX. That is
(AX) = 1BBC16

611 37100 Lecture 05-26

5.2 Arithmetic Instructions

ADD AX, BX
IP

1100
1200

CS
DS
SS
ES

1100
0ABC

AX
BX
CX
DX

Address Memory
Content
11100
11101
11102

03
C3
XX

12000
12001

XX
XX

5.2 Arithmetic Instructions

Addition Instructions: ADD, ADC, INC, AAA, DAA

0100

611 37100 Lecture 05-29

Instruction

ADD AX, BX
Next instruction

EXAMPLE
The original contents of AX, BL, word-size memory location
SUM, and carry flag (CF) are 123416, AB16, 00CD16, and 016,
respectively. Describe the results of executing the following
sequence of instruction?
ADD AX, [SUM]
ADC BL, 05H
INC WORD PTR [SUM]

Solution:
(AX)(AX)+(SUM) = 123416 + 00CD16 =130116

SP
BP
SI
DI

(BL)(BL)+imm8+(CF) = AB16 + 516+016 = B016

(SUM)(SUM)+ 116 = 00CD16 + 116 = 00CE16

8088/8086 MPU
Before execution
611 37100 Lecture 05-27

611 37100 Lecture 05-30

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

EXAMPLE

Subtraction Instructions:
SUB, SBB, DEC, AAS, DAS, and NEG

What is the result of executing the following instruction

sequence?
ADD AL, BL
AAA
Assuming that AL contains 3216 (ASCII code for 2) and BL contains
3416 (ASCII code 4), and that AH has been cleared.

Solution:
(AL)(AL)+(BL)= 3216 + 3416=6616
The result after the AAA instruction is
(AL) = 0616
(AH) = 0016
with both AF and CF remain cleared

Source
Register

Register

Memory

Memory

Register

Register

Immediate

Reg16

Memory

Immediate

Reg8

Accumulator Immediate
Allowed operands for SUB and SBB
instructions

611 37100 Lecture 05-31

Destination
Register

Destination

Memory
Allowed operands
for DEC instruction

611 37100 Lecture 05-34

Destination
Register
Memory
Allowed operands
for NEG instruction

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

EXAMPLE

EXAMPLE

Perform a 32-bit binary add operation on the contents of the

processors register.

Assuming that the contents of register BX and CX are 123416

and 012316, respectively, and the carry flag is 0, what is the result
of executing the instruction SBB BX, CX?

Solution:
(DX,CX) (DX,CX)+(BX,AX)
(DX,CX) = FEDCBA9816
(BX,AX) = 0123456716
MOV DX, 0FEDCH
MOV CX, 0BA98H
MOV BX, 01234H
MOV AX, 04567H
ADD CX, AX
ADC DX, BX

Solution:
(BX)-(CX)-(CF) (BX)
We get
(BX) = 123416 012316 016
= 111116
the carry flag remains cleared.

; Add with carry

611 37100 Lecture 05-32

611 37100 Lecture 05-35

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

Subtraction Instructions:
SUB, SBB, DEC, AAS, DAS, and NEG

EXAMPLE

Mnemonic

Meaning

Format

Operation

Verify the previous example using DEBUG program.

Flags affected

SUB

Subtract

SUB D, S

(D)-(S)(D)
Borrow (CF)

OF, SF, ZF, AF, PF, CF

SBB

Subtract with
borrow

SBB D, S

(D)-(S)-(CF)(D)

OF, SF, ZF, AF, PF, CF

DEC

Decrement by
1

DEC D

(D)-1(D)

OF, SF, ZF, AF, PF

NEG

Negate

NEG D

0-(D) (D)
1 (CF)

OF, SF, ZF, AF, PF,CF

DAS

Decimal adjust
for subtraction

DAS

SF, ZF, AF, PF, CF,

OF undefined

AAS

ASCII adjust
for subtraction

AAS

AF,CF
OF,SF, ZF,PF undefined

611 37100 Lecture 05-33

Solution:

611 37100 Lecture 05-36

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

Multiplication Instructions:

MUL, DIV, IMUL, IDIV, AAM, AAD, CBW, and CWD

EXAMPLE
Assuming that the register BX contains 003A16, what is the
result of executing the following instruction?
NEG BX

Mnemonic

Meaning

Format
MUL S

(AL)(S8)(AX)
(AX)(S16)(DX)(AX)

OF, CF
SF,ZF, AF, PF undefined

DIV

Division
(unsigned)

DIV S

(1)Q((AX)/(S8))(AL)
R((AX)/(S8))(AH)
(2)Q((DX,AX)/(S16))(AX)
R((DX,AX)/(S16))(DX)
If Q is FF16 in case (1) or
FFFF16 in case (2), then type 0

OF, SF, ZF, AF, PF, CF

undefined

Integer multiply
(signed)

IMUL S

(AL)(S8)(AX)
(AX)(S16)(DX)(AX)

OF, CF
SF,ZF, AF, PF undefined

IDIV S

(1)Q((AX)/(S8))(AL)
R((AX)/(S8))(AH)
(2)Q((DX,AX)/(S16))(AX)
R((DX,AX)/(S16))(DX)
If Q is positive and exceeds
7FFF16 or if Q is negative and
become less than 800116, then
type 0 interrupt occurs

OF, SF, ZF, AF, PF, CF

undefined

interrupt occurs

IMUL
IDIV

Integer divide
(signed)

Since no carry is generated in this add operation, the carry flag is

complemented to give
(CF) = 1

611 37100 Lecture 05-37

611 37100 Lecture 05-40

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

EXAMPLE

Multiplication Instructions:

Verify the previous example using DEBUG program.

MUL, DIV, IMUL, IDIV, AAM, AAD, CBW, and CWD

Mnemonic

Solution:

Flags affected

Multiply
(unsigned)

Solution:
(BX) = 000016-(BX)=000016+2complement of 003A16
= 000016+FFC616
= FFC616

Operation

MUL

Meaning

Format

Operation

Flags affected

AAM

Adjust AL for
multiplication

AAM

Q((AL)/10)(AH)
R((AL)/10)(AL)

SF,ZF,PF
OF,AF,CF undefined

AAD

Adjust AX for
division

AAD

(AH)10+(AL)(AL)
00(AH)

SF,ZF,PF
OF,AF,CF undefined

CBW

Convert byte to
word

CBW

(MSB of AL)(All bits of AH) None

CWD

Convert word
to double word

CWD

(MSB of AX)(All bits of DX)

None

Destination
Reg8
Reg16
Mem8
Mem16

611 37100 Lecture 05-38

Allowed operands

611 37100 Lecture 05-41

5.2 Arithmetic Instructions

5.2 Arithmetic Instructions

EXAMPLE

EXAMPLE

Perform a 32-bit binary subtraction for variable X and Y.

Solution:
MOV SI, 200H
MOV DI, 100H
MOV AX, [SI]
SUB AX, [DI]
MOV [SI],AX
MOV AX, [SI]+2
SBB AX, [DI]+2
MOV [SI]+2, AX

; Initialize pointer for X

; Initialize pointer for Y
; Subtract LS words
; Save the LS word of result
; Subtract MS words
; Save the MS word of result

611 37100 Lecture 05-39

The 2s-complement signed data contents of AL are 1 and that

of CL are 2. What result is produced in AX by executing the
following instruction?
MUL CL
and
IMUL CL

Solution:
(AL) = -1 (as 2s complement) = 111111112 = FF16
(CL) = -2 (as 2s complement) = 111111102 = FE16
Executing the MUL instruction gives
(AX) = 111111112x111111102=11111101000000102=FD0216
Executing the IMUL instruction gives
(AX) = -116 x -216 = 216 = 000216

611 37100 Lecture 05-42

5.2 Arithmetic Instructions

5.3 Logic Instructions

Logic instructions : AND, OR, XOR, NOT

EXAMPLE
Verify the previous example using DEBUG program.

Destination

Solution:

Source

Register

Register

Register

Memory

Memory

Register

Register

Immediate

Memory

Immediate

Register

Accumulator Immediate

Memory

Allowed operands for AND, OR, and

XOR instructions

611 37100 Lecture 05-43

611 37100 Lecture 05-46

5.2 Arithmetic Instructions

5.3 Logic Instructions

EXAMPLE

EXAMPLE

What is the result of executing the following instructions?

MOV AL, 0A1H
CBW
CWD

Allowed operands
for NOT instruction

Describe the results of executing the following instructions?

MOV
AND
OR
XOR
NOT

AL, 01010101B
AL, 00011111B
AL, 11000000B
AL, 00001111B
AL

Solution:

Solution:
(AL) = A116 = 101000012
Executing the CBW instruction extends the MSB of AL
(AH) = 111111112 = FF16 or (AX) = 11111111101000012
Executing the CWD instruction, we get
(DX) = 11111111111111112 = FFFF16
That is,
(AX) = FFA116 (DX) = FFFF16

611 37100 Lecture 05-44

(AL)=010101012 000111112= 000101012=1516

Executing the OR instruction, we get
(AL)= 000101012 +110000002= 110101012=D516
Executing the XOR instruction, we get
(AL)= 110101012 000011112= 110110102=DA16
Executing the NOT instruction, we get
(AL)= (NOT)110110102 = 001001012=2516

611 37100 Lecture 05-47

5.3 Logic Instructions

5.3 Logic Instructions

The logic instructions include

EXAMPLE

AND
OR
XOR (Exclusive-OR)
NOT
Mnemonic

Destination

Meaning

Masking and setting bits in a register.

Solution:
Mask off the upper 12 bits of the word of data in AX
AND AX, 000F16

Format

Operation

Flags affected

AND

Logical AND

AND D, S

(S) (D)(D)

OF, SF, ZF, PF, CF

AF undefined

OR

Logical
Inclusive-OR

OR D, S

(S) (D)(D)

OF, SF, ZF, PF, CF

AF undefined

XOR

Logical
exclusive-OR

XOR D, S

(S)(D)(D)

OF, SF, ZF, PF, CF

AF undefined

NOT

Logical NOT

NOT D

(NOT D)(D)

None

611 37100 Lecture 05-45

Setting B4 of the byte at the offset address CONTROL_FLAGS

MOV AL, [CONTROL_FLAGS]
OR AL, 10H
MOV [CONTROL_FLAGS], AL
Executing the above instructions, we get
(AL)=XXXXXXXX2 +000100002= XXX1XXXX2

611 37100 Lecture 05-48

5.4 Shift Instructions

5.4 Shift Instructions

Shift instructions: SHL, SHR, SAL, SAR

Mnemonic

Meaning

Format

Operation

Flags
affected

SAL/SHL

Shift
arithmetic left /
Shift logical
left

SAL D, Count
SHL D, Count

Shift the (D) left by the

number of bit positions
equal to Count and fill the
vacated bits positions on
the right with zeros

CF, PF, SF, Z

AF undefined
OF undefined
if count 1

SHR

Shift logical
right

SHR D, Count

Shift the (D) right by the

number of bit positions
equal to Count and fill the
vacated bits positions on
the left with zeros

CF, PF, SF, Z

AF undefined
OF undefined
if count 1

SAR

Shift
arithmetic
right

SAR D, Count

Shift the (D) right by the

number of bit positions
equal to Count and fill the
vacated bits positions on
the left with the original
most significant bits

CF, PF, SF, Z

AF undefined
OF undefined
if count 1

611 37100 Lecture 05-49

5.4 Shift Instructions

EXAMPLE
Assume that CL contains 0216 and AX contains 091A16.
Determine the new contents of AX and the carry flag after the
instruction SAR AX, CL is executed.

Solution:
(AX)=00000010010001102=024616
and the carry flag is (CF)=12

611 37100 Lecture 05-52

5.4 Shift Instructions

Shift instructions: SHL, SHR, SAL, SAR

EXAMPLE
Verify the previous example using DEBUG program.

Destination

Solution:

Count

Register

Register

CL

Memory

Memory

CL

Allowed operands for shift instructions

611 37100 Lecture 05-50

5.4 Shift Instructions

611 37100 Lecture 05-53

5.4 Shift Instructions

Shift instructions: SHL, SHR, SAL, SAR

SHL AX, 1

EXAMPLE
Isolate the bit B3 of the byte at the offset address
CONTROL_FLAGS.

Solution:

SHR AX, CL

SAR AX, CL

611 37100 Lecture 05-51

MOV AL, [CONTROL_FLAGS]

MOV CL, 04H
SHR AL, CL
Executing the instructions, we get
(AL)=0000B7B6B5B4
and
(CF)=B3

611 37100 Lecture 05-54

5.5 Rotate Instructions

5.5 Rotate Instructions

Rotate instructions: ROL, ROR, RCL, RCR

Mnemonic
ROL

Meaning
Rotate left

Format

Operation

Flags
affected

ROL D, Count

Rotate the (D) left by the number

of bit positions equal to Count.
Each bit shifted out from the
leftmost bit goes back into the
rightmost bit position.

CF
OF undefined
if count 1

ROR

Rotate right

ROR D, Count

Rotate the (D) right by the

number of bit positions equal to
Count. Each bit shifted out from
the rightmost bit goes back into
the leftmost bit position.

CF
OF undefined
if count 1

RCL

Rotate left
through
carry

RCL D, Count

Same as ROL except carry is

attached to (D) for rotation.

CF
OF undefined
if count 1

RCR

Rotate right
through
carry

RCR D, Count

Same as ROR except carry is

attached to (D) for rotation.

CF
OF undefined
if count 1

611 37100 Lecture 05-55

5.5 Rotate Instructions

611 37100 Lecture 05-58

Register

CL

Memory

Memory

CL

EXAMPLE
What is the result in BX and CF after execution of the following
instructions?
RCR BX, CL
Assume that, prior to execution of the instruction, (CL)=0416,
(BX)=123416, and (CF)=0

Count

Register

Solution:
The original contents of BX are
(BX) = 00010010001101002 = 123416
Execution of the RCR command causes a 4-bit rotate right
through carry to take place on the data in BX, the results are
(BX) = 10000001001000112 = 812316
(CF) = 02

Allowed operands for rotate instructions

611 37100 Lecture 05-56

For RCL, RCR, the bits are rotate through the carry flag

5.5 Rotate Instructions

Rotate instructions: ROL, ROR, RCL, RCR

Destination

Rotate instructions: ROL, ROR, RCL, RCR

5.5 Rotate Instructions

611 37100 Lecture 05-59

5.5 Rotate Instructions

Rotate instructions: ROL, ROR, RCL, RCR

EXAMPLE
Verify the previous example using DEBUG program.

ROL AX, 1

Solution:

ROR AX, CL
(CL)=4

611 37100 Lecture 05-57

611 37100 Lecture 05-60

10

5.5 Rotate Instructions

EXAMPLE
Disassembly and addition of 2 hexadecimal digits stored as a
byte in memory.

Solution:
MOV
MOV
MOV
ROR
AND
AND
ADD

AL, [HEX_DIGITS]
BL, AL
CL, 04H
BL, CL
AL, 0FH
BL, 0FH
AL, BL

611 37100 Lecture 05-61

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