LD7750

2/23/2010

High Voltage Green-Mode PWM Controller with

Over Temperature Protection
Rev. 00b

General Description

Features

The LD7750 integrates several functions of protections,

High-Voltage (500V) Startup Circuit

and EMI-improved solution in a SOP-8, SOP-7, or DIP-8

Current Mode Control

package to minimize the component counts and the circuit

Non-Audible-Noise Green Mode Control

space.

UVLO (Under Voltage Lockout)

LEB (Leading-Edge Blanking) on CS Pin

Internal Frequency Swapping

Internal Slope Compensation

Internal Over Current Protection

OVP (Over Voltage Protection) on Vcc

OLP (Over Load Protection)

External OTP through a NTC

500mA Driving Capability

The device provides functions of low startup current,

green-mode

power-saving

operation,

leading-edge

blanking of the current sensing and internal slope

compensation.

Also,

the

LD7750

features

more

protections like OLP (Over Load Protection), OVP (Over

Voltage

Protection),

and

OTP

(Over

Temperature

Protection) to prevent the circuit being damaged under the

abnormal conditions. The LD7750 features built-in
auto-recovery function for OVP on Vcc pin and OLP.

Applications

Furthermore, the LD7750 features frequency swapping to

Switching AC/DC Adaptor and Battery Charger

depress radiation noise, providing an excellent solution for

Open Frame Switching Power Supply

EMI filter design.

LCD Monitor/TV Power

Typical Application
AC
input

EMI
Filter

HV VCC OUT

OTP

LD7750
CS
GND

photocoupler

COMP

*See Application Information

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LD7750
Pin Configuration

OUT

VCC

VCC

HV

NC

SOP-7 (TOP VIEW)

OUT

HV

SOP-8 & DIP-8 (TOP VIEW )

GND

YY:
WW:
PP:

CS

COMP

GND

OTP

YYWWPP

CS

YYWWPP

COMP

TOP MARK

OTP

TOP MARK

Year code
Week code
Production code

Ordering Information
Switching

Protection

Freq.

Mode

LD7750 GR

65KHz

Auto recovery

SOP-7

Green package

LD7750GR

2500 /tape & reel

LD7750 GS

65KHz

Auto recovery

SOP-8

Green package

LD7750GS

2500 /tape & reel

LD7750 GN

65KHz

Auto recovery

DIP-8

Green package

LD7750GN

3600 /tube /Carton

Part number

Package

Top Mark

Shipping

The LD7750 is ROHS compliant.

Pin Descriptions
PIN
DIP-8
SOP-8

NAME

FUNCTION

SOP-7
Pulling this pin below 0.95V will shutdown the controller to enter latch

OTP

mode until the AC power-on recycles. Connecting a NTC between this

pin and ground will achieve OTP protection function. Let this pin float to
disable the latch protection.
Voltage feedback pin. By connecting a photo-coupler to close the control

COMP

CS

GND

Ground.

OUT

Gate drive output to drive the external MOSFET.

VCC

Supply voltage pin.

***

NC

Unconnected Pin.

loop can achieve the regulation.

Current sense pin, for sensing the MOSFET current.

Connect this pin to a positive terminal of bulk capacitor to provide the

8

HV

startup current for the controller. When Vcc voltage trips the UVLO(on),
this HV loop will be turned off to reduce the power loss on the startup
circuit.

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LD7750
Block Diagram

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LD7750
Absolute Maximum Ratings
Supply Voltage VCC

30V

High-Voltage Pin, HV

-0.3V~500V

COMP,OTP, CS

-0.3V ~7V

OUT

-0.3V ~Vcc+0.3

Maximum Junction Temperature

150C

Operating Ambient Temperature

-20C to 85C

Operating Junction Temperature

-40C to 125C

Storage Temperature Range

-65C to 150C

Package Thermal Resistance (SOP-8, SOP-7)

160C/W

Package Thermal Resistance (DIP-8)

100C/W

Power Dissipation (SOP-8, SOP-7, at Ambient Temperature = 85C)

400mW

Power Dissipation (DIP-8, at Ambient Temperature = 85C)

650mW

Lead temperature (Soldering, 10sec)

260C

ESD Voltage Protection, Human Body Model (except HV Pin)

2.5KV

ESD Voltage Protection, Machine Model

250V

Gate Output Current

500mA

Caution:
Stresses beyond the ratings specified in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.

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LD7750
Electrical Characteristics
(TA = +25C unless otherwise stated, VCC=15.0V)
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

0.5

1.0

1.5

mA

35

400

High-Voltage Supply (HV Pin)

High-Voltage Current Source

VCC< UVLO(on), HV=500V

Off-State Leakage Current

VCC> UVLO(off), HV=500V

Supply Voltage (Vcc Pin)

Startup Current

200

320

VCOMP=0V, LD7750

2.5

mA

Operating Current

VCOMP=3V, LD7750

2.9

mA

(with 1nF load on OUT pin)

OLP tripped, LD7750

0.50

mA

OVP tripped, VCC=OVP

0.63

mA

UVLO (off)

9.0

10.0

11.0

UVLO (on)

15.0

16.0

17.0

OVP Level

24.5

26.0

27.5

1.45

1.75

mA

Voltage Feedback (COMP Pin)

Short Circuit Current

VCOMP=0V

Open Loop Voltage

COMP pin open

5.3

5.7

Green Mode Threshold VCOMP

2.75

Burst Mode

2.0

Current Sensing (CS Pin)

Maximum Input Voltage,Vcs_off

0.80

Leading Edge Blanking Time

250

Input impedance

Delay to Output

LD7750-DS-00b February 2010

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0.90

V
nS
M

100

5
Leadtrend Technology Corporation

0.85

nS

LD7750
Electrical Characteristics
(TA = +25C unless otherwise stated, VCC=15.0V)
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Oscillator for Switching Frequency

Frequency

LD7750

Green Mode Frequency

LD7750

Swapping Frequency

LD7750

61.0

65.0

69.0

KHz

20

KHz

KHz

Temp. Stability

-20 C~85 C

Voltage Stability

(VCC=11V-25V)

OTP Pin Latch Protection (OTP Pin)

92

100

108

Turn-On Trip Level

0.95

1.05

1.10

Turn-Off Trip Level

0.85

0.95

1.0

OTP Pin Source Current

De-latch VCC Level

(PDR, Power Down Reset)

8.0

Gate Drive Output (OUT Pin)

Output Low Level

VCC=15V, Io=20mA

Output High Level

VCC=15V, Io=20mA

Rising Time

Load Capacitance=1000pF

100

160

nS

Falling Time

Load Capacitance=1000pF

30

60

nS

5.0

5.2

1
9

V
V

OLP (Over Load Protection)

OLP Trip Level

4.8

OLP Delay Time

64

mS

ms

OTP Level

140

OTP Hysteresis

30

Soft Start Duration

Soft Start Duration
On Chip OTP (Internal Over Temperature Protection, Auto-Recovery)

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LD7750
Typical Performance Characteristics
0.88

0.87

1.3

VCS (off) (V)

HV Current Source (mA)

1.5

1.1

0.86

0.85

0.9
0.84

0.7
-40

40

80

0.83

120 125

-40

Temperature (C)

UVLO (off) (V)

UVLO (on) (V)

120 125

11.2

17.2

16.4

15.6

10.4

9. 6

8.8

14.8

8
-40

40

80

120 125

-40

Temperature (C)
Fig. 3 UVLO (on) vs. Temperature

40

80

120

125

120

125

Temperature (C)
Fig. 4 UVLO (off ) vs. Temperature

70

26

68

24

Frequency (KHz)

Frequency (KHz)

80

12

18.0

66

64

22

20

18

62

60

40

Temperature (C)
Fig. 2 VCS (off) vs. Temperature

Fig. 1 HV Current Source vs. Temperature (HV=500V, Vcc=0V)

14.0

-40

40

80

120

16

125

-40

80

Fig. 6 Green Mode Frequency vs. Temperature

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LD7750-DS-00b February 2010

40

Temperature (C)

Temperature (C)
Fig. 5 Frequency vs. Temperature

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LD7750
25

Green mode frequency (KHz)

70

Frequency (KHz)

68

66

64

62

12

14

16

18

20

22

24

19

17

14

16

18

20

22

Vcc (V)

Fig. 7 Frequency vs. Vcc

Fig. 8 Green mode frequency vs. Vcc

85

35

80

30

75

70

24

25

120

125

25

20

15

60
-40

40

80

10

120 125

-40

40

80

Temperature (C)

Temperature (C)

Fig. 9 Max Duty vs. Temperature

Fig. 10 VCC OVP vs. Temperature

6.0

6.5

5.5

6.0

5.0

OLP (V)

7.0

5.5

5.0

4.5

12

Vcc (V)

65

VCOMP (V)

21

15
11

25

VCC OVP (V)

Max Duty (%)

60
11

23

4.5

4.0

-40

40

80

3.5

120 125

-40

Temperature (C)

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LD7750-DS-00b February 2010

40

80

Temperature (C)
Fig. 12 OLP-Trip Level vs. Temperature

Fig. 11 VCO MP open loop voltage vs. Temperature

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120

125

LD7750
Application Information
When Vcc voltage reaches UVLO(on) threshold, the

Operation Overview

LD7750 is powered on to start issuing the gate drive

As green power requirements become a trend and the

signal, the high-voltage current source is then disabled,

power saving gets more and more important for the

and the Vcc supply current will be only provided from the

switching power supplies and switching adaptors, the

auxiliary winding of the transformer.

traditional PWM controllers are not able to support such

power loss on the startup circuit beyond the startup period

new requirements. Furthermore, the cost and size

can be eliminated and the power saving can be easily

limitations force PWM controllers to be more powerful by

achieved. In general application, a 39K resistor is still

integrating more functions and, thus, reducing the

recommended to be placed in high voltage path to limit

external part count.

the current if there is a negative voltage applying in any

LD7750 is designed for such

Therefore, the

case.

application to provide an easy and cost effective solution.

Its detail features are described as below.

An UVLO comparator is included to detect the voltage on

the VCC pin to ensure the supply voltage is high enough to

Internal High-Voltage Startup Circuit and

power on the LD7750 PWM controller and in addition to

Under Voltage Lockout (UVLO)

drive the power MOSFET as well.

Traditional circuits power on the PWM controller through a

Hysteresis is provided to prevent the shutdown caused by

startup resistor to constantly provide current from a

the voltage dip during startup. The turn-on and turn-off

rectified voltage to the capacitor connected to Vcc pin.

threshold levels are set at 16V and 10.0V, respectively.

Nevertheless, this startup resistor was usually of larger

resistance, and it therefore consumed more power and
required longer time to start up.
To achieve an optimized topology, as shown in Fig. 13,
The LD7750 is built in with high voltage startup circuit to
optimize the power saving. During the startup sequence, a
high-voltage current source sinks current from CBULK
capacitor to provide the startup current as well as to
charge the Vcc capacitor C1. During the initialization of
the startup, Vcc voltage is lower than the UVLO(off)
Fig. 13

threshold thus the current source is on to supply a current

of 1mA. Meanwhile, as the Vcc current consumed by the
LD7750 is as low as 320A thus most of the HV current is
utilized to charge the Vcc capacitor.

By using such

configuration, the turn-on delay time will be almost the

same no matter whether operation condition is under
low-line or high-line.

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As shown in Fig. 14, a

LD7750
Nevertheless, it is strongly recommended to add a small
R-C filter (as shown in Fig. 16) for higher power
applications to avoid the CS pin being damaged by the
negative turn-on spike.

Output Stage and Maximum Duty-Cycle

An output stage of a CMOS buffer, with typical 500mA
driving capability, is incorporated to drive a power
MOSFET directly.

And the maximum duty-cycle of

LD7750 is limited to 75% to avoid the transformer

saturation.

Voltage Feedback Loop

The voltage feedback signal is provided from the TL431 in
the secondary side through the photo-coupler to the

Fig. 14

COMP pin of LD7750. The input stage of LD7750, like

the UC384X, is incorporated with 2 diodes voltage offset

and the Negative Spike on CS Pin

circuit and a voltage divider with 1/3 ratio. Therefore,

1
V+ (PWM COMPARATOR ) = ( VCOMP 2VF )
3

The typical current mode PWM controller feeds back both

A pull-high resistor is embedded internally and thus an

current signal and voltage signal to close the control loop

external one is not required.

Current Sensing, Leading-edge Blanking

and achieve regulation. The LD7750 detects the primary

Switching Frequency

MOSFET current from the CS pin, which is not only for the
peak current mode control but also for the pulse-by-pulse

The LD7750 is implemented with frequency swapping

current limit. The maximum voltage threshold of the

function which helps the power supply designers both

current sensing pin is set as 0.85V. Thus the MOSFET

optimize EMI performance and lower system cost. The

peak current can be calculated as:

switching frequency substantially centers at 65KHz, and

IPEAK(MAX)

0.85V
=
RS

trembles within the range of 4KHz.

A 250nS leading-edge blanking (LEB) time is included in

the input of CS pin to prevent false-trigger caused by the
current spike. For low power application, if the total pulse
width of the turn-on spike is less than 250nS and the
negative spike on the CS pin is not as low as -0.3V, the
R-C filter (as shown in Fig.15) can be eliminated.
However, the total pulse width of the turn-on spike is
related to the output power, circuit design and PCB layout.

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LD7750
Internal Slope Compensation
Stability is crucial for current mode control when it
operates at more than 50% of duty-cycle. To stabilize the
control loop, the slope compensation is required in the
traditional UC384X design by injecting the ramp signal
from the RT/CT pin through a coupling capacitor. In the
LD7750, the internal slope compensation circuit has been
implemented to simplify the external circuit design.

On/Off Control
The LD7750 can be turned off by pulling COMP pin to
lower than 2.0V. The gate output pin of LD7750 will be
disabled immediately under such condition. The off-mode
can be released when the pull-low signal is removed.
Fig. 15

Green-Mode Operation
By using the green-mode control, the switching frequency
can be reduced under the light load condition. This feature
helps to improve the efficiency in light load conditions.
The green-mode control is Leadtrend Technologys own
IP.

Over

Load

Protection

(OLP)

Auto

Recovery
To protect the circuit from the damage caused by
overload condition or output short condition, a smart OLP
function is implemented in the LD7750 for it. The OLP
function in LD7750 is an auto-recovery type protection.
Fig. 17 shows the waveforms of the OLP operation.
Under such fault condition, the feedback system will force
the voltage loop toward saturation and thus pull the
voltage on COMP pin (VCOMP) to high. Whenever the
VCOMP trips the OLP threshold of 5.0V and stays for over
Fig. 16

63mS, the protection will be activated to turn off the gate

output and to shutdown the switching of power circuit.
The 63mS delay time is to prevent the false-trigger during
the power-on and turn-off transient.

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LD7750
A divided-by-2 counter is implemented to reduce the

The Vcc OVP function in LD7750 is an auto-recovery type

average power consumption under OLP behavior.

protection. If the OVP condition, usually caused by open

Whenever OLP is activated, the output is latched off and

feedback loop, is not released, the Vcc will trip the OVP

the divided-by-2 counter starts to count the number of

level again and shutdown the output. The Vcc is working

UVLO(off).

in hiccup mode.

The latch will be released if the 2nd

Fig. 18 shows its operation.

UVLO(off) point is counted, and then the output recovers

Once the OVP condition is removed, the Vcc and the

switching again.

output will resume to normal operation.

By using such protection mechanism, the average input

power can be reduced to a very low level so that the
component temperature and stress can be controlled
within a safe operating area.

Fig. 18

OTP Pin --- Latched Mode Protection

To protect the power circuit from damage due to system
failure, over temperature protection (OTP) is required. The
OTP circuit is implemented to sense a hot-spot of power
circuit like power MOSFET or output rectifier. It can be
easily achieved by connecting a NTC with OTP pin of
LD7750.

Fig. 17

As the device temperature or ambient

temperature rises, the resistance of NTC decreases. So,

the voltage on the OTP pin could be written as below.

OVP (Over Voltage Protection) on Vcc- Auto

VOTP = 100A R NTC

Recovery

When the VOTP is less than the defined threshold voltage

The VGS ratings of the nowadays power MOSFETs are

(typical 0.95V), LD7750 will shutdown the gate output and

mostly with 30V maximum. To protect the VGS from the

then latch the power supply off.

fault condition, LD7750 is implemented with OVP function

remain latched unless the Vcc drops below 8V (power

on Vcc.

Whenever the Vcc voltage is larger than the

down reset) and the fault condition is removed at the

OVP threshold voltage, the output gate drive circuit will be

same time. There are 2 conditions required to restart it

shut down simultaneously and stop switching of the power

successfully. First, cool down the circuit so that NTC

MOSFET until the next UVLO(ON).

resistance will increase and raise VOTP above 1.05V. Then,

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The controller will

LD7750
remove the AC power cord and restart AC power-on

V(-)Latch

recycling. The detailed operation is depicted in Fig. 19.

OTP Release
1.05V
0.95V

Pull-Low Resistor on the Gate Pin of

OTP

MOSFET

VCC

An anti-floating resistor is built in with the OUT pin to

UVLO(on)

prevent the output from any uncertain state. Otherwise, it

UVLO(off)
PDR (8V)

may cause the MOSFET to work abnormally or mis-trigger.

Latch Released

However, such design wont cover the condition of

AC input Voltage

disconnection between the OUT pin and the gate terminal

AC Off

AC On (Recycle)

for the MOSFET. Thus it is still strongly recommended

t

to have a resistor connected at the MOSFET gate

terminal (as shown in Fig. 20) to provide extra protection
for fault conditions.

OUT

This external pull-low resistor is to prevent the MOSFET

Switching

from damage during power-on when the gate resistor Rg

Non-Switching
Switching

is disconnected. In such a fault condition, as show in Fig.

Fig. 19

21, the resistor R8 can provide a discharge path to avoid

the MOSFET from being falsely triggered by the current
through the gate-to-drain capacitor CGD. Therefore, the
MOSFET should be always pulled-low to persist in
off-state.

Fig. 20

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LD7750
than similar products. Nevertheless, a 39K resistor is
recommended to implement on the Hi-V path as a current
limit resistor no matter what negative voltage is present in
any situation.
dV
i = Cgd bulk
dt

Fig. 22

Fig. 21

Protection Resistor on the Hi-V Path

In some other Hi-V processes and designs, there may be
a parasitic SCR between HV pin, Vcc and GND.

As

shown in Fig. 22, a small negative spike on the HV pin

may trigger this parasitic SCR and cause latchup between
Vcc and GND. And such latchup will easily damage the
chip because of the equivalent short-circuit induced.
Fig. 23
With the Leadtrends proprietary Hi-V technology, there is
no such parasitic SCR in LD7750. Fig. 23 shows the
equivalent circuit of LD7750s Hi-V structure.

The

LD7750 has higher capability to sustain negative voltage

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LD7750
Reference Application Circuit --- 10W (5V/2A) Adapter
Pin < 0.15W when Pout = 0W & Vin = 264Vac
L

AC
input

F1

R1A

R1B

NTC1

Schematic

Z1

NTC2

CX1
FL1

IC1

(-)LATCH

HV
R9

OUT

CS

D1A~D1D

C1

VCC

GND

LD7750

COMP

D2

C2

R7

R6
R4A

R4B

R8

C5

D4
C4

RS1

T1

Q1

RS2

C51

C52
R56A ZD51

R54

L51

C55

R55

R56B

R52

R53

C54

LD7750-DS-00b February 2010

www.leadtrend.com.tw

R51B

R51A

CR51

IC2

photocoupler

CY1
IC5

15
Leadtrend Technology Corporation

LD7750
BOM
P/N
R1A

Component Value

Original

P/N

Component Value

Note

N/A

C1

22F, 400V

R1B

N/A

C2

22F, 50V

L-tec

R4A

39K, 1206

C4

1000pF, 1000V, 1206

Holystone

R4B

39K, 1206

C5

0.01F, 16V, 0805

R6

2.2, 1206

C51

1000pF, 50V, 0805

R7

10, 1206

C52

1000F, 10V

L-tec

R8

10K, 1206

C54

470F, 10V

L-tec

R9

40K, 1206

C55

0.022F, 16V, 0805

RS1

2.7, 1206, 1%

CX1

0.1F

X-cap

RS2

2.7, 1206, 1%

CY1

2200pF

Y-cap

RT

100K, 0805, 1%

D1A

1N4007

R51A

100, 1206

D1B

1N4007

R51B

100, 1206

D1C

1N4007

R52

2.49K, 0805, 1%

D1D

1N4007

R53

2.49K, 0805, 1%

D2

PS102R

R54

100, 0805

D4

1N4007

R55

1K, 0805

Q1

2N60B

R56A

2.7K, 1206

CR51

SB540

R56B

N/A

ZD51

6V2C

NTC1

5, 3A

08SP005

IC1

LD7750 GS

FL1

20mH

UU9.8

IC2

EL817B

T1

EI-22

IC51

TL431

L51

2.7H

F1

250V, 1A

Z1

N/A

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L-tec

600V, 2A

SOP-8
1%

LD7750
Package Information
SOP-7

Dimensions in Millimeters

Dimensions in Inch

Symbols

MIN

MAX

MIN

MAX

4.801

5.004

0.189

0.197

3.810

3.988

0.150

0.157

1.346

1.753

0.053

0.069

0.330

0.508

0.013

0.020

1.194

1.346

0.047

0.053

0.178

0.229

0.007

0.009

0.102

0.254

0.004

0.010

5.791

6.198

0.228

0.244

0.406

1.270

0.016

0.050

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LD7750
SOP-8

Dimensions in Millimeters

Dimensions in Inch

Symbols
MIN

MAX

MIN

MAX

4.801

5.004

0.189

0.197

3.810

3.988

0.150

0.157

1.346

1.753

0.053

0.069

0.330

0.508

0.013

0.020

1.194

1.346

0.047

0.053

0.178

0.229

0.007

0.009

0.102

0.254

0.004

0.010

5.791

6.198

0.228

0.244

0.406

1.270

0.016

0.050

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LD7750
Package Information
DIP-8

Symbol

Dimension in Millimeters

Dimensions in Inches

Min

Max

Min

Max

9.017

10.160

0.355

0.400

6.096

7.112

0.240

0.280

-----

5.334

------

0.210

0.356

0.584

0.014

0.023

1.143

1.778

0.045

0.070

2.337

2.743

0.092

0.108

2.921

3.556

0.115

0.140

7.366

8.255

0.29

0.325

0.381

------

0.015

--------

Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers
should verify the datasheets are current and complete before placing order.

19
Leadtrend Technology Corporation
LD7750-DS-00b February 2010

www.leadtrend.com.tw

LD7750
Revision History
Rev.

Date

Change Notice

00

9/16/2009

Original specification

00a

11/11/2009

Package option: SOP-7

00b

2/22/2010

Frequency TremblingFrequency Swapping

20
Leadtrend Technology Corporation
LD7750-DS-00b February 2010

www.leadtrend.com.tw