BU2090F
BU2090F
Applications
Radio
cassette players, telephones, compact audio systems, car stereos, and others
1)Features
Low power dissipation.
2) Operating voltages ranging from 2.7 to 5.5V.
3) Output is Nch open drain.
4) High output withstand voltage of + 25V.
Standard ICs
maximum ratings (Ta = 25C)
Absolute
(BU2090 / F / FS, BU2092 / F / FV)
Parameter
Symbol
VDD
BU2090 / F / FS
Pd
BU2092 / F / FV
BU2090 / F / FS
Limits
Unit
0.3 ~ + 7.0
Pd
mW
Operating temperature
Topr
25 ~ + 75
Storage temperature
Tstg
55 ~ + 125
Input voltage
VIN
Output voltage
VO
VSS ~ 25.0
BU2092 / F / FV
1 Unmounted
2 When mounted on a glass epoxy board of 50mm 50mm 1.6mm
3 When mounted on a glass epoxy board of 90mm 50mm 1.6mm
4 When mounted on a glass epoxy board of 70mm 70mm 1.6mm
mW
Symbol
Limits
Unit
VDD
2.7 ~ 5.5
Standard ICs
Block diagram
BU2090 / F / FS
BU2092 / F
VSS 1
VSS 1
DATA 2
CLOCK 3
Control circuit
12-bit shift register
16 VDD
Control circuit
DATA 2
18 VDD
17 OE
15 Q11
CLOCK 3
14 Q10
Latch
LCK 4
16 Q11
112-bit storage register
15 Q10
13 Q9
Q0 4
Q0 5
Output buffer
(open drain)
Q1 5
12 Q8
Q2 6
11 Q7
Q3 7
10 Q6
Q4 8
9 Q5
Output buffer
(open drain)
14 Q9
Q1 6
13 Q8
Q2 7
12 Q7
Q3 8
11 Q6
Q4 9
10 Q5
BU2092FV
VSS 1
Control circuit
DATA 2
20 VDD
19 OE
18 Q11
CLOCK 3
LCK 4
Q0 5
17 Q10
16 Q9
Q1 6
15 Q8
Q2 7
14 Q7
Q3 8
13 N.C.
Q4 9
12 N.C.
Q5 10
11 Q6
Standard ICs
Pin descriptions
Pin No.
BU2090 / F / FS
BU2092 / F BU2092 / FV
Pin name
VSS
DATA
Function
GND
Serial data input
CLOCK
LCK
Q0
Q1
Q2
Q3
Q4
10
10
Q5
10
11
11
Q6
12
N.C.
Not connected
Not connected
13
N.C.
11
12
14
Q7
12
13
15
Q8
13
14
16
Q9
14
15
17
Q10
15
16
18
Q11
17
19
OE
Output Enable
16
18
20
VDD
Power supply
Standard ICs
characteristics (Ta = 25C)
Electrical
DC characteristics (unless otherwise noted, Ta = 25C, V
Parameter
Symbol
VIH
VIL
SS
= 0V)
Min.
Typ.
Max.
3.5
2.5
1.5
VOL
0.4
2.0
1.0
Unit
VDD
Conditions
3
5
IOL = 20mA
IOL = 5mA
IOZH
10.0
VO = 25.0V
IOZL
5.0
VO = 0V
Current dissipation
IDD
5.0
3.0
OUTPUT: OPEN
Symbol
tW
Min.
Typ.
Max.
500
1000
200
300
200
400
50
100
250
500
200
400
250
500
tSU
tH
tLSUH
tLHH
tLSUL
tLHL
Unit
VDD
Conditions
ns
3
5
ns
3
5
ns
3
5
ns
3
5
ns
3
5
ns
3
5
ns
CLOCK
tW
90%
10%
tSU
DATA
90%
10%
tH
tLSUL
10%
10%
tLSUH
tLHL
90%
90%
10%
VDD
90%
10%
GND (VSS)
tLHH
90%
VDD
GND (VSS)
Fig.1
Standard ICs
Symbol
tPLZ (LCK)
tPLZ
Output disable time
(OE to OUTPUT QX)
tPZL
tW
tW (LCK)
tS
Setup time
(DATA to CLOCK)
tSU
Hold time
(CLOCK to DATA)
tH
Min.
Typ.
Max.
55
90
50
115
45
70
35
80
500
1000
500
1000
200
400
200
400
200
400
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDD
5
3
5
3
5
3
5
3
Conditions
RL = 5k
CL = 10pF
RL = 5k
CL = 10pF
RL = 5k
CL = 10pF
RL = 5k
CL = 10pF
3
5
3
5
3
5
3
5
CLOCK
10%
90%
10%
tSU
tW
90%
90%
10%
VDD
GND (VSS)
tH
VDD
90% 90%
tS
DATA
GND (VSS)
tW (LCK)
90%
50%
10%
50%
LCK
tPLZ (LCK)
VDD
90%
GND (VSS)
VDD
tPZL (LCK)
50%
50%
OE
GND (VSS)
tPLZ
Qx
10%
50%
Fig.2
tPZL
10%
50%
Standard ICs
table
Truth
BU2092 / F / FV
INPUT
CLOCK DATA
LCK
OE
FUNCTION
First cell of the shift register stores the LOW. Other cells, respectively, store
data from the preceding cells or other prior data. (Output state is HOLD.)
First cell of the shift register stores the HIGH. Other cells, respectively, store
data from the preceding cells or other prior data. (Storage state and output state are HOLD.)
Q0 to Q11 output for the BU2090 / F / FS and BU2092 / F / FV is Nch open drain output. When the shift register transfer data is LOW,
the corresponding output FET is ON (continuous state). When the transfer data is HIGH, the output FET is OFF (discontinuous).
BU2092 / F
BU2092FV
BU2090 / F / FS
BU2092 / F
BU2092FV
5, 6, 7, 8, 9,
5, 6, 7, 8, 9,
4, 5, 6, 7, 8, 9
Pin No. 2, 3, 4, 17 Pin No. 2, 3, 4, 19 Pin No. 10, 11, 12, 13 Pin No. 10, 11, 12, 13 Pin No. 10, 11, 14, 15
14, 15
14, 15, 16
16, 17, 18
2, 3
VDD
GND (VSS)
VDD
GND (VSS)
GND (VSS)
Standard ICs
operation
TheCircuit
logic of the DATA pin is sent to the 12-bit shift register on the rising edge of the CLOCK pulse. Subsequently, it
is shifted from Q0 to Q11 for every clock rising edge.
CLOCK
DATA
Q11
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Note 1)
Standard ICs
CLOCK
DATA
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LCK
OE
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Note 1)
Standard ICs
Application example
BU2090
/ F / FS
VDD
CLOCK DATA
GND
(VSS)
GND
(VSS)
Latch
Control
circuit
Fig.5
BU2092 / F / (FV)
VDD
GND
DATA (VSS)
GND (VSS)
CLOCK
OE
Control
circuit
LCK
Fig.6
10
Standard ICs
DIP16 (Unmounted)
1000
800
mounted on a 90mm 50mm 1.6mm
SSOP16 (when
glass epoxy board)
400
SOP16 (Unmounted)
200
25
50
75
100
125
150
800
SSOP-B20
(When mounted on a 70mm 70mm 1.6mm glass epoxy board)
SOP18 (Unmounted)
400
SSOP-B20
(Unmounted)
200
25
50
75
100
125
150
1000
30
1200
POWER DISSIPATION: Pd (mW)
1200
25
VDD
= 5V
VDD
= 3V
20
15
10
5
0.5
1.0
1.5
2.0
2.5
11
Standard ICs
BU2092
22.9 0.3
19.4 0.3
10
6.5 0.3
0.51Min.
0.51Min.
6.5 0.3
16
18
7.62
7.62
0.3 0.1
0.3 0.1
3.29 0.2
0.5 0.1
2.54
0 ~ 15
0.5 0.1
2.54
DIP16
DIP18
BU2090F
BU2092F
11.2 0.2
0.4 0.1
0.3Min.
1.27
0.4 0.1
0.15 0.1
0.15 0.1
1.5 0.1
0.11
1.27
10
5.4 0.2
1.8 0.1
18
0.11
4.4 0.2
16
7.8 0.3
10.0 0.2
6.2 0.3
0 ~ 15
0.3Min.
0.15
0.15
SOP16
SOP18
BU2090FS
BU2092FV
0.8
0.3Min.
11
10
0.65
0.15 0.1
0.15 0.1
0.36 0.1
20
4.4 0.2
1.15 0.1
0.1
9
6.4 0.3
6.5 0.2
16
4.4 0.2
0.11
1.5 0.1
6.2 0.3
6.6 0.2
0.22 0.1
0.3Min.
0.1
0.15
SSOP-A16
12
SSOP-B20