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Chapter 18

The document discusses the design of various counters using different types of flip-flops like RS, JK, T and D flip-flops. It provides the solution for designing 3-bit, 4-bit counters with different counting sequences. The solutions include developing the state table, excitation table, deriving the Boolean expressions from K-maps and providing the final logic diagram.

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kumarguptav91
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125 views

Chapter 18

The document discusses the design of various counters using different types of flip-flops like RS, JK, T and D flip-flops. It provides the solution for designing 3-bit, 4-bit counters with different counting sequences. The solutions include developing the state table, excitation table, deriving the Boolean expressions from K-maps and providing the final logic diagram.

Uploaded by

kumarguptav91
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Chapter 18
Sequential Circuits: Flip-flops and Counters
1. Design a counter that has the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6,
7. Use RS flip-flops.

Fig. 1.1 State diagram of a 3-bit binary counter


Solution:
Step 1: Since it is a 3-bit counter, the number of flip-flops required is 3.
Step 2: Let the type of flip-flops be RS flip-flops.
Step 3: Let the three flip-flops be A, B, C.
Step 4: The state table is as shown in Table 1.1.
Table 1.1 State table
Present State
ABC
000
001
010
011
100
101
110
111

Next State
ABC
001
010
011
100
101
110
111
000

Step 5: The next step is to develop an excitation table from the state table, which is
shown in Table 1.2.
Table 1.2 Excitation table
Output State Transitions
Present State
Next State
ABC
ABC

Dorling Kindersley India Pvt. Ltd 2010

Flip-flop inputs
RA SA

RB SB

RC SC

Pulse and Digital Circuits

000
001
010
011
100
101
110
111

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

001
010
011
100
101
110
111
000

X0
X0
X0
01
0X
0X
0X
10

X0
01
0X
10
X0
01
0X
10

01
10
01
10
01
10
01
10

Step 6: Now transfer the RS states of the flip-flop inputs from the excitation table to
Karnaugh maps in Tables 1.31.8 to derive a simplified Boolean expression for each flipflop input.
Table 1.3 K-map for RA

Table 1.4 K-map for SA

Table 1.5 K-map for RB

Table 1.6 K-map for SB

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Table 1.7 K-map for RC

Table 1.8 K-map for SC

From the K-maps, the following expressions for the R and S inputs of each flip-flop are
obtained:
RA = ABC
SA = ABC
RB = AB + BC = B(A+C)
SB = BC
RC = C
SC = C
Step 7: The final step is to implement the combinational logic from the equations and
connect the flip-flops to form the sequential circuit. The complete logic of a 3-bit binary
counter is shown in Fig 1.2.

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig. 1.2 Logic diagram of a 3-bit binary counter

2. Design a counter with the following binary sequence: 1, 2, 5, 7 and repeat. Use JK
flip-flops.
Solution:
Step 1: Since it is a 3-bit counter, the number of flip-flops required is three.
Step 2: Let the type of flip-flops be RS flip-flops.
Step 3: Let the three flip-flops be A,B,C.
Step 4: The state table is as shown in Table 2.1.
Table 2.1: State table
Present State
ABC
001
010
10 1
11 1

Next State
ABC
010
101
111
001

Step 5: The next step is to develop an excitation table from the state table, which is
shown in Table 2.2.
Table 2.2: Excitation table
Output State Transitions
Present State
Next State
ABC
ABC
001
010
010
101
10 1
111
11 1
001

Flip-flop Inputs
JA KA
0 X
1 X
X 0
X 1

JB KB
1 X
X 1
1 X
X 1

JC KC
X 1
1 X
X 0
X 0

Step 6: Now transfer the JK states of the flip-flop inputs from the excitation table to
Karnaugh maps in Tables 2.32.8 to derive a simplified Boolean expression for each flipflop input.

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Table 2.3 K-map for JA

Table 2.4 K-map for KA

Table 2.5 K-map for JB

Table 2.6 K-map for KB

Table 2.7 K-map for JC

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Table 2.8 K-map for KC

From the K-maps, the following expressions for the J and K inputs of each flip-flop are
obtained:
JA = JC = ABC
KA = ABC
JB = BC AC
KB = AC
KC = A BC
Step 7: The final step is to implement the combinational logic from the equations and
connect the flip-flops to form the sequential circuit. The complete logic of a counter is
shown in Fig. 2.1.

Fig. 2.1 Logic diagram of a counter

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

3. Design a counter with the following repeated binary sequence: 0, 4, 2, 1, 6. Use T flipflops.
Solution:
Step 1: Since it is a 3-bit counter, the number of flip-flops required is three.
Step 2: Let the type of flip-flops be RS flip-flops.
Step 3: Let the three flip-flops be A, B and C.
Step 4: The state table is as shown in Table 3.1.
Table 3.1 State table
Present State
ABC
0 0 0
1 0 0
010
00 1
11 0

Next State
ABC
1 0 0
0 1 0
0 0 1
110
000

Step 5: The next step is to develop an excitation table from the state table, which is
shown in Table 3.2.
Table 3.2 Excitation table
Output State Transitions
Present State
Next State
ABC
ABC
1 0 0
0 0 0
1 0 0
0 1 0
010
0 0 1
00 1
110
11 0
000

Flip-flop Inputs
TA
1
1
0
1
1

TB
0
1
1
1
1

TC
0
0
1
1
0

Step 6: Now transfer the T states of the flip-flop inputs from the excitation table to
Karnaugh maps in Tables 3.33.5 to derive a simplified Boolean expression for each flipflop input.
Table 3.3 K-map for TA

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Table 3.4 K-map for TB

Table 3.5 K-map for TC

From the K-maps, the following expressions for the T input of each flip-flop are
obtained:
TA = A B BC AC
TB = A BC AC BC
TC = A BC ABC
Step 7: The final step is to implement the combinational logic from the equations and
connect the flip-flops to form the sequential circuit. The complete logic of a counter is
shown in Fig 3.1.

Fig. 3.1 Logic diagram of a counter

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

4. Design a sequential circuit whose state tables are specified in Table 18p.36, using D
flip-flops.
Solution:
First, we make the stable state and the next step is to derive the excitation table for the
design circuit, which is shown in Table 4.1. The output of the circuit is labelled Z.
Table 4.1 Excitation table
Present State
AB

Next State
AB

Input
x

Flip-flop
Inputs
DA DB

Output
Z

00
00
01
01
10
10
11
11

00
01
00
10
11
10
00
01

0
1
0
1
0
1
0
1

0
0
0
1
1
1
0
0

0
0
0
0
0
0
0
1

0
1
0
0
1
0
0
1

Table 4.2 K-maps for DA, DB and Z

The simplified Boolean expressions are:


DA = AB A Bx
DB = A B x ABx AB x
Z = ABx
Finally, the logic diagram is as shown in Fig.4.1.

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig. 4.1 Logic diagram

Dorling Kindersley India Pvt. Ltd 2010

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