SNAP Design Capture Overview –

Starting a Design from Scratch

SNAP Design Capture
This tutorial is designed to walk you through creating a simple
SNAP configuration and to get you familiar with the SNAP
Capture Tool and working environment.
Interface Overview:

Tool
Tool Bar
Bar

Design
Design
SNAP
SNAP Window
Window
Components
Components

Configuration
Configuration Quick
Quick
Tabs
Tabs Help
Help
SNAP Design Capture
Overview
■ In this demonstration, we will create a simple SNAP instance
with the following elements:
o 2 Hubs
o One AHB Layer
o One AXI initiator
o One OCP initiator
o One AHB branch
o One AHB target
o One APB branch
o One APB target
o One AXI target
o One OCP target
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First… Some Definitions:

■ Hubs (aka interconnect matrix,
crossbar, exchange):
o Provide dedicated connections
between agents embedded in the
hub. SNAP allows two hubs per
design which can be connected
through a pipeline point
■ Layers
o Allow multiple masters to be
connected to a single hub port
■ Branches
o Allow multiple slaves to be
connected to a single hub port
■ Initiator agents
o Embedded into a hub and connect
to layers, bridges, or master cores
outside the hub via sockets
■ Target agents
o Embedded into a hub and connect
to layers, bridges, or slave cores
outside the hub via sockets
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Creation methodology:
■ The preferred way to create your SNAP instance is to define
its topology first, by creating the desired SNAP components in
the design window: Hubs, Layers, Branches, Initiator and
Targets.
■ Once the topology is defined, you will refine your
configuration step by step, using each of the configuration
Tabs, in the left to right order: Connections, Performances &
QoS, Pipelining, Address Map, Sockets, Clocks.
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Create the file name and name your design
■ Go to the File / Properties menu, and enter:
o Design Name: snap_lab
o Design Identifier LAB1
o Click ‘OK’
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Create the hubs
■ [NOTE]
o At startup, the tool creates a “default design” with one Hub, one AHB Layer and one
AHB branch. This “default design” has been chosen because it is expected that most
SNAP design will have at least these three elements, but, if this is not the case it is
possible and easy to change it.
■ Since our example has 2 hubs, let’s add a Hub to this “default design” first:
o Right click on Hub1 body, and select Add Hub.
o A new Hub named Hub2 appear on the right of the existing Hub, with automatically
created AHB layer and branch.
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Creating the hubs
■ Rename Hubs to give them a
meaningful name
o For instance, let’s consider one Hub
will connect a CPU and the slaves it
accesses most frequently;
o The other Hub will connect a DSP, and
the slaves it accesses most frequently:
■ Right-click on Hub1 body, and select
Rename Hub. Rename the Hub
CPU_XB.
■ Right-click on Hub2 body, and select
Rename Hub. Rename the Hub
DSP_XB.
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Next, we need create the Layers, Branches, Initiator port and
Target port that will be attached to our hubs.
■ On our Hub named CPU_XB we want to have:
o One AHB Layer for 4 DMA AHB masters ports: DMA0, DMA1, DMA2,
DMA3
o One AXI initiator for a CPU master port: CPU0
o One AHB branch for 4 peripheral slave ports: UART, SPI, I2C, TIMER
o One AHB slave for a static memory slave port: SRAM
■ On our Hub named DSP_XB we want to have:
o One OCP initiator for a DSP master port: DSP0
o One APB branch for 4 peripheral slave ports: GPIO0, GPIO1, INTC,
CRYPTO
o One APB slave for a configuration port: DMACONFIG
o One AXI slave for a dynamic memory slave port: DDRC
o One OCP slave for a read-only memory slave port: ROM
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Let’s rename / modify some
of the pre-existing
components
■ Right-click on layer1 body,
and select Rename Layer.
Rename the Layer DMA.
■ Right-click on branch1 body,
and select Rename Branch.
Rename the Branch
CPU_PERI.
■ Right-click on layer2 body,
and select Delete Layer.
■ Right-click on branch2 body,
and select Rename Branch.
Rename the Branch
DSP_PERI.
■ In the drop-down menu of
the DSP_PERI branch,
select APB as the protocol.

Your design should now

look like this:
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Creating Initiator Ports
■ Right-click on CPU_XB body, and select Add Master.
o A new initiator port is created. While AHB Layers can have multiple AHB master
ports, an initiator port is a single master port of the Hub. Initiator ports are used to
connect non-AHB initiators (AXI and OCP), or AHB initiators that need the high
performance that the use of a dedicated port allows.
■ The default protocol for the master port is AXI, and this is what we need.
■ Click into the text box which says “master1”, and rename to CPU.
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Creating Initiator Ports
■ Now we need to add the DMA ports
to the DMA AHB Layer.
■ Right-click on DMA layer body, and
select Add Port. Name the port
DMA0_IF.
o The new created port is now displayed
in the Layer body, along with its
“priority”. This number, starting from 0,
indicate which AHB master has the
highest priority on the layer, which uses
a fixed priority arbitration. The highest
priority is 0, the lowest is 8.

■ Right-click on DMA layer body, and

select Add Port. Name the port
DMA1_IF.
■ Right-click on DMA layer body, and
select Add Port. Name the port
DMA2_IF.
■ Right-click on DMA layer body, and
select Add Port. Name the port
DMA3_IF.
Now our DMA Layer structure is
completely defined
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Creating Initiator Ports
■ Let’s now add the DSP to its Hub.
o Right-click on DSP_XB body, and select Add Master.
o The default protocol for the master port is AXI, and we need to change it to OCP.
o In the drop-down menu of master1, select OCP as the protocol.
o Click into the text box which says “master1”, and rename to “DSP”
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Creating the Slave Ports – now we’ll create the CPU_XB slave
ports; on the AHB branch for UART, SPI, I2C, TIMER; and
SRAM with its own dedicated port
■ Right-click on CPU_XB body, and select Add Slave.
■ In the drop-down menu of ‘slave1’, select AHB as the protocol.
■ Click on ‘slave1’ body, and rename the target: ‘SRAM’
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Creating the Slave Ports
■ Add the AHB target ports to the AHB branch of our CPU cross-bar:
o Right-click on CPU_PERI branch body, and select Add Port. Name the port UART_IF.
o Right-click on CPU_PERI branch body, and select Add Port. Name the port SPI_IF.
o Right-click on CPU_PERI branch body, and select Add Port. Name the port I2C_IF.
o Right-click on CPU_PERI branch body, and select Add Port. Name the port
TIMER_IF.
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Now, we’ll create the DSP_XB slave ports
■ on the APB branch we’ll add GPIO0, GPIO1, INTC, CRYPTO ports;
■ one APB port for DMACONFIG,
■ one AXI port for DDRC
■ one OCP slave for ROM

Right-click on DSP_XB body, and select Add Slave.

■ In the drop-down menu of ‘slave1’, select APB as the protocol.
■ Click on ‘slave1’ body, and rename the target: ‘DMACONFIG’
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Creating the DSP_XB slave ports

■ Right-click on DSP_XB body, and select Add Slave.
■ Keep AXI as the protocol used by this target.
■ Click on ‘slave1’ body, and rename the Target: DDRC
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Creating the DSP_XB slave ports
■ Right-click on DSP_XB body, and select Add Slave.
■ In the drop-down menu of ‘slave1’, select OCP as the
protocol.
■ Click on ‘slave1’ body, and select rename the target: ‘ROM’
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Creating the DSP_XB slave ports
■ Add the APB target ports to the APB branch of our DSP cross-bar:
o Right-click on DSP_PERI branch body, and select Add Port. Name the port
GPIO0_IF.
o Right-click on DSP_PERI branch body, and select Add Port. Name the port
GPIO1_IF.
o Right-click on DSP_PERI branch body, and select Add Port. Name the port INTC_IF.
o Right-click on DSP_PERI branch body, and select Add Port. Name the port
CRYPTO_IF.
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The complete topology of your SNAP design is now
complete
■ It should look like this:
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Defining Connectivity
■ Now that all the ports of your SNAP instance have been created, you can
specify the connectivity required amongst them.
■ Click on the “Connections” configuration TAB
o A table showing the Master ports in rows, and the Slave ports in columns appear [You
can resize the windows to read as much information as required]
o At each intersection between a master port row and a slave port column, it is possible
to specify if the master can access the slave by clicking into the check box.
o To speed-up the process, it is also possible to connect a master to all slaves at once
by pressing the Set Row button; and to connect a slave to all master at once by
pressing the Set Col button.
■ In our example, we want full connectivity, so click the “Set All” button to check
all boxes.
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Defining Performance and Quality-of-Service settings
■ Each initiator, layer, branch, and target component can be set
to be optimized for performance, or optimized for area.
■ Tradeoffs
o Performance optimized components will cost more gates but will
behave as fast as possible
o Area optimized components will be implemented with the least
possible amount of logic, at the expense of bandwidth
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Defining Performance and Quality-of-Service settings
■ In our example, we want all masters and slaves to be optimized for
performance, except the APB branch for which we do not need high
throughput
o Click on the “Performance & QoS” configuration TAB
o On the left side [Initiator side] of the TAB, click on the “Set All” button under the
‘optimize’ column. All Initiators should switch to optimize = performance at
once.
o On the right side [Targets side] of the TAB, click on the “Set All” button under
the ‘optimize’ column. All Targets should switch to optimize = performance at
once. Then click on the drop-down menu of the DSP_PERI Target, and select
“area”
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Defining Performance and Quality-of-Service settings
■ To configure quality of service in our example, we need to specify which
masters will have a “priority” attribute, and which slaves will take this
attribute into account.
o Configuring a slave to take the priority attribute into account modifies its
arbitration and might cost some additional gates, so we want to specify only
those slaves for which this matters.
o SDRAM controllers are a typical slave to which you might want a CPU or a DSP
to have priority over a DMA, for instance, to reduce latency.
■ In our example, we will just define the CPU as having the priority
attribute over all other masters, and the SRAM to respect this attribute.
o On the left side [Initiator side] of the TAB, click the check box under the
priority_en column, for the CPU initiator.
o On the right side [Target side] of the TAB, click the check box under the
priority_en column, for the SRAM target [target1].
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Defining Pipelining Options
■ Click on the “Pipelining” configuration TAB.
■ From this TAB, it is possible to configure register slices, in request path and
in response path, for each element connected to the HUBs.
o A register slice adds one cycle of latency to the path it is inserted in, and breaks all
timing arcs, forward and backwards. Register slices are added for timing closure
reasons.
■ In our example, let’s add a register slice on the CPU master port in request
path, and one register slice on the DDRC slave port on the response path.
o On the Layer Pipelining Option table, check the box on the CPU row, in the request
column.
o On the Branch Pipelining Option table, check the box on the DDRC row, in the
response column.
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Defining Pipelining Options
■ Now, let’s configure all the targets to have a “registered input” timing
style in request, which costs slightly more gates than “none” but is
guaranteed to support all our socket interfaces
■ On the Branch Pipelining Option table, in the “Response” column, in the
“retime column”, select “input” from the drop-down menu. Do this for
every slave.
■ Your Pipelining tab should now look like this:
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Define Address Map
■ Click on the “Address Map” configuration TAB.
■ A default address map has been generated when slaves ports were created.
o There is a chance that this default configuration will not exactly match your expected
address map, so you may need/want to edit it
o The base address is a text edition field, and it is sufficient to click on it to start editing
its value.
o The Size field is a “spinner”, and you need to use the small arrows “up” and “down” to
increase / decrease by one the size of the decoding region.
■ In our simple example, we will only edit the SRAM and DDRC region base
address and size, leaving everything else untouched.
o Click on the Base Address value of the SRAM row, and modify it to 0x20000000.
Then increase the Size value to 2^19 (512Kbytes).
o Click on the Base Address vale of the DDRC row, and modify it to 0x10000000. Then
increase the Size value to 2^26 (64MBytes).
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Configure each interface
■ Click on the “Sockets” configuration TAB.
o This Windows enable precise configuration of each interface. Most
interface types have multiple options, like data and address width,
protocol variants used, etc.
o The Windows is organized per protocol which appear as radio
buttons; one button per protocol (AHB and OCP further distinguish
between masters and slaves)
■ In our example we will choose to keep the default for all
interfaces except:
o All slaves will have 10 address bits except SRAM (19) and DDRC
(26)
o CPU and DDRC AXI will use 8 bits of ID
o OCP configurations will be specific
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Configure each interface
■ Select the AHB Slaves button inside the Protocol selection dialog.
■ The list of our AHB slaves ports appear:

■ The top row in light green is the “template”. This function allows a user to
modify the template, and then use cut & paste operations to quickly modify all
the sockets in a uniform way.
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Configure each interface
■ For our example, we’ll use the Green template line to modify
our AHB slaves
o In the template line, use the “arrow” to configure an Address Width
= 10.
o Right-click in the area in the Slave column, template row, and
select “Copy”.
o Right-click on each Slave name, and select “Paste”.
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Configure each interface
■ All slaves shall have the same address width now (10 bits).

■ But, we need to correct the SRAM address width to be 19.

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Configure each interface
■ Use the “arrow” to configure an Address Width = 19 for the
SRAM slave.
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Configure each interface
■ Let’s configure our APB slaves the same way
o Select the APB button inside the Protocol selection dialog.
o In the template line, use the “spinner” to configure an Address Width =
10.
o Right-click in the area in the Slave column, template row, and select
“Copy”.
o Right-click on each Slave name, and select “Paste”.
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Configure each interface

■ Now let’s configure the AXI interfaces for our CPU and DDRC
o Select the AXI button inside the Protocol selection dialog.
o For the CPU, use the “arrow” to configure an ID Width = 3.
o For the DDRC,
• use the “arrow” to configure an Address Width = 26
• use the “arrow” to configure an ID Width = 3.
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Configure each interface

■ For OCP, since the configuration
options are so numerous, the
direction of the rows and
columns is switched compared to
the AMBA interfaces: the master
or slave ports are in columns, the
OCP parameters of the
interfaces are in rows.
■ Select the OCP Master button
inside the Protocol selection
dialog.
o For our DSP master interface,
modify the following OCP
parameters:
• writeresp_enable = 1 (check the box)
• response_flow_control = 1 (check the
box)
• burstlength_width = 5
• address_width = 32
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Configure the clocks
■ Click the Clocks tab
■ When this Tab is clicked, it shows a basic system clock
■ A Frequency box is also provided, which will be used as an
input to generated synthesis scripts.
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Configure the clocks
■ Our example will use only one base clock, so we want to keep
only the snap_clk clock as it is
■ We also want to keep the frequency at the current value of
100MHz.
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Design Captured!
■ Your full sample SNAP design has now been captured
■ Be sure to save your work using the File > Save command on
the tool bar
More Information

■ Now that you have now successfully captured your own design
using the SNAP Capture tool you may want to submit it for
evaluation and RTL generation. You can find a tutorial on
evaluating a design here:
o http://www.sonicsinc.com/snap-help.htm
■ Please visit our SNAP support page for more tutorials
including:
o SNAP Registration and Download
o SNAP Installation and Configuration
o SNAP Design Capture Overview
o SNAP Evaluation and RTL Generation
o And more…