UNIT I

INTRODUCTION
Integrated Circuit(IC)
An integrated circuit (IC), or microchip, is a semiconductor wafer on which thousands or millions of tiny
resistors, capacitors, and transistors are fabricated. An IC can function as an amplifier, oscillator, timer, counter,
computer memory, or microprocessor.

Advantages of IC
1. Miniature in size. As fabrication process is used for the integration of active and passive components on to a
silicon chip, the IC becomes a lot smaller. When compared to a discrete circuit, it may be at least a thousand
times smaller.
2. To produce hundreds of discrete circuits on a PCB for the same logic takes more time and increase the cost
factor. But for the production of hundreds of ICs the cost of production will be very low and less time
consuming.
3. The small size of ICs causes lesser power consumption and lesser power loss.
4. Increased operating speed because of absence of parasitic capacitance effect.
5. Improved functional performance as more complex circuits can be fabricated for achieving better
characteristics.
6. As all the components are fabricated very close to each other in an IC, they are highly suitable for small
signal operation, as there wont be any stray electrical pickup.

Disadvantages of Integrated Circuits

1. Some complex ICs maybe costly. If such integrated circuits are used roughly and become faulty, they have to
be replaced by a new one. They cannot be repaired as the individual components inside the IC are too small.
2. Some components like transformers and inductors cannot be integrated into an IC. They have to be connected
externally to the semiconductor pins
3. It is difficult to achieve low temperature coefficient.
4. It is not possible to fabricate capacitors that exceed a value of 30pF. Thus, high value capacitors are to be
connected externally to the IC.

Integrated Circuit Classification

ICs can be classified on the basis of their chip size as given below:
Small scale integration (SSI)3 to 30 gates/chip.
Medium scale integration (MSI)30 to 300 gates/chip.
Large scale integration (LSI)300 to 3,000 gates/chip.
Very large scale integration (VLSI)more than 3,000 gates/chip.
ultra-scale integration (ULSI) - 100,000 and more

On the basis of applications ICs are of two types namely: Linear Integrated Circuits and Digital
Integrated Circuits.

Linear ICs have continuously variable output that depends on the input signal level. As the term
implies, the output signal level is a linear function of the input signal level. The operational
amplifier(op amp) is a common device in these applications.

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Digital ICs

operate at only a few defined levels or states, rather than over a continuous range of
signal amplitudes. These devices are used in computers, computer networks, modems, and frequency
counters. The fundamental building blocks of digital ICs are logic gates, which work with binary data,
that is, signals that have only two different states, called low (logic 0) and high (logic 1).

1.Monolithic Integrated Circuits

The word monolithic comes from the Greek words monos and lithos which means single and
stone. As the name suggests, monolithic ICs refer to a single stone or a single crystal. The single
crystal refers to a single chip of silicon as the semiconductor material, on top of which all the active
and passive components needed are interconnected. This is the best mode of manufacturing IC as
they can be made identical, and produces high reliability. The cost factor is also low and can be
manufactured in bulk in very less time.

2. Thin and Thick Film Integrated Circuit

Thick and thin film ICs are comparatively larger than monolithic ICs and smaller than discrete
circuits. They find their use in high power applications. Though it is a little large in size, these ICs
cannot be integrated with transistors and diodes. Such devices have to be externally connected on to
its corresponding pins. Passive components like resisters and capacitors can be integrated.

Thin Film Integrated Circuits

This IC is fabricated by depositing films of conducting material on the surface of a glass or ceramic
base. The resistors are fabricated by controlling the width and thickness of the films and by using
different materials selected for their resistivity. For capacitors, a film of insulating oxide is
sandwiched between two conducting films.

3. Hybrid or Multi-chip Integrated Circuits

As the name suggests, the circuit is fabricated by interconnecting a number of individual chips.
Hybrids ICs are mostly used for high power audio amplifier .The active components are diffused
transistors or diodes. The passive components may be group of diffused resistors or capacitors on a
single chip, Interconnection between the individual chips is made by wiring process or a metallized
pattern.

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1. Process steps in IC fabrication

Fabrication of Integrated Circuits
The basic semiconductor materials used in chips are crystalline silicon.
1.1.1Crystals
Solid materials are classified by the way the atoms are arranged within the solid. Materials in which
atoms are placed at random are called amorphous. Materials in which atoms are placed in a high
ordered structure are called crystalline. Poly-crystalline materials are materials with a high degree of
short-range order and no long-range order. These materials consist of small crystalline regions with
random orientation called grains, separated by grain boundaries.

The crystal can be thought of as consisting of two separate parts: the lattice and the basis. The lattice
is an ordered arrangement of points in space, while the basis consists of the simplest arrangement of
atoms which is repeated at every point in the lattice to build up the crystal structure. Fig illustrates the
basis and lattice in a crystal.

A crystal structure is composed of a unit cell, a set of atoms arranged in a particular way and is
periodically repeated in three dimensions on a lattice. In a cubic system, the lattice parameter is the
side length of a cube and angles between the edges are 90. The cubic lattices are an important subset
of these fourteen Bravais lattices since a large number of semiconductors are cubic. The three cubic
lattices are the simple cubic lattice, the body-centered cubic lattice and the face-centered cubic lattice
as shown in Fig.3.3. The positions of the atoms inside the unit cell are described by the set of atomic
positions (x, y, z) measured from a lattice point.

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In Simple Cubic (SC) structure, atoms lie on the corners of a cube as shown in Fig Very few
crystals exhibit this structure. In this structure each atom has six equidistant nearest
neighbors.
In Body centered Cubic (BCC) structure, structure atoms lie on the corners of a cube with an
additional atom at the centre of the cube as shown in Fig2 Its atomic positions are (000),
(100), (010), (001), (101), (110), (011), (111) and (
,
,
). Metals like Molybdenum,
tantalum (Ta) and tungsten (W), iron (Fe), Platinum (Pt), Sodium (Na) and Potassium (K)
have this structure. In this structure each atom has eight nearest neighbours. By placement of
an atom at the center of the cube, the body-centered cubic structure has twice the atom
density of the simple cubic lattice.
In Face centered Cubic (FCC) structure, atoms lie on the corners of a cube with additional
atoms at the centers of each cube face as shown in Fig. 3. Its atomic positions are (000),
(100), (010), (001), (101), (110), (011), (111), (

, 0), (

, 0,

), ( 0,

),

,
, 0), (
, 1,
, 0) and (1,
,
). In this structure each atom has twelve
equidistant nearest neighbours. Due to its low energy, FCC is extremely common and the
examples are lead (Pb), aluminum (Al), copper (Cu), and gold (Au).
The most common crystal structure among frequently used semiconductors such as silicon
and germanium is the diamond lattice, shown in Fig. Each atom in the diamond lattice has a
covalent bond with four adjacent atoms, which together form a tetrahedron.

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1.1.2 Why and how is silicon prevailing as a semiconductor?

The semiconductor materials are either silicon and germanium or compound such as gallium
arsenide. Silicon is the most used semiconductor for discrete devices and integrated circuits.
Si is less expensive due to the greater abundance of element. The major raw material for Si
wafer fabrication is sand and there is lots of sand available in nature.
Silicon has large band gap than Ge(1.1eV)
The structure of Germanium crystals will be destroyed at higher temperature. However,
Silicon crystals are not easily damaged by excess heat.
But there is a disadvantage for Silicon over Germanium. The potential Barrier of Silicon is
more compared to Germanium.
1.2 Crystal Growth
Integrated circuits are built on single-crystal silicon substrates that possess a high degree of
chemical purity, a high degree of crystalline perfection, and high structure uniformity. Such
silicon crystal preparation involves two major steps: (1) refinement of raw material (such as
quartzite, a type of sand) into electronic grade polycrystalline silicon (EGS) and (2) growing
of single-crystal silicon from this EGS either by Czochralski or Float Zone process.
A single-crystal Si or mono crystalline silicon or mono-Si is a base material of the electronic
industry. It consists of silicon in which the crystal lattice of the entire solid is continuous,
unbroken to its edges. The mono crystalline form is used in the semiconductor device
fabrication since grain boundaries would bring discontinuities and favour imperfections in the
microstructure of silicon, such as impurities and crystallographic defects, which can have
significant effects on the local electronic properties of the material.
1.2.1 Metallurgical Grade Silicon (MGS), MGS is poly crystalline material with a purity of
about 99%. It is made by the reduction of SiO 2 (quartz sand) with carbon (coal) in huge
furnaces lined with carbon, with big graphite electrodes inside (carrying huge amounts of
current) at about 2000C. The reaction is
C (s) + SiO2 (s)

Si (l) + CO (g)

The process starts by the production of Metallurgical Grade Silicon (MGS) by charging it
with quartzite and carbon in an arc furnace. Quartzite is a relatively pure form of sand (SiQ2),
and carbon is obtained in the form of coal, coke, and wood chips.
The overall reaction in the furnace is given below.

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SiC+Si02 = Si + SiO + CO
The MGS after being drawn off, has to be solidified at a purity of 98%. But this purity is not
enough for the manufacture of semiconductor devices. So, the MGS has to be pulverized
mechanically and reacted with anhydrous hydrogen chloride (HCI) to form trichlorosilane
(SiHCI3). The reaction is shown below.

Si + 3HCl = SiHCI3 + H2
With the help of a catalyst, the reaction takes place at a nominal temperature of 300C. The
reaction creates products like silicon tetrachloride (SiCl4) and the chlorides of impurities. At
this point the purification process occurs. The purification process has to be done by
fractional distillation method as the products trichlorosilane and unwanted chlorides are
liquids at room temperature.
The purified SiHCI3 is subjected to chemical vapor deposition (CVD). The chemical reaction
is a hydrogen reduction of SiHCl3.
The chemical reaction is shown below.
2SiHCl3 + 2H2 = 2Si + 6HCl
Electronic-Grade Silicon (EGS) is the raw material that is used for the preparation of single-crystal
silicon. EGS is actually a polycrystalline material of high purity. EGS has some major impurities like
boron, carbon, and residual donors. The pure EGS will have doping elements in the parts per billion
(ppb) range, and carbon less than 2 parts per million (ppm).

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The next step is to convert this poly-Si to a single crystal. There are two methods for crystal growth
used in this case; Czochralski or crucible grown crystals (CZ crystals) and Float zone (FZ) crystals.

1.2.3Czochralski Crystal Growth Process

The highly refined silicon (EGS) though free from impurities, is still polycrystalline The
Czochralski crystal growth process is often used for producing single-crystal silicon ingots.
The diagram is given below.

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Since monolithic ICs are usually fabricated on a substrate which is doped with impurity, the
poly-crystalline silicon with an appropriate amount of dopant is-put into a quartz crucible,
which is then placed inside a crystal growth furnace. The material is then heated to a
temperature that is slightly in excess of the silicon melting pint of 1420 degree Celsius. A
small single-crystal rod of silicon called a seed crystal is then dipped into the silicon melt.
The conduction of heat up the seed crystal will produce a reduction in the temperature of the
melt in contact with the seed crystal to slightly below the silicon melting point. The silicon
will therefore freeze onto the end of the seed crystal, and as the seed crystal is slowly pulled
up out of the melt it will pull up with it a solidified mass of silicon that will be a
crystallographic continuation of the seed crystal. Both the seed crystal and the crucible are
rotated but in opposite directions during the crystal pulling process in order to produce
crystalline ingots of circular cross section.
The liquid solid interface remains near to the surface of the melt if the temperature and
pulling rate are correctly chosen. Even a long single crystal silicon is pulled from it. The
diameter of the ingot is controlled by the pulling rate and the melt temperature, with ingot
diameters of about 100 to 150 mm (4 to 6 inches) being the most common. The ingot length
will generally be of the order of 3 meter, and several hours are required for the pulling of a
complete ingot. The crystal pulling is done in an inert-gas atmosphere (usually argon or
helium), and sometimes a vacuum is used. This is done to prevent oxidation
The pull-rate is closely related to the heat input and losses, crystal properties and dimensions.
The conditions for crystal pulling are therefore carefully controlled. For example, the melt
temperature is monitored with a thermocouple and feedback controller. The crystal growth
apparatus shown in the figure above consists of the following parts.

Furnace
Crystal pulling mechanism

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Ambient control facility

Control system circuitry

The furnace consists of a crucible, susceptor (crucible support) and rotational mechanism,
heating element and power supply, and a chamber. As the crucible contains the melt, it is the
most important component of the growth apparatus. The crucible material should be
chemically unreactive with molten silicon. Also, the material should have high melting point,
thermal stability, and hardness. The materials for crucible, which satisfy these properties, are
silicon nitride (Si3N4) and fused silica (SiO2). Fused silica; however, reacts with silicon,
releasing silicon and oxygen into the melt. In tins process the crucible undergoes erosion. The
susceptor, is used to support the silica crucible. It also provides for better thermal conditions.
Graphite is the material of choice because of its high-temperature properties. The graphite
should be pure to prevent contamination of the crystal from impurities that would be
volatilized from the graphite at the temperature involved. The susceptor rests on a pedestal
whose shaft is connected to a motor that provides rotation. The whole assembly can usually
be raised and lowered to keep the melt level equidistant from a fixed reference point, which is
needed for automatic diameter control.
The chamber housing the furnace must provide easy access to the furnace components to
facilitate maintenance and cleaning. The furnace structure must be airtight to prevent
contamination from the atmosphere, and have a specific design that does not allow any part
of the chamber to become so hot that its vapour pressure would be a factor in contaminating
the crystal. Hottest parts of the apparatus are water cooled. Insulation is usually provided
between the heater and the chamber wall.
The crystal-pulling mechanism consists of seed shaft or chain, rotation mechanism, and seed
chuck. The mechanism controls two parameters of die growth process: pull rate and crystal
rotation. Also, the pulling mechanism must have minimum vibration and great precision. The
seed holder and pulling mechanism must maintain precise orientation perpendicular to the
melt surface.
From the figure we can see that the crystal leaves the furnace through a purge tube, where
ambient gas, if present, is directed along the surface of the crystal to cool it. From the purge
tube, the crystal enters an upper chamber, which is usually separated from the furnace by an
isolation valve.
The ambient control for the crystal growth apparatus consists of gas source, flow control,
purge lube, and exhaust or vacuum system. The crystal growth must be conducted in an inert
gas or vacuum as staled earlier. This is necessary becauseThe hot graphite parts must be
protected from oxygen to prevent erosion and The gas around the process should not react
with the molten silicon. Growth in vacuum meets these requirements.
Growth in a gaseous atmosphere, generally used on large growers, must use an inert gas such
as helium or argon. The inert gas may be at atmospheric pressure or at reduced pressure.
The control system for crystal growing may consist of micro processing sensors, and outputs
and provides control of process parameters such as temperature, crystal diameter, pull rate
and rotation speed.

1.2.4 Ingot Trimming and Slicing

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As soon as the crystal ingot is obtained using the above processes, the extreme top and
bottom portions of the ingot are cut off and the ingot surface is grounded to produce a
constant and exact diameter. The normal diameter is usually 100,125, or 150 mm. A
crystallographic orientation flat is also ground along the length of the ingot. The ingot is then
sliced using a large-diameter stainless steel saw blade with industrial diamonds embedded
into the inner-diameter cutting edge. This will help in producing circular slices or wafers that
are about 600 to 1000 micro meters thick. The orientation flat serves as a useful reference
plane for various device processes.
1.2.5 Wafer Polishing and Cleaning

When the wafer is sliced, its surface will be heavily damaged. This can be made normal only
by polishing. The reasons for polishing are given below.

To remove the damaged silicon from the sawn surface.

To produce a highly planar or flat surface that will be required for the photo-lithographic
process especially when flue-line geometries are involved.

To improve the parallel.

The sliced wafer will have saw marks and is 0.6 to 1 mm thick. This is quite rough. Hence it
has to be lapped to produce a flat surface. The wafer, before polishing, may have a surface
damage in the order of 75 micro meters. Even through lapping, only 60 micro meters can be
polished and scraped. The remaining 15 micro meters has to be removed with the help of
etching process. The chemical etch consists of an acid mixture, including nitric acid to
oxidize the surface and hydrofluoric acid to dissolve the oxide.
The wafer is then made into a mirror like finish by polishing it. This polishing is carried out
by using aluminium abrasive powders of decreasing grit size (down to a final 1 micro meters
diameter). Even after the polishing, the wafer will still have a surface damage of around 2
micro meters deep. This is removed by an additional chemical etching stage, which can
sometimes be simultaneous with the final polishing stage.

In most cases, only one side of the wafer s carefully polished to produce a mirror like image.
The other side is given a normal lapping procedure to provide a somewhat flat surface with
agreeable parallelism. After the wafer polishing operations are completed, the wafers are
thoroughly cleaned, and dried, and they are now ready to be used for the various processing
steps described in the following sections. Before discussing these steps let us discuss some
processing considerations necessary to maintain the purity and perfection of the material.

1. Chemical Cleaning
The wafers are cleaned thoroughly as soon as the polishing is completed. Originally, the
silicon wafers are cleaned so as to remove all organic films, heavy metals, and particulars:.

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The commonly used cleaning agents are aqueous mixtures of NH4OH H2O2, HCI
H2O2, and,H2SO4 H2O2.

2. Gettering Treatments
The transition group elements which act as the metallic impurities are located at the
interstitial or substitutional lattice sites and act as generation-recombination centres for the
carriers. The precipitated forms of these impurities are usually silicides. These silicides are
known to be electrically conductive . In the case of VLSI circuits, these transition group
elements decrease their performance, especially in the case of dynamic random access
memories and narrow-base bipolar transistors, as they are sensitive to conductive impurity
precipitates.
Normally, a process called gettering treatment is carried out to remove the impurities.
Gettering is a process that removes, and harms the impurities or defects them from the
regions in a wafer where devices are fabricated. Pregettering refers to a gettering treatment
provided to silicon wafers that are used for IC processing. When the wafer with sinks are
developed for device processing, the impurities are absorbed with the help of pregettering
process. The common techniques that are used for gettering treatment are given below:

Common mechanical abrasion methods like lapping and sand blasting are carried out to
damage the back surface of the wafer.

A focused heat beam from a Q-pulsed, Nd-YAG laser is used to damage the wafer.
Dislocations are made in the wafer by rastering the laser beam along the wafers back surface.
Thus they become favorable trapping sites for fast-diffusing species.

Intrinsic gettering As told earlier, when an impurity oxygen precipitates, defects are
generated. The defects generated by oxygen precipitation are useful as trapping sites. As the
wafer is needed for device fabrication, high temperature cycle is employed to lower the
oxygen content near the surface of the wafer. Additional thermal cycles are added to promote
the formation of oxygen precipitates and defects in the interior of the wafer.

1.3 Diffusion of Dopant Impurities

The process of junction formation, that is transition from p to n type or vice versa, is typically
accomplished by the process of diffusing the appropriate dopant impurities in a high
temperature furnace. Impurity atoms are introduced onto the surface of a silicon wafer and
diffuse into the lattice because of their tendency to move from regions of high to low
concentration. Diffusion of impurity atoms into silicon crystal takes place only at elevated
temperature, typically 900 to 1100C.
Although these are rather high temperatures, they are still well below the melting point of
silicon, which is at 1420C. The rate at which the various impurities diffuse into silicon will
be of the order of 1 micro meter per hour at a temperature range stated above, and the
penetration depth that are involved in most diffusion processes will be of the order of 0.3 to
30 micro meter. At room temperature the diffusion process will be so extremely slow such
that the impurities can be considered to be essentially frozen in place.

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A method of p-n junction formation which was popular in the early days is the grown
junction technique. In this method the dopant is abruptly changed in the melt during the
process of crystal growth. A convenient technique for making p-n junction is the alloying of a
metal containing doping atoms on a semiconductor with the opposite type of dopant. This is
called the alloyed junction technique. The p-n junction using epitaxial growth is widely used
in ICs. An epitaxial grown junction is a sharp junction. In terms of volume of production, the
most common technique for forming p-n junctions is the impurity diffusion process. This
produces diffused junction. Along with diffusion process the use of selective masking to
control junction geometry, makes possible the wide variety of devices available in the form of
ICs. Selective diffusion is an important technique in its controllability, accuracy and
versatility.
1.3.2Nature of Impurity Diffusion

The diffusion of impurities into a solid is basically the same type of process as occurs when
excess carriers are created non-uniformly in a semiconductor which cause carrier gradient. In
each case, the diffusion is a result of random motion, and particles diffuse in the direction of
decreasing concentration gradient The random motion of impurity atoms in a solid is, of
course, rather limited unless the temperature is high. Thus diffusion of doping impurities into
silicon is accomplished at high temperature as stated above.
There are mainly two types of physical mechanisms by which the impurities can diffuse into
the lattice. They are
1. Substitutional Diffusion
At high temperature many atoms in the semiconductor move out of their lattice site, leaving
vacancies into which impurity atoms can move. The impurities, thus, diffuse by this type of
vacancy motion and occupy lattice position in the crystal after it is cooled. Thus,
substitutional diffusion takes place by replacing the silicon atoms of parent crystal by
impurity atom. In other words, impurity atoms diffuse by moving from a lattice site to a
neighbouring one by substituting for a silicon atom which has vacated a usually occupied site
as shown in the figure below.

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Substitutional diffusion mechanism is applicable to the most common diffusants, such as

boron, phosphorus, and arsenic. These dopants atoms are too big to fit into the interstices or
voids, so the only way they can enter the silicon crystal is to substitute for a Si atom.
In order for such an impurity atom to move to a neighbouring vacant site, it has to overcome
energy barrier which is due to the breaking of covalent bonds. The probability of its having
enough thermal energy to do this is proportional to an exponential function of temperature.
Also, whether it is able to move is also dependent on the availability of a vacant neighbouring
site and since an adjacent site is vacated by a Si atom due to thermal fluctuation of the lattice,
the probability of such an event is again an exponent of temperature.
2. Interstitial Diffusion
In such, diffusion type, the impurity atom does not replace the silicon atom, but instead
moves into the interstitial voids in the lattice. The main types of impurities diffusing by such
mechanism are Gold, copper, and nickel. Gold, particularly, is introduced into silicon to
reduce carrier life time and hence useful to increase speed at digital ICs.
Because of the large size of such metal atoms, they do not usually substitute in the silicon
lattice. To understand interstitial diffusion, let us consider a unit cell of the diamond lattice of
the silicon which has five interstitial voids. Each of the voids is big enough to contain an
impurity atom. An impurity atom located in one such void can move to a neighbouring void,
as shown in the figure below.

1.3.4 Ficks Laws of Diffusion

The diffusion rate of impurities into semiconductor lattice depends on the following
Mechanism of diffusion
Temperature
Physical properties of impurity

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The properties of the lattice environment

The concentration gradient of impurities
The geometry of the parent semiconductor

The behaviour of diffusion particles is governed by Ficks Law, which when solved for appropriate
boundary conditions, gives rise to various dopant distributions, called profiles which are
approximated during actual diffusion processes.
In 1855, Fick drew analogy between material transfer in a solution and heat transfer by conduction.
Fick assumed that in a dilute liquid or gaseous solution, in the absence of convection, the transfer of
solute atoms per unit area in a one-dimensional flow can be described by the following equation
F = -D N(x,t)/x = -F(x,t)/x
where F is the rate of transfer of solute atoms per unit area of the diffusion flux density (atoms/cm2sec). N is the concentration of solute atoms (number of atoms per unit volume/cm3), and x is the
direction of solute flow. (Here N is assumed to be a function of x and t only), t is the diffusion time,
and D is the diffusion constant (also referred to as diffusion coefficient or diffusivity) and has units of
cm2/sec.
The above equation is called Ficks First law of diffusion and states that the local rate of transfer
(local diffusion rate) of solute per unit area per unit time is proportional to the concentration gradient
of the solute, and defines the proportionality constant as the diffusion constant of the solute. The
negative sign appears due to opposite direction of matter flow and concentration gradient. That is, the
matter flows in the direction of decreasing solute concentration.
Ficks first law is applicable to dopant impurities used in silicon. In general the dopant impurities are
not charged, nor do they move in an electric field, so the usual drift mobility term (as applied to
electrons and holes under the influence of electric field) associated with the above equation can be
omitted. In this equation N is in general function of x, y, z and t.
The change of solute concentration with time must be the same as the local decrease of the diffusion
flux, in the absence of a source or a sink. This follows from the law of conservation of matter.
Therefore we can write down the following equation N(x,t)/t = -F(x,t)/x
Substituting the above equation to F. We get
N(x,t)/t = /x[D*N(x,t)/x]
When the concentration of the solute is low, the diffusion constant at a given temperature can be
considered as a constant.Thus the equation becomes,
N(x,t)/t = D[2N(x,t)/x2]
This is Ficks second law of distribution.

1.3.5 Diffusion Profiles

Depending on boundary equations the Ficks Law has two types of solutions. These solutions
provide two types of impurity distribution namely constant source distribution following

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complimentary error function (erfc) and limited source distribution following Gaussian
distribution function.
Constant Source (erfc) Distribution
In this impurity distribution, the impurity concentration at the semiconductor surface is
maintained at a constant level throughout the diffusion cycle. That is,
N (o,t) = NS = Constant
The solution to the diffusion equation which is applicable in this situation is most easily
obtained by first considering diffusion inside a material in which the initial concentration
changes in same plane as x=0, from NS to 0. Thus the equation can be written as
N (o,t) = NS = Constant and N(x,t) = 0
Shown below is a graph of the complementary error function for a range of values of its
argument. The change in concentration of impurities with time, as described by the equation
is also shown in the figure below. The surface concentration is always held at N S, falling to
some lower value away from the surface. If a sufficiently long time is allowed to elapse, it is
possible for the entire slice to acquire a dopant level of NS per m3.

If the diffused impurity type is different from the resistivity type of the substrate material, a
junction is formed at the points where the diffused impurity concentration is equal to the
background concentration already present in the substrate.
In the fabrication of monolithic ICs, constant source diffusion is commonly used for the
isolation and the emitter diffusion because it maintains a high surface concentration by a
continuous introduction of dopant.
There is an upper limit to the concentration of any impurity that can be accommodated at the
semiconductor wafer at some temperature. This maximum concentration which determines

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the surface concentration in constant source diffusion is called the solid solubility of the
impurity.

1.3.5 Limited Source Diffusion or Gaussian Diffusion

Here a predetermined amount of impurity is introduced into the crystal unlike constant source
diffusion. The diffusion takes place in two steps.
1. Predeposition Step In this step a fixed number of impurity atoms are deposited on the
silicon wafer during s short time.
2. Drive-in step Here the impurity source is turned off and the amounts of impurities
already deposited during the first step are allowed to diffuse into silicon water.
The essential difference between the two types of diffusion techniques is that the surface
concentration is held constant for error function diffusion. It decays with time for the
Gaussian type owing to a fixed available doping concentration Q. For the case of modelling
the depletion layer of a p-n junction, the erfc is modelled as a step junction and the Gaussian
as a linear graded junction. In the case of the erfc, the surface concentration is constant,
typically the maximum solute concentration at that temperature or solid solubility limit.

1.3.6 Parameters which affect diffusion profile

Solid Solubility In deciding which of the availability impurities can be used, it is

essential to know if the number of atoms per unit volume required by the specific
profile is less than the diffusant solid solubility.

Diffusion temperature Higher temperatures give more thermal energy and thus
higher velocities, to the diffused impurities. It is found that the diffusion coefficient
critically depends upon temperature. Therefore, the temperature profile of diffusion
furnace must have higher tolerance of temperature variation over its entire area.

Diffusion time Increases of diffusion time, t, or diffusion coefficient D have similar

effects on junction depth as can be seen from the equations of limited and constant
source diffusions. For Gaussian distribution, the net concentration will decrease due
to impurity compensation, and can approach zero with increasing diffusion tunes. For
constant source diffusion, the net Impurity concentration on the diffused side of the pn junction shows a steady increase with time.

Surface cleanliness and defects in silicon crystal The silicon surface must be
prevented against contaminants during diffusion which may interfere seriously with
the uniformity of the diffusion profile. The crystal defects such as dislocation or
stacking faults may produce localized impurity concentration. This results in the
degradation of junction characteristics. Hence silicon crystal must be highly perfect.

1.3.7 Basic Properties of the Diffusion Process

Following properties could be considered for designing and laying out ICs.

When calculating the total effective diffusion time for given impurity profile, one
must consider the effects of subsequent diffusion cycles.
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The erfc and Gaussian functions show that the diffusion profiles are functions of (x/
Dt). Hence, for a given surface and background concentration, the junction depth x1
and x2 associated with the two separate diffusions having different times and
temperature

Lateral Diffusion Effects The diffusions proceed sideways from a diffusion

window as well as downward. In both types of distribution function, the side diffusion
is about 75 to 80 per cent of the vertical diffusion.

1.3.8 Dopants and their Characteristics

The dopants selection affects IC characteristics. Boron and phosphorus are the basic dopants
of most ICs. Arsenic and antimony, which are highly soluble in silicon and diffuse slowly, are
used before epitaxial processing or as a second diffusion. Gold and silver diffuse rapidly.
They act as recombination centres and thus reduce carrier life time.
Boron is almost an exclusive choice as an acceptor impurity in silicon since other p-type
impurities have limitations as follows :
Gallium has relatively large diffusion coefficient in Si0 2, and the usual oxide windowopening technique for locating diffusion would be inoperative, Indium is of little interest
because of its high acceptor level of 0.16 eV, compared with 0.01 eV for boron, which
indicates that not all such acceptors would be ionized at room temperature to produce a hole.
Aluminium reacts strongly with any oxygen that is present in the silicon lattice.
The choice of a particular n-type dopant is not so limited as for p-type materials. The n-type
impurities, such as phosphorus, antimony and arsenic, can be used at different stages of IC
processing. The diffusion constant of phosphorus is much greater than for Sb and As, being
comparable to that for boron, which leads to economies resulting from shorter diffusion
times.
Dopants in VLSI Technology
The common dopants in VLSI circuit fabrication are boron, phosphorus. and arsenic.
Phosphorus is useful not only as an emitter and base dopant, but also far gettering fastdiffusing metallic contaminants, such as Cu and An, which cause junction leakage current
problems. Thus, phosphorus is indispensable in VLSI technology. However, n-p-n transistors
made with arsenic-diffused emitters have better low-current gain characteristics and better
control of narrow base widths than those made with phosphorus-diffused emitters. Therefore,
in V LSI, the use of phosphorus as an active dopant in small, shallow junctions and lowtemperature processing will be limited to its use as the base dopant of p-n-p device and as a
gettering agent. Arsenic is the most frequently used dopant for the source and drain regions in
n-channel MOSFETs.

Diffusion Systems
Impurities are diffused from their compound sources as mentioned above. The method
impurity delivery to wafer is determined by the nature of impurity source; Two-step diffusion
is widely technique. Using this technique, the impurity concentration and profiles can be

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carefully controlled. The type of impurity distribution (erfc or Gaussian) is determined by the
choice of operating conditions.
The two-step diffusion consists of a deposition step and a drive-in step. In the former step a
constant source diffusion is carried out for a short time, usually at a relatively low
temperatures, say, 1000C. In the latter step, the impurity supply is shutoff and the existing
dopant is allowed to diffuse into the body of the semiconductor, which is now held at a
different temperature, say 1200C, in an oxidizing atmosphere. The oxide layer which forms
on tire surface of the wafer during this step prevents further impurities from entering, or those
already deposited, from diffusing out. The final impurity profile is a function of diffusion
condition, such as temperature, time, and diffusion coefficients, for each step.

Diffusion Furnace

For the various types of diffusion (and also oxidation) processes a resistance-heated tube
furnace is usually used. A tube furnace has a long (about 2 to 3 meters) hollow opening into
which a quartz tube about 100,150 mm in diameter is placed as shown in the figure below.

The temperature of the furnace is kept about1000C. The temperature within the
quartz furnace tube can be controlled very accurately such that a temperature
within 1/2C of the set-point temperature can be maintained uniformly over a
hot zone about 1 m in length. This is achieved by three individually controlled
adjacent resistance elements. The silicon wafers to be processed are stacked up
vertically into slots in a quartz carrier or boat and inserted into the furnace
lube.

1.3.9 Diffusion Of p-Type Impurity

Boron is an almost exclusive choice as an acceptor impurity in silicon. It has a moderate
diffusion coefficient, typically of order I0-16 m2/sec at 1150C which is convenient for
precisely controlled diffusion. It has a solid solubility limit of around 5 x 1026 atoms/m3, so
that surface concentration can be widely varied, but most reproducible results are obtained

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when the concentration is approximately 1024/m3, which is typical for transistor base
diffusions.

Boron Diffusion using B2H6 (Diborane) Source

This is a gaseous source for boron. This can be directly introduced into the diffusion furnace.
A number of other gases are metered into the furnace. The principal gas flow in the furnace
will be nitrogen (N2) which acts as a relatively inert gas and is used as a carrier gas to be a
dilutent for the other more reactive gases. The N 2, carrier gas will generally make up some 90
to 99 percent of the total gas flow. A small amount of oxygen and very small amount of a
source of boron will make up the rest of the gas flow. This is shown in the figure below. The
following reactions will be occurring simultaneously at the surface of the silicon wafers:
Si + 02 = SiO2 (silica glass)
2B2H6 + 302 = B2O3 (boron glass) + 6H2
This process is the chemical vapour deposition (CVD) of a glassy layer on (lie silicon surface
which is a mixture of silica glass (Si02) and boron glass (B203) is called borosilica glass
(BSG). The BSG glassy layer, shown in the figure below, is a viscous liquid at the diffusion
temperatures and the boron atoms can move around relatively easily.

1.4 ION IMPLANTATION

Ion Implantation is an alternative to a deposition diffusion and is used to produce a shallow
surface region of dopant atoms deposited into a silicon wafer. This technology has made
significant roads into diffusion technology in several areas. In this process a beam of impurity
ions is accelerated to kinetic energies in the range of several tens of kV and is directed to the
surface of the silicon. As the impurity atoms enter the crystal, they give up their energy to the
lattice in collisions and finally come to rest at some average penetration depth, called the
projected range expressed in micro meters. Depending on the impurity and its implantation
energy, the range in a given semiconductor may vary from a few hundred angstroms to about
1micro meter. Typical distribution of impurity along the projected range is approximately
Gaussian. By performing several implantations at different energies, it is possible to
synthesize a desired impurity distribution, for example a uniformly doped region.

1.4.1Ion Implantation System

A typical ion-implantation system is shown in the figure below.

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A gas containing the desired impurity is ionized within the ion source. The ions
are generated and repelled from their source in a diverging beam that is
focussed before if passes through a mass separator that directs only the ions of
the desired species through a narrow aperture. A second lens focuses this
resolved beam which then passes through an accelerator that brings the ions to
their required energy before they strike the target and become implanted in the
exposed areas of the silicon wafers. The accelerating voltages may be from 20
kV to as much as 250 kV. In some ion implanters, the mass separation occurs
after the ions are accelerated to high energy. Because the ion beam is small,
means are provided for scanning it uniformly across the wafers. For this purpose
the focussed ion beam is scanned electrostatically over the surface of the wafer
in the target chamber.

1.4.2Properties of Ion Implantation

The depth of penetration of any particular type of ion will increase with increasing
accelerating voltage. The penetration depth will generally be in the range of 0.1 to 1.0 micro
meters.

1.5 Annealing after Implantation

After the ions have been implanted they are lodged principally in interstitial positions in the
silicon crystal structure, and the surface region into which the implantation has taken place
will be heavily damaged by the impact of the high-energy ions. The disarray of silicon atoms
in the surface region is often to the extent that this region is no longer crystalline in structure,
but rather amorphous. To restore this surface region back to a well-ordered crystalline state
and to allow the implanted ions to go into substitutional sites in the crystal structure, the
wafer must be subjected to an annealing process. The annealing process usually involves the
heating of the wafers to some elevated temperature often in the range of 1000C for a suitable
length of time such as 30 minutes.

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Laser beam and electron-beam annealing are also employed. In such annealing techniques
only the surface region of the wafer is heated and re-crystallized. An ion implantation process
is often followed by a conventional-type drive-in diffusion, in which case the annealing
process will occur as part of the drive-in diffusion.
Ion implantation is a substantially more expensive process than conventional deposition
diffusion, both in terms of the cost of the equipment and the throughput, it does, however,
offer following advantages.

1.4.4 Advantages of Ion Implantation

Ion implantation provides much more precise control over the density of dopants deposited
into the wafer, and hence the sheet resistance. This is possible because both the accelerating
voltage and the ion beam current are electrically controlled outside of the apparatus in which
the implants occur. Also since the beam current can be measured accurately during
implantation, a precise quantity of impurity can be introduced. Tins control over doping level,
along with the uniformity of the implant over the wafer surface, make ion implantation
attractive for the IC fabrication, since this causes significant improvement in the quality of an
IC.
Due to precise control over doping concentration, it is possible to have very low values of
dosage so that very large values of sheet resistance can be obtained. These high sheet
resistance values are useful for obtaining large-value resistors for ICs. Very low-dosage, lowenergy implantations are also used for the adjustment of the threshold voltage of MOSFETs
and other applications.
An obvious advantage of implantation is that it can be done at relatively low temperatures,
this means that doped layers can be implanted without disturbing previously diffused regions.
This means a lesser tendency for lateral spreading.

1.4.5 Importance of Ion Implantation for VLSI Technology

Ion implantation is a very popular process for VLSI because it provides more precise control
of dopants (as compared to diffusion). With the reduction of device sizes to the submicron
range, the electrical activation of ion-implanted species relies on a rapid thermal annealing
technique, resulting in as little movement of impurity atoms as possible. Thus, diffusion
process has become less important than methods for introducing impurity atoms into silicon
for forming very shallow junctions, an important feature of VLSI circuits. Ion, implantation
permits introduction of the dopant in silicon that is controllable, reproducible and free from
undesirable side effects. Over the past few years, ion implantation has been developed into a
very powerful tool for IC fabrication. Its attributes of controllability and reproducibility make
it a very versatile tool, able to follow the trends to finer-scale devices. Ion implantation
continues to find new applications in VLS technologies.

1.5 Utility of Thermal Oxidation

The function of a layer of silicon dioxide (SiO 2) on a chip is multipurpose. SiO2 plays an
important role in IC technology because no other semiconductor material has a native oxide
which is able to achieve all the properties of SiO 2. The role of SiO2 in IC fabrication is as
below :

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It acts as a diffusion mask permitting selective diffusions into silicon wafer through the
window etched into oxide.

It is used for surface passivation which is nothing but creating protective SiO2 layer
on the wafer surface. It protects the junction from moisture and other atmospheric
contaminants.

It serves as an insulator on the water surface. Its high relative dielectric constant,
which enables metal line to pass over the active silicon regions.

SiO2 acts as the active gate electrode in MOS device structure.

It is used to isolate one device from another.

It provides electrical isolation of multilevel metallization used in VLSI.

It is fortunate that silicon has an easily formed protective oxide, for otherwise we should have
to depend upon deposited insulators for surface protection. Since SiO2 produces a stable
layer, this has held back germanium IC technology.

1.5.2 Growth and Properties of Oxide Layers on Silicon

Silicon dioxide (silica) layer is formed on the surface of a silicon wafer by thermal oxidation
at high temperatures in a stream of oxygen.
Si+02 = SiO2 (solid)
The oxidation furnace used for this reaction is similar to the diffusion furnace. The thickness
of the oxide layer depends on the temperature of the furnace, the length of time that the
wafers are in it, and the flow rate of oxygen. The rate of oxidation can be significantly
increased by adding water vapour to the oxygen supply to the oxidizing furnace.
Si + 2H2O = SiO2 + 2H2
The time and temperature required to produce a particular layer thickness arc obtained from
empirically determined design curves, of the type shown in the figures given below
corresponding to dry- oxygen atmosphere and also corresponding to steam atmosphere.

1.5.3 Growth Rate of Silicon Oxide Layer

The initial growth of the oxide is limited by the rate at which the chemical reaction takes
place. After the first 100 to 300 A of oxide has been produced, the growth rate of the oxide
layer will be limited principally by the rate of diffusion of the oxidant (0 2 or H20) through the
oxide layer, as shown in the figures given below.
The rate of diffusion of O2 or H2O through the oxide layer will be inversely proportional to
the thickness of the layer, so that we will have that
dx/dt = C/x

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where x is the oxide thickness and C is a constant of proportionality. Rearranging this

equation gives
xdx = Cdt
Integrating this equation both sides yields, x2/2 = Ct
Solving for the oxide thickness x gives, x = 2Ct
We see that after an initial reaction-rate limited linear growth phase the oxide growth will
become diffusion-rate limited with the oxide thickness increasing as the square root of the
growth time. This is also shown in the figure below.

The rate of oxide growth using H 2O as the oxidant will be about four times faster than the
rate obtained with O2. This is due to the fact that the H 2O molecule is about one-half the size
of the O2 molecule, so that the rate of diffusion of H 2O through the SiO2 layer will be much
greater than the O2 diffusion rate.

1.5.3 Oxide Charges

The interlace between silicon and silicon dioxide contains a transition region. Various charges
are associated with the oxidised silicon, some of which are related to the transition region. A
charge at the interface can induce a charge of the opposite polarity in the underlying silicon,
thereby affecting the ideal characteristics of the MOS device. This results in both yield and
reliability problems. The figure below shows general types of charges.

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Oxide Charges

Interface-trapped charges

These charges at Si-SiO2 are thought to result from several sources including structural
defects related to the oxidation process, metallic impurities, or bond breaking processes. The
density of these charges is usually expressed in terms of unit area and energy in the silicon
band gap.

Fixed oxide charge

This charge (usually positive) is located in the oxide within approximately 30 A of the Si
SiO2 interface. Fixed oxide charge cannot be charged or discharged. From a processing point
of view, fixed oxide charge is determined by both temperature and ambient conditions.

Mobile ionic charge

This is attributed to alkali ions such as sodium, potassium, and lithium in the oxides as well
as to negative ions and heavy metals. The alkali ions are mobile even at room temperature
when electric fields are present.

Oxide trapped charge

This charge may be positive or negative, due to holes or electrons trapped in the bulk of the
oxide. This charge, associated with defects in the Si02, may result from ionizing radiation,
avalanche injection.

1.5.6 Effect of Impurities on the Oxidation Rate

The following impurities affect the oxidation rate
1. Water
2. Sodium

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3. Group III and V elements

4. Halogen
In addition damage to the silicon also affects oxidation rate. As wet oxidation occurs at a
substantially greater rate than dry oxygen, any unintentional moisture accelerates the dry
oxidation. High concentrations of sodium influence the oxidation rate by changing the bond
structure in the oxide, thereby enhancing the diffusion and concentration of the oxygen
molecules in the oxide.
During thermal oxidation process, an interface is formed, which separates the silicon from
silicon dioxide. As oxidation proceeds, this interface advances into the silicon. A doping
impurity, which is initially present in the silicon, will redistribute at the interface until its
chemical potential is the same on each side of the interface. This redistribution may result in
an abrupt change in impurity concentration across the interface. The ratio of the equilibrium
concentration of the impurity, that is, dopant in silicon to that in SiO 2 at the interface is called
the equilibrium segregation coefficient. The redistribution of the dopants at the interface
influences the oxidation behaviour. If the dopant segregates into the oxide and remains there
(such as Boron, in an oxidizing ambient), the bond structure in the silica weakens. This
weakened structure permits an increased incorporation and diffusivity of the oxidizing
species through the oxide thus enhancing the oxidation rate. Impurities that segregate into the
oxide but then diffuse rapidly through it (such as aluminium, gallium, and indium) have no
effect on the oxidation kinetics. Phosphorus impurity shows opposite effect to that of boron,
that is, impurity segregation occurs in silicon rather than Si0 2. The same is true for As and Sb
dopants.
Halogen (such as chlorine) impurities are intentionally introduced into the oxidation ambient
to improve both the oxide and the underlying silicon properties. Oxide improvement occurs
because there is a reduction in sodium ion contamination, increase in oxide breakdown
strength, and a reduction in interface trap density. Traps arc energy levels in the forbidden
energy gap which are associated with defects in the silicon.

1.5.6 Growth and Properties of Thin Oxides

MOS VLSI technology requires silicon dioxide thickness in the 50 to 500 A range in a
repeatable manner. This section is devoted to the growth and properties of such thin oxide.
This oxide must exhibit good electrical properties and provide long-term reliability. As an
example, the dielectric material for MOS devices can be thin thermal oxide. This dielectric is
an active component of the storage capacitor in dynamic RAMs, and its thickness determines
the amount of charge that can be stored.
The growth of thin oxide must be slow enough to obtain uniformity and reproducibility.
Various growth techniques for thin oxide are dry oxidation, dry oxidation with HCl,
sequential oxidations using different temperatures and ambients, wet oxidation, reduced
pressure techniques, and high pressure/low temperature oxidation. High pressure oxidation is
discussed later. The oxidation rate will, of course, be lower at lower temperatures and at
reduced pressures. Ultra-thin oxide (<50 A) have been produced using hot nitric acid, boiling
water, and air at room temperatures. Some recent developments in thin oxide growth
technique are
(i) Rapid thermal oxidation performed in a controlled oxygen ambient with heating provided
by tungsten-halogen lamps and

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(ii) Ultraviolet pulsed laser excitation in an oxygen environment.

The properties of thin oxide depend upon the growth technique employed. For example,
oxide density increases as the oxidation temperature is reduced. Additionally, HCl ambients
have typically been used to passivate ionic sodium, improve the breakdown voltage, and
getter impurities and defects in the silicon. This passivation effect begins to occur only in the
higher temperature range.
For thin oxides, there is an increase in leakage for a given voltage. In thin oxides the
dielectric breakdown may be field-dependent (breakdown in a ramping field) or timedependent (breakdown at a constant field). This breakdown is a failure mode for MOS ICs.
Thinner oxides are more prone to failure.

High Pressure Oxidation

There is a benefit of increase in the oxidation rate if the thermal oxidation is carried out at
pressures that are much above atmospheric pressure. The rate of diffusion of the oxidant
molecules through an oxide layer is proportional to the ambient pressure. For example, at a
pressure of 10 atm the diffusion rate will be increased by a factor of 10 and the corresponding
oxidation time can be reduced by nearly the same factor. Alternatively, the oxidation can be
done for the same length of time, but the temperature required will be substantially lower.
Thus, one principal benefit of high-pressure oxidation processing is lower-temperature
processing. The lower processing temperature reduces the formation of crystalline defects
and produces less effect on previous diffusions and other processes. The shorter oxidation
time is also advantageous in increasing the system throughput. The major limitation of this
process is the high initial cost of the system.

Oxide Masking
The oxide layer is used to mask an underlying silicon surface against a diffusion (or ion
implantation) process. The oxide layer is patterned by the phtolithographic process to produce
regions where there are opening or windows where the oxide has been removal to expose
the underlying silicon. Then these exposed silicon regions are subjected to the diffusion (or
implantation) of dopants, whereas the unexposed silicon regions will be protected. The
pattern of dopant that will be deposited into the silicon will thus be a replication of the pattern
of opening in the oxide layer. The replication is a key factor in the production of tiny
electronic components.
The thickness of oxide needed for diffusion masking is a function of the type of diffusant and
the diffusion time and temperature conditions. In particular, an oxide thickness of some 5000
A will he vufftcieni to mask against almost all diffusions. This oxide thickness will also be
sufficient to block almost alt but the highest-energy ion implantation.

Oxide Passivation
The other function of Si02 in IC fabrication is the surface passivation. This is nothing but
creating protective Si02 layer on the wafer surface. The figure below shows a cross-sectional
view of a p-n junction produced by diffusion through an oxide window. There are lateral
diffusion effects, that is, the diffusion not only proceeds in the downward direction, but also
sideways as well, since diffusion is an isotropic process. The distance from the edge of the
oxide window to the junction in the lateral direction underneath die oxide is indicated as yj.
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1.6 Photolithography
When a sample of crystalline silicon is covered with silicon dioxide, the oxide-layer acts as a
barrier to the diffusion of impurities, so that impurities separated from the surface of the
silicon by a layer of oxide do not diffuse into the silicon during high-temperature processing.
A p-n junction can thus be formed in a selected location on the sample by first covering the
sample with a layer of oxide [oxidation step] removing the oxide in the selected region, and
then performing a predeposition and diffusion step. The selective removal of the oxide in the
desired area is performed with photolithography. Thus, the areas over which diffusions are
effective are defined by the oxide layer with windows cut in it, through which diffusion can
take place. The windows are produced by the photolithographic process. This process is the
means by which microscopically small electronic circuits and devices can be produced on
silicon wafers resulting in as many as 10000 transistors on a 1 cm x 1 cm chip.
In fact photolithography or optical lithography is a kind of lithography. The lithography
technique was first used in the late 18th century by people interested in art. A lithograph is a
less expensive picture made from a flat, specially prepared stone or metal plate and the
lithography is art of making lithographs. Therefore, lithography for IC manufacturing is
analogous to the lithography of the art world. In this process the exposing radiation, such as
ultraviolet (UV) light in case of photolithography, is transmitted through the clear parts of the
mask. The circuit pattern of opaque chromium blocks some of die radiation. This type of
chromium/glass mask is used with UV light. Other types of exposing radiations are electrons,
X-rays, or ions. Thus for IC manufacturing we have following types of lithography.
Photolithography has been explained in this post. To know about the other types of
lithographic process, click on the link below.
1. Photolithography
2. Electron-beam Lithography
3. X-ray lithography
4. Ion-beam lithography
In IC fabrication a number of masks are employed. Except for the first mask, every mask
must be aligned to the pattern produced by the previous mask. This is done using mask

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aligner. The mask aligner may be contact type or proximity type or projection type.
Accordingly we have three types of printing. They are

Contact printing

Proximity printing

Projection printing

1.6.1 Photolithographic Process Steps

1. Photoresist Application (Spinning)
A drop of light-sensitive liquid called photoresist is applied to the centre of the oxidized
silicon wafer that is held down by a vacuum chuck. The wafer is then accelerated rapidly to a
rotational velocity in the range 3000 to 7000 RPM for some 30 to 60 seconds. This action
spreads the solution in a thin, nearly uniform coat and spins off the excess liquid. The
thickness of the coat so obtained is in the range 5000 to 10000 A, as shown in the figure
below. The thickness of the photoresist layer will be approximately inversely proportional to
the square root of the rotational velocity.
Sometimes prior to the application of the photoresist the silicon wafers are given a bake-out
at a temperature Of at least 100C to drive off moisture from the wafer surfaces so as to
obtain better adhesion of the photoresist. Typical photoresist used is Kodak Thin Film Resist
(KTFR).
2. Prebake
The silicon wafers coated with photoresist are now put into an oven at about 80C for about
30 to 60 minutes to drive off solvents in the photoresist and to harden it into a semisolid film.
3. Alignment and Exposure
The coated wafer, as above, is now placed in an apparatus called a mask aligner in very close
proximity (about 25 to 125 micro meters) to a photomask. The relative positions of the wafer
and the photomasks are adjusted such that the photomask is correctly lined up with reference
marks or a pre-existing pattern on the wafer.
The photomask is a glass plate, typically about 125 mm square and about 2 mm thick. The
photomask has a photographic emulsion or thin film metal (generally chromium) pattern on
one side. The pattern has clear and opaque areas. The alignment of the photomask to the
wafer is often required to be accurate to within less than 1 micro meter, and in some cases to
within 0.5 micro meters. After proper alignment has been achieved, the wafer is brought into
direct contact with the photomask. Photomask making will be described separately.
A highly collimated ultraviolet (UV) light is then turned on and the areas of the silicon wafer
that are not covered by the opaque areas of the photomask are exposed to ultraviolet
radiation, as shown in the figure. The exposure time is generally in the range 3 to 10 seconds
and is carefully controlled such that the total UV radiation dosage in watt-seconds or joules is
of the required amount.
4. Development
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Two types of photoresist exist- negative photoresist and positive photoresist. In the present
description negative photoresist is used in which the areas of the photoresist that are exposed
the ultraviolet radiation become polymerized. The polymerization process increases the
length of the organic chain molecules that make up the photoresist. This makes the resist
tougher and makes it essentially insoluble in the developer solution. The resisting photoresist
pattern after the development process will therefore be a replication of the photomask pattern,
with the clear areas on the photomask corresponding to the areas where the photoresist
remains on the wafers, as shown in the figure below.
An opposite type of process occurs with positive photoresist. Exposure to UV radiation
results in depolymerization of the photoresist. This makes these exposed areas of the
photoresist readily soluble in the developer solution, whereas the unexposed areas are
essentially insoluble. The developer solution will thus remove the exposed or depolymerized
regions of the photoresist, whereas the unexposed areas will remain on the wafer. Thus again
there is a replication of the photomask pattern, but this time the clear areas of the photomask
produce the areas on the wafer from which the photoresist has been removed.
5. Postbake
After development and rinsing the wafers are usually given a postbake in an oven at a
temperature of about 150C for about 30 to 60 minutes to toughen further the remaining resist
on the wafer. This is to make it adhere better to the wafer and to make it more resistant to the
hydrofluoric acid [HF] solution used for etching of the silicon dioxide.
6. Oxide Etching
The remaining resist is hardened and acts as a convenient mask through which the oxide layer
can be etched away to expose areas of semiconductor underneath. These exposed areas are
ready for impurity diffusion.
For etching of oxide, the wafers are immersed in or sprayed with a hydrofluoric [HF] acid
solution. This solution is usually a diluted solution of typically 10: 1, H2O : HF, or more often
a 10 : 1 NH4F [ammonium fluoride]: HF solution. The HF solutions will etch the SiO 2 but
will not attack the underlying silicon, nor will it attack the photoresist layer to any
appreciable extent. The wafers are exposed to the etching solution ion enough to remove the
SiO2 completely in the areas of the wafer that are not covered by the photoresist as shown in
the figure.
The duration of oxide etching should be carefully controlled so that all of the oxide present
only in the photoresist window is removed. If etching time is excessively prolonged, it will
result in more undercutting underneath the photoresist and widening of the oxide opening
beyond what is desired.
The above oxide etching process is termed wet etching process since the chemical reagents
used are in liquid form. A newer process for oxide etching is a dry etching process called
plasma etching. Another dry etching process is ion milling.
7. Photoresist Stripping
Following oxide etching, the remaining resist is finally removed or stripped off with a
mixture of sulphuric acid and hydrogen peroxide and with the help of abrasion process.

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Finally a step of washing and drying completes the required window in the oxide layer. The
figure below shows the silicon wafer ready for next diffusion.

1.6.2 Photoresists
One of the major factors in providing increasingly complex devices has been improvement in
photolithographic art. A large part of this improvement has been due to high quality
photoresist, materials as improved techniques of coating, baking, exposing and developing
photoresists.
The principal constituents of a photoresist solution are a polymer, a sensitizer and a suitable
solvent system Polymers have properties of excellent film forming and coating. Polymers
generally used are polyvinyl cinnamate, partially cyclized isoprene family and other types are
phenol formaldehyde.
When photoresist is exposed to light, sensitizer absorbs energy and initiates chemical changes
in the resist. The sensitizers are chromophoric organic molecules. They greatly enhance cross
linking of the photoresist. Cross linking of polymer or long chain formation of considerable
number of monomers makes high molecular weight molecules on exposure to light radiation,
termed as photo-polymerization. Typical sensitizers are carbonyl compounds, Benzoin,
Benzoyl peroxide, Benzoyl disulphide, nitrogen compounds and halogen compounds.
The solvents used to keep the polymers in solution are mixture of organic liquids. They
include aliphetic esters such as butyl acetate and cellosolve acetate, aromatic hydrocarbons
like xylene and Ethylbenzene, chlorinated hydrocarbons like chlorobenzene and methylene
chloride and ketones such as cyclohexanone. The same solvents are used as thinners and
developers.

Characteristics of Good Photoresist

To achieve faithful registration of the mask geometry over the substrate surface, the resist
should satisfy following conditions.

Uniform film formation

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Good adhesion to the substrate

Resolution

Resistance to wet and dry etch processes

Types of Photoresist
Polymers film is either photosensitive or capable or reacting with the pholysis product of
additional compound so that the solubility increases or decreases greatly by exposure to UV
(ultra-violet) radiation. According to the changes that take place, photoresists are termed
negative or positive. Materials which are rendered less soluble in a developer solution by
illumination^ yield a negative pattern of the mask and are called negative photoresists.
Conversely, positive photoresists become more soluble when subjected to light and therefore
yield a positive image of the mask.
Negative Photoresist
Kodak negative photoresist contain polyvinyl cinnametes. KPR is being used in printing
circuit boards. KTFR is widely used in fabrication of ICs. It provides good adhesion to
silicon dioxide and metal surfaces. It gives well etch results to different etchant solutions. For
finer resolution, thinner coating of KTFR is used. To achieve controlled and uniform
thickness, the viscosity of resist is suitably lowered using thinners.
Another negative photoresist is Kodak Microneg 747 which provides high scan speeds at
high aperature giving high throughput and resolution.
Positive Photoresist
Positive Photoresists have solved the problem of resolution and substrate protection. Photo
resists can be used at a coating thickness of 1 micro meter that eliminates holes and
minimises defects from dust.
Positive photoresist is inherently of low solubility (polymerized) material. The base polymer
is active by itself. A sensitizer, when absorbs light, makes the base resist soluble in an alkali
developer. Positive photoresists are Novolac resins. Typical solvents are cellosolve acetate,
butyl acetate, xylene and toluene.
Resist requirements for VLSI
For fine line geometries in VLSI circuits, the resist requirements become more stringent. The
resist properties should meet the required demand of high resolution. Here the resist should
exhibit

High sensitivity for partial exposure tool chosen

Dry developing, dry compatibility

Vertical profile control

Photomask Fabrication

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Photolithography is used to produce windows in the oxide layer of the silicon wafer, through
which diffusion can take place. For this purpose photomask is required. In this section we
shall discuss various techniques of mask fabrication. The pattern appearing on the mask is
required to be transferred to the wafer. For this purpose various exposure techniques are
employed. We will also discuss these techniques.
Mask Making
IC fabrication is done by the batch processing, where many copies of the same circuit are
fabricated on a single wafer and many wafers are fabricated at the same time. The number of
wafers processed at one time is called the lot size and many vary between 20 to 200 wafers.
Since each IC chip is square and the wafer is circular, the number of chips per wafer is the
number of complete squares of a given size that can fit inside a circle.
The pattern for the mask is designed from the circuit layout. Many years ago, bread boarding
of the circuit was typical. In this, the circuit was actually built and tested with discrete
components before its integration. At present, however, when LSI and VLSI circuits contain
from a thousand to several hundred thousand components, and switching speeds are of such
high order where propagation delay time between devices is significant, bread boarding is
obviously not practical. Present-day mask layout is done with the help of computer.
The photographic mask determines the location of all windows in the oxide layer, and hence
areas over which a particular diffusion step is effective. Each complete mask consists of a
photographic plate on which each window is represented by an opaque are, the remainder
being transparent. Each complete mask will not only include all the windows for the
production of one stage of a particular IC, but in addition, all similar areas for all such
circuits on the entire silicon as shown in the figure below.
It will be obvious that a different mask is required for each stage in the production of an array
of ICs on a wafer. There is also a vital requirement for precise registration between one mask
and the other in series, to ensure that there is no overlap between components, and that each
section of a particular transistor is formed in precisely the correct location.
To make a mask for one of the production stages, a master is first prepared which is an exact
replica of that portion of the final mask associated with one individual integrated circuit, but
which is 250x [say] enlargement of the final size of IC. The figure below shows a possible
master for the production of a mask to define a particular layer of diffusion for a hypothetical
circuit. Art work at enlarge size avoids large tolerance errors. Large size also permits the art
work to be dealt easily by human operator. In the design of the art work, the locations of all
components that is, resistor, capacitor, diode, transistor and so on, are determined on the
surface of the chip. Therefore, six or more layout drawings are required. Each drawing shows
the position of Windows that are required for a particular step of the fabrication. For complex
circuit the layout is generated by the use of computer-aided graphics.

1.6.3 Various Printing Techniques

Photolithography comprises the formation of images with visible or U V radiation in a
photoresist using contact proximity, or projection printing. Here we will discuss about these
printing techniques.
1. Contact Printing

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In this printing technique, the photomask is pressed against the resist coated wafer with a
pressure typically in the range of 0.05 atm to 0.3 atm and exposure by light of wavelength
near 400 micro meters. A resolution of less than 1 micro meter linewidth is possible, but it
may vary across the wafer because of spatial non-uniformity of the contact. To provide better
contact over the whole wafer, a thin (0.2 mm) flexible mask has been used.
2. Proximity Printing
In proximity or shadow printing, there exists a gap between mask and wafer in the range of
20 to 50 micro meters. This has the advantage of longer mask life because there is no contact
between the mask and the wafer. In the proximity printing, the mask and wafer are both
placed in an equipment called a projection aligner. Looking through a microscope, an
operator brings the mask into close proximity [say 10 to 20 micro meters] to the wafer and
properly aligns the wafer and mask using alignment mark on the mask and the wafer. UV
light is then projected through the mask on to the entire resist coated wafer at one time. This
mask that is used is a full wafer x 1 mask. The resolution of this process is a function of the
wavelength of the light source and the distance between the mask and the wafer. Typically,
the resolution of proximity printing is 2 to 4 micro meter and is therefore not suitable for a
process requiring less than a 2 um minimum line width.
3. Projection Printing
In this case the image is actually projected with the help of a system of lenses, onto the wafer.
The mask can be used a large number of times, substantially reducing the mask cost per
wafer. Theoretically a mask can be used an unlimited-number of times, but actual usage is
limited to about 100,000 times because the mask must be cleaned due to dust accumulation,
and it is scratched at each cleaning. This is costliest of the conventional systems, however
mask life is good, and resolution obtained is higher than proximity printing together with
large separation between mask and wafer.

Automated Mask Generation

As discussed above, layouts of electronic circuit are drawn on large mylar sheets. They can
also be drawn on a CRT screen by which layouts are stored digitally in a magnetic tape (or
disk). In this case we need to prepare many layouts since each layout represents a pattern on
each mask to be used during fabrication. Since the layouts are to be stored digitally, it is
required to convert the layouts drawn on mylar sheets into digital data. This is performed by a
digitizer with the aid of a computer. Then different portions of each layout are displayed on a
CRT one by one and inspected for further mistakes. After all the corrections have been made,
a reticle, which is a small photographic plate of the layout image, is prepared from each
layout stored on the magnetic tape.
Depending upon the type of equipment used, the mask to be fabricated contains one IC chip
pattern which is repeated as many times as there are on the wafer. Alternatively, the mask
consists of only magnified chip pattern as shown in the figure below.

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Automated Mask generation

The two most common approaches to automated mask making or generation are

Using optical projection and

Using electron beam

A pattern generator (PG) tape is used as the Input to both approaches. The PG tape, contains
the digitized data necessary to control the light source or electron beam that is used to write a
pattern on a photosensitive glass plate. An Ax10 pattern for a single chip (called a x10 reticle)
is first produced. This reticle is then photo enlarged by a factor of 15, yielding x 150
blowback, which is used for visual checking. A x 1 mask of the type shown in the figure is
then produced from the x 10 reticle by optical reduction and projection onto a second
photosensitive plate. The same pattern is stepped and repeated on this plate as many as there
are chips on the wafer. This step and repat operation is performed by photo repeater. The
glass plate is then developed yielding a x 1 mask which is called a master mask and looks like
a tile floor where each rectangular tile has the same layout image of the chp. During the step
and repeat process the position and angle of the reticle are precisely aligned with the help of
two fiducial marks incorporated in the PG files of all layouts in the same relative position
with respect to the entire chip. The master mask plate is then placed in close proximity to the
wafer and optically projected on to a resist-coated wafer during the lithographic process.
The figure below shows the second approach. This employs electron-beam mask generation
equipment winch generates the mask plate in one step. The layout data are converted into a
hit map of 1s and 0s on a raster image. The electron beam sweeps the row in a repeating S
pattern, blanking or unblanking the beam according to the input bit value, 0 or 1. In the
figure, the x10 reticle is optically reduced and stepped directly onto the wafer. This is referred
to as direct-step on wafer (DSW) lithography.

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Automated Mask Generation Process

The main advantage of electron-beam pattern generator is speed in the case of complex chips.
A large, dense chip can require 20 hours or more of optical pattern generator time, but only
two hours or less of electron-beam pattern generator time.
1.7 Chemical Vapor Deposition (CVD) is the deposition of a solid material onto a heated
substrate through decomposition or chemical reaction of compounds contained m the gas
passing over the substrate. Many materials such as, silicon nitride, silicon dioxide, noncrystalline silicon, and single crystal silicon, can be deposited through CVD method.
A special method in CVD, called Epitaxy or Epitaxial Layer Deposition or Vapor-Phase
Epitaxy (VPE), has only a single-crystal form as the deposited layer . This process is usually
carried out for certain combinations of substrate and layer materials and under special
deposition conditions.
In CVD process, a reaction chamber is introduced in which the materials to be deposited are
passed through. These materials should be in the gaseous or vapor phase and react on or near
the surface of the substrates, which are at some elevated temperature. This produces a
chemical reaction and forms atoms or molecules that are to be deposited on entire substrate
surface. A number of different materials can be deposited by the CVD process. These are
listed below:

Silicon epitaxial layer on a single-crystal silicon substrate (homoepitaxy or commonly

referred to as epitaxy).

Silicon epitaxial layer deposition on a sapphire (Heteroepitaxy).

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Silicon dioxide deposition.

Silicon nitride deposition.

Each one of these depositions will be described in this post.

1.7.1 Epitaxial Deposition

Epitaxy is referred to as an arrangement of atoms in a crystal form upon a crystal substrate, so
that the resulting added layer structure is an exact extension of the substrate crystal structure.
In other words, deposited atoms arrange themselves along existing planes of the crystalline
substrate material. This will cause the deposited atoms to bond to the parent atoms to form an
unbroken chain of the crystal structure. The structure of the grown epitaxial layer is thus a
continuation of that single-crystal substrate.

1.7.2 Epitaxy and Crystal Growing

There is no difference between epitaxy and crystal growing technique. But where, in epitaxy
a thin film of single crystal silicon is grown from a vapor phase upon a existing single crystal
of the same material, in crystal growing, a single crystal is grown from the liquid phase, in
contrast to the growth technique in epitaxy. Furthermore, epitaxial process involves no
portion of the system at a temperature anywhere near the melting point of the material.
Epitaxial deposition was the initial form in which CVD was used in IC fabrication, and it
continues to play a very important role

Uses of Epitaxy
Epitaxy was first developed so as to improve the performance of discrete bipolar transistors.
The breakdown voltage of the collector was determined by fabricating the devices in bulk
wafers using the wafers resistivity to determine the breakdown voltage of the collector.
However, high breakdown voltages need high-resistivity material. This requirement, coupled
with the thickness of the wafer, results in excessive collector resistance that limits highfrequency response and increases power dissipation. Epitaxial growth of a high resistivity
layer on a low-resistivity substrate solves this problem.
Epitaxy is also used to improve the performance of dynamic random-access memory devices
and CMOS ICs.
Epitaxial wafers have two basic advantages over bulk wafers:

Epitaxial layers make it possible to control the doping profile in a device structure that
available with diffusion or ion implantation.

The physical properties of lire epi-layer differ from those of bulk material. For
example, epi -layers are generally oxygen and carbon free, a situation not obtained
with the crystal grown silicon.

The most common example of epitaxy is the deposition of silicon epitaxial layer on a singlecrystal silicon substrate. In this case the substrate and layer materials are the same, and this is

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called homoepitaxy. Here the epi-layer becomes a crystallographic continuation of the

substrate.
The CVD of single-crystal silicon is usually performed in a reader consisting of a quartz
reaction chamber into which a susceptor is placed. The susceptor provides physical support
for the substrate wafers and provides a more uniform thermal environment. Deposition occurs
at a high temperature at which several chemical reactions take place when process gases flow
into the chamber.

Epitaxial Growth of Silicon

There are a number of different chemical reactions that can be used for the deposition of
epitaxial layers. Four silicon sources have been used for growing epitaxial silicon. These are
silicon tetrachloride [SiCl4], dichlorosilane [SiH2Cl2], trichlorosilane [SiHCl3] and silane
[SiH4].
Silicon tetrachloride has been the most studied and has seen the widest industrial use. The
overall reaction can be classed as a hydrogen reduction of a gas.
SiCl4 [gas] + 2H2 [gas] = Si [solid] + 4HCl [gas]
For understanding the above reaction, we should determine for the Si CI H system the
equilibrium constant for each possible reaction and the partial pressure of each gaseous
species at the temperature of interest. Equilibrium calculations reveal fourteen species to be
in equilibrium with solid silicon. In practice many of the species can be ignored because their
partial pressures are less than 10-6 atm.

Doping and Autodoping

The considerations applied to epitaxial growth process are also applicable to doping. Typical
hydrides of the impurity atoms are used as the source of dopant. Typical reaction for arsenic
dopant is as below

2AsH3(gas) = 2As[solid] + 3H2 [gas] = 2As (solid) = 2As+ [solid] + 2e

The hydride AsH3 does not decompose spontaneously as it is relatively stable because of the
large volume of hydrogen present in the reaction. Interactions also take place between the
doping process and the growth process. In addition to intentional dopants incorporated into
the layer, unintentional dopants are introduced from the substrate. This effect is termed
autodoping. Autodoping limits the minimum layer thickness that can be grown with
controlled doping as well as the minimum doping level.

1.7.2 Epitaxial Reactors

The epitaxial layer deposition takes place in a chamber called an epitaxial reactor. There are
three basic types of reactors.

Horizontal Reactor

Vertical Reactor and

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Cylindrical Reactor

The three reactors have been explained in the figure below.

Horizontal reactors offer lowest cost construction, however, controlling the deposition
process over the entire susceptor length is a problem. Vertical reactors are capable of very
uniform deposition but suffer from mechanical complexity. Cylindrical reactors are also
capable of uniform deposition due to employment of radiant heating, but arc not suited for
extended operation at temperature above 1200C.
Epitaxial Growth Process

A typical epitaxial growth process includes several steps as follows.

A hydrogen carrier gas is used to purge the reactor of air.

The reactor is then heated to a temperature.

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After thermal equilibrium is established in the chamber, anhydrous HCl gas

is fed into the reactor. The HCl gas reacts with the silicon at the surface of
wafers in reaction that is reverse of that given for [SiCl 4+H2].This reverse
reaction results in vapor-phase-etching of the silicon surface and usually
occurs at a temperature between 1150 and 1200C for 3 min.

The temperature is then reduced to the growth temperature with time

allowed for stabilizing the temperature and flushing the HCI gas. For [SiCI 2
+H2] reaction, the graphite boat is heated to a temperature in the range
1150 1250 degree Celsius. The vapor of SiCl 4 and hydrogen as a carrier
gas arc introduced into the lube for producing epitaxial layer.

Once growth is complete, the dopant and silicon flows are eliminated and
the temperature reduced, usually by shutting of the power.

As the reactor cools toward ambient temperature, the hydrogen flow is

replaced by a nitrogen flow so that the reactor may be opened safely.

Depending on wafer diameter and reactor type, capacities range from 10 to 15 wafer per
batch. Process cycle times are about 1 hour. The vapor-phase etching (VPE) described above
is necessary to remove a small amount of Si and other contaminants from the wafer surfaces
to ensure that a clear freshly etched silicon surface will be available for epitaxial layer
deposition. When the concentration of SiCI4, is high, etching can still occur even when
hydrogen chloride is not present due to a competing interaction.
SiC4 + Si = 2SiCl2
Thus, the growth rate of epitaxial silicon, which will be negative if etching occurs. It is
critically dependent on the concentration of silicon chloride as well as the temperature. In
typical environmental conditions for growth, at a rate of around 1 micro meter per min,
produces layers which are well within the region for single-crystal epitaxy
When reduction of SiC4 lakes place, the reaction gives rise to free silicon atoms. Atoms from
the gas phase skid about on the surface of the growing epitaxial film until they find correct
position in the lattice before becoming fastened into the growing structure.
For producing doped p-type or n-type epitaxial layers, a number of gases can be metered into
the reactor tube, including some very small amounts of doping gases, such as B2H6
[diborane] for boron doping and PH3 [phosphine] for phosphorus doping of the epitaxial
layer. During the epitaxial layer deposition the dopant gas molecules react and become
decomposed and the dopant atoms thus produced become incorporated into the epitaxial
layer. Doping of the epitaxial layer is also achieved by adding controlled amounts of-the
appropriate impurity in liquid form, for example, phosphorus trichloride or arsenic
trichloride, to the silicon chloride.
The main advantages and disadvantages of SiCl4 as a source of Si epitaxy are as follows:
Advantages

SiCl4 is non-toxic, inexpensive and easy to purify.

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The reaction making silicon from SiCl4 takes place only at surface and not
on the boat or reaction chamber walls.

Disadvantages

The growth process is accompanied by the diffusion phenomenon which

causes an exchange of impurities between silicon wafer and growing Film.
This prevents the fabrication of an ideal step junction.

SiCl4 process requires higher temperature than silane process and also
has slower growth rate.

Problems in Growing Impurity Doped Epitaxial Layers

Epitaxial layer deposition takes place at temperatures in the range 950 to 1250C. Due to this,
diffusion of impurities may occur across the epitaxial layer or substrate interface due to the
deposition and high temperature processing steps. This will cause a blurring of the impurity
profile in the region of this interface. But the main problem will be the deposition of a very
thin and very lightly doped epitaxial layer on a very heavily doped substrate. The outdiffusion
of impurities from the heavily doped substrate into the lightly doped epitaxial layer will blot
out the sharp n/n+ transition that would otherwise be present at the layer-substrate interface.
The influx of donor atoms from the substrate will reduce the effective thickness of the lightly
doped epitaxial layer by 1 or 2 micro meter. To minimize this problem of outdiffusion from
heavily doped n+ substrate, slow donor diffusants such as antimony and arsenic are often used
for the doping of substrate in preference to phosphorus.
Molecular Beam Epitaxy (MBE)

Molecular beam epitaxy differs from vapor-phase epitaxy (VPE) in that it employs
evaporation t [instead of deposition] method. Thus it is a non-CVD epitaxial process.
Although the method has been known since the early 1960s, it has recently been considered a
suitable technology for silicon device fabrication. In the MBE process the silicon along with
dopants is evaporated. The evaporated species are transported at a relatively high velocity in a
vacuum to the substrate.
The relatively low vapor pressure of silicon and the dopants ensures condensation on a lowtemperature substrate. Usually, silicon MBE is performed under ultra-high vacuum [UHV]
conditions of 10-8 to l0-16 Torr.
The two major reasons why MBE was not used were in earlier years were that the quality was
not commensurate with device needs and that no industrial equipment existed. Equipments
are now available, but the process has low throughput and is expensive. MBE, however, does
have a number of inherent advantages over CVD techniques:

It is a low temperature process. Thus outdiffusion and autodoping is minimized.

It allows precise control of doping and permits complicated doping profiles in he generated,
This is useful for discrete microwave devices.

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A linear voltage -capacitance relationship is desired for varactor diodes used in FM

modulators. For this linear doping profile is required, which is easily obtained with MBE.

1.7.3CVD Reactors
The most common deposition methods are

Atmospheric-pressure chemical vapor deposition (APCVD)

Low-pressure chemical vapor deposition (LPCVD), and

Plasma-enhanced chemical vapor deposition (PECVD) or plasma deposition

In earlier years, dielectric and poly-silicon films have been deposited at atmospheric pressure
with the use of different types of reactors. But the use of such Atmospheric-Pressure
Reactors have caused problems like low wafer throughput, and also require excessive wafer
handling during loading and unloading, and provide uniformity in thickness. As time passed
by, they have been replaced by low-pressure, hot-wall reactors. Plasma assisted depositions in
hot-wall reactors or with parallel-plate geometries are also available for application that
require low sample temperatures,(100 to 350C). The major advantages of low-pressure CVD
processes are

Uniform step coverage

Precise control of composition and structure

Low temperature processing

Fast deposition rates

High throughput

Low processing costs

The figure below shows the four reactors commonly used for deposition.

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Diagram [a] shows an LPCVD reactor that is used to deposit polysilicon, silicon dioxide, and
silicon nitride. The reactor consists of a quartz tube heated by a three-zone furnace. Te gas is
introduced through one end of the furnace and pumped out f the other. The pressures inside
the reaction chambers vary from 30 to 250 Pa, with a temperature range between 300 and 900
degree Celsius. Wafers are kept in a quartz holder and are kept to stand in the vertical
position, and perpendicular to the gas flow. In special cases, special insert are used so as to
bring a drastic change in the dynamics of the gas flow. Such a reactor can easily hold 150
millimeters diameter wafers. Each run processes 50 to 200 wafers with thickness uniformities
of the deposited films within 5%.
Advantages LPCVD Reactor

Excellent uniformity,

Large load size

Ability to accommodate large diameter wafers

Disadvantages LPCVD Reactor

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Low deposition rate

Frequent use of toxic corrosive or flammable gases

An APCVD reactor is shown in diagram [b]. This reactor is used to deposit silicon dioxide.
The samples reach the reactor through a conveyor belt. Due to the high speed flow of
nitrogen, gas curtains are formed which cover the reactant gases flowing through the centre
of the reactor. The samples are heated by convection. The advantages and disadvantages of
APCVD reactors are as follows.
Advantages APCVD Reactor

High throughput

Good uniformity

Ability to handle large diameter wafers

Disadvantages APCVD Reactor

Fast gas flows are required, and

Reactors must be cleaned frequently

Diagram [c] shows a Plasma-Enhanced CVD (PECVD) or Plasma Deposition Reactor

which is a radial-flow, parallel-plate type. The reaction chamber is a cylinder, usually glass
or aluminium, with aluminium, plates on the top and bottom. Samples lie on the grounded
bottom electrode. An RF voltage is supplied to the top electrode so as to create a glow
discharge between the two plates. This causes the gases to flow radially through the
discharge. These gases begin at the outer edge and take the direction towards the centre. But,
if needed the pattern of the flow can also be reversed. Resistance heaters or high-intensity
lamps heat the bottom, grounded electrode to a temperature between 100 and 400C. Due to
its low temperature deposition, this reactor finds its application in the plasma-enhanced
deposition of silicon dioxide and silicon nitride.
Disadvantages Plasma Deposition Reactor

Capacity is limited, especially for large diameter wafers

Wafers must be loaded and unloaded individually

Wafers may be contaminated by loose adhering deposits falling on them

Diagram [d] shows a PECVD or plasma deposition reactor of Hot-Wall Type. This reactor
will help in solving most of the problems that occurred in radial-flow reactor. The reaction
takes place in a quartz tube heated by a furnace. The samples should be held vertically, and
that too parallel to the gas flow. The samples should be supported with the help of materials
like long graphite or aluminium slabs, kept in the electrode assembly. A discharge is produced
in the space between the electrodes. This discharge is produced by the alternating slabs that
are connected to the power supply.

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Advantages Hot-Wall Type

High capacity

Low deposition temperature

Disadvantages Hot-Wall Type

Particles can be formed while the electrode assembly is being inserted

Wafers must be individually handled during loading and unloading

Metallization is the final step in the wafer processing sequence. Metallization is the process
by which the components of ICs are interconnected by aluminium conductor. This process
produces a thin-film metal layer that will serve as the required conductor pattern for the
interconnection of the various components on the chip. Another use of metallization is to
produce metalized areas called bonding pads around the periphery of the chip to produce
metalized areas for the bonding of wire leads from the package to the chip. The bonding
wires are typically 25 micro meters diameter gold wires, and the bonding pads are usually
made to be around 100100 micro meters square to accommodate fully the flattened ends of
the bonding wires and to allow for some registration errors in the placement of the wires on
the pads.

Aluminium
Aluminium (At) is the most commonly used material for the metallization of most ICs,
discrete diodes, and transistors. The film thickness is as about 1 micro meters and conductor
widths of about 2 to 25 micro meters are commonly used. The use of aluminium offers the
following advantages:

It has as relatively good conductivity.

It is easy to deposit thin films of Al by vacuum evaporation.

It has good adherence to the silicon dioxide surface.

Aluminium forms good mechanical bonds with silicon by sintering at about 500C or
by alloying at the eutectic temperature of 577C.

Aluminium forms low-resistance, non-rectifying (that is, ohmic) contacts with p-type
silicon and with heavily doped n-type silicon.

It can be applied and patterned with a single deposition and etching process.

Aluminium has certain limitations:

1. During packaging operation if temperature goes too high, say 600C, or if there is
overheating due to current surge, Al can fuse and can penetrate through the oxide to
the silicon and may cause short circuit in the connection. By providing, adequate
process control and testing, such failures can be minimized.

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2. The silicon chip is usually mounted in the package by a gold perform or die backing
that alloys with the silicon. Gold lead wires have been bonded to the aluminium film
bonding pads on the chip, since package lead are usually gold plated. At elevated
temperatures, a reaction between the metal of such systems causes formation of
intermetallic compounds, known as the purple plague. Purple plague is one of six
phases that can occur when gold and aluminium inter-diffuse. Because of dissimilar
rate of diffusion of gold and aluminium, voids normally occur in the form of the
purple plague. These voids may result in weakened bonds, resistive bonds or
catastrophic failure. The problem is generally solved by using aluminium lead wires,
or another metal system, in circuits that will be subjected so elevated temperatures.
One method is to deposit gold over an under layer of chromium. The chromium acts
as a diffusion barrier to the gold and also adheres well to both oxide and gold. Gold
has poor adhesion to oxide because it does not oxide itself. However, the chromiumgold process is comparatively expensive, and it has an uncontrollable reaction with
silicon during alloying.
3. Aluminium suffers from electromigration which can cause considerable material
transport in metals. It occurs because of the enhanced and directional mobility of
atoms caused by the direct influence of the electric field and the collision of electrons
with atoms, which leads to momentum transfer. In thin-film conductors that carry
sufficient current density during device operations, the mode of material transport can
occur at much lower temperature (compared to bulk metals) because of the presence
of grain boundaries, dislocations and point defects that aid the material transport.
Eecctromigration-induced failure is the most important mode of failure in Al lines.
In general the desired properties of the metallization for IC can be listed as follows.

Low resistivity.

Easy to form.

Easy to etch for pattern generation.

Should be stable in oxidizing ambient , oxidizable.

Mechanical stability; good adherence, low stress.

Surface smoothness.

Stability throughout processing including high temperature sinter, dry or wet

oxidation, gettering, phosphorous glass (or any other material) passivation,
metallization.

No reaction with final metal, aluminium.

Should not contaminate device, wafers, or working apparatus.

Good device characteristics and life times.

For window contacts-low contact resistance, minimum junction penetration, low

electromigration.
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1.8 Metallization Application in VLSI

For VLSI, metallization applications can be divided into three groups:
1. Gates for MOSFET
2. Contacts, and
3. Interconnects.
Interconnection metallization interconnects thousands of MOSFETs or bipolar devices using
fine-line metal patterns. It is also same as gate metallization for MOSFET. All metallization
directly in contact with semiconductor is called contact metallization. Polysilicon film is
employed in the form of metallization used for gate and interconnection of MOS devices.
Aluminium is used as the contact metal, on devices and as the second-level inter-connection
to the outside world. Several new schemes for metallization have been suggested to produce
ohmic contacts to a semiconductor. In several cases a multiple-layer structure involving a
diffusion barrier has been recommended. Platinum silicide (PtSi) has been used as a Schottky
barrier contact and also simply as an ohmic contact for deep junction. Titanium/platinum/gold
or titanium/palladium/gold beam lead technology has been successful in providing highreliability connection to the outside world. The applicability of any metallization scheme in
VLSI depends on several requirements. However, the important requirements are the stability
of the metallization throughout the IC fabrication process and its reliability during the actual
use of the devices.

Ohmic contacts
When a metal is deposited on the semiconductor a good ohmic contact should be formed.
This is possible, if the deposition metal does not perturb device characteristics. Also die
contact should be stable both electrically and mechanically.
Other important application of metallization is the top-level metal that provides a connection
to the outside world. To reduce interconnection resistance and save area on a chip, multilevel
metallization, as discussed in this section is also used. Metallization is also used to produce
rectifying (Schottky barrier) contacts, guard rings, and diffusion barriers between reacting
metallic films.
We have already stated the desired properties of metallization for ICs. None of the metals
satisfies all the desired characteristics. Even Al, which has most of the desired properties
suffers from a low melting point-limitation and electromigration as discussed above.
Poly-silicon has been used for gate metallization, for MOS devices. Recently, polysilicon/refractory metal silicide bi-layers have replaced poly-silicon so that lower resistance
an be achieved at the gale and interconnection level. By preserving the use of polysilicon as
the metal in contact with the gate oxide, well known device characteristics and processes
have been unaltered. The silicides of molybdenum (MoSi2), tantalum (TaSi2) and tungsten
(WSi2) have been used in the production of microprocessors and random-access memories.
TiSi2 and CoSi2 have been suggested to replace MoSi2, TaSi2, and WSi2. Aluminium and
refractory metals tungsten and Mo are also being considered for the gate metal.
For contacts, Al has been the preferred metal for VLSI. However, for VLSI applications,
several special factors such as shallower junctions, step coverage, electromigration (at higher

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current densities), and contact resistance can no longer be ignored. Therefore, several
possible solutions to the contact problems in VLSI have been considered. These include use
of

Dilute Si-Ai alloy.

Polysilicon layers between source, drain, or gate and top-level Al.

Selectively deposited tungsten, that is, deposited by CVD methods so that metal is
deposited only on silicon and not on oxide.

A diffusion barrier layer between silicon and Al, using a silicide, nitride, carbide, or
their combination.

Use of self-aligned silicide, such as, PtSi, guarantees extremely good metallurgical contact
between silicon and silicide. Silicides are also recommended in processes where shallow
junctions and contacts are formed at the same time. The most important requirement of an
effective metallization scheme in VLSI is that metal must adhere to the silicon in the
windows and to the oxide that defines die window. In this respect, metals such as, Al, Ti, Ta,
etc., that form oxides with a heat of formation higher than that of Si0 2 are the best. This is
why titanium is the most commonly used adhesion promoter.
Although silicides are used for contact metallization, diffusion barrier is required to protect
from interaction with Al which is used as the top metal. Aluminium interacts with most
silicides in the temperature range of 200-500 degree Celsius. Hence transition metal nitrides,
carbides, and borides are used as a diffusion barrier between silicide (or Si) and Al due to
their high chemical stability.

1.8 Metallization Processes

Metallisation process can be classified info two types:
1. CVD and
2. Physical Vapour Deposition

3. Deposition Methods
4. In the evaporation method, which is the simplest, a film is deposited by the
condensation of the vapour on the substrate. The substrate is maintained at a lower
temperature than that of the vapour. All metals vaporize when heated to sufficiently
high temperatures. Several methods of heating are employed to attain these
temperatures. For AI deposition, resistive, inductive (RF), electron bombardment
[electron-gun] or laser heating can be employed. For refractory metals, electron-gun is
very common. Resistive heating provides low throughput. Electron-gun cause
radiation damage, but by heat treatment it can be annealed out. This method is
advantageous because the evaporations take place at pressure considerably lower than
sputtering pressure. This makes the gas entrapment in the negligible. RF heating of
the evaporating source could prove to be the best compromise in providing large
throughput, clean environment, and minimal levels of radiation damage.
5. In sputtering deposition method, the target material is bombarded by energetic ions to
release some atoms. These atoms are then condensed on the substrate to form a film.

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Sputtering, unlike evaporation is very well controlled and is generally applicable to all
materials metals, alloys, semiconductors and insulators. RF-dc and dc-magnetron
sputtering can be used for metal deposition. Alloy-film deposition by sputtering from
an alloy target is possible because the composition of the film is locked to the
composition of the target. This is true even when there is considerable difference
between the sputtering rates of the alloy components. Alloys can also be deposited
with excellent control of composition by use of individual component targets. In
certain cases, the compounds can be deposited by sputtering the metal in a reactive
environment. Thus gases such as methane, ammonia, or nitrogen, and diborane can be
used in the sputtering chamber to deposit carbide, nitride, and boride, respectively.
This technique is called reactive sputtering. Sputtering is carried out at relatively high
pressures (0.1 to 1 pascal or Pa). Because gas ions are the bombarding species, the
films usually end up including small amount of gas. The trapped gases cause stress
changes. Sputtering is a physical process in which the deposited film is also exposed
to ion bombardment. Such ion bombardment causes sputtering damage, which leads
to unwanted charges and internal electric fields that affect device proxies. However
such damages can be annealed out at relatively low temperatures (<500C), unless the
damage is so severe as to cause an irreversible breakdown of the gate dielectric.

6. Deposition Apparatus
7. The metallization is usually done in vacuum chambers. A mechanical pump can
reduce the pressure to about 10 to 0.1 Pa. Such pressure may be sufficient for
LPCVD. An oil-diffusion pump can bring the pressure down to 10 -5 Pa and with the
help of a liquid nitrogen trap as low as 10 -7 Pa. A turbomolecular pump, can bring the
pressure down to 10-8-10-9 Pa. Such pumps are oil-free and are useful HI molecularbeam epitaxy where oil contamination must be avoided. Besides the pumping system,
pressure gauges and controls, residual gas analyzers, temperature sensors, ability to
clean the surface of the wafers by backsputtering, contamination control, and gas
manifolds, and the use of automation should be evaluated.
8. As typical high-vacuum evaporation apparatus is shown in the figure below.

9.

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10. Metallization Process

11. The apparatus consists of a hell jar, a stainless-steel cylindrical vessel closed at the top
and sealed at the base by a gasket. Beginning at atmospheric pressure the jar is
evacuated by a roughing pump, such as a mechanical rotary-van pump reducing
pressure to about 20 Pa or a combination mechanical pump and liquid-nitrogencooled molecular pump (reducing pressure lo about 0.5 Pa). At the appropriate
pressure, the jar is opened to a high-vacuum pumping system that continues to reduce
the pressure. The high-vacuum, pumping system may consist of a liquid nitrogencooled trap and an oil-diffusion pump, a trap and a turbomolecular pump, or a trap
and a closed-cycle helium refrigerator cryopump. The cryopump acts as a trap and
must be regenerated periodically, the turbomolecular and diffusion pumps act as
transfer pumps, expelling their gas t a forepump. The high vacuum pumping system
brings the jar to a low pressure that is tolerable for the deposition process.
12. All components in the chamber are chemically cleaned and dried. Freedom from
sodium contamination is vital when coating MOS devices.
13. The sputtering system operates with about 1 Pa of argon pressure during film
deposition. For sputtering, a throttle valve should be placed between the trap and the
high-vacuum pumping system. The argon gas pressure can to be maintained by
reducing the effective pumping speed of the high-vacuum pump, while the full
pumping speed of the trap for water vapour is utilized. Water vapour and oxygen are
detrimental to film quality at background pressures of about 10-2 Pa.
14. The use of thickness monitors is common in evaporation and sputtering deposition.
This is necessary for controlling the thickness of the film, because thinner film can
cause excess current density and excessive thickness can lead to difficulties in
etching.

15.Metallization Patterning
16. Once the thin-film metallization has been done the film must be patterned to produce
the required interconnection and bonding pad configuration. This is done by a
photolithographic process of the same type that is used for producing patterns in Si0 2
layers. Aluminium can be etched by a number of acid and base solutions including
HCl, H3PO4, KOH, and NaOH. The most commonly used aluminium etchant is
phosphoric acid with the addition of small amounts of HN03 (nitric acid) and acetic
acid, to result a moderate etch rate of about 1 micro meter per minute at 50C. Plasma
etching can also be used with aluminium.

17.Lift-off Process
18. The lift-off process is an alternative metallization patterning technique. In this process
a positive photoresist is spun on the wafer and patterned using the standard
photolithographic process. Then the metallization thin film is deposited on top of the
remaining photoresist. The wafers are then immersed in suitable solvent such as
acetone and at the same time subjected to ultrasonic agitation. This causes swelling
and dissolution of the photoresist. As the photoresist comes off it lifts off the
metallization on top of it, for the lift-off process to work, the metallization film
thickness must generally be somewhat less than the photoresist thickness. This
process can, however produce a very fine line-width metallization pattern, even with
metallization thickness that are greater than the line width.

19.Pattering for VLSI Applications

20. VLSI applications require anisotropic etching techniques for metallization patterning
because of the requirements of tight control on metallization dimensions. Therefore
dry-etching techniques are most suitable. Reactive-ion etching (RIE) is anisotropic.
Hence it is preferred. For RIE, reactive gases such as, Cl 2 and CCI3F are used, hence
the name reactive ion etching.

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