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MIPS Pipeline: 1. Instruction Fetch (IF) Stage

The document discusses the MIPS pipeline architecture, which consists of 5 stages - Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (M), and Write Back (WB). It describes the key operations that occur in each stage, such as instruction decoding in ID and ALU operations in EX. The document also explains why the Harvard architecture, with separate instruction and data memory units, is required to avoid resource conflicts in the pipeline. Finally, it provides a graphical representation of how different MIPS instruction types, like R-type and load/store instructions, progress through each pipeline stage.

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Jaweria Siddiqui
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51 views

MIPS Pipeline: 1. Instruction Fetch (IF) Stage

The document discusses the MIPS pipeline architecture, which consists of 5 stages - Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (M), and Write Back (WB). It describes the key operations that occur in each stage, such as instruction decoding in ID and ALU operations in EX. The document also explains why the Harvard architecture, with separate instruction and data memory units, is required to avoid resource conflicts in the pipeline. Finally, it provides a graphical representation of how different MIPS instruction types, like R-type and load/store instructions, progress through each pipeline stage.

Uploaded by

Jaweria Siddiqui
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CS-421 Parallel Processing

Discussion-07

BE (CIS) Batch 2005-06

MIPS Pipeline
1. Instruction Fetch (IF) Stage
a. Instruction Fetch
Instructions address in PC is applied to instruction memory that causes the addressed instruction to become
available at the output lines of instruction memory.
b. Updating PC
The address in PC is incremented by 4 but what is written in PC is determined by the control signal PCSrc.
Depending upon the status of control signal PCSrc, PC is either written by the branch target address (BTA) or the
sequential address (PC + 4).
2. Instruction Decode (ID) Stage
a. Instruction is decoded by the control unit that takes 6-bit opcode and generates control signals.
b. The control signals are buffered in the pipeline registers until they are used in the concerned stage by the
corresponding instruction.
c. Registers are also read in this stage. Note that the first source registers identifier in every instruction is at bit
positions [25:21] and second source registers identifier (if any) is at bit positions [20:16].
d. The destination registers identifier is either at bit positions [15:11] (for R-type) or at [20:16] (for lw and addi).
The correct destination registers identifier is selected via multiplexer controlled by the control signal RegDst.
However, this multiplexer is placed in the EX stage because the instruction decoding is not finished until the
second stage is complete. However this identifier is buffered until the WB stage because an instruction writes a
register in the WB stage.
3. Execution (EX) Stage
a. This stage is marked by the use of ALU that performs the desired operation on registers (R-type), calculates
address (memory reference instructions), or compares registers (branch).
b. An ALU control accepts 6-bit funct field and 2-bit control signal ALUOp to generate the required control
signal for the ALU.
c. BTA is also calculated in the EX stage by a separate adder.
4. Memory (M) Stage
a. Data memory is read (lw) or written (sw) using the address calculated by the ALU in EX stage.
b. ZERO output of ALU and BRANCH signal generated by the control unit are ANDed to determine the fate of
branch (taken or not taken).
5.

Write Back (WB) Stage


a. Result produced by ALU in EX stage (R-type) or data read from data memory in M stage (lw) is written in
destination register. The data to be written in destination register is selected via multiplexer controlled by the
control signal MemToReg.

Page - 1 - of 2

CS-421 Parallel Processing


Discussion-07

BE (CIS) Batch 2005-06

Harvard Architecture
Separate memory units for instructions and data (Harvard Architecture) are required because in a given pipeline cycle two
instructions may need to use memory (one for instruction fetch and another for data read/write) as shown below.
I1 I2 I3 I4 I5
I6
WB
I7
M
I1 I2 I3 I4 I5 I6
I1 I2 I 3 I 4 I5 I 6 I 7
I8
EX
I1 I2 I3 I4 I5 I6 I7 I8
I9
ID
I1 I2 I3 I4 I5 I6 I7 I8 I9 I10
IF
2
3
5
6
7
8
9
10
cycles 1
4
As indicated, in cycle 4 I1 accesses memory for data read/write and I4 is being fetched accessing instruction memory.
Harvard Architecture averts this problem.
Exercise
1. What are the sizes of pipeline registers IF/ID, ID/EX, EX/M and M/WB?
2. Why there is no pipeline register needed after WB stage?
Graphical Representation of MIPS Pipeline

Consider pipelined execution of following MIPS instructions:


lw

$1, 0($2)

add $3, $4, $5


The lw instruction uses all stages in the pipeline but add (like any other R-type instruction) doesnt access data memory
i.e. it doesnt use M stage. Thus the progress of above instructions through the MIPS pipeline is illustrated below:

lw

CC1

CC2

CC3

CC4

CC5

IF

ID

EX

WB

IF

ID

EX

WB

add

Did you notice any problem? In CC5 a resource conflict is observed. That is, two different instructions attempt to use the
same hardware in the same cycle. This can be averted by ensuring uniformity: make all instructions pass through all the
stages in the same order.
As a consequence, some instructions will do nothing (accomplished through disabling corresponding control signals) in
some stages.
R-Type

IF

ID

EX

WB

sw

IF

ID

EX

WB

beq

IF

ID

EX

WB

Where shaded boxes represent pipeline stages in which given instruction does nothing. Only lw uses all five stages.
*****
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