3932

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

A New General Topology for Cascaded Multilevel

Inverters With Reduced Number of Components
Based on Developed H-Bridge
Ebrahim Babaei, Member, IEEE, Somayeh Alilu, and Sara Laali, Student Member, IEEE

AbstractIn this paper, a new general cascaded multilevel

inverter using developed H-bridges is proposed. The proposed
topology requires a lesser number of dc voltage sources and power
switches and consists of lower blocking voltage on switches, which
results in decreased complexity and total cost of the inverter.
These abilities obtained within comparing the proposed topology
with the conventional topologies from aforementioned points of
view. Moreover, a new algorithm to determine the magnitude of
dc voltage sources is proposed. The performance and functional
accuracy of the proposed topology using the new algorithm in
generating all voltage levels for a 31-level inverter are confirmed
by simulation and experimental results.
Index TermsCascaded multilevel inverter,
H-bridge, multilevel inverter, voltage source inverter.

developed

I. I NTRODUCTION

OWADAYS, multilevel inverters have received more attention for their ability on high-power and mediumvoltage operation and because of other advantages such as high
power quality, lower order harmonics, lower switching losses,
and better electromagnetic interference [1], [2]. These inverters
generate a stepped voltage waveform by using a number of dc
voltage sources as the input and an appropriate arrangement of
the power-semiconductor-based devices [3].
Three main structures of the multilevel inverters have been
presented: diode clamped multilevel inverter, flying capacitor multilevel inverter, and cascaded multilevel inverter [4].
The cascaded multilevel inverter is composed of a number of
single-phase H-bridge inverters and is classified into symmetric
and asymmetric groups based on the magnitude of dc voltage
sources. In the symmetric types, the magnitudes of the dc voltage sources of all H-bridges are equal while in the asymmetric
types, the values of the dc voltage sources of all H-bridges are
different.
In recent years, several topologies with various control techniques have been presented for cascaded multilevel inverters
[5][8]. In [4] and [9][15], different symmetric cascaded multilevel inverters have been presented. The main advantage of all
these structures is the low variety of dc voltage sources, which
Manuscript received February 18, 2013; revised June 8, 2013; accepted
August 4, 2013. Date of publication October 21, 2013; date of current version
February 7, 2014.
The authors are with the Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz 51664, Iran (e-mail: [email protected];
[email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2013.2286561

is one of the most important features in determining the cost

of the inverter. On the other hand, because some of them use a
high number of bidirectional power switches, a high number of
insulated gate bipolar transistors (IGBTs) are required, which
is the main disadvantage of these topologies. An asymmetric
topology has been presented in [16]. The main disadvantage
of this structure is related to its bidirectional power switches,
which cause an increase in the number of IGBTs and the
total cost of the inverter. In [15], a new topology with three
algorithms have been presented, which reduce the number of
required power switches but increase the variety of dc voltage
sources. In [1], [4] and [17], and [18], several algorithms
for determining the magnitudes of dc voltage sources for the
conventional cascaded multilevel inverter have been presented.
The major advantage of this topology and its algorithms is
related to its ability to generate a considerable number of output
voltage levels by using a low number of dc voltage sources
and power switches but the high variety in the magnitude of
dc voltage sources is their most remarkable disadvantage.
In this paper, in order to increase the number of output
voltage levels and reduce the number of power switches, driver
circuits, and the total cost of the inverter, a new topology of
cascaded multilevel inverters is proposed. It is important to
note that in the proposed topology, the unidirectional power
switches are used. Then, to determine the magnitude of the
dc voltage sources, a new algorithm is proposed. Moreover,
the proposed topology is compared with other topologies from
different points of view such as the number of IGBTs, number
of dc voltage sources, the variety of the values of the dc
voltage sources, and the value of the blocking voltages per
switch. Finally, the performance of the proposed topology in
generating all voltage levels through a 31-level inverter is
confirmed by simulation using power system computer aided
design (PSCAD) software and experimental results.
II. P ROPOSED T OPOLOGY
In Fig. 1, two new topologies are proposed for a seven-level
inverter [19]. As shown in Fig. 1, the proposed topologies are
obtained by adding two unidirectional power switches and one
dc voltage source to the H-bridge inverter structure. In other
words, the proposed inverters are comprised of six unidirectional power switches (Sa , Sb , SL,1 , SL,2 , SR,1 , and SR,2 ) and
two dc voltage sources (VL,1 and VR,1 ). In this paper, these
topologies are called developed H-bridge. As shown in Fig. 1,
the simultaneous turn-on of SL,1 and SL,2 (or SR,1 and SR,2 )

0278-0046 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS

Fig. 1. Proposed seven-level inverters. (a) First proposed topology. (b) Second
proposed topology.

3933

Fig. 2. Proposed 31-level inverter.

TABLE I
O UTPUT VOLTAGES OF THE P ROPOSED S EVEN -L EVEL I NVERTERS

Fig. 3. Proposed 127-level inverter.

causes the voltage sources to short-circuit. Therefore, the simultaneous turn-on of the mentioned switches must be avoided.
In addition, Sa and Sb should not turn on, simultaneously. The
difference in the topologies illustrated in Fig. 1 is in the connection of the dc voltage sources polarity. Table I shows the output
voltages of the proposed inverters for different states of the
switches. In this table, 1 and 0 indicate the ON- and OFF-states
of the switches, respectively. As it is obvious from Table I, if
the values of the dc voltage sources are equal, the number of
voltage levels decreases to three. Therefore, the values of dc
voltage sources should be different to generate more voltage
levels without increasing the number of switches and dc voltage
sources. Considering Table I, to generate all voltage levels (odd
and even) in the proposed topology shown in Fig. 1(a), the
magnitudes of VL,1 and VR,1 should be considered 3pu and
1pu, respectively. Similarly, for the topology shown in Fig. 1(a),
the magnitudes of VL,1 and VR,1 should be considered 2pu and
1pu, respectively. Considering the aforementioned explanations, the total cost of the proposed topology in Fig. 1(b) is low
because dc voltage sources with low magnitudes are needed.
By developing the seven-level inverter shown in Fig. 1(b),
the 31-level inverter shown in Fig. 2 can be proposed. This
topology consists of ten unidirectional power switches and four
dc voltage sources. According to Fig. 2, if the power switches of
(SL,1 , SL,2 ), (SL,3 , SL,4 ), (SR,1 , SR,2 ), and (SR,3 , SR,4 ) turn
on simultaneously, the dc voltage sources of VL,1 , VL,2 , VR,1 ,
and VR,2 will be short-circuited, respectively. Therefore, the
simultaneous turn-on of these switches should be avoided. In
addition, Sa and Sb should not turn on simultaneously. It is
important to note that the 31-level topology can be provided
through the structure presented in Fig. 1(a), where the only difference will be in the polarity of the applied dc voltage sources.
By developing the proposed 31-level inverter, a 127-level
inverter can be proposed as shown in Fig. 3. This topology

Fig. 4. Proposed general topology.

consists of 14 unidirectional power switches and 6 dc voltage

sources. Similarly, by developing the proposed basic topology,
a general topology, as shown in Fig. 4, can be proposed. The
general topology consists of 2n dc voltage sources (n is the
number of the dc voltage sources on each leg) and 4n + 2
unidirectional power switches.
In the proposed general topology, the number of output
voltage levels (Nstep ), number of switches (Nswitch ), number
of dc voltage sources (Nsource ), and the maximum magnitude
of the generated voltage (Vo,max ) are calculated as follows,
respectively:
Nstep = 22n+1 1
Nswitch = 4n + 2
Nsource = 2n
Vo,max = VL,n + VR,n .

(1)
(2)
(3)
(4)

3934

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

The other important parameters of the total cost of a multilevel inverter for evaluation are the variety of the values of
dc voltage sources and the value of the blocking voltage of the
switches. As the variety of dc voltage sources and the value of
the blocking voltage of the switches are low, the inverters total
cost decreases [20]. The number of variety of the values of dc
voltage sources (Nvariety ) is given by
Nvariety = 2n.

(5)

The following pattern is utilized to calculate the maximum

magnitude of the blocking voltage of the power switches. As
shown in Fig. 1(b), the blocking voltage of SR,1 and SR,2 are
calculated as follows:
VSR,1 = VSR,2 = VR,1

(6)

where VSR,1 and VSR,2 indicate the maximum blocking voltages of SR,1 and SR,2 , respectively.
The blocking voltage of SL,1 and SL,2 are as follows:
VSL,1 = VSL,2 = VL,1

(7)

III. P ROPOSED A LGORITHM TO D ETERMINE THE

M AGNITUDES OF DC VOLTAGE S OURCES
In this paper, the following algorithm is applied to determine
the magnitude of dc voltage sources. It is important to note that
all voltage levels (even and odd) can be generated.
A. Proposed Seven-Level Inverter
The magnitudes of the dc voltage sources of the seven-level
inverter shown in Fig. 1(b) are determined as follows:

= 4(VR,1 + VL,1 ).

(8)

Considering Fig. 2, the maximum blocking voltage of the

switches is as follows:
VSR,1 = VSR,2 = VR,1

(9)

VSR,3 = VSR,4 = VR,2 VR,1

(10)

VSL,1 = VSL,2 = VL,1

(17)

VR,1 = 2Vdc .

(18)

Considering (17), (18), and Table I, the proposed seven-level

inverter can generate 0, Vdc , 2Vdc , and 3Vdc at output.
B. Proposed 31-Level Inverter
The magnitudes of the dc voltage sources of the proposed
31-level inverter are recommended as follows:

where VSL,1 and VSL,2 indicate the maximum blocking voltages

of SL,1 and SL,2 , respectively.
Therefore, the maximum blocking voltage of all switches
in the proposed seven-level inverter (Vblock,1 ) is calculated as
follows:
Vblock,1 = VSR,1 + VSR,2 + VSL,1 + VSL,2 + VSa + VSa

VL,1 = Vdc

VL,1 = Vdc
VR,1 = 2Vdc

(19)
(20)

VL,2 = 5Vdc
VR,2 = 10Vdc .

(21)
(22)

The proposed inverter can generate all negative and positive

voltage levels from 0 to 15Vdc with steps of Vdc .
C. Proposed 127-Level Inverter
The magnitudes of the dc voltage sources of the proposed
127-level inverter are calculated as follows:
VL,1 = Vdc

(23)

(11)

VR,1 = 2Vdc

(24)

VSL,3 = VSL,4 = VL,2 VL,1

(12)

VL,2 = 5Vdc

(25)

VSa = VSb = VR,2 + VL,2 .

(13)

VR,2 = 10Vdc

(26)

Therefore, the maximum blocking voltage of all switches of the

proposed 31-level inverter (Vblock,2 ) is as follows:

VL,3 = 25Vdc

(27)

VR,3 = 50Vdc .

(28)

Vblock,2 = VSR,1 + VSR,2 + VSR,3 + VSR,4 + VSL,1 + VSL,2

+ VSL,3 + VSL,4 + VSa + VSb
= 4(VR,2 + VL,2 ).

(14)

Similarly, the maximum blocking voltage of all switches of the

127-level inverter is calculated as follows:
Vblock,3 = 4(VR,3 + VL,3 ).

(15)

Finally, the maximum blocking voltage of all the switches of

the general topology (Vblock,n ) is calculated as follows:
Vblock,n = 4(VR,n + VL,n ).

(16)

By using this algorithm, the inverter can generate all negative

and positive voltage levels from 0 to 63Vdc with steps of Vdc .
D. Proposed General Multilevel Inverter
The magnitudes of the dc voltage sources of the proposed
general multilevel inverter can be obtained as follows:
VL,j = 5j1 Vdc

for j = 1, 2, 3, . . . , n

(29)

VR,j = 2 5j1 Vdc

for

j = 1, 2, 3, . . . , n.

(30)

Considering (4) and (16), the values of Vo,max and Vblock,n

of the proposed general multilevel inverter are as follows,

BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS

respectively:
Vo,max = VL,n + VR,n = 3 5n1 Vdc
Vblock,n = 4(VL,n + VR,n ) = 12(5n1 )Vdc .

(31)
(32)

3935

where f is the fundamental frequency and Non,k and No,k

are the numbers of turn-on and turn-off of the switch k during
a fundamental cycle. Also, Eon,ki is the energy loss of the
switch k during the ith turn-on and Eo,ki is the energy loss
of the switch k during the ith turn-off.
The total loss (Ploss ) of the multilevel converter is the sum
of the conduction and switching losses as follows:

IV. C ALCULATION OF L OSSES

Mainly, two kinds of losses (i.e., conduction and switching
losses) are associated with the switches. Since the switches
include IGBTs and diodes, the conduction losses of an IGBT
(pc,IGBT (t)) and a diode (pc,D (t)) are calculated as follows,
respectively [7], [22]:


(33)
pc,IGBT (t) = VIGBT + RIGBT i (t) i(t)
pc,D (t) = [VD + RD i(t)] i(t)

(34)

where VIGBT and VD are the forward voltage drops of the IGBT
and diode, respectively. RIGBT and RD are the equivalent
resistances of the IGBT and diode, respectively, and is a
constant related to the specification of the IGBT.
Considering that at instant t, there are NIGBT transistors
and ND diodes in the current path, the average value of the
conduction power loss (Pc ) of the multilevel inverter can be
written as follows:
Pc =

1
2

2
[NIGBT (t)pc,T (t) + ND (t)pc,D (t)] dt.

(35)

The switching losses are calculated based on the energy

loss calculation. The switching losses occur during the turn-off
and turn-on periods. For simplicity, the linear variations of the
voltage and current of the switches in the switching period are
considered. Based on this assumption, the following relations
can be written [7], [22]:
toff

1
Vsw,k I to
6

(36)

ton
1
=
v(t)i(t)dt = Vsw,k I  ton
6

(37)

Eo,k =

v(t)i(t)dt =
0

Eon,k

where Eo,k and Eon,k are the turn-off and turn-on losses of
the switch k, respectively. to and ton are the turn-off and turnon times of the switch, respectively, I is the current through the
switch before turning off, I  is the current through the switch
after turning on, and Vsw,k is the OFF-state voltage on the
switch.
The switching power loss (Psw ) is equal to the sum of
all turn-on and turn-off energy losses in a fundamental cycle of the output voltage. This can be written as follows
[7], [22]:

Non,k
Noff,k
N
switch



Psw = f
(38)
Eon,ki +
Eo,ki
k=1

i=1

i=1

Ploss = Pc + Psw .

(39)

Finally, the efficiency () of the inverter is calculated as

follows:
=

Pout
Pout
=
Pin
Pout + Ploss

(40)

where Pout and Pin denote the output and input powers of the
inverter.
V. C OMPARING THE P ROPOSED G ENERAL T OPOLOGY
W ITH THE C ONVENTIONAL T OPOLOGIES
In order to clarify the advantages and disadvantage of the
proposed topology, it should be compared with the different
kinds of topologies presented in literature. In [4], the conventional cascaded multilevel inverter with two different algorithms has been presented. These algorithms are known as the
symmetric cascaded multilevel inverters and the asymmetric
ones with the binary method for determining the magnitude
of dc voltage sources. In the comparison, the conventional
symmetric cascaded multilevel inverter is indicated by R1
and the conventional binary asymmetric cascaded multilevel
inverter is shown by R2 . Three other algorithms have been
presented for this topology in [1], [17], and [18], which are
indicated by R3 R5 , respectively. Moreover, another topology
with three different algorithms for determining the value of
dc voltage sources have been introduced in [15], which are
shown by R13 R15 in this comparison. In [9][12], four different structures for the cascaded multilevel inverter have been
presented, and in this paper, they are indicated by R6 R7 and
R11 R12 . It is important to note that the power switches in the
aforementioned topologies are unidirectional. In addition, other
topologies based on bidirectional switches have been presented
in [13] and [14]. In [14], three different algorithms have been
recommended, which are denoted as R8 R10 , and the presented
topology in [13] is indicated by R16 in this comparison. Fig. 5
shows all of the aforementioned structures.
Fig. 6 compares the number of IGBTs of the proposed
general topology with the aforementioned cascaded multilevel
inverters. It is obvious that the proposed inverter requires a
lesser number of IGBTs in comparison with the other mentioned topologies to generate particular levels.
Fig. 7 compares the number of dc voltage sources of the
proposed inverter with the aforementioned cascaded multilevel
inverter. As shown in Fig. 7, the proposed inverter has better
performance in comparison with the other presented topologies
except the topology presented in R3 . However, the magnitude
of the dc voltage sources in R3 is a little more than that of the
proposed topology.

3936

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

Fig. 5. Cascaded multilevel inverters presented in literature: (a) Conventional cascaded multilevel inverters R1 for V1 = V2 = = Vn = Vdc , R2 for
V1 = 2j1 Vdc (j = 1, 2, . . . , n), R3 for V1 = 3j1 Vdc (j = 1, 2, . . . , n), R4 for V1 = 0.5V2 = 0.5V3 = = 0.5Vn = Vdc , and R5 for V1 = V2 /3 =
V3 /3 = = Vn /3 = Vdc . (b) Presented topology in [12], namely, R12 for V1 = V2 = = Vn = Vdc . (c) Presented topology in [10], i.e., R7 for
V1 = V2 = = Vn = Vdc . (d) Presented topology in [9], i.e., R6 for V1 = V2 = = Vn = Vdc . (e) Presented topologies in [14], i.e., R8 for V1 = V2 =
= Vn = Vdc , R9 for V1 = 0.5V2 = 0.5V3 = = 0.5Vn = Vdc , and R10 for V1 = 2j1 Vdc (j = 1, 2, . . . , n). (f) Presented topologies in [15], i.e.,
R13 for V1 = V2 = = Vn = Vdc , R14 for V1 = 2j1 Vdc (j = 1, 2, . . . , n), and R15 for V1 = 0.5V2 = 0.5V3 = = 0.5Vn = Vdc . (g) Presented
topology in [13], i.e., R16 for V1 = V2 = = Vn = Vdc . (h) Presented topology in [11], i.e., R11 for V1 = V2 = = Vn = Vdc .

Fig. 6. Variation of NIGBT versus Nstep .

Fig. 8.

Fig. 7. Variation of Nsource versus Nstep .

Fig. 8 compares the variety of magnitudes of the dc voltage

sources of the proposed inverter with that of the aforementioned cascaded multilevel inverter. Obviously, the proposed

Variation of Nvariety versus Nstep .

inverter uses a wider variety of magnitudes of the dc voltage

sources in comparison with those of all the aforementioned
topologies. This feature is the most important disadvantage
of the proposed topology because the variety of the values
of dc voltage sources is as one of the remarkable factors in
determining the cost of the inverter. However, this feature in the
proposed topology is similar to the presented topologies of R2
and R14 .
Fig. 9 compares the magnitude of the blocking voltage of
the switches of the proposed inverter with that of the aforementioned cascaded multilevel inverter. This figure shows the
reduction of the magnitude of the blocking voltage of the
proposed inverter in comparison with those of all the aforementioned multilevel inverters.

BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS

Fig. 9.

3937

Variation of Vblock versus Nstep .

TABLE II
O UTPUT VOLTAGES OF THE P ROPOSED 31-L EVEL I NVERTER

Fig. 10. Photograph of the experimental setup.

Fig. 11. Proposed 31-level inverter. (a) Output voltage waveform. (b) Output
current waveform.

VI. S IMULATION AND E XPERIMENTAL R ESULTS

In order to verify the correct performance of the proposed
multilevel inverter in generating all output voltage levels (even
and odd), a 31-level inverter based on the topology shown
in Fig. 2 has been used for the simulation and experimental
prototypes. Table II shows the switching states of the 31-level

inverter. The simulation is done by using PSCAD software, and

the practical prototype is made in the experimental environment. Fig. 10 shows the experimental setup. It is important to
note that the IGBTs used in the prototype are HGTP10N40CID
(with an internal antiparallel diode) with the voltage and current
ranges of 400 V and 10 A, respectively. The 89C52 microcontroller by ATMEL Company has been used to generate
all switching patterns. In all processes of the simulation and
experiment, the load is assumed as RL with R = 45 and
L = 55 mH. Moreover, the magnitude of VL,1 is considered
15 V, so based on (29) and (30), the magnitudes of the other
dc voltage sources will be 30, 75, and 150 V, which are
related to VR,1 , VL,2 , and VR,2 , respectively. According to (31),
the maximum output voltage of this inverter will be 225 V.
In this paper, the fundamental frequency switching control
method has been used [21]. In this method, the sinusoidal
reference voltage is compared with the available dc voltage
levels and the level that is nearest to the reference voltage
is chosen [22]. The main advantage of this control method
is related to its low switching frequency, which is leads to
reduction of switching losses.
The simulated output voltage and current waveforms are
shown in Fig. 11. As Fig. 11(a) shows, the proposed topology
is able to generate 31 levels (15 positive levels, 15 negative
levels, and 1 zero level) with the maximum voltage of 225 V.
Comparing the output voltage and current waveforms indicates
that the output current waveform is more similar to the ideal
sinusoidal waveform than the output voltage because the RL
load acts as a low-pass filter. In addition, there is a phase
difference between the output voltage and current waveforms,
which is caused by the inductive feature of the load. The
total harmonic distortions of the output voltage and current
are equal to 0.94% and 0.19%, respectively. Fig. 12(a) and (b)
shows the harmonic spectrum of the output voltage and current,
respectively. The figure shows that the magnitudes of harmonics
of both voltage and current waveforms are low. However, the
harmonics of the current waveform are lower than the voltage

3938

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

Fig. 12. Harmonic spectrum of (a) output voltage and (b) current.

waveform. It is important to note that in Fig. 12, in order

to show the magnitudes of the fundamental and high-order
harmonics, the scale of the vertical axis is considered nonlinear.
In the test condition, the measured input and output powers are
about 1203 and 1112 W, respectively. Therefore, the efficiency
is about 92.4%. Based on the loss calculations given before, the
power loss is about 86 W. Therefore, the calculated loss has a
good accordance with the measured efficiency.
As mentioned before, the power switches in the proposed
topology are unidirectional from the voltage viewpoint. In order
to prove this issue, the voltages on the switches of a single leg
of the inverter (i.e., SL,1 , SL,2 , SL,3 , SL,4 , and Sa ) are shown
in Fig. 13. As can be seen, the maximum blocking voltage by
switches SL,1 , SL,2 , SL,3 , SL,4 , and Sa are equal to 15, 15, 60,
60, and 225 V, respectively. Obviously, the voltage values are
zero or equal to the positive ones, which is well in accordance
to the unidirectional feature of the switches from the voltage
viewpoint. Considering the magnitude of the blocking voltage
of the switches, the relations associated to the maximum voltage drop of the switches are well confirmed. Fig. 14 shows the
experimental results of the implemented inverter. It is important
to note that there is a good agreement between the experimental
and simulation results.

Fig. 13.
(e) Sa .

Voltages of switches (a) SL,1 , (b) SL,2 , (c) SL,3 , (d) SL,4 , and

VII. C ONCLUSION
In this paper, two basic topologies have been proposed for
multilevel inverters to generate seven voltage levels at the
output. The basic topologies can be developed to any number of
levels at the output where the 31-level, 127-level, and general
topologies are consequently presented. In addition, a new algorithm to determine the magnitude of the dc voltage sources has
been proposed. The proposed general topology was compared
with the different kinds of presented topologies in literature
from different points of view. According to the comparison results, the proposed topology requires a lesser number of IGBTs,
power diodes, driver circuits, and dc voltage sources. Moreover,
the magnitude of the blocking voltage of the switches is lower

Fig. 14. Experimental results: (a) Output voltage and output current voltage;
(b) SL,1 ; (c) SL,2 ; (d) SL,3 ; (e) SL,4 ; and (f) Sa .

than that of conventional topologies. However, the proposed

topology has a higher number of variety of dc voltage sources
in comparison with the others. The performance accuracy of the
proposed topology was verified through the PSCAD simulation
and the experimental results of a 31-level inverter.

BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS

R EFERENCES
[1] E. Babaei and S. H. Hosseini, Charge balance control methods for asymmetrical cascade multilevel converters, in Proc. ICEMS, Seoul, Korea,
2007, pp. 7479.
[2] K. Wang, Y. Li, Z. Zheng, and L. Xu, Voltage balancing and fluctuationsuppression methods of floating capacitors in a new modular multilevel
converter, IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 19431954,
May 2013.
[3] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, A new topology of
cascaded multilevel converters with reduced number of components for
high-voltage applications, IEEE Trans. Power Electron., vol. 26, no. 11,
pp. 31093118, Nov. 2011.
[4] M. Manjrekar and T. A. Lipo, A hybrid multilevel inverter topology for
drive application, in Proc. APEC, 1998, pp. 523529.
[5] M. Narimani and G. Moschopoulos, A novel single-stage multilevel type
full-bridge converter, IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 31
42, Jan. 2013.
[6] N. Abd Rahim, M. F. Mohamad Elias, and W. P. Hew, Transistor-clamped
H-bridge based cascaded multilevel inverter with new method of capacitor
voltage balancing, IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 2943
2956, Aug. 2013.
[7] M. Farhadi Kangarlu and E. Babaei, A generalized cascaded multilevel
inverter using series connection of submultilevel inverters, IEEE Trans.
Power Electron., vol. 28, no. 2, pp. 625636, Feb. 2013.
[8] S. R. Pulikanti, G. Konstantinou, and V. G. Agelidis, Hybrid seven-level
cascaded active neutral-point-clamped-based multilevel converter under
SHE-PWM, IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 47944804,
Nov. 2013.
[9] Y. Hinago and H. Koizumi, A single-phase multilevel inverter using
switched series/parallel dc voltage sources, IEEE Trans. Ind. Electron.,
vol. 57, no. 8, pp. 26432650, Aug. 2010.
[10] G. Waltrich and I. Barbi, Three-phase cascaded multilevel inverter using
power cells with two inverter legs in series, IEEE Trans. Ind. Appl.,
vol. 57, no. 8, pp. 26052612, Aug. 2010.
[11] W. K. Choi and F. S. Kang, H-bridge based multilevel inverter using
PWM switching function, in Proc. INTELEC, 2009, pp. 15.
[12] E. Babaei, M. Farhadi Kangarlu, and F. Najaty Mazgar, Symmetric
and asymmetric multilevel inverter topologies with reduced switching
devices, Elect. Power Syst. Res., vol. 86, pp. 122130, May 2012.
[13] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, A new multilevel converter topology with reduced number of power electronic components,
IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655667, Feb. 2012.
[14] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. Tarafdar Haque, and
M. Sabahi, Reduction of DC voltage sources and switches in asymmetrical multilevel converters using a novel topology, Elect. Power Syst. Res.,
vol. 77, no. 8, pp. 10731085, Jun. 2007.
[15] E. Babaei and S. H. Hosseini, New cascaded multilevel inverter topology
with minimum number of switches, Energy Convers. Manage., vol. 50,
no. 11, pp. 27612767, Nov. 2009.
[16] S. Mekhilef and M. N. Kadir, Voltage control of three-stage hybrid multilevel inverter using vector transformation, IEEE Trans. Power Electron.,
vol. 25, no. 10, pp. 25992606, Oct. 2010.
[17] A. Rufer, M. Veenstra, and K. Gopakumar, Asymmetric multilevel converter for high resolution voltage phasor generation, presented at the
Proc. EPE, Lausanne, Switzerland, 1999.
[18] S. Laali, K. Abbaszades, and H. Lesani, A new algorithm to determine
the magnitudes of dc voltage sources in asymmetrical cascaded multilevel
converters capable of using charge balance control methods, in Proc.
ICEMS, Incheon, Korea, 2010, pp. 5661.

3939

[19] S. Alilu, E. Babaei, and S. B. Mozafari, A new general topology for

multilevel inverters based on developed H-bridge, in Proc. PEDSTC,
Tehran, Iran, 2013, pp. IR-113IR-118.
[20] E. Babaei, A cascade multilevel converter topology with reduced number
of switches, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 26572664,
Nov. 2008.
[21] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo,
M. A. M. Prats, and M. A. Perez, Multilevel converters: An enabling
technology for high power applications, Proc. IEEE, vol. 97, no. 11,
pp. 17861817, Nov. 2009.
[22] M. Farhadi Kangarlu and E. Babaei, Cross-switched multilevel inverter:
An innovative topology, IET Power Electron., vol. 6, no. 4, pp. 642651,
Apr. 2013.

Ebrahim Babaei (M10) was born in Ahar, Iran,

in 1970. He received the B.S. and M.S. degrees in
electrical engineering from the Department of Engineering, University of Tabriz, Tabriz, Iran, in 1992
and 2001, respectively, graduating with first class
honors, and the Ph.D. degree in electrical engineering from the Department of Electrical and Computer
Engineering, University of Tabriz, in 2007.
In 2004, he joined the Faculty of Electrical and
Computer Engineering, University of Tabriz. He was
an Assistant Professor from 2007 to 2011 and has
been an Associate Professor since 2011. He is the author of more than
230 journal and conference papers. His current research interests include the
analysis and control of power electronic converters, power system transients,
and power system dynamics.

Somayeh Alilu was born in Khoy, Iran, in 1983. She

received the B.S degree in electronics engineering
from Islamic Azad University, Tabriz, Iran, in 2007
and the M.S degree in electrical engineering from the
Science and Research Branch, Islamic Azad University, Tehran, Iran, in 2013.
She is currently with the Faculty of Electrical and
Computer Engineering, University of Tabriz, Tabriz.

Sara Laali (S12) was born in Tehran, Iran, in 1970.

She received the B.S. degree in electronics engineering from Islamic Azad University, Tabriz, Iran, in
2008 and the M.S. degree in electrical engineering
from Islamic Azad University, Tehran, Iran, in 2010.
She is currently working toward the Ph.D. degree in
electrical engineering in the Faculty of Electrical and
Computer Engineering, University of Tabriz, Tabriz.
In 2010, she joined the Department of Electrical Engineering, Adiban Higher Education Institute,
Semnan, Iran. Her major fields of interest include the
analysis and control of power electronic converters.