CCD4720 Back Illuminated

High Performance AIMO

Back Illuminated CCD Sensor
FEATURES
*

1024 by 1024 1:1 Image Format

Image Area 13.3 x 13.3 mm

Back Illuminated Format

Frame Transfer Operation

13 mm Square Pixels

Symmetrical Anti-static Gate Protection

Very Low Noise Output Amplifiers

Gated Dump Drain on Output Register

100% Active Area

Advanced Inverted Mode Operation (AIMO)

APPLICATIONS
*

Spectroscopy

Scientific Imaging

Star Tracking

Medical Imaging

INTRODUCTION
This version of the CCD47 family of sensors has full-frame
architecture. Back illumination technology, in combination with
extremely low noise amplifiers, makes the device well suited to
the most demanding scientific applications. To improve the
sensitivity further, the CCD is manufactured without antiblooming structures.
This device has a single serial output register. Separate charge
detection circuits are incorporated at each end of the register,
which is split so that a line of charge can be transferred to either
output, or split between the two.
The register is provided with a drain and control gate along the
outer edge of the channel for charge dump purposes.
The sensor is made using e2v technologies Advanced Inverted
Mode process to minimise dark current, allowing the device to
be operated with extended integration periods and minimal
cooling.
Other variants of the CCD47-20 available are front illuminated
format and non-inverted mode. In common with all e2v
technologies CCD Sensors, the CCD47-20 is also available with
a fibre-optic window or taper, or with a phosphor coating.
Designers are advised to consult e2v technologies should they
be considering using CCD sensors in abnormal environments or
if they require customised packaging.

TYPICAL PERFORMANCE
Maximum readout frequency
Output responsivity . . .
Peak signal . . . . . .
Dynamic range (at 20 kHz) .
Spectral range . . . . .
Readout noise (at 20 kHz) .

.
.
.
.
.
.

.
.
.
.
.
.

. . .
5
MHz
. . .
4.5
mV/e7
. . . 100 ke7/pixel
*50 000:1
200 1100
nm
. . .
2.0
e7 rms

GENERAL DATA
Format
Image area . . . . . . . . .
Active pixels (H) . . . . . . .
(V)
. . . . . . .
Pixel size . . . . . . . . . .
Storage area . . . . . . . . .
Pixels (H) . . . . . . . . . .
(V) . . . . . . . . . .
Additional pixels are provided in the
reference and over-scanning purposes.
Number of output amplifiers
. . .
Weight (approx, no window) . . .

13.3 x 13.3
mm
.
1024
.
1024
13 x 13
mm
13.3 x 13.3
mm
.
1024
.
1033
image area for dark
. . . . . . .
. .
7.5

2
g

Package
Package size . .
Number of pins .
Inter-pin spacing
Window material
Type . . . .

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

.
.
.
.
.

. . . 22.7 x 42.0 mm
. . . . . . .
32
. . . . .
2.54 mm
quartz or removable glass
. .
ceramic DIL array

e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU, UK Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
e-mail: [email protected] Internet: www.e2v.com
Holding Company: e2v technologies plc
e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148
e-mail: [email protected]

# e2v technologies (uk) limited 2007

A1A-100041 Version 7, September 2007

102636

PERFORMANCE
Min

Typical

Max
e7/pixel

Peak charge storage (see note 1)

60k

100k

Peak output voltage (no binning)

450

mV

Dark signal at 293 K (see notes 2 and 3)

250

500

e7/pixel/s

Dynamic range (see note 4)

50 000

Charge transfer efficiency (see note 5):

parallel
serial

Output amplifier responsivity (see note 3)

3.0

99.9999
99.9993

4.5

%
%
mV/e7

6.0

Readout noise at 253 K (see notes 3 and 6)

2.0

4.0

Maximum readout frequency (see note 7)

5.0

MHz

Dark signal non-uniformity (std. deviation)

(see notes 3 and 8)

125

e7/pixel/s

60

rms e /pixel

Spectral Response (at 253 K)

Wavelength
(nm)

Minimum Response (QE)

Midband Coated Broadband Coated

Uncoated

Maximum Response
Non-uniformity (1s)

300

not specified

not specified

not specified

350

15

25

10

400

40

55

25

500

85

75

55

650

85

75

50

900

30

30

30

ELECTRICAL INTERFACE CHARACTERISTICS

Electrode capacitances (measured at mid-clock level)
Min

Typical

Max

S1/S1 interphase

3.5

nF

I1/I1 interphase

3.5

nF

I1/SS and S1/SS

nF

R1/R1 interphase

40

4.5

pF

R1/(SS+DG+OD)

60

nF

1R/SS

10

pF

Output impedance (at typ. operating condition)

300

NOTES
1. Signal level at which resolution begins to degrade.
2. Measured between 253 and 293 K and VSS +9.5 V. Dark
signal at any temperature T (kelvin) between 230 and 300 K
may be estimated from:
Qd/Qd0 = 1.14 x 106T3e79080/T
where Qd0 is the dark signal at T = 293 K (20 8C).
Below 230 K, additional dark current components with a
weaker temperature dependence may become significant.
3. Test carried out at e2v technologies on all sensors.

A1A-100041, page 2

4. Dynamic range is the ratio of full-well capacity to readout

noise measured at 253 K and 20 kHz readout speed.
5. CCD characterisation measurements made using charge
generated by X-ray photons of known energy.
6. Measured using a dual-slope integrator technique (i.e.
correlated double sampling) with a 20 ms integration period.
7. Readout at speeds in excess of 5 MHz into a 15 pF load can
be achieved but performance to the parameters given
cannot be guaranteed.
8. Measured between 253 and 293 K, excluding white defects.

# e2v technologies

BLEMISH SPECIFICATION
Traps

Pixels where charge is temporarily held.

Traps are counted if they have a capacity
greater than 200 e7 at 253 K.
Slipped columns Are counted if they have an amplitude
greater than 200 e7.
Black spots
Are counted when they have a signal level
of less than 80% of the local mean at a
signal level of approximately half full-well.
White spots
Are counted when they have a generation
rate 125 times the specified maximum dark
signal generation rate (measured between
253 and 293 K). The typical temperature
dependence of white spot defects is different from that of the average dark signal
and is given by:
Qd/Qd0 = 122T3e76400/T
White column
A column which contains at least 21 white
defects.
Black column
A column which contains at least 21 black
defects.
GRADE

Column defects:
black or slipped

white

Black spots

50

100

200

Traps 4200 e7
White spots
Grade 5

12

50

80

100

Devices which are fully functioning, with

image quality below that of grade 2, and
which may not meet all other performance
parameters.

Note The effect of temperature on defects is that traps will be

observed less at higher temperatures but more may appear
below 253 K. The amplitude of white spots and columns will
decrease rapidly with temperature.

TYPICAL OUTPUT CIRCUIT NOISE

(Measured using clamp and sample)
VSS = 9.5 V VRD = 17 V VOD = 29 V
7

7508

NOISE EQUIVALENT SIGNAL (e7 rms)

6
5
4
3
2
1
0
10k
FREQUENCY (Hz)

# e2v technologies

50k

100k

500k

1M

A1A-100041, page 3

TYPICAL SPECTRAL RESPONSE (At 720 8C, no window)

100

8123

90

MIDBAND
COATED

80
BROADBAND
COATED
70

60

UNCOATED

50

40

QUANTUM EFFICIENCY (%)

30

20

10

0
300

400

500

600

700

800

900

1000

1100

WAVELENGTH (nm)

TYPICAL VARIATION OF DARK SIGNAL WITH SUBSTRATE VOLTAGE

106

7835

DARK SIGNAL AT 293 K (e7/pixel/s)

105

104

103

TYPICAL RANGE

102

10

0
1
2
3
SUBSTRATE VOLTAGE VSS (V)

A1A-100041, page 4

10

11

12

# e2v technologies

TYPICAL VARIATION OF DARK SIGNAL WITH TEMPERATURE (VSS = +9.5 V)

104

7329A

103

102

DARK SIGNAL (e7/pixel/s)

10

1071

1072
740
720
PACKAGE TEMPERATURE (8C)

20

40

DEVICE SCHEMATIC
7518

3 DARK REFERENCE ROWS

SS

32 SS

ABD

31 ABG

I13

30 S13

I12

29 S12

I11

28 S11
IMAGE SECTION
1024 x 1024 ACTIVE PIXELS
13 x 13 mm

SS

OG

26 DG

RDL

25 RDR

24

16 DARK
REFERENCE
COLUMNS

27 SS

OSL 10

23 OSR
STORE SECTION
1024(H) x 1033(V) ELEMENTS
13 x 13 mm

ODL 11

22 ODR

SS 12

21 SS

1RL 13

20 1RR
8 16

16 8

R13L 14

19 R13R

R12L 15

18 R12R

R11L 16

17 R11R
8 BLANK ELEMENTS

# e2v technologies

16 DARK
REFERENCE
COLUMNS

8 BLANK ELEMENTS

A1A-100041, page 5

CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS

PIN
1

REF

DESCRIPTION

SS

Substrate

PULSE AMPLITUDE OR
DC LEVEL (V) (See note 9)
Min
Typical
Max
8

9.5

11

MAXIMUM RATINGS
with respect to VSS

70.3 to +25 V

ABD

Anti-blooming drain (see note 10)

I13

Image area clock

12

15

16

+20 V

I12

Image area clock

12

15

16

+20 V

12

15

16

+20 V

11

I11

Image area clock

SS

Substrate

VOD

9.5

+20 V

15

17

19

70.3 to +25 V

OG

Output gate

RDL

Reset transistor drain (left amplifier)

No connection

10

OSL

Output transistor source (left amplifier)

11

ODL

Output transistor drain (left amplifier)

12

SS

Substrate

11

13

1RL

Output reset pulse (left amplifier)

12

15

+20 V

14

R13L

Output register clock (left section)

10

15

+20 V

15

R12L

Output register clock (left section)

10

15

+20 V

16

R11L

Output register clock (left section)

10

15

+20 V

17

R11R

Output register clock (right section)

10

15

+20 V

18

R12R

Output register clock (right section)

10

15

+20 V

19

R13R

Output register clock (right section)

10

15

+20 V

20

1RR

Output reset pulse (right amplifier)

12

15

+20 V

21

SS

Substrate

22

ODR

Output transistor drain (right amplifier)

23

OSR

Output transistor source (right amplifier)

24

No connection

25

RDR

Reset transistor drain (right amplifier)

26

DG

27

SS

28

S11

Storage area clock

12

29

S12

Storage area clock

30

S13

Storage area clock

31

ABG

32

SS

see note 11
27

8
27

29
9.5

9.5
29

n/a
32

11

32

70.3 to +35 V

see note 11

n/a

15

17

Dump gate (see note 12)

Substrate

9.5

70.3 to +35 V

19

70.3 to +25 V

+20 V

11

15

16

+20 V

12

15

16

+20 V

12

15

16

+20 V

Anti-blooming gate

+20 V

Substrate

9.5

11

Maximum voltages between pairs of

pin 10 (OSL) to pin 11 (ODL) .
pin 22 (ODR) to pin 23 (OSR) .
Maximum output transistor current

pins:
. . . . . +15
V
. . . . . +15
V
. . . . . . 10 mA

NOTES
Readout register clock pulse low levels +1 V; other clock low levels 0 + 0.5 V.
Drain not incorporated, but bias is still necessary.
3 to 5 V below OD. Connect to ground using a 2 to 5 mA current source or appropriate load resistor (typically 5 to 10 kO).
Non-charge dumping level shown. For operation in charge dumping mode, DG should be pulsed to 12 + 2 V.
All devices will operate at the typical values given. However, some adjustment within the minimum to maximum range may be
required to optimise performance for critical applications. It should be noted that conditions for optimum performance may differ
from device to device.
14. With the R1 connections shown, the device will operate through the right-hand output only. In order to operate from both
outputs R11(L) and R12(L) should be reversed.
9.
10.
11.
12.
13.

A1A-100041, page 6

# e2v technologies

FRAME TRANSFER TIMING DIAGRAM

7837

CHARGE COLLECTION PERIOD

1033 CYCLES
I11

I12

I13
Ti

51028 CYCLES

S11

S12
S13
SEE DETAIL OF
LINE TRANSFER

FRAME TRANSFER PERIOD

41 LINE TIME

R11

R12
R13

1R

OS
SEE DETAIL OF
OUTPUT CLOCKING

READOUT PERIOD

DETAIL OF FRAME TRANSFER

Tfi

Tti

7838A

I11

toi
I12

twti
I13

toi
S11

S12

S13

# e2v technologies

A1A-100041, page 7

DETAIL OF LINE TRANSFER

(For output from a single amplifier)
7836

Ti
S11

tdri

toi

S12

twi

tdir

S13

toi
R11

R12

R13

1R

A1A-100041, page 8

# e2v technologies

DETAIL OF VERTICAL LINE TRANSFER (Single line dump)

7843

S11

S12

S13

R11

R12

R13

1R

DG
END OF
PREVIOUS LINE
READOUT

LINE
TRANSFER
INTO
REGISTER

DUMP SINGLE LINE

FROM REGISTER TO
DUMP DRAIN

LINE
TRANSFER
INTO
REGISTER

START OF
LINE
READOUT

DETAIL OF VERTICAL LINE TRANSFER (Multiple line dump)

7844

S11

S12

S13

R11

R12

R13

1R

DG
END OF
PREVIOUS LINE
READOUT

# e2v technologies

1ST LINE

2ND LINE

3RD LINE

DUMP MULTIPLE LINE FROM REGISTER

TO DUMP DRAIN

CLEAR
READOUT
REGISTER

LINE
TRANSFER
INTO
REGISTER

START OF
LINE
READOUT

A1A-100041, page 9

DETAIL OF OUTPUT CLOCKING

7133A

R11
Tr

tor

R12

R13
twx

tdx

1R
SIGNAL
OUTPUT

OUTPUT
VALID
OS

RESET FEEDTHROUGH

LINE OUTPUT FORMAT

7512

8 BLANK

15 DARK REFERENCE

1024 ACTIVE OUTPUTS

15 DARK REFERENCE

8 BLANK

RECOMMENDED
DC CLAMP TIME

* = Partially shielded transition elements

CLOCK TIMING REQUIREMENTS

Symbol
Tfi
Tti
twti
Ti
twi
tri
tfi
toi
tdir
tdri
Tr
trr
tfr
tor
twx
trx, tfx
tdx

Description
First frame transfer pulse width
Frame transfer clock period
Frame transfer image clock pulse width
Store clock period
Image/store clock pulse width
Image/store clock pulse rise time (10 to 90%)
Image/store clock pulse fall time (10 to 90%)
Image/store clock pulse overlap
Delay time, S1 stop to R1 start
Delay time, R1 stop to S1 start
Output register clock cycle period
Clock pulse rise time (10 to 90%)
Clock pulse fall time (10 to 90%)
Clock pulse overlap
Reset pulse width
Reset pulse rise and fall times
Delay time, 1R low to R13 low

Min

Typical

Max

100
7
3.5
50
25
0.1
tri
(tri+tfi)/2
1
1
200
50
trr
20
30
0.2twx
30

150
10
5
100
50
5
5
5
2
1
1000
0.1Tr
0.1Tr
0.5trr
0.1Tr
0.5trr
0.5Tr

see note 15
see note 15
0.2Tfi
see note 15
see note 15
0.2Ti
0.2Ti
0.2Ti
see note 15
see note 15
see note 15
0.3Tr
0.3Tr
0.1Tr
0.3Tr
0.1Tr
0.8Tr

ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns

NOTES
15. No maximum other than that necessary to achieve an acceptable dark signal at the longer readout times.

A1A-100041, page 10

# e2v technologies

OUTPUT CIRCUIT
8074

RD

R13

1R

S12 (SEE
NOTE 16)

OD

OG
OS

OUTPUT

EXTERNAL
LOAD (SEE
NOTE 17)

SS

SS

0V

NOTES
16. The amplifier has a DC restoration circuit which is internally
activated whenever S12 is high.
17. Not critical; can be a 3 to 5 mA constant current supply or
an appropriate load resistor.

# e2v technologies

A1A-100041, page 11

OUTLINE
(All dimensions without limits are nominal)
A

7522A

M
32

17

IMAGE AREA
N

16

PIN 1
INDICATOR

TEMPORARY COVERGLASS

L
IMAGE PLANE

Ref

Millimetres

A
B
C
D
E

42.00 + 0.42
22.73 + 0.26
16.60 + 0.25
3.64 + 0.37
22.86 + 0.25
+ 0.051
0.254
7 0.025
5.0 + 0.5
0.457 + 0.051
2.54 + 0.13
38.1
1.65 + 0.25
13.3
13.3
12.2 + 0.5

J PITCH

F
K

A1A-100041, page 12

G
H
J
K
L
M
N
P

# e2v technologies

ORDERING INFORMATION

HANDLING CCD SENSORS

Options include:

CCD sensors, in common with most high performance MOS IC

devices, are static sensitive. In certain cases a discharge of
static electricity may destroy or irreversibly degrade the device.
Accordingly, full antistatic handling precautions should be
taken whenever using a CCD sensor or module. These include:-

Temporary Quartz Window

Permanent Quartz Window

Temporary Glass Window

Permanent Glass Window

Working at a fully grounded workbench

Fibre-optic Coupling

Operator wearing a grounded wrist strap

X-ray Phosphor Coating

All receiving socket pins to be positively grounded

Unattended CCDs should not be left out of their conducting

foam or socket.

*
*

For further information on the performance of these and other

options, please contact e2v technologies.

Evidence of incorrect handling will invalidate the warranty.

HIGH ENERGY RADIATION

Device characteristics will change when subject to ionising
radiation.
Users planning to operate CCDs in high radiation environments
are advised to contact e2v technologies.

TEMPERATURE LIMITS
Min
Typical Max
Storage . . . . . . . 153

373
K
Operating . . . . . . . 153
273
323
K
Operation or storage in humid conditions may give rise to ice on
the sensor surface on cooling, causing irreversible damage.
Maximum device heating/cooling
. . . .
5 K/min

Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use
thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in its standard
conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.

# e2v technologies

Printed in England

A1A-100041, page 13