ECA

COURSE FILE

Courses file contents:

1. Cover Page
2. Syllabus copy
3. Vision of the Department
4. Mission of the Department
5. PEOs and POs
6. Course objectives and outcomes
7. Brief note on the course &how it fits in to the curriculum
8. Prerequisite, if any
9. Instructional Learning Outcomes
10. Course mapping with PEOs and POs
11. Class Time Table
12. Individual Time Table
13. Lecture schedule with methodology being used/adopted.
14. Detailed notes
15. Additional topics
16. University Question papers of previous years
17. Question Bank
18. Assignment questions
19. Unit wise Quiz Questions and long answer questions
20. Tutorial problems
21. Known gaps ,if any and inclusion of the same in lecture schedule
22. Discussion topics if any
23. References, Journals, websites and E-links
24. Quality Control Sheets. a)course end survey b)Teaching Evaluation
25. Student List
26. Group-Wise students list for discussion topics

GEETHANJALICOLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF Electronics and Communication Engineering
(Name of the Subject ) : Electronic Circuit Analysis
(JNTU CODE A40412)

Course file

Programme : UG

Branch: ECE
Year: II ECE A/B/C/D

IIDocument No. GCET/ECE/----/-----

Semester: 2

No.of pages :

Classification status (Unrestricted / Restricted ) : Unrestricted

Distribution List : Dept. Library, Dept Office, Concerned Faculty
Prepared by

Updated by

1) Name : Mr.G.Madhu

1)Name :Dr.C.Venkata Narasimhulu

2) Sign

2) Sign : Professor and HOD.

: Assistant professor

3) Design:
4) Date

3) Design :
: 15-12-2014

4) Date :25-11-2015

Verified by : 1) Name : Mr.U.Appala Raju

&Mr.A.Shankar
2) Sign

1) Name :
2) Sign

3) Design :Associate Professor

4) Date

* For Q.C Only.

: 30-11-2015

2) Sign

3) Design :
4) Date

Approved by : (HOD ) 1) Name :Dr.P.Srihari

:

3) Date :

2. Syllabus:

3. VISION OF THE DEPARTMENT

To impart quality technical education in Electronics and Communication Engineering
emphasizing analysis, design/synthesis and evaluation of hardware/embedded software using
various Electronic Design Automation (EDA) tools with accent on creativity, innovation and
research thereby producing competent engineers who can meet global challenges with societal
commitment.

4. MISSION OF THE DEPARTMENT

i. To impart quality education in fundamentals of basic sciences, mathematics, electronics and
communication engineering through innovative teaching-learning processes.
ii. To facilitate Graduates define, design, and solve engineering problems in the field of
Electronics and Communication Engineering using various Electronic Design Automation
(EDA) tools.
iii. To encourage research culture among faculty and students thereby facilitating them to be
creative and innovative through constant interaction with R & D organizations and Industry.
iv. To inculcate teamwork, imbibe leadership qualities, professional ethics and social
responsibilities in students and faculty
5. PEOS AND POS
5.1 Program Educational Objectives of B. Tech (ECE) Program :

I.

To prepare students with excellent comprehension of basic sciences, mathematics and

engineering subjects facilitating them to gain employment or pursue postgraduate studies
with an appreciation for lifelong learning.

II.

To train students with problem solving capabilities such as analysis and design with
adequate practical skills wherein they demonstrate creativity and innovation that would
enable them to develop state of the art equipment and technologies of multidisciplinary
nature for societal development.

To inculcate positive attitude, professional ethics, effective communication and interpersonal

skills which would facilitate them to succeed in the chosen profession exhibiting creativity and
innovation through research and development both as team member and as well as leader.

5.2 Program Outcomes of B.Tech ECE Program:

1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve

complex engineering problems of Electronics and Communication Engineering systems.
2. An ability to model, simulate and design Electronics and Communication Engineering
systems, conduct experiments, as well as analyze and interpret data and prepare a report
with conclusions.
3. An ability to design an Electronics and Communication Engineering system, component,
or process to meet desired needs within the realistic constraints such as economic,
environmental, social, political, ethical, health and safety, manufacturability and
sustainability.
4. An ability to function on multidisciplinary teams involving interpersonal skills.
5. An ability to identify, formulate and solve engineering problems of multidisciplinary
nature.
6. An understanding of professional and ethical responsibilities involved in the practice of
Electronics and Communication Engineering profession.
7. An ability to communicate effectively with a range of audience on complex engineering
problems of multidisciplinary nature both in oral and written form.
8. The broad education necessary to understand the impact of engineering solutions in a
global, economic, environmental and societal context.
9. A recognition of the need for, and an ability to engage in life-long learning and acquire
the capability for the same.
10. A knowledge of contemporary issues involved in the practice of Electronics and
Communication Engineering profession
11. An ability to use the techniques, skills and modern engineering tools necessary for
engineering practice.

12. An ability to use modern Electronic Design Automation (EDA) tools, software and
electronic equipment to analyze, synthesize and evaluate Electronics and Communication
Engineering systems for multidisciplinary tasks.
13. Apply engineering and project management principles to one's own work and also to

manage projects of multidisciplinary nature.

6. Course objectives and outcomes:

Course objectives
1. To develop the basic understanding of amplifier designing and its analysis using hybrid
model
2. To make students aware of amplifier operation at low and high frequency and its frequency
responses.
3. To make students learn about different types of feedback amplifiers and oscillators.
4. To make students aware of large signal amplifiers.
5. To make students learn about different types of Tuned amplifiers.

Course outcomes:
After finishing the course, the students are able to:
CO1: Explain classification of amplifiers and analyze the CE, CB, CC amplifiers using
small signal hybrid model and derive the voltage gain, current gain, input impedance and
output impedance.
CO2: Design and analyze the cascaded RC coupled BJT amplifier and different types of
the coupled amplifiers.
CO3: Design and analyze single stage amplifiers and their frequency response, its gain
band width product and effect of coupling and bypass capacitors in amplifiers.
CO4: Design and analyze different types of the MOS amplifiers and their frequency
response by using the small signal model.
CO5: Design and analyze the different types of feedback amplifiers.
CO6: Explain the condition for oscillations in oscillators, design and analyze different
types of oscillators.
CO7: Design and analyze different types of power amplifiers and compare them in terms
of efficiency.
CO8: Design and analyze the effects of cascading on single, double tuned amplifiers on
bandwidth and explain their stability.

7.Brief note on the course & how it fits into the curriculum
This course is a one of the core courses of this program . In order to study VLSI Design, various
Analog Design in IV-year I-sem and M.Tech level, it will help to understand the concepts of
analog communication subject in III-B.Tech I- sem and also will help to under stand the concepts
of IC Applications in III-B.Tech I- sem.

8. Prerequisite, if any
Student should know the basic concepts of Electronics Devices and Circuits and Electrical
circuits.

9. INSTRUCTIONAL LEARNING OUTCOMES

After the completition of the each lecture,the students will be able to
1. Analyse different types of single stage amplifiers by using small signal model.
2. Design different types of single stage amplifiers.
3. Identify and calculate different types of distortions and percentage of distortions in amplifiers.
4. Analyse different types of multi stage amplifiers by using small signal model.
5. Design different types of multi stage amplifiers.
6. Distinguish between the different types of cascading schemes in multi stage amplifiers.
7. Analyse different types of single stage amplifiers by using hybrid-pi model.
8. Calculate 3-dB frequencies in multi stage amplifiers.
9. Analyse and design different types of MOS amplifiers by using small signal model.
10.Distinguish between negative and positive feedback in amplifiers.
11. Analyse and Design different types of feedback amplifiers.
12 .Analyse and Design different types of Oscillators.
13. Analyse and Design different types of Power amplifiers and calculate their efficiency.
14. Analyse and Design different types of Tuned amplifiers.

10. Course mapping with PEOs and POs

Relationship of the course to program outcomes :

1.An ability to apply knowledge of Mathematics, Science, and Engineering to solve

complex engineering problems of Electronics and Communication Engineering

systems.
2.An ability to model, simulate and design Electronics and Communication
Engineering systems, conduct experiments, as well as analyze and interpret data and
prepare a report with conclusions

3. An ability to design an Electronics and Communication Engineering system,

component, or process to meet desired needs within the realistic constraints such as
economic,

environmental,

social,

political,

ethical,

health

and

safety,

manufacturability and sustainability.

4. An ability to function on multidisciplinary teams involving interpersonal skills.

5. An ability to identify, formulate and solve engineering problems of

multidisciplinary nature.

6.An understanding of professional and ethical responsibilities involved in the

practice of Electronics and Communication Engineering profession
7. An ability to communicate effectively with a range of audience on complex
engineering problems of multidisciplinary nature both in oral and written form.
8.The broad education necessary to understand the impact of engineering solutions
in a global, economic, environmental and societal context
9. A recognition of the need for, and an ability to engage in life-long learning and

acquire the capability for the same.

10.A knowledge of contemporary issues involved in the practice of Electronics and
Communication Engineering profession
11.An ability to use the techniques, skills and modern engineering tools necessary
for engineering practice.
12.An ability to use modern Electronic Design Automation (EDA) tools, software
and electronic equipment to analyze, synthesize and evaluate Electronics and
Communication Engineering systems for multidisciplinary tasks.
13. Apply engineering and project management principles to one's own work and
also to manage projects of multidisciplinary nature

Relationship of the course to the program educational objectives :

I.

To prepare students with excellent comprehension of basic

sciences, mathematics and engineering subjects facilitating them
to gain employment or pursue postgraduate studies with an
appreciation for lifelong learning.

2. To train students with problem solving capabilities such as analysis

and design with adequate practical skills wherein they demonstrate
creativity and innovation that would enable them to develop state of the
art equipment and technologies of multidisciplinary nature for societal
development.
3.To inculcate positive attitude, professional ethics, effective
communication and interpersonal skills which would facilitate them to
succeed in the chosen profession exhibiting creativity and innovation
through research and development both as team member and as well as
leader

Class Time Table

11.Class time table

Time table of concerned classes

Department of Electronics & Communication Engineering
Year/Sem/Sec: II-B. Tech-I Sem-C Section
Class
Incharge:
09.30- 10.20- 11.10Time
10.20
11.10
12.00
Period

Room no.: LH-17

12.00-12.50

Acad Year 2014-15, WEF: 29-12-2014

12.5013.30

13.3014.20

14.2015.10

15.10-16.00

Subject
Code

Periods/Week

LUNCH

Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
No

Subject(T/P)

1
2

3
4
5
6
7

8
9
10

11
12
13

12.Individual Time table

Individual time table

ECA-II ECE- 2-2 A

Faculty Name

Hard copy available

Work Load: 11
III
IV

W.E.F: 29/12/14
VI
VII

LUNCH

Name: Dr.C.Venkata Narasimhulu

I
II
Day/Hour
MON
TUE
WED
THU
FRI
SAT

13. Lecture schedule with methodology being used/adopted.

UNIT-I: Singlestage and Multistage Amplifiers
(a) Single stage Amplifiers:
(b) Multistage Amplifiers
UNIT-II: BJT Amplifiers and MOS Amplifiers
(a) BJT Amplifiers:
(b) MOS Amplifiers:
UNIT-III: Feedback Amplifiers and Oscillators
(a) Feedback Amplifiers:
(b) Oscillators:
UNIT-IV: Large Signal Amplifiers
UNIT-IV: Tuned Amplifiers
Introduction:
Electronic circuit analysis subject teaches about the basic knowledge required to design an
amplifier circuit, oscillators etc..It provides a clear and easily understandable discussion of designing
of different types of amplifier circuits and their analysis using hybrid model, to find out their
parameters. Fundamental concepts are illustrated by using small examples which are easy to
understand. It also covers the concepts of MOS amplifiers ,oscillators and large signal amplifier.

MICROPLAN
Sl.no

Unit

1.

2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

12.
13.
14.
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II

18.
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20.
21.
22.
23.
24.
25.

26.
27.
28.
29.
30.
31.
32.
33.

III

Topics to be covered
(a)Single Stage Amplifiers: classification of amplifiers ,
Distortion in Amplifiers.
Analysis of CE configuration using simplified hybrid
model.
Analysis of CB & CC configuration using simplified
hybrid model.
Analysis of CE Amplifier with Emitter resistance.
Analysis of Emitter follower.
Millers Theorem and its Dual.
Design of single stage RC coupled amplifier using BJT.
Design of single stage RC coupled amplifier using BJT
Revision class with problems
Assignment Test
(b)Multi Stage Amplifiers: Analysis of Cascaded RC
coupled BJT amplifiers.
Cascode Amplifier, Darlington pair.
RC coupled Amplifier, Direct coupled amplifier
Transformer coupled amplifier.
Solving University papers- problems.
Assignment test
(a)BJT Amplifiers Frequency Response: Logarithims,
Decibles, General frequency considerations.
Frequency response of BJT Amplifier,
Effect of Coupling capacitor and B ypass capacitor.
The Hybrid pi- common emitter transistor model.
CE short circuit current gain, current gain with resistive
load.
Single stage CE transistor amplifier response,Gain
bandwidth product.
Emitter follower at high frequencies.
Tutorial class
(b)MOS Amplifiers:Basic concepts, MOS small signal
model.
Common Source amplifier with resistive load.
Diode Connected load and current source load.
Source follower, folded cascode amplifier and their
frequency response.
Common stage gate cascode amplifier
Tutorial Class
Solving University papers
Assignment test
(a)Feedback Amplfiers: concepts of feedback and

Additional topics

Effect of cascading
on Bandwidth in
multistage amplifiers.

Characteristics of
MOS transistor to
obtain small signal
equivalent model

classification of feedback amplifiers

General charactersistics of negative feedback amplifiers.
Effect of feed back on amplifier characteristics.
Voltage shunt and voltage series feedback configurations.
Current shunt and current series feedback configurations.

34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.

49.

Problems
University papers
Assignment test.
(c)Oscillators:introduction
Classification of oscillators
Conditions for oscillations
RC phase shift oscillator
Generalized analysis of LC oscillators
Hartley and colpitts oscillators
Wein bridge & crystal oscillators
Stability of oscillators
University papers
Assignment test
IV

50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.

Concept of positive
feedback its
characteristics

Large signal amplifiers

Classification ,class A large signal amplifiers
Transformer coupled class A audio power
amplifier,efficiency of class A amplifier
class B amplifier,efficiency of class B amplifier
Complementary symmetry class B push pull amplifier
Tuned amplifiers
Introduction, Q-factor
Small signal tuned amplifiers
Effect of cascading single tuned amplifiers on band width
Effect of cascading double tuned amplifiers on band
width
Stagger tuned amplifiers,
Stability of tuned amplifiers
Solving University papers
Assignment test

Tuned circuits its

working principle used
in tuned amplifiers

Unit wise Summary

S.no

Unit

1.

Total
no of
Periods

Topics to be covered

13

Single Stage
Amplifiers:classification of
amplifiers , Distortion in
Amplifiers.
Analysis of CE configuration
using simplified hybrid model.
Analysis of CB & CC
configuration using simplified
hybrid model.
Analysis of CE Amplifier with
Emitter resistance.
Analysis of Emitter follower.
Millers Theorem and its Dual.
Design of single stage RC
coupled amplifier using BJT.
Design of single stage RC
coupled amplifier using BJT
Revision class with problems
Assignment Test
Multi Stage
Amplifiers:Analysis of
Cascaded RC coupled BJT
amplifiers.
Cascode Amplifier, Darlington
pair.
RC coupled Amplifier, Direct
coupled amplifier
Transformer coupled amplifier.
Effect of cascading on
Bandwidth in multistage
amplifiers.
Assignment test
BJT Amplifiers Frequency
Response:Logarithims,Decibles,
General frequency
considerations.
Frequency response of BJT
Amplifier,
Effect of Coupling capacitor and

2.
3.

4.
5.
6.
7.
8.
9.
10.
11.

12.
13.
14.
15.

16.
17.

18.
19.

II

14

Reg/
Additional

Regular

Teaching
aids
used
LCD/OHP
/BB
,BB

Regular

BB

Regular

BB

Regular

BB

Regular
Regular
Regular

BB
BB
BB
BB

Regular

OHP,BB

Regular

BB

Regular

BB

Regular

BB

Regular
Additional

BB
BB

Regular

BB

Regular
Regular

BB

Remarks

20.
21.
22.

23.
24.
25.

26.
27.
28.

29.
30.
31.

32.
33.

34.
35.
36.
37.
38.
39.
40.
41.
42.

III

15

B y pass capacitor.
The Hybrid pi- common emitter
transistor model.
CE short circuit current gain,
current gain with resistive load.
Single stage CE transistor
amplifier response,Gain
bandwidth product.
Emitter follower at high
frequencies.
Tutorial class
MOS Amplifiers:Basic
concepts, MOS small signal
model.
Common Source amplifier with
resistive load.
Diode Connected load and
current source load.
Source follower, folded cascode
amplifier and their frequency
response.
Common stage gate cascode
amplifier
Tutorial Class
Characteristics of MOS
transistor to obtain small signal
equivalent model
Assignment test
Feedback Amplfiers: concepts
of feedback and classification of
feedback amplifiers
General charactersistics of
negative feedback amplifiers.
Effect of feed back on amplifier
characteristics.
Voltage shunt and voltage series
feedback configurations.
Current shunt and current series
feedback configurations.
Concept of positive feedback its
characteristics
Problems
University papers
Assignment test.
Oscillators:introduction

Regular

OHP,BB

Regular

BB

Regular

BB

Regular

OHP,BB

Regular
Regular

BB
OHP,BB

Regular

OHP,BB

Regular

BB

Regular

OHP,BB

Regular

OHP,BB

Regular
Additional

BB
OHP,BB

Regular

BB

Regular

OHP,BB

Regular

OHP,BB

Regular

BB
BB

Additional

BB

Regular
Regular
Regular
Regular

BB
BB
OHP,BB
BB

43.
44.
45.
46.
47.
48.
49
50
51.
52.

IV

12

53.

54.
55
56.

10

57.
58.
59.
60.
61

62.
63.
64.

Classification of oscillators
Conditions for oscillations
RC phase shift oscillator
Generalized analysis of LC
oscillators
Hartley and colpitts oscillators
Wein bridge & crystal oscillators
Stability of oscillators
University papers
Assignment test
Large signal amplifiers:
Classification ,class A large
signal amplifiers
Transformer coupled class A
audio power amplifier,efficiency
of class A amplifier
class B amplifier,efficiency of
class B amplifier
Complementary symmetry class
B push pull amplifier
Tuned amplifiers: Introduction,
Q-factor
Small signal tuned amplifiers

Regular
Regular
Regular
Regular

BB
BB
BB
BB

Regular
Regular
Regular

BB
BB
BB
BB

Regular

BB

Regular

BB

Regular

BB

Regular

OHP,BB

Regular

OHP,BB

Regular

OHP,BB

Effect of cascading single tuned

amplifiers on band width
Effect of cascading double tuned
amplifiers on band width
Stagger tuned amplifiers
Tuned circuits its working
principle used in tuned
amplifiers
Stability of tuned amplifiers
Solving University papers
Assignment test

Regular
Regular

BB

Regular
Additional

BB
BB

Regular
Regular

BB
OHP,BB

GUIDELINES
Distribution of periods:

No. of classes required to cover JNTU syllabus : 64

No. of classes required to cover Additional topics : 4
No. of classes required to cover Assignment tests (for every 2 units 1 test) : 3
No. of classes required to cover tutorials: 8
No. of classes required to cover Mid tests: 2
No of classes required to solve University: 2

14. Detailed notes

UNIT I

H Parameter model : The equivalent circuit of a transistor can be dram using simple approximation by retaining its
essential features.
These equivalent circuits will aid in analyzing transistor circuits easily and rapidly.

Two port devices & Network Parameters: A transistor can be treated as a two part network. The terminal behaviour of any two part
network can be specified by the terminal voltages V1 & V2 at parts 1 & 2 respectively and current i1 and
i2, entering parts 1 & 2, respectively, as shown in figure.

Two port network

Of these four variables V1, V2, i1 and i2, two can be selected as independent variables and the
remaining two can be expressed in terms of these independent variables. This leads to various two part
parameters out of which the following three are more important.
1. Z Parameters (or) Impedance parameters
2. Y Parameters (or) Admittance parameters
3. H Parameters (or) Hybrid parameters.

Hybrid parameters (or) h parameters: If the input current i1 and output Voltage V2 are takes as independent variables, the input
voltage V1 and output current i2 can be written as
V1 = h11 i1 + h12 V2
i2 = h21 i1 + h22 V2
The four hybrid parameters h11, h12, h21 and h22 are defined as follows.

h11 = [V1 / i1] with V2 = 0

= Input Impedance with output part short circuited.
h22 = [i2 / V2] with i1 = 0
= Output admittance with input part open circuited.
h12 = [V1 / V2] with i1 = 0
= reverse voltage transfer ratio with input part open circuited.
h21 = [i2 / i1] with V2 = 0
= Forward current gain with output part short circuited.

The dimensions of h parameters are as follows:

h11 -
h22 mhos
h12, h21 dimension less.
as the dimensions are not alike, (ie) they are hybrid in nature, and these parameters are
called as hybrid parameters.
I = 11 = input ; 0 = 22 = output ;
F = 21 = forward transfer ; r = 12 = Reverse transfer.

Notations used in transistor circuits:hie = h11e = Short circuit input impedance

h0e = h22e = Open circuit output admittance
hre = h12e = Open circuit reverse voltage transfer ratio
hfe = h21e = Short circuit forward current Gain.

The Hybrid Model for Two-port Network:-

V1 = h11 i1 + h12 V2
I2 = h1 i1 + h22 V2


V1 = h1 i1 + hr V2
I2 = hf i1 + h0 V2

The Hybrid Model for Two-port Network

Transistor Hybrid model:Use of h parameters to describe a transistor have the following

advantages.
1.
2.
3.
4.
5.
6.

h parameters are real numbers up to radio frequencies .

They are easy to measure
They can be determined from the transistor static characteristics curves.
They are convenient to use in circuit analysis and design.
Easily convert able from one configuration to other.
Readily supplied by manufactories.

CE Transistor Circuit
To Derive the Hybrid model for transistor consider the CE circuit shown in figure.The variables
are iB, ic, vB(=vBE) and vc(=vCE). iB and vc are considered as independent variables.
Then ,

vB= f1(iB, vc ) ----------------------(1)

iC= f2(iB, vc ) ----------------------(2)

Making a Taylors series expansion around the quiescent point IB, VC and neglecting higher order
terms, the following two equations are obtained.
vB =

(f /i )

. iB + f1/vc

iC =

(f /i )

. iB + f2/vc

IB

B Vc

B Vc

IB

. vC ---------------(3)

. vC ----------------(4)

The partial derivatives are taken keeping the collector voltage or base current constant as
indicated by the subscript attached to the derivative.
vB , vC , iC , iB represent the small signal(increment) base and collector voltages and
currents,they are represented by symbols vb , vc , ib and ic respectively.
Eqs (3) and (4) may be written as

Vb = hie ib + hre Vc
ic = hfe ib + hoe Vc

Where

hie =(f1/iB) c =
V

(v /i ) = (v /i ) = (v / i )
B

hre =(f1/vc)I =
B

B Vc

B Vc

b Vc

(v /v ) = (v /v ) = (v /v )
B

IB

IB

hfe =(f2/iB) c =

(i /i ) = ( i /i ) = (i / i )

hoe= (f2/vc)I =

(i /v ) = ( i /v ) = (i /v )

B Vc

IB

B Vc

IB

b Vc

IB

IB

The above equations define the h-parameters of the transistor in CE configuration.The same
theory can be extended to transistors in other configurations.
Hybrid Model and Equations for the transistor in three different configurations are are given
below.

MULTISTAGE AMPLIFIER
Introduction to feedback (block diagram and types of feedback), Analysis at mode, low and
high frequency of multistage amplifier with RC coupling and direct coupling, cascade
amplifiers-Darlington Pair.

Concept of multistage / cascade amplifier.

The performance obtainable from a single stage amplifier is often insufficient for many applications,
hence several stages may be combined forming a multistage amplifier. These stages may be combined
forming a multistage amplifier. These stages are connected in cascade, i.e. output of the first stage is
connected to form input of second stage, whose output becomes input of third stage, and so on.

The overall gain of a multistage amplifier is the product of the gains of the individual stage (ignoring
potential loading effects):

Gain (A) = A1 * A2 * A3 * A4 * *An.

Alternately, if the gain of each amplifier stage is expressed in decibels (dB), the total gain is the sum of
the gains of the individual stages :

Gain in dB (A) = A1 + A2 + A3 + A4 + + An.

When we want to achieve higher amplification than a single stage amplifier can offer, it is a common practice to
cascade various stages of amplifiers, as it is shown in Fig.1.a. In such a structure the input performance of the
resulted multistage amplifier is the input performance of the first amplifier while the output performance is that of the
last amplifier. It is understood that combining amplifiers of various types we can create those characteristics that are
necessary to fulfill the specifications of a specific application. In addition, using feedback techniques in properly
chosen multistage amplifiers can further increase this freedom of the design.

Fig.1 a) A Multistage amplifier configuration b) Small-signal equivalent of the amplifier in Fig.1a

According to the small signal equivalent circuit of a two stage amplifier shown in Fig.1.b, we can calculate the ac
performance of the circuit.
Voltage amplification:

Current amplification:

Power amplification:

In conclusion, the gain is the product of the gains of the individual stages (properly terminated).

Analysis of multistage amplifier.

i)

RC coupling configuration

One way to connect various stages of a multistage amplifier is via capacitors, as indicated in the two-stage amplifier
in Fig.3. where two stages of common emitter amplifiers are coupled to each other by the capacitor C 3.

Fig.3 A typical configuration of an RC-coupled amplifier

In RC-coupled amplifiers:

The various stages are DC isolated. This feature facilitates the biasing of individual stages.
The various stages can be similar. Hence the design of the amplifier is simplified.
The coupling capacitors influence the responses of the amplifier.
A great number of biasing resistors is necessary.

RC-coupled transistor amplifier.

The most commonly used coupling in amplifiers is RC coupling. An RC-coupling network is shown in the illustration
above.
The network of R1, R2, and C1 enclosed in the dashed lines of the figure is the coupling network. You may notice
that the circuitry for Q1 and Q2 is incomplete. That is intentional so that you can concentrate on the coupling network.
R1 acts as a load resistor for Q1 (the first stage) and develops the output signal of that stage. Do you remember how
a capacitor reacts to ac and dc? The capacitor, C1, "blocks" the dc of Q1's collector, but "passes" the ac output
signal. R2 develops this passed, or coupled, signal as the input signal to Q2 (the second stage).
This arrangement allows the coupling of the signal while it isolates the biasing of each stage. This solves many of the
problems associated with direct coupling.

ii)

Direct coupling configuration

a)

The CE-CC configuration

in practical amplifier
circuits, since it provides good voltage, current, and power gain. The input to the CE is applied to
The COMMON-EMITTER CONFIGURATION (CE) is the most frequently used configuration

the base-emitter circuit and the output is taken from the collector-emitter circuit, making the emitter the element

"common" to both input and output. The CE is set apart from the other configurations, because it is the only
configuration that provides a phase reversal between input and output signals.

Common emitter configuration:

In this configuration emitter terminal is conncted as a common terminal.

The input is applied between the base and emitter terminals.The output is taken between the collector and base
terminals.

Input characteris

The output voltage VCE is maintained constant and the input voltage VBE is set at several convenient levels.For each
level of input voltage, the input current IB is recorded.
IB is then plotted versus VBE to give the common-base input character

Output characteristic

The Base current IB is held constant at each of several fixed levels. For each fixed value of IB , the output voltage
VCE is adjusted in convenient steps and the corresponding levels of collector current IC are recorded
For each fixed value of IB, IC level is Recorded at each VCE step.For each IB level, IC is plotted versus VCE to give a
family of characteristics.

Common collector configuration:

In this configuration collector terminal is conncted as a common terminal.

The input is applied between the base and collector terminals.The output is taken between the emitter
and collector t

Input characteristics:

The common-collector input characteristics are quite different from either common base or common-emitter input
characteristics.
The difference is due to the fact that the input voltage (VBC) is largely determined by (VEC) level .

VEC = VEB + VBC

VEB = VEC - VBC

Output characteristics:

The operation is much similar to that of C-E configuration.When the base current is ICO, the emitter current will be
zero and consequently no current will flow in the load.
When the base current is increased, the transistor passes through active region and eventually reaches saturation.
Under the saturation conditions all the supply voltage, except for a very small drop across the transistor will appear
across the load resistor.

b)

The Darlington Pair

This is two transistors connected together so that the amplified current from the first is amplified further by the second
transistor. This gives the Darlington pair a very high current gain such as 10000. Darlington pairs are sold as
complete packages containing the two transistors. They have three leads (B, C and E) which are equivalent to the
leads of a standard individual transistor.
The overall current gain is equal to the two individual gains multiplied together:
Darlington pair current gain, hFE = hFE1 hFE2
(hFE1 and hFE2 are the gains of the individual transistors)
This gives the Darlington pair a very high current gain, such as 10000, so that only a tiny base current is required to
make the pair switch on.
A Darlington pair behaves like a single transistor with a very high current gain. It has three leads (B, C and E) which
are equivalent to the leads of a standard individual transistor. To turn on there must be 0.7V across both the baseemitter junctions which are connected in series inside the Darlington pair, therefore it requires 1.4V to turn on.
Darlington pairs are available as complete packages but you can make up your own from two transistors; TR1 can be
a low power type, but normally TR2 will need to be high power. The maximum collector current Ic(max) for the pair is
the same as Ic(max) for TR2.

A Darlington pair is sufficiently sensitive to respond to the small current passed by your skin and it can be used to
make a touch-switch as shown in the diagram. For this circuit which just lights an LED the two transistors can be
any general purpose low power transistors. The 100k resistor protects the transistors if the contacts are linked with
a piece of wire.
Two transistors may be combined to form a configuration known as the Darlington pair which behaves like a single
transistor with a current gain equivalent to the product of the current gain of the two transistors. This is especially
useful where very high currents need to be controlled as in a power amplifier or power-regulator circuit. Darlington
transistors are available whereby two transistors are combined in one single package. The base-emitter volt-drop is
twice that of a
small transistor.

ii)

The transformer coupling configuration

Figure 3 shows a transformer-coupling network between two stages of amplification. The transformer action of T1
couples the signal from the first stage to the second stage. In figure 1-12, the primary of T1 acts as the load for the
first stage (Q1) and the secondary of T1 acts as the developing impedance for the second stage (Q2). No capacitor is
needed because transformer action couples the signal between the primary and secondary of T1.

Figure 3.Transformer-coupled transistor amplifier.

The inductors that make up the primary and secondary of the transformer have very little dc resistance, so the
efficiency of the amplifiers is very high. Transformer coupling is very often used for the final output (between the final
amplifier stage and the output device) because of the impedance-matching qualities of the transformer. The
frequency response of transformer-coupled amplifiers is limited by the inductive reactance of the transformer just as it
was limited in impedance coupling.
The circuit in Figure below (a) is a simplified transformer coupled push-pull audio amplifier. In push-pull, pair of
transistors alternately amplify the positive and negative portions of the input signal. Neither transistor nor the other
conducts for no signal input. A positive input signal will be positive at the top of the transformer secondary causing
the top transistor to conduct. A negative input will yield a positive signal at the bottom of the secondary, driving the
bottom transistor into conduction. Thus the transistors amplify alternate halves of a signal. As drawn, neither
transistor in Figure below (a) will conduct for an input below 0.7 Vpeak. A practical circuit connects the secondary
center tap to a 0.7 V (or greater) resistor divider instead of ground to bias both transistor for true class B.

(a) Transformer coupled push-pull amplifier. (b) Direct coupled complementary-pair amplifier replaces transformers
with transistors.
The circuit in Figure above (b) is the modern version which replaces the transformer functions with transistors.
Transistors Q1 and Q2 are common emitter amplifiers, inverting the signal with gain from base to collector. Transistors
Q3 and Q4 are known as a complementary pair because these NPN and PNP transistors amplify alternate halves
(positive and negative, respectively) of the waveform. The parallel connection the bases allows phase splitting without
an input transformer at (a). The speaker is the emitter load for Q3 and Q4. Parallel connection of the emitters of the
NPN and PNP transistors eliminates the center-tapped output transformer at (a) The low output impedance of the
emitter follower serves to match the low 8 impedance of the speaker to the preceding common emitter stage. Thus,
inexpensive transistors replace transformers. For the complete circuit see Direct coupled complementary symmetry
3 w audio amplifier.
REVIEW:

iv)

Capacitive coupling acts like a high-pass filter on the input of an amplifier. This tends to make the
amplifier's voltage gain decrease at lower signal frequencies. Capacitive-coupled amplifiers are all but
unresponsive to DC input signals.
Direct coupling with a series resistor instead of a series capacitor avoids the problem of frequencydependent gain, but has the disadvantage of reducing amplifier gain for all signal frequencies by attenuating
the input signal.
Transformers and capacitors may be used to couple the output of an amplifier to a load, to eliminate
DC voltage from getting to the load.
Multi-stage amplifiers often make use of capacitive coupling between stages to eliminate problems
with the bias from one stage affecting the bias of another.

Frequency response curve of multistage amplifier

For a multistage amplifier that consists of n similar stages, the corner cut-off frequencies are given by,

where, L and H are the low and high corner frequencies of the individual stages.

Frequency response

Noise:

The noise produced by the first stage of a multistage amplifier is the one that dominates the total
figure of the amplifier.

Single ended noiseless amplifiers retain the same S/N ratio at the input and output of the amplifier

Noisy amplifiers have a worst S/N ratio at the output compared to the input

UNIT II

noise

Frequency Response of BJT Amplifiers

All amplifiers typically exhibit a band-pass frequency response as in Figure 1. The cut-off frequency on
the low end is usually determined by the coupling and bypass capacitors (if there are no such capacitors
the low end extends all of the way to DC). The high frequency limit is typically determined by internal
capacitances in the transistor itself.

Av0

flow1

flow2

fhigh

Figure 1 Frequency response of a typical amplifier.

Low frequency response

If an amplifier does not have coupling or bypass capacitors, then in general the low frequency response
goes all of the way down to DC. However, as we discussed in class, it is desirable to have these
capacitors in the circuit to isolate the amplifiers DC bias point from the outside world.

In the most general case (Figure 2), the input and output coupling capacitors lead to a high-pass filter
response determined by the resistances they see:

Ri

C2

C1

Vin
Rin

Ro

Figure 2 Two port model of a general amplifier.

In general, we can calculate their cutoff frequencies using the following formulas:

f Low _ C 2

f Low _ C1

1
2 2
1
2 1

1
2C 2 ( Ri Rin )
1
2C1 ( Ro RL )

RL

Where Ri is the source resistance, RL is the load resistance, Rin is the input resistance for your amplifier
and Ro is the output resistance for your amplifier. These last two are calculated based on the type of
amplifier you are working with (See the handout on small signal amplifier calculations).
Once you have calculated the frequencies due to C1 and C2, the cutoff is determined by the following
rules:

1) If the two frequencies are more than a decade apart then flow2 in Figure 1 (the 3db point of the amp)
is simply the higher of the two values.
2) If the two frequencies are closer than one decade, then the actual cutoff frequency of the amp is
somewhat larger than either of the two calculated frequencies.
3) If the amplifier has a bypass capacitor, then it can also influence the cutoff frequency. Typical,
emitter bypass capacitors are chosen large enough so that their effects are negligible.

High Frequency Response

As previously stated, the high frequency response of a discrete transistor amp is determined by the
internal capacitances of the transistor itself (Figure 3).
CoB

Cbe

Figure 3 High frequency model of a BJT

If either Cbe or CoB short out at high frequencies, then the transistor stops acting as an amplifier and so
the response is cut off. The values of Cbe and CoB can be found or calculated from the transistor spec
sheet. Typically, CoB is on the spec sheet and Cbe is calculated from fT (the gain-bandwidth product) also
found on the spec sheet using:

Cbe

I CQ
1

2f T hib 52f T x10 3

Once the capacitance values are known, the high frequency cutoff value can be calculated from the
following formulas:

Common Emitter Amp

f High

2 ( Rin Ri )(Cbe CoB (1 Av ))

Common Collector Amp

f High

2CoB

1
( RB ( RE RL ) Ri

Common Base Amp

f High

1
2Cbe (hib RE Ri )

BJT CE Amplifiers at High Frequencies

Recall the following common emitter BJT amplifier:

If we add a load resistor, RL , across the amplifier output, the signal equivalent circuit (using the
hybrid pi equivalent for the BJT and neglecting gce ) is

The capacitors Cb ' c and Cb ' e represent small capacitances internal to the transistor that are
negligible at midband and low frequencies, but which begin to short out and reduce the gain of
the amplifier at the upper limit of the midband range of frequencies. Specifically, note that Cb ' e
reduces vb ' e as it begins to short out as the frequency increases and hence reduces the size of the
dependent source and, thereby, the amplifier gain. The coupling capacitors, Cb and Cc ,
remember, become short circuits as the frequency increases into the midband range. They
certainly are short circuits at the still higher frequencies at which the much smaller capacitors,
Cb ' c and Cb ' e , begin to short out. As we investigate the effects of Cb ' c and Cb ' e on high
frequency performance, therefore, we can work with the following slightly simpler equivalent
circuit:

The capacitor, Cb ' c , complicates the analysis of the circuit considerably. Actually, it is not so
much that it adds so much complexity that we cannot analyze the circuit. Rather, it clutters the
results of the analysis with relatively insignificant terms that make it hard to sort out the essential
behavior of the circuit. We, therefore, simplify the circuit before begin the analysis so that we
can concentrate on the most important aspects of the circuits behavior.
We begin by noting that the capacitor, Cb ' c , connects the base and collector circuits of the BJT.
In effect, it lets part of the base current leak into the collector circuit and, more importantly, lets
part of the collector current leak into the base circuit. This perspective suggests, correctly as it
turns out, that Cb ' c , affects the base circuit much more than it does the collector circuit. Lets
consider this point more carefully.
Consider the capacitor, Cb ' c , that connects the base and collector circuits:

The following circuit presents exactly the same i-v characteristics to any circuit(s) connected to
terminal pairs b'e and ce:

Although we know from the original configuration that the current into nodes b' and c is equal
but opposite, the current in the collector circuit is very much larger (roughly times larger)
than the current in the base circuit. As a consequence, we neglect the right hand controlled
source and the right hand copy of Cb ' c and approximate the effects of Cb ' c by the following
simpler equivalent circuit:

Our modified signal equivalent circuit thus becomes:

From this equivalent circuit, we can determine vce in terms of vb ' e . We can safely ignore the base
current contribution to the current through the emitter resistor, Re . Thus, we can write:
vce t Re Rc RL g m vb ' e t

Thus the current through the capacitor Cb ' c is given by

iCb ' c t Cb ' c

d vb ' e vce
d
Cb ' c vb ' e t Re Rc RL g m vb 'e t
dt
dt

iCb ' c t 1 g m Re Rc RL Cb 'c

dvb ' e t
dt

Note that the current through Cb ' c , driven by vce and vb ' e in the base circuit, is equal to the
current through a capacitor with value

CM 1 g m Re Rc RL Cb ' c

driven only by vb ' e . Effectively, Cb ' c , acts like a much larger capacitor in the base circuit
because one end is driven by a voltage, vce that is much larger than vb ' e . The enhancement of the
capacitance is called the Miller effect.
We can now draw the equivalent circuit as follows:

If we convert to phasor representation of the currents and voltages, the equivalent circuit can be
redrawn as follows:

where
1
1

j Cb ' e CM
Z b ' e rb ' e

For comparison, recall the signal equivalent circuit for the midband case (with g ce 0 and
RL ):

Note that the high frequency signal equivalent circuit, expressed in phasor notation, is identical
in form to the midband signal equivalent circuit, expressed in the time domain. We exploit this
identical form, plus the fact that real and complex quantities obey essentially identical rules of
algebra, to adapt some of our earlier results for the midband case to the current high frequency
case.
First, recall the result for the open-circuit voltage gain at midband:

Avoc

vc

vin

rbb '
rb ' e

g m Rc
1

Re
gm
rb ' e

The output Thevenin resistance of the amplifier was found to be simply Rc . These two results
mean that the midband gain when the amplifier is loaded with a resistor, RL , across its output is
given by:

ARL

RL
RL Rc

rbb '
rb ' e

g m Rc
1

Re
gm
rb ' e

or

ARL

g m Rc RL
1

rbb '
Re
gm
rb ' e
rb ' e

To carry this result over to the high frequency case, we make the following substitutions:

ARL ARL
rb ' e Z b ' e

Thus, we see that

ARL

ARL

g m Rc RL
1

Zb ' e

rbb '
Re
gm
Zb 'e
Zb 'e

g m Rc RL Zb ' e
rbb ' Re 1 g m Zb ' e

ARL

g m Rc RL Zb 'e
Re rbb ' Zb ' e 1 g m Re

ARL

g m Rc RL
Zb ' e
1 g m Re Re rbb ' Z
b 'e
1 g m Re

ARL

g m Rc RL
1 g m Re 1

ARL

g m Rc RL
1 g m Re

ARL

g m Rc RL
1
Re rbb '
1 g m Re 1 1 Re rbb ' j C C
b 'e
M
rb ' e 1 g m Re
1 g m Re

ARL

g m Rc RL
1 g m Re 1

1
1 Re rbb '
Zb ' e 1 g m Re
1

1
R rbb '
1
j Cb ' e CM e
rb ' e
1 g m Re

1
Re rbb '
j
rb ' e rb ' e g m Re

Cb 'e

1 g m Re
CM Re rbb '

We can simplify this expressions considerably. Recall that

gm

rb ' e

and that, for our biasing system,

rb ' e hie
Re

0.026
I cq

2
I cq

Then, we see that

2
2

77 1
0.026 I cq
0.026
I cq

g m Re

We can therefore simplify our result for the complex high frequency gain, as follows:
ARL

Rc RL
1
Re 1 j
*

where

Cb 'e

b 'e

gm
CM
gm

1 g m Re Rc RL Cb ' c

The frequency, * , marks the upper end of midband. For

* (midband), the gain of the

amplifier with a load resistance of value RL is Rc RL Re , a value consistent with the open
circuit midband gain of Rc Re that we found during our midband analysis of the amplifier.
Note that the bandwidth of the amplifier is * c * which depends on the load resistor, RL ,
as well as parameters of the BJT. Specifically, note that the gain increases as Rc RL increases
but that the bandwidth decreases as Rc RL increases.
It is informative to calculate the product of the magnitude of the midband gain and the bandwidth
to obtain the gain-bandwidth product, or GBW:

GBW

where

Rc RL *
R R
gm
c L
Re
Re Cb ' e 1 g m Re Rc RL Cb ' c

Amb

Rc RL
Re

As we noted above, varying Rc RL permits the designer to trade off gain for bandwidth, and
vice versa. Ideally, GBW would remain constant as we trade off gain and bandwidth. For this
particular amplifier, unfortunately, such usually is not the case. Note, however, that

GBW

Rc RL
gm
Re Cb ' e 1 g m Re Rc RL Cb ' c

Rc RL
gm
Re 1 g m Re Rc RL Cb ' c

R R
1
c L
Re Re Rc RL Cb ' c

R R
1
c L
Re Rc RL Cb ' c

or
GBW

1
Re Cb ' c

Recall that for our biasing approach,

g m Re 77
so that

GBW

gm
C
1 gm
1 Cb ' c Cb ' e
1

1 b ' e T
77 Cb ' c
77
Cb ' c
Cb ' c Cb ' e 77
Cb ' c

where quantity

T 2 fT

gm

Cb ' c
rb ' e Cb ' c

is termed the gain-bandwidth product of the BJT and depends only on the BJT parameters. (On
specification sheets for BJTs, the gain-bandwidth product is usually expressed as fT , in Hz,
rather than as T , in rad/sec.) In typical small BJTs,

Cb ' e 10 Cb ' c
so that

GBW

Cb ' e
1
1
1
T T
77
Cb ' c
7

or, for the common emitter amplifier,

GBW T
Thus, the gain-bandwidth product for the common emitter BJT amplifier configuration is
substantially less than T , the gain-bandwidth product for the BJT. In contrast, a (BJT) emitter
follower amplifier (with a voltage gain of nearly one) has a gain-bandwidth product only slightly
less than T . In some sense, then, the common emitter BJT amplifier configuration is wasteful
of the gain-bandwidth product of the BJT. This feature of the configuration may, or may not, be
important to a designer for a particular situation.
It turns out that any amplifier built with an amplifying device (FET, BJT, opamp or vacuum
tube) with a gain-bandwidth product, T , has a gain-bandwidth product that is no more than

T.
Conveniently for designers, some amplifier configurations, including operational amplifiers,
maintain a constant GBW as negative feedback is used to trade off gain and bandwidth. By
adjusting the amount of negative feedback, therefore, a designer can trade gain and bandwidth to
meet the specific requirements of particular design problem.
Proceeding as before, we can find the Bode plot for the high frequency end of midband to be
given by:

Gdb 20 log10 ARL

where
Amb

and

Rc RL
Re

20 log10 Amb

20 log10 Amb 20 log10 *

*
*

*
*

Proceeding as in the analysis for the midband case, we find that the output Thevenin resistance
is, once again, Rc . The input Thevenin resistance, again, is approximately R b .

MOSFET Amplifiers
The Basic Principles of Common Source NMOS Amplifiers
In Fig. 2.1-1, we show an NMOS circuit with its I-V curves and a load line.

VDD
IDS

RL

D
S

Vout

VGS

IDS
For a particular VGS

VDD/RL

Increasing VGS

Operating point

Vout=VDS

VDD

Fig. 2.1-1 An NMOS circuit without any AC

In Fig. 2.1-2, an input signal vin is added to VGS . We shall show later that Vin will be amplified.
Since the source is signal grounded, we shall call this kind of amplifiers common source amplifiers. It
must be noted that the signal is a small signal and is also an alternating current (AC) signal. It will
become clear that this kind of amplifiers can hardly amplify large signals.

VDD
IDS

RL

D
S

vin

Vout

VGS

vin

Fig 2.1-2 An NMOS circuit with an AC signal

Consider Fig. 2.1-3. As shown in Fig. 2.1-3, the input signal induces an AC voltage between gate
and source. Let us denote this AC voltage by v gs . Throughout this lecture notes, we shall use small
letters to denote AC parameters. Obviously, v gs vin . In Fig. 2.1-2, we can see that

Vin VGS vin VGS v gs

Vout VDS vout
I out I DS iout

Since the amplitude of v out is larger than that of vin , this circuit functions as an amplifier. It is
important to note that the DC voltage VDS still exists. In some sense, we may say that v out (AC) rides on

VDS (DC). But, so far as amplification is concerned, we are only interested in the AC output voltage
signal v out . Note that the polarity of v out id opposite to that of vin . In other words, the input is
inverted.

IDS

A particular VGS

VDD/RL

vout

Increasing VGS

vin(AC)
VDD

VDS

Vout

vout(AC)

Fig. 2.1-3 The amplification of vin

Suppose a smaller load RL is used, as shown in Fig. 2.1-4. This amplifier will not function very
well now because v out is not significantly different from vin .

IDS

VDD/RL

A small RL
A particular VGS

vin
Increasing VGS

vout

VDD

Vout

Fig. 2.1-4 The behavior of an amplifier with a small load

It will be shown later that a large load is usually desirable and needed. But, this may drive the
transistor out of saturation, as shown in Fig. 2.1-5. Once the transistor is out of saturation, the output
signal will be distorted and the circuit is no longer an amplifier any more.

IDS

A particular VGS

A larger RL

vin

Increasing VGS

VDD

Vout

vout

Fig. 2.1-5 A large RL driving the transistor out of saturation

On the other hand, if VGS is not proper, the output signal will also be distorted, as shown in
Fig.2.1-6.

IDS

A particular VGS
Increasing VGS

vin
Vout
vout

Fig. 2.1-6 An improper VGS causing the distortion of v out

The DC Analysis of An NMOS Common e Amplifier

In this section, we shall show that the performance of an amplifier can be easily understood by having a
DC analysis of the circuit. That is, we temporarily ignore the existence of the AC input signal and
concentrate our mind on the DC parameters.

Consider Fig. 2.2-1.

VDD
IDS

RL

Vout

VGS

Fig. 2.2-1 An amplifier circuit

We shall first see how the value of the load RL affects the performance of the amplifier. Fig.
2.2-2 shows three possible cases of RL . As we showed before, if the load RL is small, the change of

VGS will induce only a small change of VDS , which is also Vout in our case. On the other hand, for a
large RL , even a small change of VGS will induce a large change of Vout .

IDS

A moderate RL

A small RL

VGS
A larger RL

VDD

VDS=Vout

Fig. 2.2-2 I-V curves and different load lines for the circuit in Fig. 2.2-1

Let us assume that the load RL is small. Fig. 2.2-3 shows the relationship between VGS and

Vout . In this case, Vout falls slowly as VGS rises. We added the AC small signals onto the diagram. It can
be seen that v out is quite small. Thus the amplifier does not function well as an amplifier.

Vout=VDS
A small RL
VDD
vout

VDD

Vt

VGS

vin
Fig. 2.2-3 Vout vs VGS for small RL

Fig. 2.2-4 shows the situation where RL is large. It can be seen that the sharp drop of Vout will
induce a large output v out and thus a large amplification.

Vout=VDS
VDD

A sharp drop indicates a large amplification.

vout

VGS
vin

Fig. 2.2-4 Vout vs VGS for large RL

It should also be seen from Fig. 2.2-5 that in this case, there is a very narrow region for the
proper biasing voltage VGS . In other words, we must be very careful in selecting the biasing voltage.
We shall see later in many experiments that a slight deviation from a proper VGS may cause great
trouble for the amplifier. Thus we may say that a DC analysis of an amplifier is always important as it
gives us information about how to set the gate bias voltage.

Vout=VDS
VDD

But the range of suitable VGS

becomes very narrow.

VGS
Suitable
VGS
Fig. 2.2-5 The proper selection of the gate biasing voltage

The Creation of the AC Current iout in the Transistor

In the above section, we presented the DC analysis of an amplifier. This explains why the circuit
works as an amplifier. But, it does not give us any idea about the gain of the amplifier. In other words,
it does not let us know how much the input signal voltage is amplified. To find the gain, an AC analysis is
needed.

An amplifier behaves as an amplifier because an AC current is created because of the input voltage

vin , which is also v gs . In the following, we shall first explain how this AC current, namely iout , is
produced. We then proceed to show how this iout affects v out .

We first point out that the transistor must be in the saturation region and the load line cannot
interest the I-V curve at the boundary between the linear tregion and the saturation region. Let us
assume that the gate bias voltage is Vgs and the operating point VDS is Vop . Let the input signal be vin .
Then the gate voltage swings from Vgs vin to Vgs vin . This causes VDS to swing from Vop v1 to

Vop v2 where Vop v1 ( Vop v2 ) is the intersection of the load line and the I-V curve
corresponding to Vgs vin ( Vgs vin ). Suppose the load line intersects at the boundary between the

linear region and the saturation region of the I-V curve corresponding to Vgs . Then most likely

v1 v2 . This will cause distortion of the output signal v out . This can be easily seen in Fig. 2.3-1.

It can be easily seen that if the load is too large, both v1 and v2 will be very small. In such a
situation, there will be almost no amplification.

IDS

v 2

vin

I-V curve for Vgs vin

I-V curve for V gs
I-V curve for Vgs vin

v1

t
V DS

vout

Fig. 2.3-1 The case where the transistor is out of saturation and distortion occurs

Once the transistor is in the saturation region, we may use Equation (1.2-3) which we display
again as follows:

I out

1 W
k n ' (VGS vin Vt ) 2
2 L

1 W
1 W 2
W
k n ' (VGS Vt ) 2 k n ' (VGS Vt )vin k n ' vin
2 L
2 L
L

(2.3-1)

In the above equation, the third term is very small because vin is very small and the first term is a
DC term. Thus so far as AC signal is concerned, we have

W
iout k n ' (VGS Vt )vin
L

(2.3-2)

We define

gm

iout
W
k n ' (VGS Vt )
vin
L

(2.3-3)

Equivalently, we have

iout g m vin g m v gs

(2.3-4)

Equation (2.3-4) indicates that the input voltage vin creates an AC current iout linearly because

g m is a constant once VGS is fixed. It should be noted that there is still a DC current I DS . We may say
that iout (AC) rides on this I DS (DC) as shown in Fig. 2.3-2.

iout
IDS

t
Fig. 2.3-2 iout riding on I DS

The Determination of vout

In the above section, we showed that the input voltage vin creates an AC current iout . This current of
course would in turn create an AC output voltage v out . We shall explain its mechanism in this section.

Let us redraw again the amplifier circuit as shown in Fig. 2.4-1.

VDD
iout
RL

D
S

vin

Vout
VGS

Fig. 2.4-1 An amplifier circuit

We first show that the iout will affect the output voltage because of the existence of RL . This can
be seen by examining Fig. 2.4-2 which illustrates how iout affects v out .

IDS

A particular VGS

VDD/RL

vin

Increasing VGS

iout

Vout
VDD
vout

t
Fig. 2.4-2 The inducing of v out by iout

Note the following:

(1) The input signal vin changes VGS . That is, vin induces an AC voltage v gs .
(2) This voltage v gs in turn induces a change of current I DS . That is, the AC voltage v gs induces
an AC output current labeled as iout .
(3) As can be seen from Fig. 2.4-2, iout finally changes VDS . That is, it induces an AC output
voltage, labeled as v out .

As can be from Fig. 2.4-2, when iout rises, v out falls and when iout falls, v out rises. Thus, the
polarity of v out is opposite to the polarity of iout . From Fig. 2.4-1, we have

Vout VDD I out R L

VDD ( I DS iout ) R L

(2.4-1)

This shows that there is an AC output voltage caused by the existence of RL . However, we shall
not let the AC output voltage simply be equal to - iout R L at this moment because there is another factor
which will affect v out , as we will explain below.

We usually assume that in the saturation region, the I-V curve of the transistor is rather flat. In
reality, it is not so flat, as illustrated in Fig. 2.4-3.

IDS
ids

slope
vds

1
r0
VDS

Fig. 2.4-3 The meaning of r0

Traditionally, we are familiar with the fact that the change of voltage will cause a change of
current. In this case, it is opposite. If there is a small signal AC current i ds , a small signal AC voltage

v ds will be induced. In other words, the AC current i ds will induce an AC voltage v ds . Thus, we may
define the output impedance r0 as

r0

v ds
ids

(2.4-2)

to illustrate the relationship between i ds and v ds . It must be noted that this r0 exists because of the IV curves, not because of the load RL . If the slope of the I V curve is very flat, r0 will be quite
large; otherwise, it will be quite small. A large r0 indicates that a small i ds will induce a large v ds . To
put this in another word, we may that a more flat I V is desirable for us to obtain a better
amplifier.

From the above discussion, we know that v out will be affected by iout , RL and r0 . In the
following, we shall explain how v out is determined.

Let us take a look at the amplifier circuit in Fig. 2.4-1. There are DC voltages in the circuits. They
are VGS and VDD . If they are not proper, the amplifier will not work. On the other hand, if they are
proper, since v out is an AC voltage, it will not be affected by the existence of these DC voltages. We
therefore first short-circuit all of the DC voltages, namely VGS and VDD . One must note that one
terminal of VDD is connected to RL and another terminal is connected to ground, as shown in Fig. 2.44(a). Once we short-circuit VDD , RL will be connected to ground and the amplifier circuit becomes that
shown in Fig. 2.4-4(b). In Fig 2.4-4(b), there is also an r0 connected between D and S(ground).

vin

D
S

RL

vDD

vin

D
S

RL

r0

vGS

(a) An amplifier circuit with DC voltage

(b)The amplifier circuit with DC voltages

short-circuited

Fig. 2.4-4 The short-circuiting of DC voltages in an amplifier circuit

As we discussed before, a small signal input voltage vin v gs induces a small signal current ids .
The relationship between v gs and i ds can be found in Equation (2.3-4), namely ids g m v gs . As shown
in Equation (2.3-4), v gs and i ds are of the same polarity. This is illustrated in Fig. 2.4-5. Note that there
is no connection between Node G and Node S as there is no current flowing into the gate. That is, there
is a voltage between G and S, but no current from G.

small signal
equivalent circuit
model

vgs

D
(a current
source)

gmvgs

D
G
S

S
Fig. 2.4-5 Small signal equivalent circuit of a transistor

Because of the short-circuiting of DC voltages, RL is across D and S as shown in Fig. 2.4.4(b). So is

r0 .

The entire small signal equivalent circuit of the amplifier is shown in Fig.2.4-6(b).

VDD

Z=RL//r0

RL
G

vin

D
S

vout

G
`

vin=vgs gmvgs

RL

r0 vout

(a) An amplifier circuit

G
`

(b) The small signal equivalent circuit

vin=vgs gmvgs

vout

(c) The small signal equivalent

circuit further simplified

Fig. 2.4-6 The small signal equivalent circuit of an amplifier circuit

From Fig. 2.4-6(c), we can see that the current will flow through the parallel connection of RL
and r0 , which is expressed as Z RL // r0 . The value of Z can be found as follows:

1
1
1

Z RL r0

RL r0
RL r0

vout g m vin ( RL // r0 )
g m vin

RL r0
RL r0

(2.4-3)

Note that the polarity of v out is opposite to that of vin , as expected by examining Fig. 2.4-2. The
meaning of the opposition of polarity is illustrated in Fig. 2.4-7.

V1

t
-V1

t
Fig. 2.4-7 The meaning of polarity of AC signals

Let us note that r0 is usually much larger than RL because in reality, the I-V curves of a
transistor are rather flat and a flat I-V curve produces a large r0 . On the other hand, as we pointed out
before, RL cannot be too large because a large RL will drive the transistor into the non-saturation
region. When a large resistor is in parallel with another resistor, it can be ignored. Thus, r0 is usually
ignored and we have

vout g m RL vin

(2.4-4)

We denote the gain of the amplifier by Av . Then

Av

vout
g m RL
vin

(2.4-5)

That a large RL will produce a better amplifier can also be seen by the DC analysis. The
reader should go back to Section 2.2 again. Take a look at the figures from Fig. 2.2-2 to Fig. 2.2-5. As
seen in these figures, we can see that a large RL will produce a sharp input-output relationship and
thus a high gain. Of course, it must be under the condition that the load will not drive the transistor
out of saturation.

In the above sections, we only talked about NMOS amplifiers. The same discussion can be used
to explain how a PMOS amplifier works. A typical PMOS amplifier is shown in Fig. 2.4-8.

VDD

G
vin

S
D
RL

`
vout

Fig. 2.4-8 A PMOS amplifier

We pointed out before that RL cannot be too small. We now will give more interpretation of

r0 . Let us consider Equation (2.4-3) which is displaced again below::

vout g m vin

RL r0
RL r0

We may rewrite the above equation as follows:

vout g m vin

RL
RL
1
r0

(2.4-6)

From Equation (2.4-6), we can see that the larger r0 is, the larger v out is. It can also be seen that a
small r0 will produce a very small v out . Let us consider Fig. 2.4-9.
IDS

A
B

C
VDS

Fig. 2.4-9 A further interpretation of r0

For Location A in Fig. 2.4-9, r0 is large. If RL is not too small, then Location A is suitable to be
the operating point of an amplifier. For Location C in Fig. 2.4-9, r0 is small and it is not suitable to be
the operating point of an amplifier. If a circuit has such an operating point, it will not be an amplifier
because the gain may be even smaller than 1. In other words, v out may be smaller than vin . As for
Location B, we can see that r0 changes from small to large and we can expect distortion to occur.

UNIT-III

Sinusoidal Oscillators
Here we consider the principles of oscillators that produce approximately sinusoidal waveforms.
(Other oscillators, such as multivibrators, operate somewhat differently.) Because the waveforms
are sinusoidal, we use phasor analysis.
A sinusoidal oscillator ordinarily consists of an amplifier and a feedback network. Let's consider
the following idealized configuration to begin understanding the operation of such oscillators.

We begin consideration of sinusoidal oscillators by conducting a somewhat artificial thought

experiment with this configuration. Suppose that initially, as shown in the figure, the switch, S,
connects the input of the amplifier is connected to the driver. Suppose, furthermore, that the
complex constant, Fvv in the feedback network is adjusted (designed) to make the output of the
feedback network exactly equal Vin , the input voltage provided by the driver circuit. Then
suppose that, instantaneously (actually, in a time negligible in comparison to the period of the
sinusoids), the switch S disconnects the driver circuit from the input of the amplifier and
immediately connects the identical voltage, Vin , supplied by the feedback network to the input
of the amplifier. A circuit, of course, cannot distinguish between two identical voltages and,
therefore, the amplifier continues to behave as before. Specifically, it continues to produce a
sinusoidal output. Now, however, it produces the sinusoidal output without connection to a
driver. The amplifier is now self-driven, or self-excited, and functions as an oscillator.
We now analyze the behavior of the amplifier when it is connected to produce self-excited
oscillations to develop a consistency condition that must be satisfied if such operation is to be
possible. First, we note that the output voltage of the amplifier can be written in terms of the
input voltage, Vin :

Vout

ZL
A v Vin AVin
Z L Zo

where we have written the gain, A , of the amplifier, under load, as

A

ZL
Av
Z L Zo

But the output of the feedback network is Fvv Vout where Fvv has been chosen so that

Fvv Vout Vin

If we substitute this result into our earlier result for Vout , we find

Vout AVin AFvv Vout

or

1 AFvv Vout 0
Of course, Vout 0 for a useful oscillator so we must have

AFvv 1
Although it is usually summarized as requiring the complex loop gain to be unity as a condition
of oscillation, let's examine this condition, known as the Barkhausen condition for oscillation, to
gain a better understanding of what it means. To begin with, A and Fvv are complex numbers
that can be written in polar form:

A A e j
Fvv Fvv e j
Thus, the Barkhausen condition can be written as

AFvv A e j Fvv e j A Fvv e j 1

or

A Fvv e j 1

This equation, being complex, gives two real equations, one from the magnitude and one from
the angle:
Magnitude: A Fvv 1
Angle: n 2 , n 0, 1, 2, ...
The magnitude portion of the Barkhausen condition requires a signal that enters the amplifier and
undergoes amplification by some factor to be attenuated by the same factor by the feedback
network before the signal reappears at the input to the amplifier. The magnitude condition
therefore ensures that the amplitude of oscillation remains constant over time. If it were true that
A Fvv 1, then the amplitude of the oscillations would gradually decrease each time the signal
passed around the loop through the amplifier and the feedback network. Similarly, if it were true
that A Fvv 1, then the amplitude of the oscillations would gradually increase each time the
signal passed around the loop through the amplifier and the feedback network. Only if A Fvv 1
does the amplitude of the oscillations remain steady.
The angle portion of the Barkhausen condition requires that the feedback network complement
any phase shift experienced by a signal when it enters the amplifier and undergoes amplification
so that the total phase shift around the signal loop through the amplifier and the feedback
network totals to 0, or to what amounts to the same thing, an integral multiple of 2 . Without
this condition, signals would interfere destructively as they travel around the signal loop and
oscillation would not persist because of the lack of reinforcement. Because the phase shift
around the loop usually depends on frequency, the angle part of the Barkhausen condition
usually determines the frequency at which oscillation is possible. In principle, the angle
condition can be satisfied by more than one frequency. In laser feedback oscillators (partially
reflecting mirrors provide the feedback), indeed, the angle part of the Barkhausen condition is
often satisfied by several closely spaded, but distinct, frequencies. In electronic feedback
oscillators, however, the circuit usually can satisfy the angle part of the Barkhausen condition
only for a single frequency.
Although the Barkhausen condition is useful for understanding basic conditions for oscillation,
the model we used to derive it gives an incomplete picture of how practical oscillators operate.
For one thing, it suggests that we need a signal source to start up an oscillator. That is, it seems
that we need an oscillator to make an oscillator. Such a circumstance would present, of course, a
very inconvenient version of the chicken-and-the-egg dilemma. Second, the model suggests that
the amplitude of the oscillations can occur at any amplitude, the amplitude apparently being
determined by the amplitude at which the amplifier was operating when it was switched to selfexcitation. Practical oscillators, in contrast, start by themselves when we flip on a switch, and a
particular oscillator always gives approximately the same output amplitude unless we take
specific action to adjust it in some way.
Let's first consider the process through which practical oscillators start themselves. The key to
understanding the self-starting process is to realize that in any practical circuit, a variety of
processes produce noise voltages and currents throughout the circuit. Some of the noise, called

Johnson noise, is the result of the tiny electric fields produced by the random thermal motion of
electrons in the components. Other noise results during current flow because of the discrete
charge on electrons, the charge carriers. This noise is analogous to the acoustic noise that results
from the dumping a shovel-full of marbles onto a concrete sidewalk, in comparison to that from
dumping a shovel-full of sand on the same sidewalk. The lumpiness of the mass of the marbles
produces more noise than the less lumpy grains of sand. The lumpiness of the charge on the
electrons leads to electrical noise, called shot noise, as they carry electrical current. Transient
voltages and currents produced during start-up by power supplies and other circuits also can
produce noise in the circuit. In laser feedback oscillators, the noise to initiate oscillations is
provided by spontaneous emission of photons. Amplification in lasers occurs through the process
of stimulated emission of photons.
Whatever the source, noise signals can be counted upon to provide a small frequency component
at any frequency for which the Barkhausen criterion is satisfied. Oscillation begins, therefore, as
this frequency component begins to loop through the amplifier and the feedback network. The
difficulty, of course, is that the amplitude of the oscillations is extremely small because the noise
amplitude at any particular frequency is likely to be measured in microvolts. In practice,
therefore, we design the oscillator so that loop gain, A Fvv , is slightly greater than one:

A Fvv 1
With the loop gain slightly greater than one, the small noise component at the oscillator
frequency is amplified slightly each time it circulates around the loop through the amplifier and
the feedback network, and hence gradually builds to useful amplitude. A problem would occur if
the amplitude continued to build toward infinite amplitude as the signal continued to circulate
around the loop. Our intuition tells us, of course, that the amplitude, in fact, is unlikely to exceed
some fraction of the power supply voltage (without a step-up transformer or some other special
trick), but more careful consideration of how the amplitude is limited in practical oscillators
provides us with some useful additional insight.
Initially, let's consider the amplifier by itself, without the feedback network. Suppose that we
drive the amplifier with a sinusoidal generator whose frequency is the same as that of the
oscillator in which the amplifier is to be used. With the generator, suppose we apply sinusoids of
increasing amplitude to the amplifier input and observe its output with an oscilloscope. For
sufficiently large inputs, the output becomes increasingly distorted as the amplitude of the
driving sinusoid becomes larger. For large enough inputs, we expect the positive and negative
peaks of the output sinusoids to become clipped so that the output might even resemble a square
wave more than a sinusoid. Suppose we then repeat the experiment but observe the oscillator
output with a tuned voltmeter set to measure the sinusoidal component of the output signal at the
fundamental oscillator frequency, the only frequency useful for maintaining self-excited
oscillations when the amplifier is combined with the feedback circuit. Then, we would measure
an input/output characteristic curve for the amplifier at the fundamental oscillator frequency
something like that shown in the following sketch.

From the curve above, note that, at low levels of input amplitude, Vin , the output amplitude,

Vout , f , of the sinusoidal component at the fundamental frequency increases in direct proportion
to the input amplitude. At sufficiently high output levels, however, note that a given increment in
input amplitude produces a diminishing increase in the output amplitude (at the fundamental
frequency). Physically, as the output becomes increasingly distorted at larger amplitudes,
harmonic components with frequencies at multiples of the fundamental frequency necessarily
increase in amplitude. Because the total amplitude is limited to some fraction of the power
supply voltage, the sinusoidal component at the fundamental frequency begins to grow more
slowly as the input amplitude increases and causes the amplitude of the distortion components to
increase, as well. Thus, the amplitude of the component of the output at the fundamental
frequency eventually must decrease as the input amplitude increases to accommodate the
growing harmonic terms that accompany the rapidly worsening distortion. Effectively, the
magnitude of the voltage gain, A , for the fundamental frequency decreases at large amplitudes.
Now let's reconsider the amplifier in its oscillator environment, that is, with the feedback
network designed so that A Fvv 1. As the oscillations build up from noise and increase to
larger and larger amplitudes, they eventually reach amplitudes at which the magnitude of the
voltage gain, A , begins to decrease. As a consequence, the loop gain, A Fvv , begins to
decrease. The amplitude of the oscillations grows until the decreasing A reduces the loop gain,

A Fvv , to unity:

A Fvv 1
At that point, the oscillations cease growing and their amplitude becomes stable, at least as long
as the gain characteristic of the amplifier shown in the curve above do not change.

In summary, the small signal loop gain in practical amplifiers is chosen so that A Fvv 1 and
oscillations grow from small noise components at the oscillator frequency. The output climbs
along the input/output characteristic curve of the amplifier at the fundamental frequency until the
voltage gain drops enough to make A Fvv 1 , at which point the oscillator amplitude stops
growing and maintains a steady level. The amplifier input/output characteristic curve therefore
explains why practical oscillators operate at approximately the same amplitude each time we turn
them on. Note designers sometimes add nonlinearities, voltage-limiting circuits with diodes, for
example, to gain more direct control of the oscillator amplitude.
The analysis of oscillator operation based on the input/output characteristic of the amplifier at the
fundamental frequency can help illuminate one more aspect of the operation of practical
sinusoidal oscillators: distortion in the output waveform. From the discussion above, it is clear
that the higher the oscillations climb along the input/output characteristic curve, the more
distortion in the output worsens. In addition, it is clear that the more the loop gain, A Fvv ,
exceeds unity at small amplitudes, the higher the oscillations climb along the curve, and the more
distorted the output will become, before the amplitude of the oscillations stabilizes. Thus, it is
clear that, in the design process, A Fvv should not be chosen to exceed unity very much, even
at small signals. On the other hand, if A Fvv is chosen too close to unity in an effort to reduce
distortion, then even small changes in the amplification characteristics at some later time can
preclude oscillation if they cause the loop gain, A Fvv , to drop below unity. Such changes can
easily be caused by, for example, changes in temperature or aging of components. The designer
must therefore choose a compromise value of A Fvv to realize low distortion, but reliable
operation, as well. If the oscillator is to operate at a single frequency, it may be possible to have
our cake and eat it too by choosing the value of A Fvv well above unity to achieve reliable
operation and then purifying the oscillator output with a tuned filter, such as an LC resonant
circuit. This solution is not very convenient if the oscillator must operate over a wide range of
frequencies, however, because a band pass filter with a wide tuning range can be difficult to
realize in practice.
As a final perspective on the Barkhausen condition, we note that when

AFvv 1
or
ZL
A v Fvv 1
Z L Zo

then our earlier result for the voltage gain, G v , with feedback,

Zth ,dr

ZL

1
A v Fvv

Zo Z L

Av

Gv

Zth ,dr
1 A v Fvv
Zi

1 Av Fvv

is infinite because the denominator in the numerator of the curly brackets is zero. In a nave
sense, then, we can say that the gain with feedback becomes infinite when the Barkhausen
criterion is satisfied. The nave perspective, then, is that oscillation corresponds to infinite gain
with feedback.
This perspective is not particularly useful, except that it emphasizes that the feedback in
sinusoidal oscillators is positive and, thereby, increases the gain of the amplifier instead of
decreasing it, as negative feedback does. It is interesting to note, however, that positive feedback
need not produce oscillations. If the feedback is positive, but A Fvv 1, then oscillations die
out and are not sustained. In this regime, the gain of the amplifier can be increased considerably
by positive feedback. Historically, Edwin H. Armstrong, the person who first understood the
importance of DeForest's vacuum triode as a dependent or controlled source, used positive
feedback to obtain more gain from a single, costly, vacuum triode in a high frequency amplifier
before Black applied negative feedback to audio amplifiers. As vacuum triodes became more
readily available at reasonable cost, however, the use of positive feedback to obtain increased
gain fell out of favor because the increased gain it produced was accompanied by enhanced noise
in the output, in much the same way that the decreased gain produced by negative feedback was
accompanied by reduced noise in the amplifier output. In practice, you got better results at a
reasonable cost by using amplifiers with negative feedback, even though they required more
vacuum triodes than would be necessary with positive feedback.
We now analyze a variety of sinusoidal oscillator circuits in detail to determine the frequency of
possible oscillation and the condition on circuit components necessary to achieve slightly more
than unity loop gain and, thereby, useful oscillations.

Phase shift Oscillator

We begin our consideration of practical oscillators with the phase shift oscillator, one that
conforms fairly closely to our idealized model of sinusoidal oscillators.

The phase shift oscillator satisfies Barkhausen condition with an angle of 2 . The inverting
amplifier provides a phase shift of . The three identical RC sections (recall that the inverting
input to the operational amplifier is a virtual ground so that V 0 ) each provide an additional
phase shift of / 3 at the frequency of oscillation so that the phase shift around the loop totals to
2 .
We begin the analysis by using the usual result for an inverting opamp configuration to express
the output voltage, Vout , in terms of the input voltage, Vin , to the inverting amplifier:

Vout

RF
Vin AVin
R

where

RF
R

Next, we write node equations to find the output of the feedback network in terms of the input to
the feedback network. Oddly enough, the figure shows that the input to the feedback network is
Vout and that the output of the feedback network is Vin . To achieve a modest increase in
notational simplicity, we use Laplace transform notation, although we will neglect transients and
eventually substitute s j and specialize to phasor analysis because we are interested only in
the steady-state sinusoidal behavior of the circuit.

(1)

V s
V1 s V2 s Cs 0
V1 s Vout s Cs 1
R

(2)

V2 s V1 s Cs

(3)

in

s V2 s Cs

V2 s
V2 s Vin s Cs 0
R

Vin s
0
R

Collecting terms, we find:

(1) '

2Cs R V1 s Cs V2 s 0 Vin s sC Vout s

(2)'

CsV1 s 2Cs V2 s Cs Vin s 0

R

(3)'

0V1 s CsV2 s Cs

1
R

Vin s 0

In matrix form,

2Cs R

Cs

Cs
1
R

2Cs

V1 s sC Vout s

Cs V2 s
0

V s
0
1 in
Cs
R
0

Cs

We calculate Cramer's delta as a step towards calculating the output of the feedback network,
Vin s , in terms of the input to the feedback network, Vout s .

2Cs

Cs
0

1
R

Cs
2Cs

0
1
R

Cs

1
2
Cs

R
2Cs

R
Cs

Cs
Cs

1
R

Cs
Cs

1
R

Cs
0
Cs Cs Cs 1
R

1
1
1

2
2Cs 2Cs Cs Cs

R
R
R

Cs Cs Cs

Cs 2
1
3
1

2
2
3
2Cs 2 Cs Cs 2 Cs Cs

R
R
R
R

 2 Cs
3

6
2
1
3
1
1
Cs 2 2 Cs Cs 2 2 Cs 3 Cs 3 Cs 2
R
R
R
R
R
R
6
5
1
Cs 2 2 Cs 3
R
R
R

3
Cs

We now use this result in Cramer's rule to solve our set of equations for Vin s in terms of
Vout s .

2Cs
Vin s

Cs

1
R

sCVout s

Cs
2Cs

1
R

Cs

0
0

1
1 Cs 2Cs
Vin s sCVout s
R
0
Cs
Vin s

Vin s

Cs 3
6
5
1
Cs Cs 2 2 Cs 3
R
R
R
3

s3
6 2
5
1
s
s
2 s
RC
RC
RC 3

Vout s

Vout s

For an alternative solution with MATLAB, enter the following commands:

syms s R C V1 V2 Vin V Vout

A=[2*C*s+1/R -C*s 0; -C*s 2*C*s+1/R -C*s; 0 -C*s C*s+1/R];

b=[s*C*Vout; 0; 0];
V=A\b;
Vin=V(3)

The result is:

Vin = C^3*s^3*R^3*Vout/(C^3*s^3*R^3+6*C^2*s^2*R^2+5*C*s*R+1)

That is,
Vin s

Vin s

C 3 s R3
Vout s
C 3 s3 R3 6 C 2 s 2 R 2 5 C s 1

s3
6
5
1
s
s2
Cs
2
3
RC
RC
RC

Vout s

This expression, recall, gives the output of the feedback network, Vin s , in terms of the input to
the feedback network, Vout s . Recall, also, that in phasor notation, the output of the amplifier,
Vout , in terms of the input to the amplifier, Vin , is given by

Vout AVin
In Laplace transform notation, this equation becomes

Vout s AVin s
If we eliminate Vin s between the input/output equations for the amplifier and for the feedback
network, we find:

1
Vout s
A
s3

s3
6 2
5
s
s
2
RC
RC

Vout s

RC

Because Vout s 0 if the oscillator is to provide useful output, we must require

As 3
1
6 2
5
s3
s
s
2
RC
RC

RC

This required consistency condition is tantamount to the Barkhausen condition for oscillation.

s3

6 2
5
s
s
2
RC
RC

A 1s

RC

As 3

6 2
5
1
s
0
2 s
RC
RC
RC 3

Because we are interested in the sinusoidal steady state, we specialize to phasor analysis by
substituting s j :

6
5
2
j

2
RC
RC

A 1 j 3

RC

6
1
5
2
2

RC 3
RC 2

RC
This complex equation is in rectangular form. We obtain two separate equations by setting the
real and imaginary parts to zero, separately. First, let's set the real part of the equation to zero:

6
1
2
0
3
RC
RC

6 2

1
0
RC 2

6 RC

1
6RC

Thus, the frequency of the possible oscillations is determined by the values of the components in
the feedback network. Whether or not oscillations will actually occur depends upon whether or
not the second equation we obtain from the equation above is satisfied. To obtain this equation,
we set the imaginary part of the equation to zero:

A 1 2

A 1

RC

RC 2

But, of course, we have already discovered the only possible value of :

1
6RC

If we use this value in our equation, we find:

1
A 1 6 RC

RC 2

A 1 30
Thus, we require
A 29

to realize a loop gain through the amplifier and the feedback network of unity. In a practical
oscillator, of course, A should be larger so that the oscillations will build up from noise.
Perhaps it should be chosen to lie in the low 30' s to ensure reliable operation without too much
distortion of the essentially sinusoidal output voltage. Recall that the gain-bandwidth product for
a 741 operational amplifier is roughly 1MHz . If we were to use it to realize an inverting
amplifier with a gain of 30 -something, then the bandwidth of the resulting amplifier would be
no more than about 30 kHz . Thus, a 741 operational amplifier can be used to realize a phase shift
oscillator in the audio range, but not much higher. A 2N3904 BJT, in contrast, has a gainbandwidth product of several hundred MHz and could be used to realize an amplifier with a gain
of 30 -something with a much larger bandwidth. Some details of the feedback circuit would
change, but the arrangement would be similar. Even if we use devices with larger gainbandwidth product, the output Thevenin resistance of the amplifier limits the maximum
frequency at which the phase shift oscillator is useful in practice. The impedance of the phase
shift feedback network at the oscillation frequency should be much larger than the Thevenin
output impedance so that the amplifier output will not be unduly loaded and so that our simple
theory will apply. As a consequence, the minimum resistance of the resistors with value, R , in
the phase shift feedback network typically cannot be less than about 1000 . The minimum
value of the capacitors, C , must be much larger than stray or parasitic capacitances in the circuit
and hence typically should be no smaller than about 1000 pF . From the result

1
6RC

we see, therefore, that phase shift oscillators are seldom useful at frequencies above 500 kHz ,
regardless of the GBW of the active device in the amplifier. Note that it is inconvenient to
change the frequency of phase shift oscillators because the values of a minimum of three
resistors or three capacitors must be changed simultaneously.

Band Pass Oscillators

If the output of a band pass amplifier is fed back to its input, it may oscillate at a frequency
within its pass band. If the pass band is narrow, the frequency will occur near the center
frequency of the amplifier pass band. To the extent that the band pass filter is effective in
attenuating signals with frequencies outside its pass band, it suppresses the harmonic content
(distortion) in the output waveform that results as the oscillations grow to the point that they are

limited by nonlinearities in the amplifier. As a consequence of this harmonic suppression, band

pass oscillators can provide more nearly sinusoidal outputs than other types of practical
oscillators.
To consider the requirements for oscillation in detail, recall that for a second order band pass
filter that

Vout s T s Vin s
where

T s

Vout s

Vin s

n1s

s 2 o s o 2
Q

Suppose that we connect the output directly to the input so that

vout t vin t
Our feedback network in this case is thus a simple piece of wire. In the Laplace transform
domain,

Vout s Vin s
so that

T s 1
This condition, tantamount to the Barkhausen condition, requires

T s

n1s
1
o
2
2
s
s o
Q

For the steady state sinusoidal case that describes the operation of the circuit after transients have
died out, we substitute s j and obtain

T j

or

n1 j

o j o 2
Q

j n1
1
o
2
2
j
o
Q


j n1 2 j o o 2
Q

2 j n1

o 2 0
Q

This complex equation, of course, gives two real equations. The real part gives

2 o 2 0
so that the frequency of oscillations, if any, must be

o
The imaginary part of the equation gives

j n1 o 0
Q

or

n1

o
Q

This equation is a requirement on the gain of the band pass amplfier.

As an example, recall the state variable filter circuit

which provides a band passed output of

VBP s

o s
o

s
s o
Q
2

where

1
RC

1 R
Q 1 F
3
R

Vin s
2

If we wait until after the transients die out, we can substitute s j and set VBP Vin to obtain

o j

2
j o j o 2
Q

or

j o

2 j o o 2
Q
2

1
j o 1 o 2 0
Q

The real part of the equation requires

1
RC

and the imaginary part requires

1 R
1 Q 1 F
3
R

or
R
3 1 F
R

or

RF
2
R
RF 2 R

Note that this requirement means that 1 3 of the band passed output is fed back to the input. To
make the loop gain slightly greater than unity so that the oscillations will build up from noise, we
need to feed back a larger fraction of the band passed output. To achieve this result, note that we
should choose, in practice, RF 2 R .

We noted earlier that band pass oscillators offer the advantage of built-in harmonic suppression
from its band pass filter to purify their output waveform. We note that the state variable circuit
offers additional harmonic suppression if we take the output from the low pass output rather than
from the band bass output. The state variable circuit has the disadvantage of greater power
requirements than circuits with only one operational amplifier. With the operational amplifier
state variable implementation, band pass filters are limited basically to the audio frequency
range. Changing the frequency of oscillations in the state variable band pass oscillator requires
changing the value of 2 capacitors simultaneously, only slightly more convenient that for the
phase shift oscillator's 3 capacitors (or resistors).

Wien Bridge Oscillator

The Wien Bridge oscillator is a band pass oscillator that requires only one operational amplifier:

where

Z1 s R

1
sC

1
R
1
sC
Z2 s R

sC R 1
sC
With a minor abuse of conventional notation, we represent impedances in this figure by
resistances. We assume that the amplifier is non-inverting and has infinite input impedance and a
real gain of A at the frequency of oscillation. For specificity, we show an operational amplifier
configuration for which we saw, earlier, the gain is

A 1

RF
R

but so our results will be more generally applicable, we express our results in terms of the open
circuit gain, A , which might be provided by a BJT or FET amplifier. As before, we assume that
we are interested in the sinusoidal steady state response so that we can neglect transients.
We begin our analysis by writing the following node equation:

Vin s Vout s Vin s

0
Z1 s
Z2 s
But

Vout s AVin s
Thus, we can write the node equation as

AVin s AVout s AVin s

0
Z1 s
Z2 s
Vout s AVout s AVout s

0
Z1 s
Z 2 s
1 A
1

Vout s 0
Z 1 s Z 2 s
Recall that

Z1 s R

1
sC

1
R
1
sC
Z2 s R

sC R 1
sC
Thus,

1 A
1
sC Vout s 0

R
R 1
sC

To investigate the sinusoidal steady state, we convert this equation to phasor notation by
substituting s j :

1 A
1
j C Vout 0

R
R 1
j C

Multiply through by R

1
j C

1
1

1 A j C R
Vout 0
R
j C

1
1 A j RC 1 1
V 0
j RC out

1
V 0
3 A j RC
RC out

If the oscillator is to produce useful output, then Vout 0 and the curly brackets must be zero.
The real and imaginary parts of the curly brackets must be zero independently. If we set the
imaginary part to zero, we find:

1
j RC
0
RC

or

RC

Thus, the frequency of possible oscillation is given

1
RC

Note that if the amplification, A , is provided by a BJT or an FET, the frequency of oscillation
can be extended beyond the audio range, just as with the phase shift oscillator. Because of the
absence of the factor 6 in the denominator, however, the Wien Bridge oscillator can achieve
more than twice the frequency of a phase shift oscillator, in practice.
By setting the real part of the equation to zero, we obtain:
A3

In practice, of course, we would choose A to be slightly larger so that the oscillations can build
up from noise. One of the advantages of the Wien Bridge oscillator is that it requires only a
modest gain from the amplifier.

Colpitts and Hartley Oscillators

The Colpitts and Hartley oscillators are band pass filter oscillators in which the band pass filters
are LC resonant circuits. In the Colpitts oscillator, a capacitive voltage divider, which also
serves as the capacitance part of the LC resonant circuit, feeds back a portion of the output back
into the input. In the Hartley oscillator, an inductive voltage divider, which also serves as the
inductance part of the LC resonant circuit, feeds back a portion of the output back into the input.
With appropriate amplifiers, these configurations can oscillate at frequencies up to a few hundred
megahertz, much higher than the configurations we have considered so far.
Because these two oscillator configurations are identical topologically, we can perform much of
the analysis of them simultaneously by considering the following circuit:

With a minor abuse of conventional notation, we represent impedances in this figure by

resistances. We assume that the amplifier is non-inverting and has infinite input impedance, a
real gain of A at the frequency of oscillation and a Thevenin output resistance of Ro . For
specificity, we show an operational amplifier configuration for which we saw, earlier, the gain is

A 1

RF
R

but so our results will be more generally applicable, we express our results in terms of the open
circuit gain, A , which might be provided by a BJT or FET amplifier that permits operation at
high frequencies. As before, we assume that we are interested in the sinusoidal steady state
response so that we can neglect transients.
Using Laplace transform notation, we have for a Colpitts oscillator that
Z1 s

1
s C1

Z2 s

1
sC2

Z3 s s L
while for a Hartley oscillator,

Z1 s s L1
Z 2 s s L1

Z3 s

1
sC

We can easily write node equations that hold for both oscillators:

(1)

Vin s Vout s
V s
in
0
Z1 s
Z2 s

(2)

Vout s Vin s
V s
V s AVin s
out
out
0
Z1 s
Z3 s
Ro

Collecting terms, we find:

(1) '

1
1
Vin s

Vout s
0
Z2 s
Z1 s
Z1 s

(2) '

1
1
A
1
1
Vin s

Vout s
0
Ro
Z3 s
Ro
Z1 s
Z1 s

From equation (1)', we find:

(1)"

Vin s

Z1 s
1

Z1 s

Vout s

Z2 s

We substitute equation (1)" into (2)':

Z1 s
1
A
1
1
1

1
Vout s 0

1 Z1 s
Ro
Z3 s
Ro
Z1 s

Z2 s

Z1 s

1
1

Z1 s
Z 1 s
A
1
1

V s 0
1
1
1
1

Ro
Z 3 s
Ro out
Z1 s

Z 2 s
Z1 s
Z 2 s

Z 1 s

1
1

1 Z s Z s Z s

1
1
2

1
1

Z
s
1

Z1 s
Z 2 s

Z 1 s
A
1
1

V s 0
1
1

Ro
Z 3 s
Ro out

Z 1 s
Z 2 s

We divide through by

Z 1 s
1

Z 1 s

Z 2 s

1
1

Z3 s
Ro 1
A
1
1

Vout s 0

1
Ro
Z 2 s
Z1 s
Z2 s
Z1 s

1
1
A
1
Z s
1 1 Vout s 0

Ro
Ro
Z 2 s
Z 3 s
Z 2 s
1

Z s 1
1
Z s
A 1 1 Vout s 0
1 1

Z 2 s Z 3 s Ro
Z 2 s

Z 2 s
We now specialize this equation for the Colpitts oscillator, for which, recall,
Z1 s

1
s C1

Z2 s

1
sC2

Z3 s s L
From these results, we obtain the following equation for the Colpitts oscillator:

C2 1
C2
1

sC2 1

A 1
Vout s 0
C1 sL Ro
C1

To investigate the sinusoidal steady state, we convert this equation to phasor notation by
substituting s j :

C2 1
C2
1

j C2 1

A 1
Vout 0
C1 j L Ro
C1

If the oscillator is to produce useful output, then Vout 0 and the curly brackets must be zero.
The real and imaginary parts of the curly brackets must be zero independently. If we set the
imaginary part to zero, we find:

C 1
j C2 1 2
0
C1 j L

C2 1

C2 1

0
C1 L

1
1 1

C2 L
C1

Thus, the frequency of possible oscillation is given

1
1 1

C2 L
C1

Because C1 and C2 are connected in series, this frequency is simply the resonant frequency of
the LC circuit, that is, the center of the pass band.
By setting the real part of the equation to zero, we obtain:
A 1

C2
0
C1

or
A 1

C2
C1

In practice, of course, we would choose A to be slightly larger so that the oscillations can build
up from noise. Because the designer can set the ratio of C1 and C2 to a convenient value, the
gain of the amplifier, A , need not be especially large, a potential advantage over the other
circuits we have investigated so far. In practice, it is difficult to vary the frequency by changing
the values of the capacitors because their ratio should remain constant. In practical variable
frequency Colpitts oscillators, therefore, the frequency is sometimes varied by partially inserting
and withdrawing a low-loss ferrite core located within an inductive winding. Notice that neither

the frequency nor the gain requirement for the Colpitts oscillator depend upon Ro , the output
Thevenin resistance of the amplifier.
We can see more clearly the physical meaning of the equation that specifies the minimum
amplitude if we write it as follows:
A 1

C2 C1 C2

C1
C1

or

1A

1
C2

1
j C2

C1
A
A
1 1
1
1
C1 C2

C1 C2
j C1 j C2
1
j C 2

The quantity

is the fraction of the output that is fed back into the input of the
1
1

j C1 j C2
amplifier in a Colpitts oscillator. Thus, the real part of the equation simply requires that the loop
gain through the amplifier and feedback network be unity. The imaginary part of the equation
requires the phase shift around the loop to be a multiply of 2 .
For a Hartley oscillator, recall that

Z1 s s L1
Z 2 s s L1
Z3 s

1
sC

Thus, the equation

Z s
1
1 1

Z2 s
Z2 s

1
Z1 s
1

A 1
Vout s 0
Z2 s

Z3 s Ro

becomes

L
L1
1

1 1 Cs

A 1
Vout s 0
L2
Ro
L2
sL2

To investigate the sinusoidal steady state, we convert this equation to phasor notation by
substituting s j :

L
L1
1

1 1 j C

A 1
Vout 0
L2
Ro
L2
j L2

If the oscillator is to produce useful output, then Vout 0 and the curly brackets must be zero.
The real and imaginary parts of the curly brackets must be zero independently. If we set the
imaginary part to zero, we find:

L
1
1 1 j C 0
j L2
L2

L
1
1 1 C 0
L2
L2

L
1 2 CL2 1 1 0
L2

2 C L2 L1 1
Thus, the frequency of possible oscillation is given

L1 L2 C

Because L1 and L2 are connected in series, this frequency is simply the resonant frequency of
the LC circuit, that is, the center of the pass band.
By setting the real part of the equation to zero, we obtain:
A 1

L1
0
L2

or
A 1

L1
L2

In practice, of course, we would choose A to be slightly larger so that the oscillations can build
up from noise. Because the designer can set the ratio of L1 and L2 to a convenient value, the

gain of the amplifier, A , need not be especially large, a potential advantage shared with the
Colpitts oscillator. In practice, it is difficult to vary the frequency by changing the values of the
inductors because their ratio should remain constant. In practical variable frequency Hartley
oscillators, therefore, the frequency usually is varied by adjusting the capacitance, C .
We can see more clearly the physical meaning of the equation that specifies the minimum
amplitude if we write it as follows:
A 1

L1 L1 L2

L2
L2

or
1A

L2
j L2
A
L1 L2
j L1 j L2

j L2
is the fraction of the output that is fed back into the input of the
j L1 j L2
amplifier in a Hartley oscillator. Thus, the real part of the equation simply requires that the loop
gain through the amplifier and feedback network be unity. The imaginary part of the equation
requires the phase shift around the loop to be a multiply of 2 .

The quantity

Piezoelectric Crystal Oscillators

When some materials are placed between conducting plates and subjected to mechanical
compression, they produce an internal electric field that causes a voltage to appear between the
conducting plates. A voltage also appears between the plates if the materials are subjected to
mechanical tension, although the polarity of the voltage produced is opposite to that produced by
compression. If the sample is subjected to neither compression nor tension, no voltage appears
between the plates. Conversely, application of a voltage between the plates produces
compression or tension in the material, depending on the polarity of the voltage applied. This
electromechancial behavior is called the piezoelectric effect.
Excitation of high frequency mechanical vibrations in a small slab of a piezoelectric material,
such as crystalline quartz, produces a damped oscillatory voltage across conducting electrodes
placed on opposite faces of the material similar to that produced by an excited LC resonant
circuit. Indeed, the electrical behavior of a small piece of piezoelectric material placed between
conducting electrodes can be modeled by the following circuit:

where the upper and lower terminals connect to the conducting electrodes attached to opposite
faces of the piezoelectric material. Given this equivalent circuit, it is not hard to show that a
piezoelectric crystal can form the heart of a band pass filter, and hence, the basis of a band pass
oscillator.
Although piezoelectric crystal oscillators can oscillate at frequencies as low as 10 kHz , they
typically oscillate at frequencies between 1 and 10 MHz . Their frequency range can be extended
to frequencies up to a few hundred megahertz by means of special tricks. Like Colpitts and
Hartley oscillators, therefore, piezoelectric crystal oscillators can operate at much higher
frequencies than the various RC oscillators that we considered earlier.
In addition to high frequency operation, piezoelectric crystal oscillators offer two main features,
one recently important and one long important. The unrelenting trend toward miniaturization in
contemporary electronics has made the capacitors and inductors required for high frequency
band pass oscillators begin to seem huge and cumbersome. For typical frequencies of oscillation,
a piezoelectric crystal in a practical oscillator will occupy less than 100 mm3 , hundreds of times
less than the volume necessary for the coil and capacitor in Colpitts or Hartley oscillators. Since
the early days of electronics, piezoelectric crystal oscillators have been known for offering
incomparable frequency stability, a feature perhaps more important today than ever before.
A rather peculiar feature of piezoelectric crystal oscillators is that the crystal can vibrate
mechanically not only at its fundamental frequency, but at harmonics of that frequency, as well.
This phenomenon is analogous to the fact that a taut string can vibrate at multiples of the lowest
possible frequency of oscillation. Oscillation at these overtones of the fundamental frequency
permits oscillators with piezoelectric crystals of reasonable size to operate at frequencies up to a
few hundred Mhz. In this respect, overtones provide a desirable feature. Overtone vibrations at
harmonic frequencies, however, also mean that a piezoelectric crystal used as a band pass filter
has pass bands at harmonics of the fundamental frequency as well as at the fundamental
frequency itself. Consequently, harmonic suppression in a piezoelectric crystal band pass filter
oscillator is not as effective as in Colpitts or Hartley oscillators. Therefore, it is usually necessary
to pass the output of a piezoelectric crystal oscillator through an LC band pass filter to achieve

harmonic suppression comparable to the in Colpitts or Hartley oscillators. In practice, the pattern
of resonant frequencies in piezoelectric crystals is actually even a little more complicated than
we just described. The three-dimensional nature of the piezoelectric crystal permits it to vibrate
at more than one fundamental frequency, as well as the harmonics of each one of these. Thus,
piezoelectric crystals can exhibit resonant frequencies that are not obviously harmonically
related.
Historically, the major disadvantage of piezoelectric oscillators was inflexibility: they operate at
a single fixed frequency. Today, however, phase-locked loops and digital technology have
liberated piezoelectric crystal oscillators from the severe limitation of single frequency operation
and made them widely useful.
A typical quality factor, Q , ( 2 divided by the fraction of the oscillatory energy dissipated
during each cycle of oscillation) for a piezoelectric crystal is a few hundred thousand, about
10,000 times larger than we can usually achieve with practical LC circuits. This high Q gives a
piezoelectric band pass filter narrow bandwidth. Because

fo
Q

the bandwidth, f , of a piezoelectric crystal filter with a center frequency, f o , of 1MHz , for
example, could be less than 10 Hz , an impossible achievement for LC band pass filters, for
which Q values of 10 or so are typical. In the equivalent circuit above, the inductor, L , may
have values of a few 100 H , the series capacitor, Cs , may have values of a few tenths of a
femtofarad ( 1015 F ), and the series resistor, Rs , may have values of a few tens of k . The
parallel capacitance, C p , results mainly from the dielectric properties of the piezoelectric
material between the conducting electrodes, often plated directly on the piezoelectric material. Its
value is typically a few picofarads.
With these values in mind, let's look at the impedance, Z s , of the piezoelectric crystal.

Z s

Z s

1
1
sC p
1
sL
Rs
sCs

sL

1
Rs
sCs

1
1 sC p sL
Rs
sCs

s 2 LCs 1 sCs Rs
sCs s 3 C p Cs L sC p s 2 C p Cs Rs

s2

Z s

Rs
1
s
L
LCs

LCs
sC p Cs
s 2 Cs L 1 sCs Rs
Cp

Rs
1
s
L
LCs
1
Z s
R
1
sC p 1
s2
s s
LC p
LCs
L
s2

Rs
1
s
1
L
LCs
Z s
sC p 2 Rs
1 1
1
s s

L
L C p Cs
s2

We are interested in the sinusoidal steady state response, so we substitute s j and obtain

1
Z j
j C p

Rs
j s 2
L
Rs
j p 2
L

2
2

where

1
LCs

1 1
1

s
L C p Cs

and

Because C p Cs , note that p is only the slightest bit larger than s . Thus, we find

1
Z j j
Cp

Rs
L R j jX j
R

j s
L

2 s 2 j
2 p2

where R j is the resistance and X j is the reactance of the piezoelectric crystal at angular
frequency and, recall, p 2 s 2 .
The dissipative resistance, R j is positive and shows a peak at a frequency between s and
p , but is otherwise uninteresting for our present purposes. Here is a sketch of the reactance,

X j , of the piezoelectric crystal vs. frequency:

Note that the reactance, X j , is positive only for frequencies, , in the range s p .
That is, for frequencies between s and p , the piezoelectric crystal behaves as an inductor.
(Outside this range, it behaves as a capacitor.) Because s and p are nearly coincident, the
crystal behaves as an inductor over only an extremely narrow range of frequencies. Because
piezoelectric crystal oscillators are designed to rely on the effective inductance for their
operation, the possible frequency of oscillation is limited to the extremely narrow frequency
range over which the piezoelectric crystal behaves, indeed, as an inductor. Thus, the frequency of
oscillation is necessarily extremely stable.
A simple example of a piezoelectric crystal oscillator is the Pierce oscillator. Consider the
following FET realization:

The popularity of this circuit is doubtless due to its apparent simplicity it is only necessary to
add a piezoelectric crystal to a fairly standard FET amplifier to form the Pierce oscillator. If the
Pierce oscillator works, it is, indeed, an extremely simple oscillator. During the course of our
analysis, however, we will discover that best operation is achieved if some additional
components are added.
1
Rs at the
Cs
frequency of oscillation. In this case, Cs can be considered to be a short circuit for signals. As a
consequence, the negative feedback for signals that Rs otherwise would provide is eliminated
and the voltage gain for the FET is higher than it would be without the presence of Cs . Note,
however, that Rs still provides negative feedback necessary to achieve good bias stability.
Similarly, we assume that Cd is chosen so that its reactance at the frequency of oscillation is
1
small in comparison to the Thevenin output resistance of the amplifier, Rd :
Rd . Thus,
Cd
Cd also behaves as a short circuit for signals. With these assumptions in mind, we can draw the
following signal equivalent circuit for the Pierce oscillator circuit:

In the circuit above, the capacitor Cs is assumed to be chosen so that

where g m is the mutual transconductance of the FET and, for the moment, we have neglected to
include the small parasitic capacitances associated with the FET so that the diagram is simpler. If
we replace the piezoelectric crystal by the equivalent circuit that we considered before and add
the parasitic capacitances associated with the FET, we obtain:

where Rg Rg1 Rg 2 . Note that Cgd , the gate to drain parasitic capacitance of the FET, parallels

C p , the capacitance between the electrodes of the piezoelectric crystal. For s p , the
inductance of the piezoelectric crystal, together with the gate-to-source capacitance, C gs , and the
drain-to-source capacitance, Cds , form a variation of the Colpitts oscillator configuration. The
variation is that the junction of the capacitive voltage divider formed by C gs and Cds is
connected to ground whereas the output of the feedback network is taken from the end of the
inductor that is opposite to the end connected to the drain of the FET. At the LC resonant
frequency, the effect of this variation is to reverse the sign of the voltage fed back to the input of
the FET amplifier in comparison with the Colpitts configuration that we considered earlier. This
sign reversal is equivalent to a phase shift of that, in addition to the phase shift of produced
by the signal inversion in the FET, gives a loop phase shift of 2 , necessary to satisfy the phase
part of the Barkhausen condition at resonance. Because C gs and Cds in practical devices are
extremely small (picofards or smaller), the operation of the capacitive voltage divider can be
unduly affected by stray capacitances external to the transistor package. As a consequence, it is
usually prudent, as we will become clear during the course of the analysis, to place larger
external capacitors in parallel with them to improve reliability of the oscillator performance.
To derive the Barkhausen conditions for the Pierce oscillator, we write node equations at the gate
and drain terminals of the FET:

(1)

1
Vgs s Vout s
Vgs s
sCgs
0
Z s

Rg

(2)

1
Vout s Vgs s
Vout s
sCds
g mVgs s 0
Z s
Rd

where, recall,

R
s 2 s s s 2
1
L
Z s
s C p s 2 Rs s 2
p
L
is the impedance of the piezoelectric crystal equivalent circuit. We rewrite equations 1 and
equation 2 as a pair of pair of simultaneous linear algebraic equations with Vgs s and Vout s
as unknowns:

(1) '

1
1
1
Vgs s
sCgs
Vout s
0
Z s
Rg
Z s

(2) '

1
1
1
Vgs s g m
sCds
Vout s
0
Z s
Z s

Rd

From equation 1 ' , we solve for Vgs s in terms of Vout s :

Vgs s

1
Z s
1
1
sCgs
Rg
Z s

Vout s

We can use this result to eliminate Vgs s from equation 2 ' :

gm

Z s
1
1
Z s

sCds
1
Vout s 0
1
R
Z
s

sCgs
Z s
Rg

1
1
1
1 1
1

V s 0

sC

sC

ds
gs
Z s
Z s Rg
Z s out
Rd
Z s



Z s
Z s
sCds Z s 1
sC gs Z s 1 Vout s 0
g m Z s 1
Rd
Rg

Z s
Z s
g m Z s 1
sCds Z s
sC gs Z s
Rd
Rg

Vout s 0

Z
s
Z
s

R sCds Z s R sC gs Z s 1

d
g

1
1
g m Z s
sCds
sC gs
Rd
Rg

Vout s 0
1
1

R sCds R sC gs

d
g

1 1
1

1
g m Z s
s 2 Cds C gs s
C gs
Cds
Rg

Rd

Rd Rg

Vout s 0
1
1

R R s Cds C gs

d
g

1 1
1

1
g m Z s
s 2 Cds C gs s
C gs
Cds
Rg

Rd

Rd Rg

Vout s 0
1
1

R R s Cds C gs

d
g

Since we are interested in the sinusoidal steady state response, we switch to phasor notation by
substituting s j :

1 1
1

1
2
g m Z j
j Cds Cgs j C gs
Cds
R

Rg

Rd Rg
d
V 0

out
1
1

R R j Cds Cgs

d
g

At this point, we take time out to discover a simple approximate form for.

Z j R j jX j j

Rs
L
Rs
j
L

2 s 2 j

1
C p Cgd 2 2
p

where we have added C gd to C p , as mentioned above. A typical value of

Rs 104
~
~ 100 so
L
100

Rs
terms in Z j are, except for
L
frequencies quite near p , negligible in comparison to 2 and to p 2 and s 2 . The main effect
R
of the j s term in the denominator is to limit the magnitude of the impedance to finite values
L
at frequencies quite near p ,. Thus, we use the approximate form
that for frequencies greater than 105 rad / sec , the j

2 s 2
1
Z j R j jX j j
C p Cgd 2 p 2
In this approximation, therefore, R j 0 and

Z j jX j
where

X j

2 s 2
1
C p Cgd 2 p 2

Thus, we can write our consistency condition as:

1 1
1

1
g m jX j
2Cds Cgs j Cgs
Cds
R

Rg

Rd Rg
d
V 0

out
1
1

R R j Cds Cgs

d
g

1 1

1
g m jX j
2 Cds Cgs X j
Cgs
Cds
Rg

Rd

Rd Rg

Vout 0
1
1

R R j Cds Cgs

d
g

1
1
1
C gs
Cds

g m X j
Rg
Rg
Rd
Rd

1 1

jX
j

C
C

ds gs j Cds C gs

R
R

d
g

Vout 0

For useful outputs, Vout 0 so that the curly brackets must be zero. Because the content of the
curly brackets is a complex number, its real and imaginary parts must be zero separately. Let's
first consider the consequences of setting the imaginary part to zero:

1 1

X j
2CdsCgs Cds Cgs 0
Rd Rg

Recalling the approximate form

X j

2 s 2
1
C p Cgd 2 p 2

we find

2 s 2 1 1
1
2

C
C

ds gs Cds C gs 0
C p Cgd 2 p 2 Rd Rg

2 s 2
p2 2

1 1

2 Cds C gs

Rd Rg

2 s 2
p2 2

1
1
1
2 2

C Cgd 0

Cds Cgs p
Rd Cds Rg Cgs

ds

C gs C p C gd 0

For proper operation of the circuit, we need to choose values so that

1
1
2
Rd Cds Rg Cgs
to minimize dependence of the oscillator frequency, as determined by the equation above, on the
resistors Rd and R g . (We prefer the frequency to depend only on the piezoelectric crystal
parameters.) During design, we can satisfy the inequality by choosing large values for Rd and
R g and/or by adding external supplemental capacitances in parallel with Cds and C gs .
Supplementing the values of Cds and C gs with sufficiently large fixed external capacitors also

has the advantage of making the equation above for the frequency of the oscillator independent
of all transistor parameters. Of course, we must be careful not to make design choices that will
require unrealistic values of the transconductance, gm , to realize unity loop gain. We'll return to
this issue later.
If the inequality above is satisfied, then the equation for the oscillator frequency becomes

1
2 s 2
1
2
2

C Cgd 0

Cds Cgs p
p2 2

or

1
2 s 2
1

C Cgd
2
2
Cds Cgs p
p

where

1
1

C p Cgd 0
Cds Cgs

is a positive dimensionless constant. Proceeding, we find

2 s 2 p 2 2

s 2 p 2

s 2 p 2

Note that, regardless of the value of , the frequency of oscillation is constrained to lie between
s and p :

s 2 2 p 2
Thus, the frequency of oscillation is forced, by the piezoelectric crystal, to lie within a very
narrow range. Remember that it is only in this frequency range that the piezoelectric crystal
behaves as an inductor, a component essential for the basic Colpitts to function as an oscillator.
We now return to the equation

1
1
1
1
Cds

g m X j Cgs

Rd
R
R
R

d
g
g

Vout 0
1 1

2
jX j R R Cds Cgs j Cds Cgs
d g

and consider the consequences of the real part of its curly brackets being zero:

1
1
1
1
gm X j Cgs
Cds

0
Rd

R
R
R
g
d
g

If we use our earlier result that

X j

2 s 2
1
C p Cgd 2 p 2

then we see

gm

2 s 2
1
C p Cgd 2 p 2

1
1
1
1
Cds

0
Cgs
R
R
R
R
d
g
d
g

gm

s 2 2
C p Cgd 2 p 2

1
1
1
1

Rg
Rd Cds Rg Cgs Rd

Cgs Cds

Recall that

1
2 s 2
1

C Cgd

Cds Cgs p
p2 2

Thus,

gm

1
1
1
1
1
1

C p Cgd

Rg Cgs Rd
Rg
C p Cgd Cds Cgs
Rd Cds
Cgs Cds

1
1
1
1
gm Cds Cgs

Rd Cds
Rg Cgs Rd
Rg

gm

Cds Cgs
RC
1
1

1 d ds
Rd Cds
Rg Cgs Rd
Rg

gm

1
Rd

Cgs

Rd Cds
1
1

1
1
Cds
Rg Cgs Rd
Rg

Because the drain in an FET is much further away from the source than is the gate, we find, in
practice, Cds C gs . In practice, it is also true that the parallel combination of the gate resistors,
Rg Rd , the drain resistor. With little error, then, we can write

gm

C gs
1
1
1

Rd
Cds Rd

gm

1
Rd

or

C gs

Cds

This equation gives the critical minimum value of g m necessary to achieve unity loop gain. To
make the loop gain slightly larger to improve reliability in the operation of the oscillator, we
should choose g m to be larger than the minimum value given by the equation:
gm

1 Cgs
Rd Cds

Notice that the minimum transconductance, g m , depends only on the ratio of the capacitances.
Note also that the required g m can be reduced by increasing Rd and/or Cds . Increasing Rd
increases the voltage gain of the FET amplifier, as we have seen. For a given operating point for
the FET, however, increasing Rd means increasing the power supply voltage, which may not be
easy to do. Increasing Cds increases the fraction of the output fed back into the input. Increasing
Cds also helps us to satisfy the inequality

1
1
2
Rd Cds Rg Cgs
Thus, it makes sense to add an external capacitor in parallel with Cds to decrease the g m
required for oscillation and to reduce the sensitivity of the frequency of oscillation to values of
the resistors Rd and R g . If it does not make satisfying the above inequality too difficult, we can
add a supplemental external capacitor in parallel with C gs to make the frequency of oscillation
essentially independent to the values of any parameters except those of the piezoelectric crystal,

which are remarkable stable. If extreme frequency stability is required, the piezoelectric crystal
can be placed in a controlled temperature oven to reduce even further the already slight variation
of the piezoelectric crystal parameters caused by changes in temperature. A further advantage of
increasing Cds is that it, together with Rd , provides low pass filtering of the output to reduce
harmonic content and prevent oscillations at overtones.
Recall that the transconductance, g m , for an FET is given by
gm

2 I dss Vgsq
1

V p V p

where V p and I dss are parameters for a particular FET and Vgsq is the bias value of the gatesource voltage. The value of g m for a particular FET is greatest when Vgsq 0 . To achieve this
condition, the Pierce oscillator circuit that we showed initially is often modified by setting
Rs 0 and letting Rb2 . With Rs 0 note that Cs is unnecessary.
If we redraw our initial circuit to reflect the addition of supplemental external capacitors for Cds
and C gs , as well as the removal of Rs , Rb2 and Cs , we have:

where Cdsx and Cgsx are the supplemental external capacitors for Cds and C gs , respectively. This
configuration, with external capacitors, is sometimes called a Colpitts crystal oscillator, rather
than a Pierce crystal oscillator. In practice, a CMOS inverter is often substituted for the FET.
Note that despite the changes, the signal equivalent circuit that we analyzed still applies, and
hence all of our analysis still holds, provided only that we replace Cdsx and Cgsx with
Cdsx Cdsxx and Cgsx Cgsxx , respectively.

UNIT-I

15.Additional Topics/Known Gaps

1. Effect of cascading on Bandwidth in multistage amplifiers.
2. Characteristics of MOS transistor to obtain small signal equivalent model.
3. Concept of positive feedback its characteristics.
4. Tuned circuits its working principle used in tuned amplifiers

16. UNIVERSITY QUESTION PAPERS WITH PREVIOUS

YEAR

II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011

ELECTRONIC CIRCUIT ANALYSIS

(Common to Electronics & Communication Systems, Electronics & Computer
Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics, Instrumentation &
Control Engineering)
Time: 3hours
Max. Marks: 75
Answer any FIVE questions
All Questions Carry Equal Marks
1.a) For the CB amplifier circuit shown, compute RIN and ROUT if C1 is i) Connected ii) Not connected
The h-parameters of the transistor in CE configuration are listed as:
hie = 2.1K, hfe = 81, hoe = 1.66 Mhos and hre is negligibly small.

b) Reason out the causes and results of Phase & Frequency distortions in transistor
amplifiers.
[9+6]
2.a) Differentiate between direct and capacitive coupling of multiple stages of amplifiers.
b) With the help of a neat circuit diagram, describe the working of a cascode amplifier.
c) What are the merits and demerits of a cascade amplifier over a simple Common Emitter amplifier?
[4+7+4]
3.a) Derive the expressions for hybrid conductance, gce, and gbb of a transistor.
b) Explain how hybrid parameters, gm and gce vary with Ic, Vce and temperature.
c) Compute the overall lower cut-off frequency of an identical two stage cascade of

amplifiers with individual lower cut-off frequency given as 432 Hz.

[7+4+4]

4.a) Discuss the effect of different type of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations.
[8+7]
5.a) If negative feedback with a feedback factor, of 0.01 is introduced into an amplifier
with a gain of 200 and bandwidth of 6 MHz, obtain the resulting bandwidth of the
feedback amplifier.
b) With the help of a suitable BJT based voltage series feedback amplifier diagram,
explain the features and benefits of negative feedback in amplifiers.
[6+9]
6.a) Substantiate the requirement of positive feedback in amplifier for oscillations. Relate
the requirement to Barkhausen Criterion.
b) With the help of neat circuit diagram, explain how sustained oscillations are obtained
in RC phase shift BJT based oscillator. Derive the expression for frequency of
oscillation.
[6+9]
7.a) A single stage class A amplifier Vcc=20V, VCEQ =10V, ICQ =600mA, RL=16 . The ac
output current varies by 300mA, with the ac input signal. Find
i) The power supplied by the dc source to the amplifier circuit.
ii) AC power consumed by the load resistor.
iii) AC power developed across the load resistor.
iv) DC power wasted in transistor collector.
v) Overall efficiency
vi) Collector efficiency.
b). List the advantages of complementary-symmetry configuration over push pull
configuration.
[9+6]
8. Describe the following briefly:
a) Stagger Tuned Amplifiers Operation and comparison with synchronous tuning
b) Heat Sinks for tuned power amplifiers.
[8+7]

II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011

ELECTRONIC CIRCUIT ANALYSIS
(Common to Electronics & Communication Systems, Electronics & Computer
Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics,
Instrumentation & Control Engineering)
Time: 3hours
Max. Marks: 75
Answer any FIVE questions
All Questions Carry Equal Marks
1. For the amplifier circuit shown with partially unbypassed emitter resistance, calculate
the voltage gain with R4 in place and with R4 shorted. Consider hie = 1.1K, hfe =
100, hre & hoe are negligibly small. Assume R1 and R2 to be 100K and 22 K
respectively.

b) Analyse what the output voltage should be if the DC power supply given to a CE
amplifier is shorted to ground.
[10+5]
2.a) With the help of circuit diagram and equivalent circuit of a Darlington amplifier
generate the expression for the overall input impedance of the pair.
b) Develop a generalized expression for overall current gain(AIS) when two transistor
stages with ROUT2 < RL, ROUT1 > RIN2, RIN1> RS and individual voltage gains are AV1,
AV2.
[7+8]
3.a) A transistor amplifier in CE configuration is operated at high frequency with the
following specifications. fT=6MHz, gm=0.04,hfe =50, rbb =100 , Rs =500 , Cbc
=10pF, RL=100 . Compute the voltage gain, upper 3dB cut-off frequency, and gain

bandwidth product (GBW).

b) Derive an expression for the overall higher cut-off frequency of a two stage amplifier
with identical stages of individual higher cut-off frequency, fH.
[7+8]
4.a) Discuss the effect of different type of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations.
[8+7]
5.a). If the non-linear distortion in a negative feedback amplifier with an open loop gain of
100 is reduced from 40% to 10%with feedback, compute the feedback factor, of the
amplifier.
b) Draw the circuit diagram of a current series feedback amplifier, Derive expressions to
show the effect of negative feedback on input & output impedances, bandwidth,
distortion of the amplifier.
[6+9]
6.a) Differentiate between RC and LC type oscillators.
b) Derive the expression for frequency of oscillation in a Hartley Oscillator.
c) State Barkhausen Critterion for Oscillations
[5+7+3]
7.a) Derive the expression for maximum conversion efficiency for a simple series fed
Class A power amplifier.
b) What are the drawbacks of transformer coupled power amplifiers?
c) A push pull amplifier utilizes a transformer whose primary has a total of 160 turns
and whose secondary has 40 turns. It must be capable of delivering 40W to an 8
load under maximum power conditions. What is the minimum possible value of Vcc?
[5+4+6]
8.a) List possible configurations of tuned amplifiers.
b) Derive an expression for bandwidth of a capacitive coupled tuned amplifier in CE
configuration. Make necessary assumptions and mention them.
[6+9]

R09 SET No -3 CODE NO: R09220402

II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
ELECTRONIC CIRCUIT ANALYSIS
(Common to Electronics & Communication Systems, Electronics & Computer
Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics,
Instrumentation & Control Engineering)
Time: 3hours
Max. Marks: 75
Answer any FIVE questions
All Questions Carry Equal Marks
1.a) For the common emitter amplifier shown, draw the AC and DC load lines. Determine
the peak-to-peak output voltage for a sinusoidal input voltage of 30mV peak-to-peak.
Assume C1, C2 and C3 are large enough to act as short circuit at the input frequency.
Consider hie = 1.1K, hfe = 100, hre & hoe are negligibly small.

b) State Millers theorem. Specify its relevance in the analysis of a BJT amplifier.
c) Write expressions for AV and RIN of a Common Emitter amplifier.
[7+4+4]
2.a) Derive expressions for overall voltage gain and overall current gain of a two-stage RC
coupled amplifier.
b) List out the special features of Darlington pair and cascode amplifiers.
[9+6]
3.a) Discuss the effect of emitter bypass capacitor and input & output coupling capacitors
on the lower cut-off frequency if number of amplifiers are cascaded.
b) Describe how an emitter follower behaves at high frequencies.
[8+7]
4.a) Discuss the effect of different types of loads to a common source MOS amplifier.

b) Differentiate between cascode and folded cascode configurations.

[8+7]

5.a) The and the open loop gain of an amplifier are -10% and -80 respectively. By how
much % the closed loop gain changes if the open loop gain increases by 25%?
b) Compare the characteristics of feedback amplifiers in all the four configurations.
c) Reason out why 2 stages are required to implement current shunt feedback. [5+6+4]
6. Starting from the description of a generalized oscillator, derive the expression for
frequency of oscillation in a colpitts oscillator.
[15]
7.a) With the help of a suitable circuit diagram, show that the maximum conversion
efficiency of a class B power amplifier is 78.5%.
b) Explain how Total harmonic distortion can be reduced in a Class B push-pull
configured amplifier.
[7+8]
8.a) Derive an expression for the bandwidth of a synchronous tuned circuit.
b) Discuss the necessity of stabilization circuits in tuned amplifiers.
[8+7]
******** R09 SET No -4 CODE NO: R09220402
II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
ELECTRONIC CIRCUIT ANALYSIS
(Common to Electronics & Communication Systems, Electronics & Computer
Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics,
Instrumentation & Control Engineering)
Time: 3hours
Max. Marks: 75
Answer any FIVE questions
All Questions Carry Equal Marks

1.a) Draw the circuit diagram of a common collector amplifier along with its equivalent
circuit. Derive expressions for AV and RI.
b) What is meant by small signal for analyzing a BJT based amplifier?
c) What is non-linear distortion? List the causes for this type of distortion in amplifiers.
[7+4+4]
2.a) Discuss various possibilities of inter-stage coupling of amplifiers.
b) For the two-stage RC coupled amplifier circuit shown, calculate the Individual stage
voltage gains and the overall voltage gain. Input impedance of individual stages is
given as 2.4 K and of individual transistors as 80.
[6+9]

3.a) A transistor has f = 8MHz, and =80.when connected as an amplifier, it has stray
capacitance of 100pF at the output terminal. Calculate its upper 3dB frequency when
Rload is
i) 10K ii) 100K.
b) Discuss the effect of coupling capacitors of a CE amplifier on the overall frequency
response of the amplifier.
[8+7]
4.a) Discuss the effect of different type of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations.
[8+7]
5.a) An amplifier has a gain of 50 with negative feedback. For a specified output voltage,
if the input required is 0.1V without feedback and 0.8V with feedback, Compute and
open loop gain.
b) Through the block schematics, show four types of negative feedback in amplifiers.
c) List the advantages of negative feedback in amplifiers.
[5+5+5]
6.a) List out the merits demerits of oscillators.
b) With the help of suitable schematic and description, show that both positive and
negative feedback are used in a Wien Bridge oscillator. Establish the condition for
oscillations.
[7+8]
7.a) State the merits of using push pull configuration? Describe the operation of class B

push pull amplifier and show how even harmonics are eliminated.
b) A single ended class A amplifier has a transformer coupled load of 8 . If the
transformer turns ration is 10, find the maximum power output delivered to the load.
Take the zero signal collector current of 500mA.
[7+8]
8.a) Derive the expressions for Bandwidth and Q-factor of single tuned, capacitively
coupled amplifiers. List the assumptions made for the derivation.
b) What is stagger tuning? Suggest possible applications.
[9+6]
********

Time: 3 hours Max. Marks.80

Answer any Five questions
All questions carry equal marks
1. Write the analysis of a CE amplifier circuit using h parameters. Derive the expressions for AI, AV, Ri,
R0, AIs, AVs. (16)
2. (a) Sketch two RC-coupled CE transistor stages. Show the middle and low frequency model for one
stage. Write the expressions for current gains. (12)
(b) Draw the circuit diagram of cascode amplifier with and without biasing circuit. What is the
advantages of this. (4)
3. Draw the hybrid-pi model, explain and derive the conductance and capacitances. (16)
4. (a) How even harmonics is eliminated using push-pull circuit, derive the expression. (8)
(b) Write about the operation of a class D amplifier. (8)
5. (a) Derive the expression for bandwidth in terms of resonant frequency and quality factor in case of
double tuned amplifiers. (10)
(b) Differentiate between synchronous tuned amplifiers and tapped tuned amplifiers. (6)
6. Design consideration for video amplifiers. (8)
(b) Explain about cascode video amplifier with neat diagram. (8)
7. Explain the operation of low and high voltage regulators using 723 IC. (16)
8. Explain the basic switching regulator and types of it with neat diagrams. Time: 3 hours Max. Marks.80

ELECTRONIC CIRCUIT ANALYSIS

(Common to Electronics & Communication Systems, Electronics & Computer

Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics,
Instrumentation & Control Engineering)
1. a) For the CB amplifier circuit shown, compute RIN and ROUT if C1 is
i) Connected ii) Not connected
The h-parameters of the transistor in CE configuration are listed as:
hie = 2.1K, hfe = 81, hoe = 1.66 Mhos and hre is negligibly small.
b) Reason out the causes and results of Phase & Frequency distortions in transistor amplifiers.
[9+6]
2. a) Differentiate between direct and capacitive coupling of multiple stages of amplifiers.
b) With the help of a neat circuit diagram, describe the working of a cascode amplifier.
c) What are the merits and demerits of a cascade amplifier over a simple Common Emitter
amplifier?
[4+7+4]
3. a) Derive the expressions for hybrid conductance, gce, and gbb of a tran sistor.
b) Explain how hybrid parameters, gm and gce vary with Ic, Vce and temperature.
c) Compute the overall lower cut-off frequency of an identical two stage cascade of amplifiers
with individual lower cut-off frequency given as 432 Hz.
[7+4+4]
4. a) Discuss the effect of different type of loads to a common source MOS amplifier
b)Differentiate between cascode and folded cascode configurations.
[8+7]
5.a) If negative feedback with a feedback factor, of 0.01 is introduced into an amplifier with a
gain of 200 and bandwidth of 6 MHz, obtain the resulting bandwidth of the feedback
amplifier.
b) With the help of a suitable BJT based voltage series feedback amplifier diagram, explain the
features
and
benefits
of
negative
feedback
in
amplifiers.
[6+9]
6.a) Substantiate the requirement of positive feedback in amplifier for oscillations. Relate the
requirement to Barkhausen Criterion.
b) With the help of neat circuit diagram, explain how sustained oscillations are obtained in RC
phase shift BJT based oscillator. Derive the expression for frequency of oscillation. [6+9]
7.a) A single stage class A amplifier Vcc=20V, VCEQ =10V, ICQ =600mA, RL=16 . The ac
output current varies by 300mA, with the ac input signal. Find
i) The power supplied by the dc source to the amplifier circuit.
ii) AC power consumed by the load resistor.
iii) AC power developed across the load resistor.
iv) DC power wasted in transistor collector.
v) Overall efficiency
vi) Collector efficiency.
b). List the advantages of complementary-symmetry configuration over push pull configuration.
8. Describe the following briefly:
a) Stagger Tuned Amplifiers Operation and comparison with synchronous tuning
b) Heat Sinks for tuned power amplifiers. [8+7]
II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
ELECTRONIC CIRCUIT ANALYSIS

(Common to Electronics & Communication Systems, Electronics & Computer

Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics,
Instrumentation & Control Engineering)
--1. For the amplifier circuit shown with partially unbypassed emitter resistance, calculate the
voltage gain with R4 in place and with R4 shorted. Consider hie = 1.1K, hfe = 100, hre &
hoe are negligibly small. Assume R1 and R2 to be 100K and 22 K respectively.
b) Analyse what the output voltage should be if the DC power supply given to a CE amplifier is
shorted to ground. [10+5]
2.a) With the help of circuit diagram and equivalent circuit of a Darlington amplifier generate the
expression for the overall input impedance of the pair.
b) Develop a generalized expression for overall current gain(A IS) when two transistor stages
with ROUT2 < RL, ROUT1 > RIN2, RIN1> RS and individual voltage gains are AV1, AV2. [7+8]
3.a) A transistor amplifier in CE configuration is operated at high frequency with the following
specifications. fT=6MHz, gm=0.04,hfe =50, rbb =100 , Rs =500 , Cbc =10pF, RL=100
. Compute the voltage gain, upper 3dB cut-off frequency, and gain bandwidth product
(GBW).
b) Derive an expression for the overall higher cut-off frequency of a two stage amplifier with
identical stages of individual higher cut-off frequency, fH. [7+8]
4.a) Discuss the effect of different type of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations.

[8+7]

5.a). If the non-linear distortion in a negative feedback amplifier with an open loop gain of 100 is
reduced from 40% to 10%with feedback, compute the feedback factor, of the amplifier.
b) Draw the circuit diagram of a current series feedback amplifier, Derive expressions to show
the effect of negative feedback on input & output impedances, bandwidth, distortion of
the amplifier. [6+9]
6.a) Differentiate between RC and LC type oscillators.
b) Derive the expression for frequency of oscillation in a Hartley Oscillator.
c) State Barkhausen Critterion for Oscillations [5+7+3]
7.a) Derive the expression for maximum conversion efficiency for a simple series fed Class A
power amplifier.
b) What are the drawbacks of transformer coupled power amplifiers?
c) A push pull amplifier utilizes a transformer whose primary has a total of 160 turns and whose
secondary has 40 turns. It must be capable of delivering 40W to an 8 load under
maximum power conditions. What is the minimum possible value of Vcc?
[5+4+6]
8.a) List possible configurations of tuned amplifiers.
b) Derive an expression for bandwidth of a capacitive coupled tuned amplifier in CE
configuration. Make necessary assumptions and mention them. [6+9]
II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011
ELECTRONIC CIRCUIT ANALYSIS

(Common to Electronics & Communication Systems, Electronics & Computer

Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics,
Instrumentation & Control Engineering)
Time: 3hours Max. Marks: 75
Answer any FIVE questions
All Questions Carry Equal Marks
--1.a) For the common emitter amplifier shown, draw the AC and DC load lines. Determine the
peak-to-peak output voltage for a sinusoidal input voltage of 30mV peak-to-peak.
Assume C1, C2 and C3 are large enough to act as short circuit at the input frequency.
Consider hie = 1.1K, hfe = 100, hre & hoe are negligibly small.
b) State Millers theorem. Specify its relevance in the analysis of a BJT amplifier.
c) Write expressions for AV and RIN of a Common Emitter amplifier. [7+4+4]
2.a) Derive expressions for overall voltage gain and overall current gain of a two-stage RC
coupled amplifier.
b) List out the special features of Darlington pair and cascode amplifiers. [9+6]
3.a) Discuss the effect of emitter bypass capacitor and input & output coupling capacitors on the
lower cut-off frequency if number of amplifiers are cascaded.
b) Describe how an emitter follower behaves at high frequencies. [8+7]
4.a) Discuss the effect of different types of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations. [8+7]
5.a) The and the open loop gain of an amplifier are -10% and -80 respectively. By how much %
the closed loop gain changes if the open loop gain increases by 25%?
b) Compare the characteristics of feedback amplifiers in all the four configurations.
c) Reason out why 2 stages are required to implement current shunt feedback. [5+6+4]
6. Starting from the description of a generalized oscillator, derive the expression for frequency of
oscillation in a colpitts oscillator.
[15]

7.a) With the help of a suitable circuit diagram, show that the maximum conversion efficiency of
a class B power amplifier is 78.5%.
b) Explain how Total harmonic distortion can be reduced in a Class B push-pull configured
amplifier. [7+8]
8.a) Derive an expression for the bandwidth of a synchronous tuned circuit.
b) Discuss the necessity of stabilization circuits in tuned amplifiers. [8+7]
********

II B.TECH - II SEMESTER EXAMINATIONS, APRIL/MAY, 2011

ELECTRONIC CIRCUIT ANALYSIS
(Common to Electronics & Communication Systems, Electronics & Computer
Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics, )
1.a) Draw the circuit diagram of a common collector amplifier along with its equivalent circuit.
Derive expressions for AV and RI.
b) What is meant by small signal for analyzing a BJT based amplifier?
c) What is non-linear distortion? List the causes for this type of distortion in amplifiers.
2.a) Discuss various possibilities of inter-stage coupling of amplifiers.
b) For the two-stage RC coupled amplifier circuit shown, calculate the Individual stage voltage
gains and the overall voltage gain. Input impedance of individual stages is given as 2.4
K and of individual transistors as 80. [6+9]
3.a) A transistor has f = 8MHz, and =80.when connected as an amplifier, it has stray
capacitance of 100pF at the output terminal. Calculate its upper 3dB frequency when
Rload is
i) 10K ii) 100K.
b) Discuss the effect of coupling capacitors of a CE amplifier on the overall frequency
response of the amplifier. [8+7]
4.a) Discuss the effect of different type of loads to a common source MOS amplifier.
b) Differentiate between cascode and folded cascode configurations. [8+7]
5.a) An amplifier has a gain of 50 with negative feedback. For a specified output voltage, if the
input required is 0.1V without feedback and 0.8V with feedback, Compute and open
loop gain.
b) Through the block schematics, show four types of negative feedback in amplifiers.
c) List the advantages of negative feedback in amplifiers. [5+5+5]
6.a) List out the merits demerits of oscillators.
b) With the help of suitable schematic and description, show that both positive and negative
feedback are used in a Wien Bridge oscillator. Establish the condition for oscillations.
[7+8]
7.a) State the merits of using push pull configuration? Describe the operation of class B push pull
amplifier and show how even harmonics are eliminated.
b) A single ended class A amplifier has a transformer coupled load of 8 . If the transformer
turns ration is 10, find the maximum power output delivered to the load. Take the zero
signal collector current of 500mA. [7+8]
8.a) Derive the expressions for Bandwidth and Q-factor of single tuned, capacitively coupled
amplifiers. List the assumptions made for the derivation.
b) What is stagger tuning? Suggest possible applications. [9+6]

17. UNIT-WISE QUESTION BANK

UNIT 1:
1. Explain the classification of amplifiers?
2. Draw the circuit of CE amplifier and derive expressions for Ri, Ro ,Av &Ai using h-parameter
model?
3. Draw the circuit of CE amplifier with un bypassed emitter resistor and derive expressions for
Ri, Ro ,Av &Ai using approximate h-parameter model?
4. Draw the circuit of CC amplifier and derive expressions for Ri, Ro ,Av &Ai using h-parameter
model?
5. Compare different types of amplifier circuits?
6. Explain the term multistage amplifiers & its advantages?
7. Draw the circuit of two stage RC coupled CE amplifier and derive expressions for Ri, Ro ,Av
&Ai using h-parameter model?
8. Draw the circuit of cascade CB-CE amplifier and derive expressions for Ri, Ro ,Av &Ai using
h-parameter model?
9. Draw the circuit of CC- CE amplifier and derive expressions for Ri, Ro ,Av &Ai using hparameter model?
10. Draw the circuit of Darlington CC amplifier and derive expressions for Ri, Ro ,Av &Ai using
h-parameter model and its merits &demerits ?
UNIT 2:
1. What is frequency response and explain how it is obtained?
2. Explain the relation between low frequency gain &mid frequency gain with suitable expres
sions?
3. Explain the terms B.W, cutoff frequencies of an amplifier circuit?
4. Draw the equivalent circuit of a transistor at high frequencies(i.e) hybrid
5. Explain Gain-bandwidth product for voltage &current?

model?

6. Explain small signal model of a MOS transistor its equivalent circuit?

7. Explain the circuit of CS amplifier with resistive load using small signal model?
8. Explain the circuit of CS amplifier with diode connected load using small signal model?
9. Explain common gate amplifier circuit and derive expressions for Ri, Ro &Av?
10. Draw the circuit for folded cascade amplifier and explain its analysis using small signal
model?
UNIT 3:
1. Show that for voltage shunt feedback amplifier transresistance gain Ri and Ro are decreased by
a factor (1+A) with feedback?
2. Explain the concept of feedback with block diagram applied to an amplifier circuit. What are
the advantages and disadvantages of positive & negative feedback?
3. Draw the circuit diagram of current shunt feedback amplifier and expressions for Rif and Rof?
4. Draw the frequency response of an amplifier with &without feedback and show the bandwidth
for each case and how these two curves are related?
5. Draw the circuit diagram of voltage series feedback amplifier and expressions for Rif and Rof?
6. Explain the concept of positive feedback used in oscillators. State and explain Barkhausen
criterion?
7. Show that the gain of Wien bridge oscillator using BJT amplifier must be at least 3 for the
oscillations to occur?
8. Explain the basic circuit of an LC oscillator and derive the conditions for the oscillations?
9. What are the factors that affect frequency stability of an oscillator? How frequency stability
improved in oscillators?
10. Draw the circuit diagram of RC phase shift oscillator using BJT.derive the expression for
frequency of oscillatoions?

UNIT 4:
1. Explain about class A, class B, class C and class AB operation of power amplifiers?
2. Draw the circuit diagram of complementary symmetry push pull amplifier and its working?
3. Distinguish between crossover distortion and harmonic distortion. How they can be
eliminated?
4. Show that the efficiency of class A amplifier is 50%?
5. Explain the concept of heat sinks?
UNIT 5:
1. What is meant by the term tuned amplifier and briefly explain the various methods of
classification of tuned amplifiers?
2. Draw the ideal and actual frequency response curves of single tuned amplifier?
3. Draw the circuit diagram and small signal A.C equivalent circuit of a single tuned amplifier
with the tank circuit connected at the input side?
4. Derive the expressions for B.W in terms of resonant frequency and quality factor in case of
double tuned amplifiers?
5. Explain in detail the effect of cascading tuned amplifier and hence derive the expression for
B.W of n-stage amplifier. Also draw the frequency response and explain what happens as the no
.of stages increases?

18. Assignment Questions

UNIT 1
Part A:
1. Explain the basic amplifier circuit and its components?
2. Using hybrid model explain the circuit of CB amplifier and derive expressions for Ri, Ro ,Av
&Ai ?
3. Draw the circuit of CE amplifier with un bypassed emitter resistor and derive expressions for
Ri, Ro ,Av &Ai using approximate h-parameter model?

4. Draw the circuit of CC amplifier and derive expressions for Ri, Ro ,Av &Ai using h-parameter
model?
5. Compare different types of amplifier circuits?
Part B:
1. Explain the concept of multistage amplifiers and its merits&demerits?
2. Draw the circuit of Bootstrapped Darlington CC amplifier and derive expressions for Ri, Ro
,Av &Ai using h-parameter model and its merits &demerits ?
3. Draw the circuit of two stage RC coupled CE amplifier and derive expressions for Ri, Ro ,Av
&Ai using h-parameter model?
4. Draw the circuit of cascade CB-CE amplifier and derive expressions for Ri, Ro ,Av &Ai using
h-parameter model?
5. Draw the circuit of CC- CE amplifier and derive expressions for Ri, Ro ,Av &Ai using hparameter model?
UNIT 2
Part A:
1. Explain the frequency response of single stage amplifier?
2. Derive the expressions for lower& upper cutoff frequencies?
3. Explain the terms B.W, cutoff frequencies of an amplifier circuit?
4. Draw the equivalent circuit of a transistor at high frequencies (i.e) hybrid

model?

5. Explain Gain-bandwidth product for voltage &current?

Part B:
1. Explain small signal model of a MOS transistor its equivalent circuit?
2. Explain the circuit of CS amplifier with resistive load using small signal model?
3. Explain the circuit of CS amplifier with diode connected load using small signal model?
4. Explain common gate amplifier circuit and derive expressions for Ri, Ro &Av?
5. Draw the circuit for folded cascade amplifier and explain its analysis using small signal
model?

UNIT 3
Part A:
1. Show that for voltage shunt feedback amplifier transresistance gain Ri and Ro are decreased by
a factor (1+A) with feedback?
2. Explain the concept of feedback with block diagram applied to an amplifier circuit. What are
the advantages and disadvantages of positive & negative feedback?
3. Draw the circuit diagram of current shunt feedback amplifier and expressions for Rif and Rof?
4. Draw the frequency response of an amplifier with &without feedback and show the bandwidth
for each case and how these two curves are related?
5. Draw the circuit diagram of voltage series feedback amplifier and expressions for Rif and Rof?
Part B:
1. Explain the concept of positive feedback used in oscillators. State and explain Barkhausen
criterion?
2. Show that the gain of Wien bridge oscillator using BJT amplifier must be at least 3 for the
oscillations to occur?
3. Explain the basic circuit of an LC oscillator and derive the conditions for the oscillations?
4. What are the factors that affect frequency stability of an oscillator? How frequency stability
improved in oscillators?
5. Draw the circuit diagram of RC phase shift oscillator using BJT.derive the expression for
frequency of oscillatoions?

UNIT 4
1. Explain about class A, class B, class C and class AB operation of power amplifiers?
2. Draw the circuit diagram of complementary symmetry push pull amplifier and its working?
3. Distinguish between crossover distortion and harmonic distortion. How they can be
eliminated?
4. Show that the efficiency of class A amplifier is 50%?
5. Explain the concept of heat sinks?

UNIT 5
1. What is meant by the term tuned amplifier and briefly explain the various methods of
classification of tuned amplifiers?
2. Draw the ideal and actual frequency response curves of single tuned amplifier?
3. Draw the circuit diagram and small signal A.C equivalent circuit of a single tuned amplifier
with the tank circuit connected at the input side?
4. Derive the expressions for B.W in terms of resonant frequency and quality factor in case of
double tuned amplifiers?
5. Explain in detail the effect of cascading tuned amplifier and hence derive the expression for
B.W of n-stage amplifier. Also draw the frequency response and explain what happens as the no
.of stages increases?

19. Unit wise Quiz Questions and long answer questions

Unit 1:
1) Critical capacitance with smallest equivalent resistance that determines the lower cut off of
CB amplifier is
a) I/P coupling capacitor
b) Emitter bypass capacitor if c1 = c2
c) c2 output coupling capacitor
d) None.
2 ).resultant phase shift of odd no of CE amplifier stages at mid band frequency is
a)3600
b) 1800
c) 450
d) 900
3) The miller input capacitance in CB AMP IS
a) Large compared to miller capacitance in CE
b) very large because of +ve voltage gain in CB
c) Small because of +ve voltage gain in CB
d) Is not negligible compare to other capacitance
4) Identify the correct statement regarding the voltage gain of a CE transistor amplifier
a) it increases with increase in ac load R
b) it is independent of ac load R & is large
c) it decreases with increase in ac load R
d) it is always approximately unity

5) Identify the incorrect statement

[d]
a) frequency distortion in an amplifier is mainly due to the reactive component circuit
b) amplitude distortion is also referred to as non-linear distortion
c) distortion in amplifier due to unequal phase shifts at different frequencies is called delay
distortion
d) phase shift distortion is same as frequency distortion
ans: [D ]
6) i/p &o/p capacitors in a transistors amplifier are not referred to as
[a]
a) inter electrode capacitors
b) coupling capacitors
c) blocking capacitors
d) dc de-coupling capacitors
ans : [ A ]

7) CB amplifier of BJT is similar in behaviour with following FET configuration

[a]
a)common gate amplifier
b) common drain amplifier
C) common source amplifier
d)swamped source resistor amplifier
ans:[ A ]
8) The miller i/p capacitance in CB amplifier
[c]
a) Is large compared to miller capacitance in CE
b) is very large because of +ve voltage gain in CB
c) is small because of +ve voltage gain in CB
d) not negligible compared to other capacitance
ans: [ C ]
9) CE is the capacitance of forward biased junction & is therefore
[c]
a) independent of collector current
b) much lager than Cc
c) mainly diffusion capacitance
d) mainly transition capacitance
ans: [ C ]
10) dissipation capability of a transistor is defined as
[a]
a) capability to launch heat generated into the surroundings
b) deviation in power delivered to load resistor

c) capability to withstand the variation in dc power at operating power

d) deviation in o/p & i/p signal wave shapes
ans: [ A ]
11) phase difference between o/p voltage &i/p voltage of a CC amplifier at mid band frequencies
[b]
a) 1800
b) 00
c) 450
d) 900
ans : [ B ]

12) major draw back of Darlington transistor pair

[d]
a) low current gain compared to single emitter follower
b) dependence of Av on transistor selected
c) low i/p impedance compared to single emitter follower
d) dependence of H -parameters on quiescent conditions
ans: [ D ]
13) cascade amplifier is 2- transistor combination has
a) collector of first transistor is connected to the base of second transistor
b) collector current of first transistor is same as emitter current of second transistor
c) emitter current of first transistor is same as the collector current of the second transistor
d) none
14) resultant phase shift of odd no of CE amplifier stages at mid band frequency is a)
3600
b) 1800
c) 450
d) 900
15) major drawbacks of Darlington transistor pair is
a) low current gain compared to single emitter follower
b) dependence of AV on transistor selected condition
c) low i /p impedance compared to single emitter follower
d) dependence of h-parameters on quiescent point.
16) Resultant current gain of a Darlington pair individual current gain of hfe is
[d]
a) hfe/2
b) hfe
c) 2hfe
d) hfe2
ans: [ D ]

17) 2-stage rc coupled amplifier is configured as

[a]
a) 2 capacitively coupled CE stages cascaded
b) a CE stage capacitively coupled to a CC stage
c) 2 capacitively coupled CB stages cascaded.
d) 2 capacitively coupled CC stages cascaded
ans: [ A ]

18) 2-transistor cascade with both collectors tied together & emitter of the transistor connected
to the base of the transistor is referred to as [ a]
a) Darlington pair
b) CE &CC cascade
c) cascade amplifier
d) differential pair
ans: [ A ]
19) the i/p impedance of cascade amplifier is [ b ]
a) hic
b) hie
c) infinity
d) hib
ans: [ B ]
20) type of inter stage coupling resulting in highest overall gain
[c]
a) direct coupling
b)inductive coupling
c) RC coupling
d) transistor coupling
ans : [ C ]
21) main disadvantage of Darlington pair amplifier is
[d]
a) low i/p impedance
b) low current gain
c) high o/p impedance
d)high leakage current
ans: [ D ]
22) Major advantage of boot strap Darlington pair over single Darlington pair is
(a) High overall Av with proper DC biasing
(b) increased Ai irrespective of bias condition
(c) high i/p impedance irrespective of bias condition

(d) increased Ai depending upon the bias condition

Ans: (c)

Unit 2:
1) identify the correct relationship
a) f alpha ~ f beta
b) f beta >> f alpha
c) f alpha ~ ft
d) f alpha >> f beta
2) lower cutoff &higher cutoff frequency of rc coupled amplifier are
a) both zero
b) both infinity
c) zero & infinity respectively
d) similar to those of CE stage

3) voltage gain of an amplifier reduces to 1/(root 2)its max

a) break frequency
b) miller frequency
c) half power frequency
d) cutoff frequency
4) rce >> rbe condition is applicable in hybrid -pie equivalent of CE amplifier because
a) collector base junction is reverse biased & emitter base junction is forward biased
b) o/p R is always much larger than i/p R
c) b is the internal base terminal
d) base region is extremely tin compared to emitter & collector terminals
5) expression for short circuit current gain bandwidth
[d]
a) gm/2pie hfe (ce+cc)
b) gm/(ce+cc)
c) gm/ hfe (ce+cc)
d)gm/2pie (ce+cc)
6) identify the expression for voltage gain CE & fet amplifier at low frequency [ c ]
a) -gm rd Rl /(rd + Rl)
b) gm rd Rl / ( rd +Rl+ gm rd Rl)
c) gm rd Rl /(rd + Rl)
d) Rl || rd / (1+ gm rd)
7) Resultant phase shift of even no of CB amplifier stage at frequency below lower cutoff
frequency [ d ]
a) always a multiple of 2 pie

b) product of phase shift introduced by individual stages

c) always 1800
d) sum of the phase shifts introduced by individual stages
8) Identify the incorrect statement for a high frequency hybrid pie model of a BJT is [ a ]
a) high frequency hybrid pie capacitances can be expressed in terms of low frequency
hparameters
b) capacitance between collector & base terminal of a BJT is called overlap -diode capacitance
c) ' B' represent internal base terminal
d) high frequency hybrid pie conductances can be expressed in terms of low frequency
hparameters.
9) identify false statement [ c ]
a) fbeta & Ic exhibits a peak value of a particular ic.
b) unity gain band width Ft is the function of Ic
c)ft & Ic both are functions of f beta
d) Ft variation with Ic is similar to hfe variation with T
ans: [ C ]
10) during the mid band frequency the gain of amplifier is [ d ]
a) 1/(root 2) times Max value
b) min
c)unity
d) constant
ans: [ D ]
11) bandwidth of an amplifier with lower & higher cutoff frequency Fl & Fh .& quantity factor
Qis [ a ]
a) Fh - F l
b) Fh/ q
c) (Fh-Fl)/1.414
d) q-Fl
ans: [ A ]
12) identify the expression for voltage gain CD & fet amplifier at low frequency
[b]
a) -gm rd Rl /(rd + Rl)
b) gm rd Rl / ( rd +Rl+ gm rd Rl)
c) gm rd Rl /(rd + Rl)
d) Rl || rd / (1+ gm rd)
ans: [ B ]
13) the transconductance gm of a transistor depend on
[b]
a) temperature
b) operation frequency
c) CE voltage

d) C c
ans : [ B ]
14) ft for a ce amplifier is defined as
[b]
a) the frequency at which the CE current gain falls to half its Max value
b) frequency at which CE current gain becomes unity
c) frequency at which CE voltage gain falls to half its Max value
d) frequency at which CE voltage gain becomes unity
15) the capacitance determining the corner frequency lag network at the i/p of CE amplifier is
[b]
a) miller i/p capacitor
b) c wiring
c) external capacitor at the base
d)cbe
ans: [ B ]
16) if Av is the voltage gain of an amplifier in db & Ai is its current gain in db then power gain
of
amplifier in db is [ d ]
a) Av- Ai
b) Av/ Ai
c)10log 10 Av/ Ai
d) Av+Ai
ans : [ D ]
17) at frequency below lower cut off frequency in CE amplifier coupling capacitor at the base of
the amplifier form an LPF [ b ]
a) with emitter resistance
b) with i/p resistance
c) with o/p resistance
d) with base resistance
ans: [ B ]
18) advantage of impedance type inter stage coupling is
[c]
a) very wide band & frequency independent gain curve
b) flat response of frequency in mid band region
c) no dc voltage drop across collector load
d) no requirement of bulky components all frequency
ans: [ C ]
19) resultant phase shift of odd number of CE amplifier stages at mid band frequency is [ b ]
a) 3600
b)1800
c) 450

d) 900
20) lower cutoff & higher cut off frequency of an rc coupled amplifier are
[c]
a) both zero
b) both infinity
c) similar to of CE stage
d) zero& infinity
ans: [ C ]
21) higher cutoff frequency of transistor amplifier is mainly because of
[a]
a) inter electrode capacitance
b) bypass capacitance
c) blocking capacitance
d ) coupling capacitance
22) ratio of slopes of the gain curve of an amplifier below lower cutoff frequency & above cutoff
frequency is [ b ]
a) 3
b) unity
c)2
d) 6
ans: [ B ]
23) the capacitors that are short circuited at low frequencies in CE amplifier are
[d]
a) o/p coupling capacitors
b) i/p coupling capacitors
c) emitter bypass capacitors
d) inter electrode capacitor
ans:[ B ]
24) the critical capacitance that determines the overall cut off frequency of an amplifier is the
one which sees an equivalent resistance [ a ]
a) of minimum value
b) of Max value
c) of infinity value
d) equals to its reactance value at that frequency
ans: [ A ]
25) distortion in amplifiers due to unequal amplitude gains at different frequencies is referred to
as [ c ]
a) phase shift distortion
b) amplitude distortion
c) frequency distortion
d) delay distortion

ans : [ C ]
26) slope of the gain curve of an amplifier below cut off frequency is
[a]
a) -20 db decade
b) 6 db decade
c)-6 db decade
d) 20 db decade
ans : [ A ]
28) the CE short circuit current gain in db at frequency f = Ft is
[d]
a) hfe/1.414
b) unity
c) hfe
d)zero
ans: [ D ]
29). Phase difference between o/p and i/p voltages of a transistor amplifier at lower cut off
frequencies is
a)180 b) 45 c) 0 d) 90
Ans: (b)
30) All frequencies below lower cut off frequency in a CE amplifier, the coupling capacitor at
the base of the amplifier forms a LPF
a)with RE b)Rip c)RB d)Rop
Ans: (b)
31) Phase reversal between i/p & o/p signal voltages occurs in
a) common base amplifier
b) common drain amplifier
c) common gate amplifier
d) common source amplifier
32) FET amplifier configuration , which is similar to CC BJT is
[b]
a) common gate amplifier
b) common drain amplifier
c) common source amplifier
d) swamped source resistor amplifier
ans:[ B ]
33) phase difference between o/p voltage &i/p voltage of a CG amplifier at mid band frequencies
[b]
a) 1800
b) 00
c) 450

d) 900
ans : [ B ]
34) Voltage gain of a given CS FET depends on its
a)Dynamic drain resistance b)i/p impedance
c) Amplification factor d)Drain load resistance
Ans: (d)
35). Resultant phase shift of even no of CG amplifier stages at higher cut off frequencies is
Ans: Sum of phase shift introduced by individual stages.
36) Phase relationship between o/p and i/p voltage of a CS amplifier for frequency below lower
cut-off frequency is
(a) both are in phase
(b) o/p lags i/p
(c) output leads i/p
(d) both are 180 out of phase
Ans: (c)

37). The phase relationship between output and input voltages of a CS amplifier for frequency
above higher cut off frequency is
a) both are 180 degrees out of phase
b) output leads input
c) both are in phase
d) output lags input
Ans: (d)

Unit 3& 4:
1) Non-linear distortion is maximum in
a) class
B mode
b) class A mode
c) class AB mode
d) class C mode
2) final stage of multistage amplifier is generally a) a
pre-amplifier
b) a voltage post amplifier
c) a power amplifier
d) a microphone amplifier
3) Max conversion efficiency of a series fed class A power amplifier is
a) 75
b) 100
c) 50

d) 25
4) even harmonics are not present in the o/p of
a) class A transformer coupled amplifier
b) class c amplifier
c)class A amplifier
d) class B push pull amplifier
5) Even harmonics in the o/p are connected in push - pull configurations only if
[a]
a) both transistors are perfectly matched
b) both NPN & PNP transistors are used
c) A phase inversion is not used at inputs of 2 transistors
d) two power supplies are used
ans:[ A ]
6) i/p signals swing in class A power amplifier is restricted to
[d]
a) a small portion around Q point in active region
b) entire portion around Q point in saturation
c) entire portion around Q point in cutoff
d) entire portion around Q point in active
ans: [ D ]
7) transistor in class C amplifier is based beyond cutoff region to
[b]
a) ensure reduced distortion of o/p signal
b) ensure conduction angle of less than 1800
c) ensure conduction angle of transistor for entire i/p cycle
d) ensure o/p wave shape to the replica of i/p wave shape
ans: [ B ]
8) increased conversion efficiency in class B over class A operation is mainly due to
[b]
a) elimination of all higher harmonics
b) elimination of dc current in the load
c) usage of single power supply
d) elimination of cross over distortion
ans: [ B ]
9). The frequency at which CE is short circuit current gain becomes unity is represented
by__fT_______
71. Non linear distortion is maximum in
a) Class B mode a) Class A mode
a) Class AB mode d) a) Class C mode
Ans: (b)
10). Even harmonics are not present in the o/p of Class B push pull amplifier.

11) Cross over distortion in class B amplifier is due to

(a) finite cut-off voltage of the two transistors
(b) non-identical behaviour of the two transistors
(c) elimination of two power supplies in the circuit
(d) elimination of even harmonics in the o/p
impedance

Unit 5
1. A parallel tuned circuit is also known as
a. matched circuit b. notch circuit
c. resonant circuit
d. anti resonant circuit
2. In tuned amplifiers equivalent circuits, the model used for transistor is a. hybrid -
b. Thevinen's
c. y parameter d. z parameter
3. What factors govern the selectivity of a single tuned amplifier ?
a. resonant frequency and gain
b. quality factor and bandwidth
c. quality factor and gain d. gain and bandwidth
4. The harmonic distortion of an ideal tuned amplifier is
a. unity
b. zero
c. infinity
d. depends on tuned circuit
5. Higher quality factor of a single tuned amplifier provides a
a. higher selectivity and bandwidth b. smaller selectivity and bandwidth
c. higher selectivity and smaller bandwidth
d. smaller selectivity and higher bandwidth
6. The function of tuned circuit in Tuned Amplifier is
a. allows only dc signal
b. reject dc and allow all frequencies
c. selecting a particular frequency and rejecting all other frequencies
d. passing all frequencies
7. In tuned amplifiers, harmonic distortion is very small because, at these frequencies
a. the impedance is high and gain is low b. the impedance is low and gain is high
c. the impedance and gain of the amplifier becomes high
d. the impedance and gain of the amplifier becomes negligible

8. If the quality factor of a resonant circuit of tuned amplifier is doubled then the bandwidth is
a. doubled b. same
c. halved
d. zero
9. The Band width of an ideal tuned amplifier is
a. unity
b. zero
c. infinity
d. depends on tuned circuit
10. The drawbacks of a single tuned amplifier are
a. wider bandwidth and the sides of gain versus frequency curve are steeper
b. wider bandwidth and the sides of gain versus frequency curve are not steeper
c. narrow bandwidth and the sides of gain versus frequency curve are not steeper
d. narrow bandwidth and the sides of gain versus frequency curve are steeper
11. The tapping of inductance of tuned circuit of a tapped single tuned capacitance coupled
amplifier
a. increases the impedance of resonant circuit b. increases the operating frequency
c. increases the resonant frequency
d. reduces the impedance of resonant circuit
12. In the tapped single tuned capacitance coupled amplifier the output voltage when the coil is
tapped a. (1-n) times of the voltage developed across the complete coil
b. n times of the voltage developed across the complete coil c. same as the voltage developed
across the complete coil
d. half of the voltage developed across the complete coil
13. Tapping in the LC tuned circuit is used to
a. reduce the impedance of the LC circuit to match the low impedance of the CE amplifier
b. increase the impedance of the LC circuit to match the low impedance of the CE amplifier c.
reduce the impedance of the LC circuit to match the high impedance of the CE amplifier d.
increase the impedance of the LC circuit to match the high impedance of the CE amplifier
15. The tapping point in a tapped single tuned capacitance coupled Amplifier divide the
inductance L into two part such that
a. L1= 2L and L2 = L/2
b. L1= ( n-1)L and L2 = (1-n)L
c. L 1=nL and L 2 = (1-n)L
d. L1=n/L and L2 = (1-n)/L
16. The gain bandwidth product of a single tuned capacitive couple amplifier is
a. depends on transconductance and independent on total input circuit capacitance
b. depends on both transconductance and total input circuit capacitance
c. independent on both transconductance and total input circuit capacitance

d. independent on transconductance and dependent on total input circuit capacitance

17. The LC tuned circuit of single tuned capacitive coupled amplifier is not connected between
collector and ground because
b. inductor
c. transistor collector
d. capacitor
18. In a single tuned transformer coupled amplifier, the output is taken by
a. capacitive coupling b. inductive coupling c. resistive coupling
d. frequency coupling
19. The sharpness of the frequency response curve if the transformer coupled amplifier is
depends on the
a. impedance of the tuned circuit
b. resonance frequency of tuned circuit c. the gain of the transistor
d. quality factor of the tuned circuit
20. In a single tuned transformer coupled amplifier the output of the tuned circuit is coupled to
the next stage or
output device through a
a. resistor
b. inductor
c. transistor collector
b. single tuned resistive coupled amplifier
c. Inductively coupled amplifier
d. single tuned capacitive coupled amplifier
21. In a single tuned transformer coupled amplifier the matching between two stages is done by
a. coil tapping
b. using pad circuits
c. capacitively coupled circuit
d. the transformer turns ratio
22. In a single tuned transformer coupled amplifier, under conditions of maximum transform of
power, total resistance appearing is shunt with the coil equals
a. R02
b. R0/2
c. R0
d. 2R0

20. Tutorial Problems (Classes)

UNIT 1:

Classification of amplifiers& distortion in amplifiers.

Analysis of CE, CB configurations with Hybrid model.
Design of single stage amplifier using BJT.
Millers theorem its dual.
Analysis of Cascaded RC coupled BJT amplifiers.
Cascode amplifier& Darlington pair
Different coupling schemes used in amplifiers.
RC coupled, Transformer coupled& direct coupled amplifiers.

UNIT 2:

Frequency response of single stage BJT amplifier.

Effect of coupling &bypass capacitors on frequency response.
The hybrid model at high frequencies.
Gain bandwidth product.
Small signal model of a MOS transistor.
CS amplifier with resistive load using small signal model.
CS amplifier with diode connected load using small signal model.
CG cascode and folded cascode amplifier and its analysis using small signal model?

UNIT 3:

The concept of feedback & advantages and disadvantages

Classification of feedback amplifiers.
Characteristics of negative feedback & its effect on amplifiers.
Voltage series &shunt, current series& shunt feedback configurations.
Classification of oscillators &conditions for oscillations.
RC phase shift& Wien bridge oscillators.
Generalized analysis of LC oscillators .
Crystal oscillators.

UNIT 4:

Classification of power amplifiers.

Class A,B&AB power amplifiers.
Efficiency of power amplifiers.
Thermal runaway &heat sinks.

UNIT 5:

Small signal Tuned amplifiers.

Effect of cascading on B.W of tuned amplifiers.
Stagger tuned amplifiers.
Stability of tuned amplifiers.

21. Known gaps, if any and inclusion of the same in lecture

schedule
1. Characteristics of MOS transistor to obtain small signal equivalent model
2. Concept of positive feedback its characteristics
3. Tuned circuits its working principle used in tuned amplifiers

22. Discussion topics if any

23. References, Journals, Websites and E-Links

Reference book names :
1. Electronic devices and circuit theory Robert L.boylestad, Louis Nashelsky,2008 PE
2. Introductory Electronic devices and circuits RobertT.paynter, 7 ed.,2009,PEL
3. Electronic circuit analysis-K.Lalkishore,2004,BSP
4. Electronic devices and circuits,DavidA.Bell -5 ed.,Oxford UniversityPress
5. Microelectronic circuits-Sedra and smith-5 ed.,2009, Oxford UniversityPress
6 .Integrated Electronics Jacob Milliman and Christos C Halkias,1991 edu,2008.TMH

WEBSITES

1. en.wikipedia.org/wiki/Digital_electronics
2. www.modernelectronics.org
3. www.electronicsforyou.com
4. www.npteliitm.ac.in
Ebooks:
http://books.google.co.in/books?id=sxswmJgMbEsC&pg=PA118&lpg=PR16&ots=DXZAEipuZ
B&focus=viewport&dq=Pulse,+Digital+and+Switching+Waveforms++J.+Millman+and+H.+Taub#v=onepage&q=Pulse%2C%20Digital%20and%20Switching%
20Waveforms%20-%20J.%20Millman%20and%20H.%20Taub&f=false
http://www.youtube.com/watch?v=aO6tA1z933k

24.Quality Control Sheets. a) Course end survey

b) Teaching Evaluation
Hard copy will attach at the end of the course of course end survey and Teaching
Evalution

25. STUDENT LIST:

S.No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Roll Number
14R11A0401
14R11A0402
14R11A0403
14R11A0404
14R11A0405
14R11A0406
14R11A0407
14R11A0408
14R11A0409
14R11A0410
14R11A0411
14R11A0412
14R11A0413
14R11A0414
14R11A0415
14R11A0416
14R11A0417

ECE 2-1A
Name of the Candidate
ADITYA B
ADULLA JANARDHAN REDDY
ANDE HEMANTH REDDY
ANKATI NAVYA
ASHFAQ AZIZ AHMED
BANDI SANDHYA
BASWARAJ SHASHANK YADAV
BITLA SRIKANTH REDDY
BUDDANA DHARANI KUMAR
CHEBARTHI RAMYA GAYATHRI
CHETLAPALLI NAGA SAI SUSHMITHA
DASARI DHAMODHAR REDDY
G AYESHA SULTANA
G MADHURI
G RISHI RAJ
G VAMSHI KRISHNA
G VENKATESH YADAV

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

14R11A0418
14R11A0419
14R11A0420
14R11A0421
14R11A0422
14R11A0423
14R11A0424
14R11A0425
14R11A0426
14R11A0427
14R11A0428
14R11A0429
14R11A0430
14R11A0431
14R11A0432
14R11A0433
14R11A0434
14R11A0435
14R11A0436
14R11A0437
14R11A0438
14R11A0439
14R11A0440
14R11A0441
14R11A0442
14R11A0443
14R11A0444
14R11A0445
14R11A0446
14R11A0447
14R11A0448
14R11A0449
14R11A0450
14R11A0451
14R11A0452
14R11A0453
14R11A0454
14R11A0455
14R11A0456
14R11A0457
14R11A0458

GONDA RISHIKA
GUDE GOPI
JAGGANNAGARI MANOJKUMAR REDDY
JAGGARI SRINIJA REDDY
JALAGAM NANDITHA
JAMMIKUNTLA SHIVA CHARAN
JATAPROLU LAKSHMI SOWMIKA
JEKSANI SHREYA
K VIJAY KUMAR
KAALISETTY KRISHNA CHAITANYA
KAKARLA MOUNICA
KARRE PRIYANKA
KL N SATYANARAYANA MURTHY
KONDA KRITISH KUMAR
KOPPULA RAHUL
KURUGANTI RUNI TANISHKA SHARMA
L THRILOK
MANDULA SANTOSHINI
MATLA PRINCE TITUS
NARSETTI SAIPRAVALIKA
NIKITHA RAGI
P VIJAYA ADITYA VARMA
PASHAM VIKRAM REDDY
PELLURI KARAN KUMAR
PERURI CHANDANA
PODUGU SRUJANA DEVI
RAJNISH KUMAR
RAJU PAVANA KUMARI
RAMIDI NITHYA
RAMOJI RAJESH
S ALEKHYA
SARANGA SAI KIRAN
SHAIK SAMEER ALI
SOUMYA MISHRA
SRIRAMOJU MANASA
T ARUN KUMAR
T S SANTHOSH KUMAR
V BAL RAJ
V POOJA
V SRIVATS VISHWAMBER
VEMI REDDY VISHNU VARDHAN REDDY

59 14R11A0459
60 14R11A0460
S.No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

Roll Number
14R11A0461
14R11A0462
14R11A0463
14R11A0464
14R11A0465
14R11A0466
14R11A0467
14R11A0468
14R11A0469
14R11A0470
14R11A0471
14R11A0472
14R11A0473
14R11A0474
14R11A0475
14R11A0476
14R11A0477
14R11A0478
14R11A0479
14R11A0480
14R11A0481
14R11A0482
14R11A0483
14R11A0484
14R11A0485
14R11A0486
14R11A0487
14R11A0488
14R11A0489
14R11A0490
14R11A0491
14R11A0492
14R11A0493
14R11A0494
14R11A0495
14R11A0496
14R11A0497
14R11A0498

VENNAMANENI VAMSI KRISHNA

YERASI TEJASRI
ECE -2-1B
Name of the Candidate
ADDAKULA SURESH
AGARTI MADHU VIVEKA
AKULA SAI KIRAN
ANUMULA SNIGDHA
B DIVYA
B MANOHAR
BANDARI MAMATHA
BINGI DIVYA SUDHA RANI
BIRE BHAVYA
CH SAI BHARGAVI
CHAVALI SUMA SIREESHA
CHELLABOINA SHIVA KUMAR
CHETTY AKHIL CHAND
CHINTAPALLI MADHAV REDDY
CHIVUKULA VENKATA SUBRAMANYA PRASANTH
D NAGA SUMANVITHA
D VAMSI
DHARMENDER KEERTHI
EADARA NAGA SIRISHA
ERANKI SAI UDAYASRI ALAKANANDA
GANGA STEPHEN RAVI KUMAR
GUNDAM SHRUTHI
GUNDREVULA SAMEERA
K NAGA REKHA
KANDADI VARSHA
KURELLI SAI VINEETH KUMAR GOUD
MADDIKUNTA SOMA SHEKAR REDDY
MAMILLA SAI NISHMA
MARELLA NAGA LASYA PRIYA
MARKU VENKATESH
MOHAMED KHALEEL
MOHAMMED WASEEM AKRAM
MOTURI DIVYA
MUDIUM KOUSHIKA
MYLAPALLI RAMBABU
NAGU MOUNIKA
NEELAM SNEHANJALI
NIDAMANURI VENKATA VAMSI KRISHNA

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

14R11A0499
14R11A04A0
14R11A04A1
14R11A04A2
14R11A04A3
14R11A04A4
14R11A04A5
14R11A04A6
14R11A04A7
14R11A04A8
14R11A04A9
14R11A04B0
14R11A04B1
14R11A04B2
14R11A04B3
14R11A04B4
14R11A04B5
14R11A04B6
14R11A04B7
14R11A04B8

S.No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Roll Number
14R11A04B9
14R11A04C0
14R11A04C1
14R11A04C2
14R11A04C3
14R11A04C4
14R11A04C5
14R11A04C6
14R11A04C7
14R11A04C8
14R11A04C9
14R11A04D0
14R11A04D1
14R11A04D2
14R11A04D3
14R11A04D4
14R11A04D5
14R11A04D6
14R11A04D7

NIKHIL KUMAR N
ORUGANTI HARSHINI
PARAMKUSAM NIHARIKA
PASAM ABHIGNA
PATI VANDANA
PODISHETTY MANOGNA
PONAKA SREEVARDHAN REDDY
R NAVSHETHA
R PRANAY KUMAR
RAMIDI ROJA
RUDRA VAMSHI
S SHARAD KUMAR
SAGGU SOWMYA
TADELA SARWANI
THOTA SAI BHUVAN
VALLAPU HARIKRISHNA
VECHA PAVAN KUMAR
Y SAI VISHWANATH
ADHINARAYANAN SARITHA
PASUPULETI AVINASH
ECE 2-1C
Name of the Candidate
ANAMALI REETHIKA
ARUMILLI LEKYA
ARUMUGAM ASHWINI
BASAVARAJU MEGHANA
BEERAM TEJASRI REDDY
BHARAT SAKETH
BOMMANA HARIKADEVI
BYRAGONI ROJA
CANDHI SHASHI REKHA
CH RENUKA
CHAGANTI MOUNICA
CHITTARLA LOKESH GOUD
D LAVANYA
D MANIKANTA
DASARI VENKATA NAGA SAISH
DODDA MANOJ
E RAHUL CHOWDHARY
GOWRISHETTY VINEETHA
GUNTUPALLI RAVI TEJA

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

14R11A04D8
14R11A04D9
14R11A04E0
14R11A04E1
14R11A04E2
14R11A04E3
14R11A04E4
14R11A04E5
14R11A04E6
14R11A04E7
14R11A04E8
14R11A04E9
14R11A04F0
14R11A04F1
14R11A04F2
14R11A04F3
14R11A04F4
14R11A04F5
14R11A04F6
14R11A04F7
14R11A04F8
14R11A04F9
14R11A04G0
14R11A04G1
14R11A04G2
14R11A04G3
14R11A04G4
14R11A04G5
14R11A04G6
14R11A04G7
14R11A04G8
14R11A04G9
14R11A04H0
14R11A04H1
14R11A04H2
14R11A04H3
14R11A04H4
14R11A04H5
14R11A04H6
14R11A04H7
14R11A04H8

K L ANUSHA
K SASIDHAR
KANAKA RAMYA PRATHIMA
KASTURI SHIVA SHANKER REDDY
KODHIRIPAKA DHENUSRI
KOLA AISHWARYA
KONDOJU AKSHITHA
KOUDAGANI ALEKHYA REDDY
KUMMARIKUNTA PRASHANTH
KURVA SAI KUMAR
M AJAY KRISHNA
M MRIDULA GAYATRI
MANGALAPALLI SRAVANTHI
MERUGU PALLAVI
MITHIN VARGHESE
MOHD EESA SOHAIL
MUCHUMARI HARSHA VARDHAN REDDY
MUNUGANTI PRADHYUMNA
N DURGA RAJU
N SAKETH
N SANDHYA
NALLAGONI SRAVANTHI
P MANMOHAN SHASHANK VARMA
PRABHALA SRUTHI
PRAYAGA VENKATA SATHYA KAMESWARA PAV
R SAILESH
SAMBANGI POOJA
SAMEENA
SANGOJI SAI CHANDU
SURANENI NAMRATHA
TADAKAPALLY VIVEK REDDY
THUMUKUMTA VAMSHI TEJA
TIRUNAGARI SRAVAN KUMAR
TRIPURARI SOWGANDHIKA
TUNIKI MADHULIKA REDDY
U SAI MANASWINI
VAIDYA KEERTHI MALINI
VANGETI PRAVALLIKA
VASIREDDY VENKATA SAI
VELDURTHY SAI KEERTHI
WILSON DAVIES

S.No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

Roll Number
14R11A04H9
14R11A04J0
14R11A04J1
14R11A04J2
14R11A04J3
14R11A04J4
14R11A04J5
14R11A04J6
14R11A04J7
14R11A04J8
14R11A04J9
14R11A04K0
14R11A04K1
14R11A04K2
14R11A04K3
14R11A04K4
14R11A04K5
14R11A04K6
14R11A04K7
14R11A04K8
14R11A04K9
14R11A04L0
14R11A04L1
14R11A04L2
14R11A04L3
14R11A04L4
14R11A04L5
14R11A04L6
14R11A04L7
14R11A04L8
14R11A04L9
14R11A04M0
14R11A04M1
14R11A04M2
14R11A04M3
14R11A04M4
14R11A04M5
14R11A04M6
14R11A04M7

ECE 2-1D
Name of the Candidate
A SHIRISHA
ABHIJEET KUMAR
ADULLA PRANAV REDDY
AINAPARTHI SAIVIJAYALAKSHMI SANDHYA
AMBATI SHIVA SAI
ANU PRASAD
B SAI APOORVA
B SRI KRISHNA SAI KIREETI
CHITTOJU LAKSHMI NARAYANAMMA
CHOWDARAPALLY SANTOSH KUMAR
D SAHITHI
DEVULAPALLI SAI CHAITANYA SANDEEP
DUSARI ANUSHA
GOLLAPUDI SRIKETH
GOLLIPALLY TEJASREE
GOUTE SHRAVAN KUMAR
GUDA PRATHYUSHA REDDY
JUNNU RAVALI
K DEVI PRIYANKA
KANDULA MANI
KARRA AVINASH
KASULA PRADEEP GOUD
KOMARAKUNTA SHASHANK
KOTHAKOTA PHANI RISHITHA
MADHADI NIKHIL KUMAR REDDY
MANDUMULA RAGHAVENDRA
MOHD HAMEED
MOHD SHAMS TABREZ
MORSU GANESH REDDY
MUKKERA VARUN
NAGULAPALLY MANOHAR REDDY
NAMBURI LAKSHMI MANJUSHA
NIROGI SURYA PRIYANKA
NUNE SAI CHAND
PALLETI SUSHMITHA
PANCHAYAT SHAMILI
POOSA JAI SAI NISHANTH
PRANAV RAJU A
RAYCHETTI CHANDRASENA

40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

14R11A04M8
14R11A04M9
14R11A04N0
14R11A04N1
14R11A04N2
14R11A04N3
14R11A04N4
14R11A04N5
14R11A04N6
14R11A04N7
14R11A04N8
14R11A04N9
14R11A04P0
14R11A04P1
14R11A04P2
14R11A04P3
14R11A04P4
14R11A04P5
14R11A04P6
14R11A04P7

REBBA BHAVANI
S BHARATH SAGAR
S V M SURYA TEJASWINI
SAMA MANVITHA REDDY
SHAMALA MEGHANA
SMITHA KUMARI PATRO
T L SARADA RAMYA KAPARDHINI
T VINAY KUMAR
TABELA OMKAR
TADACHINA SAINATH REDDY
VANGA MOUNIKA
VARRI PRASHANTHI
VASARLA SAI TEJA
VISHWANATHAM ANUSHA
Y SRI SAI ADITYA
YAKKALA ASHIKA
YALAVARTHY MAHIMA
YALLAPRAGADA SAI TEJASRI
YARASI SAI RAMYA REDDY
S TARUN

DISCUSSION GROUPS:

S.No
1
2
3
4
5
6

Roll Number
14R11A0401
14R11A0402
14R11A0403
14R11A0404
14R11A0405
14R11A0406

ECE - A
( Group 1 )
Name of the Candidate
ADITYA B
ADULLA JANARDHAN REDDY
ANDE HEMANTH REDDY
ANKATI NAVYA
ASHFAQ AZIZ AHMED
BANDI SANDHYA

7
8
9
10

14R11A0407
14R11A0408
14R11A0409
14R11A0410

11
12
13
14
15
16
17
18

14R11A0411
14R11A0412
14R11A0413
14R11A0414
14R11A0415
14R11A0416
14R11A0417
14R11A0418

19
20
21
22
23
24
25
26
27

14R11A0419
14R11A0420
14R11A0421
14R11A0422
14R11A0423
14R11A0424
14R11A0425
14R11A0426
14R11A0427

28
29
30
31
32
33
34
35
36
37
38

14R11A0428
14R11A0429
14R11A0430
14R11A0431
14R11A0432
14R11A0433
14R11A0434
14R11A0435
14R11A0436
14R11A0437
14R11A0438

39
40
41
42
43

14R11A0439
14R11A0440
14R11A0441
14R11A0442
14R11A0443

BASWARAJ SHASHANK YADAV

BITLA SRIKANTH REDDY
BUDDANA DHARANI KUMAR
CHEBARTHI RAMYA GAYATHRI
( Group 2 )
CHETLAPALLI NAGA SAI SUSHMITHA
DASARI DHAMODHAR REDDY
G AYESHA SULTANA
G MADHURI
G RISHI RAJ
G VAMSHI KRISHNA
G VENKATESH YADAV
GONDA RISHIKA
( Group 3 )
GUDE GOPI
JAGGANNAGARI MANOJKUMAR REDDY
JAGGARI SRINIJA REDDY
JALAGAM NANDITHA
JAMMIKUNTLA SHIVA CHARAN
JATAPROLU LAKSHMI SOWMIKA
JEKSANI SHREYA
K VIJAY KUMAR
KAALISETTY KRISHNA CHAITANYA
( Group 4 )
KAKARLA MOUNICA
KARRE PRIYANKA
KL N SATYANARAYANA MURTHY
KONDA KRITISH KUMAR
KOPPULA RAHUL
KURUGANTI RUNI TANISHKA SHARMA
L THRILOK
MANDULA SANTOSHINI
MATLA PRINCE TITUS
NARSETTI SAIPRAVALIKA
NIKITHA RAGI
( Group 5 )
P VIJAYA ADITYA VARMA
PASHAM VIKRAM REDDY
PELLURI KARAN KUMAR
PERURI CHANDANA
PODUGU SRUJANA DEVI

44
45
46
47
48
49

14R11A0444
14R11A0445
14R11A0446
14R11A0447
14R11A0448
14R11A0449

50
51
52
53
54
55
56
57
58
59
60

14R11A0450
14R11A0451
14R11A0452
14R11A0453
14R11A0454
14R11A0455
14R11A0456
14R11A0457
14R11A0458
14R11A0459
14R11A0460

S.No
1
2
3
4
5
6
7
8
9

Roll Number
14R11A0461
14R11A0462
14R11A0463
14R11A0464
14R11A0465
14R11A0466
14R11A0467
14R11A0468
14R11A0469

10
11
12
13
14

14R11A0470
14R11A0471
14R11A0472
14R11A0473
14R11A0474

RAJNISH KUMAR
RAJU PAVANA KUMARI
RAMIDI NITHYA
RAMOJI RAJESH
S ALEKHYA
SARANGA SAI KIRAN
( Group 6 )
SHAIK SAMEER ALI
SOUMYA MISHRA
SRIRAMOJU MANASA
T ARUN KUMAR
T S SANTHOSH KUMAR
V BAL RAJ
V POOJA
V SRIVATS VISHWAMBER
VEMI REDDY VISHNU VARDHAN REDDY
VENNAMANENI VAMSI KRISHNA
YERASI TEJASRI

ECE - B
( Group 1 )
Name of the Candidate
ADDAKULA SURESH
AGARTI MADHU VIVEKA
AKULA SAI KIRAN
ANUMULA SNIGDHA
B DIVYA
B MANOHAR
BANDARI MAMATHA
BINGI DIVYA SUDHA RANI
BIRE BHAVYA
( Group 2 )
CH SAI BHARGAVI
CHAVALI SUMA SIREESHA
CHELLABOINA SHIVA KUMAR
CHETTY AKHIL CHAND
CHINTAPALLI MADHAV REDDY

15
16
17
18
19

14R11A0475
14R11A0476
14R11A0477
14R11A0478
14R11A0479

20
21
22
23
24
25
26
27
28
29

14R11A0480
14R11A0481
14R11A0482
14R11A0483
14R11A0484
14R11A0485
14R11A0486
14R11A0487
14R11A0488
14R11A0489

30
31
32
33
34
35
36
37
38
39
40

14R11A0490
14R11A0491
14R11A0492
14R11A0493
14R11A0494
14R11A0495
14R11A0496
14R11A0497
14R11A0498
14R11A0499
14R11A04A0

41
42
43
44
45
46
47
48

14R11A04A1
14R11A04A2
14R11A04A3
14R11A04A4
14R11A04A5
14R11A04A6
14R11A04A7
14R11A04A8

49
50
51
52

14R11A04A9
14R11A04B0
14R11A04B1
14R11A04B2

CHIVUKULA VENKATA SUBRAMANYA PRASANTH

D NAGA SUMANVITHA
D VAMSI
DHARMENDER KEERTHI
EADARA NAGA SIRISHA
( Group 3 )
ERANKI SAI UDAYASRI ALAKANANDA
GANGA STEPHEN RAVI KUMAR
GUNDAM SHRUTHI
GUNDREVULA SAMEERA
K NAGA REKHA
KANDADI VARSHA
KURELLI SAI VINEETH KUMAR GOUD
MADDIKUNTA SOMA SHEKAR REDDY
MAMILLA SAI NISHMA
MARELLA NAGA LASYA PRIYA
( Group 4 )
MARKU VENKATESH
MOHAMED KHALEEL
MOHAMMED WASEEM AKRAM
MOTURI DIVYA
MUDIUM KOUSHIKA
MYLAPALLI RAMBABU
NAGU MOUNIKA
NEELAM SNEHANJALI
NIDAMANURI VENKATA VAMSI KRISHNA
NIKHIL KUMAR N
ORUGANTI HARSHINI
( Group 5 )
PARAMKUSAM NIHARIKA
PASAM ABHIGNA
PATI VANDANA
PODISHETTY MANOGNA
PONAKA SREEVARDHAN REDDY
R NAVSHETHA
R PRANAY KUMAR
RAMIDI ROJA
( Group 6 )
RUDRA VAMSHI
S SHARAD KUMAR
SAGGU SOWMYA
TADELA SARWANI

53
54
55
56
57
58

14R11A04B3
14R11A04B4
14R11A04B5
14R11A04B6
14R11A04B7
14R11A04B8

S.No
1
2
3
4
5
6
7
8
9

Roll Number
14R11A04B9
14R11A04C0
14R11A04C1
14R11A04C2
14R11A04C3
14R11A04C4
14R11A04C5
14R11A04C6
14R11A04C7

10
11
12
13
14
15
16
17
18
19
20

14R11A04C8
14R11A04C9
14R11A04D0
14R11A04D1
14R11A04D2
14R11A04D3
14R11A04D4
14R11A04D5
14R11A04D6
14R11A04D7
14R11A04D8

21
22
23
24
25
26
27
28
29
30

14R11A04D9
14R11A04E0
14R11A04E1
14R11A04E2
14R11A04E3
14R11A04E4
14R11A04E5
14R11A04E6
14R11A04E7
14R11A04E8

THOTA SAI BHUVAN

VALLAPU HARIKRISHNA
VECHA PAVAN KUMAR
Y SAI VISHWANATH
ADHINARAYANAN SARITHA
PASUPULETI AVINASH
ECE 2-1C
( Group 1 )
Name of the Candidate
ANAMALI REETHIKA
ARUMILLI LEKYA
ARUMUGAM ASHWINI
BASAVARAJU MEGHANA
BEERAM TEJASRI REDDY
BHARAT SAKETH
BOMMANA HARIKADEVI
BYRAGONI ROJA
CANDHI SHASHI REKHA
( Group 2 )
CH RENUKA
CHAGANTI MOUNICA
CHITTARLA LOKESH GOUD
D LAVANYA
D MANIKANTA
DASARI VENKATA NAGA SAISH
DODDA MANOJ
E RAHUL CHOWDHARY
GOWRISHETTY VINEETHA
GUNTUPALLI RAVI TEJA
K L ANUSHA
( Group 3 )
K SASIDHAR
KANAKA RAMYA PRATHIMA
KASTURI SHIVA SHANKER REDDY
KODHIRIPAKA DHENUSRI
KOLA AISHWARYA
KONDOJU AKSHITHA
KOUDAGANI ALEKHYA REDDY
KUMMARIKUNTA PRASHANTH
KURVA SAI KUMAR
M AJAY KRISHNA

31
32
33
34
35
36
37
38
39
40

14R11A04E9
14R11A04F0
14R11A04F1
14R11A04F2
14R11A04F3
14R11A04F4
14R11A04F5
14R11A04F6
14R11A04F7
14R11A04F8

41
42
43
44
45
46
47
48
49
50

14R11A04F9
14R11A04G0
14R11A04G1
14R11A04G2
14R11A04G3
14R11A04G4
14R11A04G5
14R11A04G6
14R11A04G7
14R11A04G8

51
52
53
54
55
56
57
58
59
60

14R11A04G9
14R11A04H0
14R11A04H1
14R11A04H2
14R11A04H3
14R11A04H4
14R11A04H5
14R11A04H6
14R11A04H7
14R11A04H8

( Group 4 )
M MRIDULA GAYATRI
MANGALAPALLI SRAVANTHI
MERUGU PALLAVI
MITHIN VARGHESE
MOHD EESA SOHAIL
MUCHUMARI HARSHA VARDHAN REDDY
MUNUGANTI PRADHYUMNA
N DURGA RAJU
N SAKETH
N SANDHYA
( Group 5 )
NALLAGONI SRAVANTHI
P MANMOHAN SHASHANK VARMA
PRABHALA SRUTHI
PRAYAGA VENKATA SATHYA KAMESWARA PAV
R SAILESH
SAMBANGI POOJA
SAMEENA
SANGOJI SAI CHANDU
SURANENI NAMRATHA
TADAKAPALLY VIVEK REDDY
( Group 6 )
THUMUKUMTA VAMSHI TEJA
TIRUNAGARI SRAVAN KUMAR
TRIPURARI SOWGANDHIKA
TUNIKI MADHULIKA REDDY
U SAI MANASWINI
VAIDYA KEERTHI MALINI
VANGETI PRAVALLIKA
VASIREDDY VENKATA SAI
VELDURTHY SAI KEERTHI
WILSON DAVIES

Roll Number
14R11A04H9
14R11A04J0
14R11A04J1
14R11A04J2
14R11A04J3

ECE 2-1D
( Group 1 )
Name of the Candidate
A SHIRISHA
ABHIJEET KUMAR
ADULLA PRANAV REDDY
AINAPARTHI SAIVIJAYALAKSHMI SANDHYA
AMBATI SHIVA SAI

S.No
1
2
3
4
5

6
7
8
9

14R11A04J4
14R11A04J5
14R11A04J6
14R11A04J7

10
11
12
13
14
15
16
17
18
19

14R11A04J8
14R11A04J9
14R11A04K0
14R11A04K1
14R11A04K2
14R11A04K3
14R11A04K4
14R11A04K5
14R11A04K6
14R11A04K7

20
21
22
23
24
25
26
27
28
29

14R11A04K8
14R11A04K9
14R11A04L0
14R11A04L1
14R11A04L2
14R11A04L3
14R11A04L4
14R11A04L5
14R11A04L6
14R11A04L7

30
31
32
33
34
35
36
37
38
39

14R11A04L8
14R11A04L9
14R11A04M0
14R11A04M1
14R11A04M2
14R11A04M3
14R11A04M4
14R11A04M5
14R11A04M6
14R11A04M7

40 14R11A04M8
41 14R11A04M9
42 14R11A04N0

ANU PRASAD
B SAI APOORVA
B SRI KRISHNA SAI KIREETI
CHITTOJU LAKSHMI NARAYANAMMA
( Group 2 )
CHOWDARAPALLY SANTOSH KUMAR
D SAHITHI
DEVULAPALLI SAI CHAITANYA SANDEEP
DUSARI ANUSHA
GOLLAPUDI SRIKETH
GOLLIPALLY TEJASREE
GOUTE SHRAVAN KUMAR
GUDA PRATHYUSHA REDDY
JUNNU RAVALI
K DEVI PRIYANKA
( Group 3 )
KANDULA MANI
KARRA AVINASH
KASULA PRADEEP GOUD
KOMARAKUNTA SHASHANK
KOTHAKOTA PHANI RISHITHA
MADHADI NIKHIL KUMAR REDDY
MANDUMULA RAGHAVENDRA
MOHD HAMEED
MOHD SHAMS TABREZ
MORSU GANESH REDDY
( Group 4 )
MUKKERA VARUN
NAGULAPALLY MANOHAR REDDY
NAMBURI LAKSHMI MANJUSHA
NIROGI SURYA PRIYANKA
NUNE SAI CHAND
PALLETI SUSHMITHA
PANCHAYAT SHAMILI
POOSA JAI SAI NISHANTH
PRANAV RAJU A
RAYCHETTI CHANDRASENA
( Group 5 )
REBBA BHAVANI
S BHARATH SAGAR
S V M SURYA TEJASWINI

43
44
45
46
47
48
49

14R11A04N1
14R11A04N2
14R11A04N3
14R11A04N4
14R11A04N5
14R11A04N6
14R11A04N7

50
51
52
53
54
55
56
57
58
59

14R11A04N8
14R11A04N9
14R11A04P0
14R11A04P1
14R11A04P2
14R11A04P3
14R11A04P4
14R11A04P5
14R11A04P6
14R11A04P7

SAMA MANVITHA REDDY

SHAMALA MEGHANA
SMITHA KUMARI PATRO
T L SARADA RAMYA KAPARDHINI
T VINAY KUMAR
TABELA OMKAR
TADACHINA SAINATH REDDY
( Group 6 )
VANGA MOUNIKA
VARRI PRASHANTHI
VASARLA SAI TEJA
VISHWANATHAM ANUSHA
Y SRI SAI ADITYA
YAKKALA ASHIKA
YALAVARTHY MAHIMA
YALLAPRAGADA SAI TEJASRI
YARASI SAI RAMYA REDDY
S TARUN