Explain why & how a MOSFET works

2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with
increasing Vgs (b) with increasing transistor width (c) considering Channel Length
Modulation

3) Explain the various MOSFET Capacitances & their significance

4) Draw a CMOS Inverter. Explain its transfer characteristics

5) Explain sizing of the inverter

6)How do you size NMOS and PMOS transistors to increase the threshold voltage?

7) What is Noise Margin? Explain the procedure to determine Noise Margin

8) Give the expression for CMOS switching power dissipation

9) What is Body Effect?

10) Describe the various effects of scaling

11) Give the expression for calculating Delay in CMOS circuit

12) What happens to delay if you increase load capacitance?

13) What happens to delay if we include a resistance at the output of a CMOS circuit?

14) What are the limitations in increasing the power supply to reduce delay?

15) How does Resistance of the metal lines vary with increasing thickness and increasing
length?

16) You have three adjacent parallel metal lines. Two out of phase signals pass through
the outer two metal lines. Draw the waveforms in the center metal line due to
interference. Now, draw the signals if the signals in outer metal lines are in phase with
each other

17) What happens if we increase the number of contacts or via from one metal layer to
the next?

18) Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth
(b) for equal rise and fall times
19) Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate
later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one
would you place near the output?

20) Draw the stick diagram of a NOR gate. Optimize it

21) For CMOS logic, give the various techniques you know to minimize power
consumption

22) What is Charge Sharing? Explain the Charge Sharing problem while sampling data
from a Bus

23) Why do we gradually increase the size of inverters in buffer design? Why not give
the output of a circuit to one large inverter?

24) In the design of a large inverter, why do we prefer to connect small transistors in
parallel (thus increasing effective width) rather than lay out one transistor with large
width?

25) Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and
a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

26) Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw
its stick diagram

27) Why don't we use just one NMOS or PMOS transistor as a transmission gate?

28) For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD,
give the output for a square pulse input going from 0 to VDD

29) Draw a 6-T SRAM Cell and explain the Read and Write operations

30) Draw the Differential Sense Amplifier and explain its working. Any idea how to size
this circuit? (Consider Channel Length Modulation)

31) What happens if we use an Inverter instead of the Differential Sense Amplifier?

32) Draw the SRAM Write Circuitry

33) Approximately, what were the sizes of your transistors in the SRAM cell? How did
you arrive at those sizes?

34) How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's
performance?

35) What's the critical path in a SRAM?

36) Draw the timing diagram for a SRAM Read. What happens if we delay the enabling
of Clock signal?

37) Give a big picture of the entire SRAM Layout showing your placements of SRAM
Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

38) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit
Lines? Why?

39) How can you model a SRAM at RTL Level?

40) What�s the difference between Testing & Verification?

41) For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0
and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some
redundant logic)

42) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do
you avoid Latch Up?

Digital Design:

1) Give two ways of converting a two input NAND gate to an inverter

2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal
Generator; you can expect any sequential ckt)

3) What are set up time & hold time constraints? What do they signify? Which one is
critical for estimating maximum clock frequency of a circuit?

4) Give a circuit to divide frequency of clock cycle by two

5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)

6) Suppose you have a combinational circuit between two registers driven by a clock.
What will you do if the delay of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit transistors)

7) The answer to the above question is breaking the combinational circuit and pipelining
it. What will be affected if you do this?

8) What are the different Adder circuits you studied?

9) Give the truth table for a Half Adder. Give a gate level implementation of the same.

10) Draw a Transmission Gate-based D-Latch.

11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR?
(Without inverting the output)

12) How do you detect if two 8-bit signals are same?

13) How do you detect a sequence of "1101" arriving serially from a signal line?

14) Design any FSM in VHDL or Verilog.

Computer Architecture:

1) What is pipelining?

2) What are the five stages in a DLX pipeline?

3) For a pipeline with 'n' stages, what�s the ideal throughput? What prevents us from
achieving this ideal throughput?

4) What are the different hazards? How do you avoid them?

5) Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages?

6) What are Branch Prediction and Branch Target Buffers?

7) How do you handle precise exceptions or interrupts?

8) What is a cache?

9) What's the difference between Write-Through and Write-Back Caches? Explain

advantages and disadvantages of each.

10) Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative.
For a 32-bit physical address, give the division between Block Offset, Index and Tag.

11) What is Virtual Memory?

12) What is Cache Coherency?

13) What is MESI?

14) What is a Snooping cache?

15) What are the components in a Microprocessor?

16) What is ACBF(Hex) divided by 16?

17) Convert 65(Hex) to Binary

18) Convert a number to its two's compliment and back

19) The CPU is busy but you want to stop and do some other task. How do you do it?

C/C++, Perl & Unix:

1) How would you decide weather to use C, C++ or Perl for a particular project?

2) What are pointers? Why do we use them?

3) What are the benefits of having Global & Local Variables?

4) What is 'malloc'? Why do we need to use it?

5) Write a C program to compare two arrays and write the common elements in another
array

6) Write a function in C to accept two integers and return the bigger integer

7) What are the advantages of C over Perl and vice versa?

8) What does '@' and '&' mean in Perl?

9) What is a 'Package' in Perl?

10) What are Perl Regular Expressions?

11) Perl Regular Expressions are greedy. What does that mean?

12) What are Associative arrays in Perl?

13) Suppose a Perl variable has your name stored in it. Now, how can you define an array
by the name? (i.e., you have $a="Adarsh"; now you want @Adarsh=[.....])

14) Write a Perl script to parse a particular txt file and output to another file in a desired
format. (You can expect the file to have some data arranged rows & columns)

15) Suppose you have the outputs of a test program in some big test file. In Perl, how can
you test if all the outputs match a particular string?

16) What are Data Abstraction and Data Encapsulation?

17) Explain Friend Functions and Polymorphism with examples

18) Commands for changing directory, making directory, going up one directory,
knowing the file permissions and changing file permissions.

19) How do you search for a particular string in all the text files in current directory from
command line?

20) How do you sort a file alphabetically from command line?

Other Simple Questions:

1) What is j to the power j?

2) What is Normal Distribution? Where is the Mean and Median on the graph for Normal
Distribution?

3) Draw a simple RC-Low pass circuit.

Some General Questions:

1) Tell me something about yourself and your interests

2) Tell me something about some problems you faced in a project and how did you
handle it?

3) Give one instance where you were criticised by your Professor

4) Where do you see yourself five years from now?

5) What salary are you expecting?

6) Any Questions for me regarding the position or the company?

7) Finally, does this position sound interesting? :-)

1. Explain why & how a MOSFET works

2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with
increasing Vgs (b) with increasing transistor width (c) considering Channel
Length Modulation
3. Explain the various MOSFET Capacitances & their significance
4. Draw a CMOS Inverter. Explain its transfer characteristics
5. Explain sizing of the inverter
6. How do you size NMOS and PMOS transistors to increase the threshold voltage?
7. What is Noise Margin? Explain the procedure to determine Noise Margin
8. Give the expression for CMOS switching power dissipation
9. What is Body Effect?
10. Describe the various effects of scaling
11. Give the expression for calculating Delay in CMOS circuit
12. What happens to delay if you increase load capacitance?
13. What happens to delay if we include a resistance at the output of a CMOS circuit?
14. What are the limitations in increasing the power supply to reduce delay?
15. How does Resistance of the metal lines vary with increasing thickness and
increasing length?
16. You have three adjacent parallel metal lines. Two out of phase signals pass
through the outer two metal lines. Draw the waveforms in the center metal line
due to interference. Now, draw the signals if the signals in outer metal lines are in
phase with each other
17. What happens if we increase the number of contacts or via from one metal layer
to the next?
18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering
Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND
gate later than signal B. To optimize delay, of the two series NMOS inputs A &
B, which one would you place near the output?
20. Draw the stick diagram of a NOR gate. Optimize it
21. For CMOS logic, give the various techniques you know to minimize power
consumption
22. What is Charge Sharing? Explain the Charge Sharing problem while sampling
data from a Bus
23. Why do we gradually increase the size of inverters in buffer design? Why not give
the output of a circuit to one large inverter?
24. In the design of a large inverter, why do we prefer to connect small transistors in
parallel (thus increasing effective width) rather than lay out one transistor with
large width?
25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate
and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor level equivalent.
Draw its stick diagram
27. Why don't we use just one NMOS or PMOS transistor as a transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate is connected to
VDD, give the output for a square pulse input going from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write operations
30. Draw the Differential Sense Amplifier and explain its working. Any idea how to
size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential Sense Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the SRAM cell? How
did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect
SRAM's performance?
35. What's the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we delay the
enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your placements of
SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and
Buffers
38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit
Lines? Why?
39. How can you model a SRAM at RTL Level?
40. What�s the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-
At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with
some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter.
How do you avoid Latch Up?

1. nsights of an inverter. Explain the working?

2. Insights of a 2 input NOR gate. Explain the working?
3. Insights of a 2 input NAND gate. Explain the working?
4. Implement F= not (AB+CD) using CMOS gates?
5. Insights of a pass gate. Explain the working?
6. Why do we need both PMOS and NMOS transistors to implement a pass gate?
7. What does the above code synthesize to?
8. Cross section of a PMOS transistor?
9. Cross section of an NMOS transistor?
10. What is a D-latch? Write the VHDL Code for it?
11. Differences between D-Latch and D flip-flop?
12. Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-
flop?
13. What is latchup? Explain the methods used to prevent it?
14. What is charge sharing?
15. While using logic design, explain the various steps that r followed to obtain the
desirable design in a well defined manner?
16. Why is OOPS called OOPS? (C++)
17. What is a linked list? Explain the 2 fields in a linked list?
18. Implement a 2 I/P and gate using Tran gates?
19. Insights of a 4bit adder/Sub Circuit?
20. For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?
21. Explain various adders and diff between them?
22. Explain the working of 4-bit Up/down Counter?
23. A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A =
1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
24. Advantages and disadvantages of Mealy and Moore?
25. Id vs. Vds Characteristics of NMOS and PMOS transistors?
26. Explain the operation of a 6T-SRAM cell?
27. Differences between DRAM and SRAM?
28. Implement a function with both ratioed and domino logic and merits and demerits
of each logic?
29. Given a circuit and asked to tell the output voltages of that circuit?
30. How can you construct both PMOS and NMOS on a single substrate?
31. What happens when the gate oxide is very thin?
32. What is setup time and hold time?
33. Write a pseudo code for sorting the numbers in an array?
34. What is pipelining and how can we increase throughput using pipelining?
35. Explain about stuck at fault models, scan design, BIST and IDDQ testing?
36. What is SPICE?
37. Differences between IRSIM and SPICE?
38. Differences between netlist of HSPICE and Spectre?
39. What is FPGA?
40. Draw the Cross Section of an Inverter? Clearly show all the connections between
M1 and poly, M1 and diffusion layers etc?
41. Draw the Layout of an Inverter?
42. If the current thru the poly is 20nA and the contact can take a max current of
10nA how would u overcome the problem?
43. Implement F = AB+C using CMOS gates?
44. Working of a 2-stage OPAMP?
45. 6-T XOR gate?
46. Differences between blocking and Non-blocking statements in Verilog?
47. Differences between Signals and Variables in VHDL? If the same code is written
using Signals and Variables what does it synthesize to?
48. Differences between functions and Procedures in VHDL?
49. What is component binding?
50. What is polymorphism? (C++)
51. What is hot electron effect?
52. Define threshold voltage?
53. Factors affecting Power Consumption on a chip?
54. Explain Clock Skew?
55. Why do we use a Clock tree?
56. Explain the various Capacitances associated with a transistor and which one of
them is the most prominent?
57. Explain the Various steps in Synthesis?
58. Explain ASIC Design Flow?
59. Explain Custom Design Flow?
60. Why is Extraction performed?
61. What is LVS, DRC?
62. Who provides the DRC rules?
63. What is validation?
64. What is Cross Talk?
65. Different ways of implementing a comparator?
66. What r the phenomenon which come into play when the devices are scaled to the
sub-micron lengths?
67. What is clock feed through?
68. Implement an Inverter using a single transistor?
69. What is Fowler-Nordheim Tunneling?
70. Insights of a Tri-state inverter?
71. If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer
characteristics?
72. Differences between Array and Booth Multipliers?
73. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the
same?
74. Which gate is normally preferred while implementing circuits using CMOS logic,
NAND or NOR? Why?
75. Insights of a Tri-State Inverter?
76. Basic Stuff related to Perl?
77. Have you studied buses? What types?
78. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1
clock per stage, what is the latency of an instruction in a 5 stage machine? What is
the throughput of this machine ?
79. How many bit combinations are there in a byte?
80. For a single computer processor computer system, what is the purpose of a
processor cache and describe its operation?
81. Explain the operation considering a two processor computer system with a cache
for each processor.
82. What are the main issues associated with multiprocessor caches and how might
you solve them?
83. Explain the difference between write through and write back cache.
84. Are you familiar with the term MESI?
85. Are you familiar with the term snooping?
86. Describe a finite state machine that will detect three consecutive coin tosses (of
one coin) that results in heads.
87. In what cases do you need to double clock a signal before presenting it to a
synchronous state machine?
88. You have a driver that drives a long signal & connects to an input device. At the
input device there is either overshoot, undershoot or signal threshold violations,
what can be done to correct this problem?
89. What are the total number of lines written by you in C/C++? What is the most
complicated/valuable program written in C/C++?
90. What compiler was used?
91. What is the difference between = and == in C?
92. Are you familiar with VHDL and/or Verilog?
93. What types of CMOS memories have you designed? What were their size?
Speed?
94. What work have you done on full chip Clock and Power distribution? What
process technology and budgets were used?
95. What types of I/O have you designed? What were their size? Speed?
Configuration? Voltage requirements?
96. Process technology? What package was used and how did you model the
package/system? What parasitic effects were considered?
 97. What types of high speed CMOS circuits have you designed?
98. What transistor level design tools are you proficient with? What types of designs
were they used on?
99. What products have you designed which have entered high volume production?
100. What was your role in the silicon evaluation/product ramp? What tools did
you use?
101. If not into production, how far did you follow the design and why did not
you see it into production?

Posted in: C++, Hardware |

4 Responses to “Large list of Intel interview questions”

1. amr Says:
January 12th, 2007 at 10:20 am

I would like to ask about how can we design NAND gate using c++,by asking the
user to enter 3 inputs and gives out an output, by drawing it’s nand gate as
follows:
example
F=[(AB)'.(CD)'.E']‘=AB+CD+E the gate looks like this:

A ————–|
|——————-|
B—————| |
|
C————-| ———-
|——————————– F
D————-| ———-
|
E————————————–

2. NIKHIL AHUJA Says:

March 7th, 2007 at 12:16 pm

ans 61/62:
LVS is Layout vs Schematic….
this basically compares the generated extracted layout with that of the netlist
extracted from the schematic.
DRC is Design Rules Check…this defines the rules we have to follow in order to
make Device work after fab.

keep mailing tech ques..to [email protected]

3. Moneesh Kumar Says:

March 16th, 2007 at 7:57 am
 Question 5:
Can any one explain elaborately about “pass gate”
bcoz ,
any gate which passes the input to output wn control signal is activated it called as
pass gate means what?

4. Gattu Venkat Says:

October 24th, 2007 at 2:41 am

Question 77:

Three Types of Busses is there .

1.Memory processor bus= high speed, short length.

2.I/O bus.
3.Backplane bus= General purpose bus

1. For a single computer processor computer system, what is the purpose of a processor cache and
describe its operation?
2. Explain the operation considering a two processor computer system with a cache for each
processor.
What are the main issues associated with multiprocessor caches and how might you solve it?
3. Explain the difference between write through and write back cache.
4. Are you familiar with the term MESI?
5. Are you familiar with the term snooping?

STATE MACHINE QUESTIONS

1. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that
results in heads.
2. In what cases do you need to double clock a signal before presenting it to a synchronous state
machine?

SIGNAL LINE QUESTIONS

1. You have a driver that drives a long signal & connects to an input device. At the input device there
is either overshoot,
undershoot or signal threshold violations, what can be done to correct this problem?

VALIDATION QUESTIONS:
What are the total number of lines written in C/C++? What is the most complicated/valuable
program written in C/C++?
What compiler was used?
Have you studied busses? What types?
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what
is the latency of an
instruction in a 5 stage machine? What is the throughput of this machine ?
How many bit combinations are there in a byte?
What is the difference between = and == in C?
Are you familiar with VHDL and/or Verilog?
MEMORY, I/O, CLOCK AND POWER QUESTIONS
1. What types of CMOS memories have you designed? What were their size? Speed? Configuration
Process technology?
2. What work have you done on full chip Clock and Power distribution? What process technology
and budgets were used?
3. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage
requirements?
Process technology? What package was used and how did you model the package/system?
What parasitic effects were considered?
4. What types of high speed CMOS circuits have you designed?
5. What transistor level design tools are you proficient with? What types of designs were they used
on?
6. What products have you designed which have entered high volume production?
What was your role in the silicon evaluation/product ramp? What tools did you use?
7. If not into production, how far did you follow the design and why did not you see it into
production?

• Two capacitors are connected in parallel through a switch. C1= 1uF, C2=
0.25uF.
Initially the switch is open, C1 is charged to 10V. What happens if we
close the switch? No losses in wires and capacitors.

Answers & follow ups

• You have 2 switches to control the light in the long corridor. You want to
be able to turn the light on entering the corridor and turn it off at the other
end. Do the wiring circuit.

Answers & follow ups

• There are 3 switches that can turn on and off a light in the room. How to
connect them?

Answers & follow ups

• What will be the voltage level between the 2 capacitors? The Vcc = 10v
DC.
Sent by Tanh, VLSI engineer

Answers & follow ups

• Suppose, you work on a specification for a system with some digital

parameters. The spec table has has Min,Typ and Max colomns for each
parameter. In what column would you put a Setup time and a Hold time?

Answers & follow ups

• Design a simple circuit based on combinational logic to double the output

frequency.

Answers & follow ups

• 8bit ADC with parallel output converts an input signal into digital numbers.
You have to come up with an idea of a circuit , that finds MAX of every 10
numbers at the output of the ADC.

Answers & follow ups

• Implement a comparator that compares two 2-bit numbers A and B. The
comparator should have 3 outputs: A > B, A < B, A = B. Do it two ways:
- using combinational logic;
- using multiplexers. Write HDL code for your schematic at RTL and gate
level.

Answers & follow ups

• You have a 8 bit ADC clocking data out every 1mS. Design a system
that will sort the output data and keep the statistics of how often each
binary number appears at the output of ADC.

Answers & follow ups

• What types of flip-flops do you know?

Answers & follow ups

• Implement D- latch from

- RS flip flop;
- multiplexer.

Answers & follow ups

• How to convert D-latch into JK-latch and JK-latch into D-latch?

Answers & follow ups

• There are two counters to 16, built from negedge D- FF . The first circuit is
synchronous and the second one is "ripple" (cascading). Which circuit has
less propagation delay?

Answers & follow ups

• What is the difference between a flip-flop and a latch?

Write an HDL code for their behavioral models.

Hint from Hitequest

• Describe the operation of a DAC. What are the most important parameters
of a DAC? Do we really need both INL and DNL to estimate linearity?

Hint from Hitequest

• Compare briefly all types of ADC that you know .

Hint from Hitequest

• How will the output signal of an ideal integrator look like after
- a positive pulse is applied to the input;
- a series of 10 positive pulses ?

Hint from Hitequest

• How to design a divide-by-3 counter with equal duty cycle ?

question from Anonymous

Answers & follow ups

• For an 8-bit flash A/D converter with an input range from 0V to 2.55V,
describe what happens when the input voltage changes from 1.27V to
1.28V

• Your system has CPU, ALU and two 8bit registers. There is no external
memory. Can you swap the contence of the registers ?

Answers & follow ups

• We swapped 2 transistors in CMOS inverter (put n-transistor at the top

and p-transistor at the bottom). Can this circuit work as a non-inverting
buffer?
(By E.Martovetsky,design eng)

NO, IT CAN NOT! - Discussion with Sriram

YES, IT CAN! - Discussion with Peter

Yuri M., National Semi, PHD

• Convert D-latch into divider by 2.

What is the max clock frequency the circuit can handle ?
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS

Hint from Hitequest

• The circle can rotate clockwise and back. Use minimum hardware to build
a circuit to indicate the direction of rotating.

Hint from Hitequest

• For ATE engineers (semiconductor test):

Draw a shmoo plot of two parameters: Clock period Tclk and setup time
Tsetup.

• For chip design/test/product engineers :

An IC device draws higher current when temperature gets:
- higher
- lower

Hint from Hitequest

• To enter the office people have to pass through the corridor. Once
someone gets into the office the light turns on. It goes off when noone is
present in the room. There are two registration sensors in the corridor.
Build a state machine diagram and design a circuit to control the light.
• A voltage source with internal impedance Z_source = 50 OHm is
connected to a transmission line with Z = 50 OHm. Z_load is also 50
OHm.
The voltage source generates a single voltage step 1V.
What will be the voltage level on the load:

a) 2V , because the reflected signal will be in-phase with the incident

signal;
b) 0.33V , because the voltage is devided between Z_source , Z_load and
Z_transm.line;
c) 0.5V , because the voltage is devided between Z_source and Z_load.

Hint from Hitequest

• Draw a transistor schematic of NOR gate,it's layout and a cross section of

the layout.
This question is quite popular on interviews.
• The silicon of a new device has memory leak. When all "0" are written into
RAM, it reads back all "0" whithout any problem. When all "1" are written,
only 80% of memory cells are read back correctly. What can be possibly
the problem with the RAM?
M.Altshuler, product engineer.

• Draw a CMOS inverter. Why does CMOS technology dominate in VLSI

manufacturing?
L.Backer, DFT engineer

• Design a FIFO 1 byte wide and 13 words deep. The FIFO is interfacing 2
blocks with different clocks. On the rising edge of clk the FIFO stores data
and increments wptr. On the rising edge of clkb the data is put on the b-
output,the rptr points to the next data to be read.
If the FIFO is empty, the b-output data is not valid. When the FIFO is full
the existing data should not be overriden.
When rst_N is asserted, the FIFO pointers are asynchronously reset.

module fifo1 (full,empty,clk,clkb,ain,bout,rst_N)

output [7:0] bout;
input [7:0] ain;
input clk,clkb,rst_N;
output empty, full;
reg [3:0] wptr, rptr;
...

endmodule

Hint from Hitequest

• What does CMOS stand for? VLSI? ASIC?

This was in the series of quick questions in the interview at Analog Devices. We use
these abbreviations daily, but not everyone remembers what they stand for.
 Hint from Hitequest

• Design a COMBINATIONAL circuit that can divide the clock frequency by

2.

• Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)

• We have a circular wheel with half painted black and the other half painted
white. There are 2 censors mounted 45 degree apart at the surface of this
wheel( not touching the wheel) which give a "1" for black and "0" for white
passing under them. Design a circuit to detect which way the wheel is
moving. Can not assume any fixed position for start.

• We have a fifo which clocks data in at 100mhz and clocks data out at
80mhz. On the input there are only 80 data bits in any order during each
100 clocks. In other words, a 100 input clock will carry only 80 data bits,
and the other twenty clocks carry no data (data is scattered in any order).
How big the fifo needs to be to avoid data over/under-run.

Hint from Hitequest

• Instead of specifying SETUP and HOLD time, can we just specify a
SETUP time for '1' and a SETUP time for '0'?

• Here some hardware digital design specific questions, offered by Suhas:

(1) When will you use a latch and a flipflop in a sequential design?
(2) Design a 1-bit fulladder using a decoder and 2 "or" gates?
(3) You have a circuit operating at 20 MHz and 5 volt supply. What would
you do to reduce the power consumption in the circuit- reduce the
operating frequency of 20Mhz or reduce the power supply of 5Volts and
why?
(4) In a nmos transistor, how does the current flows from drain to source in
saturation region when the channel is pinched off?
(5) In a SRAM circuit, how do you design the precharge and how do you
size it?
(6) In a PLL, what elements(like XOR gates or Flipflops) can be used to
design the phase detector?
(7) While synthesis of a design using synopsys design compiler, why do
you specify input and output delays?
(8) What difference do you see in the timing reports for a propogated clock
and an ideal clock?
(9) What is timeborrowing related to Static timing anaylsis in Primetime?

1. Explain why & how a MOSFET works

2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a)
with increasing Vgs (b) with increasing transistor width (c) considering Channel
Length Modulation
3. Explain the various MOSFET Capacitances & their significance
4. Draw a CMOS Inverter. Explain its transfer characteristics
5. Explain sizing of the inverter
6. How do you size NMOS and PMOS transistors to increase the threshold
voltage?
7. What is Noise Margin? Explain the procedure to determine Noise Margin
8. Give the expression for CMOS switching power dissipation
9. What is Body Effect?
10. Describe the various effects of scaling
11. Give the expression for calculating Delay in CMOS circuit
12. What happens to delay if you increase load capacitance?
13. What happens to delay if we include a resistance at the output of a CMOS
circuit?
14. What are the limitations in increasing the power supply to reduce delay?
15. How does Resistance of the metal lines vary with increasing thickness and
increasing length?
16. You have three adjacent parallel metal lines. Two out of phase signals pass
through the outer two metal lines. Draw the waveforms in the center metal line
due to interference. Now, draw the signals if the signals in outer metal lines are in
phase with each other
17. What happens if we increase the number of contacts or via from one metal
layer to the next?
18. Draw a transistor level two input NAND gate. Explain its sizing (a)
considering Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the
NAND gate later than signal B. To optimize delay, of the two series NMOS
inputs A & B, which one would you place near the output?
20. Draw the stick diagram of a NOR gate. Optimize it
21. For CMOS logic, give the various techniques you know to minimize power
consumption
22. What is Charge Sharing? Explain the Charge Sharing problem while sampling
data from a Bus
23. Why do we gradually increase the size of inverters in buffer design? Why not
give the output of a circuit to one large inverter?
24. In the design of a large inverter, why do we prefer to connect small transistors
in parallel (thus increasing effective width) rather than lay out one transistor with
large width?
25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND
gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor level equivalent.
Draw its stick diagram
27. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate is connected to
VDD, give the output for a square pulse input going from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write operations
30. Draw the Differential Sense Amplifier and explain its working. Any idea how
to size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential Sense
Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the SRAM cell?
How did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect
SRAM’s performance?
35. What’s the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we delay the
enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your placements of
SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and
Buffers
38. In a SRAM layout, which metal layers would you prefer for Word Lines and
 Bit Lines? Why?
39. How can you model a SRAM at RTL Level?
40. What’s the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do you test for
Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit
with some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter.
How do you avoid Latch Up?
==========================================================
=====
1. Give two ways of converting a two input NAND gate to an inverter
2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random
Signal Generator; you can expect any sequential ckt)
3. What are set up time & hold time constraints? What do they signify? Which
one is critical for estimating maximum clock frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the
Clock)
6. Suppose you have a combinational circuit between two registers driven by a
clock. What will you do if the delay of the combinational circuit is greater than
your clock signal? (You can’t resize the combinational circuit transistors)
7. The answer to the above question is breaking the combinational circuit and
pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
9. Give the truth table for a Half Adder. Give a gate level implementation of the
same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you convert it to
XNOR? (Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence of "1101" arriving serially from a signal line?
14. Design any FSM in VHDL or Verilog.
15. Explain RC circuit’s charging and discharging.
16. Explain the working of a binary counter.
17. Describe how you would reverse a singly linked list.

| No Comments »

Ultimate Technical Interview Question - Take 2

January 31, 2008

Allow me to quote from Martin Gardner’s excellent, excellent book Mathematical

Carnival (chapter 17):
When a mathematical puzzle is found to contain a major flaw - when the
answer is wrong, when there is no answer, or when, contrary to claims,
there is more than one answer or a better answer - the puzzle is said
to be "cooked".

From the number of hits, it looks like the last post was quite popular. Therefore, I decided
to give the problem some more thought and to try to find more minimal solutions - or as
defined in the above quote “to cook this problem”.

My initial hunch was to try and utilize an SR latch somehow. After all it is a memory
element for the price of only two gates. I just had a feeling there is someway to do it like
that.
I decided to leave the count-to-3 circuitry, cause if we want to do a divide by 3, we
somehow have to count…
Here is what I first came up with:

The basic idea is to use the LSB of the counter to set the SR flop and to reset the SR flop
with a combination of some states and the low clock.
Here is the timing diagram that corresponds to the circuit above.

But! not everything is bright. The timing diagram is not marked red for nothing.
In an ideal world the propagation time through the bottom NOR gate would be zero. This
would mean that exactly when the S pin of the SR latch goes high the R pin of the flop
goes low - which means both pins are never high at the same time. Just as a reminder, if
both inputs of an SR latch are high, we get a race condition and the outputs can toggle -
not something you want on your clock signal. Back to the circuit… In our case, the
propagation time through the bottom NOR gate is not zero, and the S pin of the latch will
first go high, then - only after some time, the R pin will go low. In other words we will
have on overlap time where both R and S pin of the latch will be high.
Looking back at the waveform, it would be nice if we could eliminate the second pulse in
each set of two pulses on the R pin of the latch (marked as a * on the waveform). This
means we just have to use the pulse which occurs during the “00″ state of the counter.
This is easy enough, since we have to use the “00″ from the counter and the “0″ from the
clock itself - this is just the logic for a 3 input NOR gate!

The complete and corrected circuit looks like this now:

And the corresponding waveform below. Notice how the S and R inputs of the SR latch
are not overlapping.

Posted in Interview Questions | No Comments »

Ultimate Technical Interview Question - The Standard Solution

January 24, 2008

OK, so I am getting tons of email with requests to post a solution for this question which
was initially posted here.
I am going to post now what I consider the “standard minimal solution”, but some of you
have come up with some neat and tricky ways, which I will save for future a post.
The basic insight was to notice that if you are doing a divide by 3 and wanna keep the
duty cycle at 50% you have to use the falling edge of the clock as well.
The trick is how to come up with a minimal design, implementing as little as possible
flip-flops, logic and guaranteeing glitch free divided clock.
Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe
is necessary. The solution, which I believe is minimal requires 3 flops - two working on
the rising edge of the clock and generating a count-to-3 counter and an additional flop
working on the falling edge of the clock.

A count-to-3 counter can be achieved with 2 flops and a NOR or a NAND gate only, as
depicted below. These counters are also very robust and do not have a “stuck state”.

The idea now is to use the falling edge of the clock to sample one of the counter bits and
generate simply a delayed version of it.
We will then use some more logic (preferably as little as possible) to combine the rising
edge bits and falling edge bit in a way that will generate a divide by 3 output (with
respect to out incoming clock).

The easiest way (IMHO) to actually solve this, is by drawing the wave forms and simply
playing around. Here is what I came up with, which I believe to be the optimal solution
for this approach - but you are more than welcome to question me!

and here is also the wave form diagram that describes the operation of the circuit, I guess
it is self-explanatory.

One more interesting point about this implementation is that it does not require reset! The
circuit will wake up in some state and will arrive a steady state operation that will
generate a divide by 3 clock on its own. We discussed some of those techniques in the
past when talking about ring counters - link to that post here.
Posted in Interview Questions | 1 Comment »

Puzzle #10 - Mux Logic

September 15, 2007

Your company is pretty tight on budget this year and it happens to have only Muxes to
design with.
You are required to design a circuit equivalent to the one below, using only Mux
structures.

1) What is latch up?

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic

silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a
high amount of current to continuously flow through it once it is accidentally triggered or
turned on. Depending on the circuits involved, the amount of current flow produced by
this mechanism can be large enough to result in permanent destruction of the device due
to electrical overstress (EOS) .

2)Why is NAND gate preferred over NOR gate for fabrication?

NAND is a better gate for design than NOR because at the transistor level the mobility of
electrons is normally three times that of holes compared to NOR and thus the NAND is a
faster gate.
Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl
and t_plh delays you will find that it is more symmetric in case of NAND ( the delay
profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher
since the higher resistance p mos's are in series connection which again increases the
resistance).

3)What is Noise Margin? Explain the procedure to determine Noise Margin

The minimum amount of noise that can be allowed on the input stage for which the
output will not be effected.
4)Explain sizing of the inverter?

In order to drive the desired load capacitance we have to increase the size (width) of the
inverters to get an optimized performance.

5) How do you size NMOS and PMOS transistors to increase the threshold voltage?

6) What is Noise Margin? Explain the procedure to determine Noise Margin?

The minimum amount of noise that can be allowed on the input stage for which the
output will not be effected.

7) What happens to delay if you increase load capacitance?

delay increases.

8)What happens to delay if we include a resistance at the output of a CMOS circuit?

Increases. (RC delay)

9)What are the limitations in increasing the power supply to reduce delay?

The delay can be reduced by increasing the power supply but if we do so the heating
effect comes because of excessive power, to compensate this we have to increase the die
size which is not practical.

10)How does Resistance of the metal lines vary with increasing thickness and
increasing length?

R = ( *l) / A.

11)For CMOS logic, give the various techniques you know to minimize power
consumption?

Power dissipation=CV2f ,from this minimize the load capacitance, dc voltage and the
operating frequency.

12) What is Charge Sharing? Explain the Charge Sharing problem while sampling
data from a Bus?

In the serially connected NMOS logic the input capacitance of each gate shares the
charge with the load capacitance by which the logical levels drastically mismatched than
that of the desired once. To eliminate this load capacitance must be very high compared
to the input capacitance of the gates (approximately 10 times).
13)Why do we gradually increase the size of inverters in buffer design? Why not
give the output of a circuit to one large inverter?

Because it can not drive the output load straight away, so we gradually increase the size
to get an optimized performance.

14)What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter.
How do you avoid Latch Up?

Latch-up is a condition in which the parasitic components give rise to the Establishment
of low resistance conducting path between VDD and VSS with Disastrous results.

15) Give the expression for CMOS switching power dissipation?

CV2

16) What is Body Effect?

In general multiple MOS devices are made on a common substrate. As a result, the
substrate voltage of all devices is normally equal. However while connecting the devices
serially this may result in an increase in source-to-substrate voltage as we proceed
vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

17) Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

we try to reverse bias not the channel and the substrate but we try to maintain the
drain,source junctions reverse biased with respect to the substrate so that we dont loose
our current into the substrate.

18) What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-

channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT
is a current controlled device and MOSFET is a voltage controlled device.

19)Which transistor has higher gain. BJT or MOS and why?

BJT has higher gain because it has higher transconductance.This is because the current in
BJT is exponentially dependent on input where as in MOSFET it is square law.

20)Why do we gradually increase the size of inverters in buffer design when trying
to drive a high capacitive load? Why not give the output of a circuit to one large
inverter?

We cannot use a big inverter to drive a large output capacitance because, who will drive
the big inverter? The signal that has to drive the output cap will now see a larger gate
capacitance of the BIG inverter.So this results in slow raise or fall times .A unit inverter
can drive approximately an inverter thats 4 times bigger in size. So say we need to drive a
cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each
inverter sees a same ratio of output to input cap. This is the prime reason behind going for
progressive sizing.

21)In CMOS technology, in digital design, why do we design the size of pmos to be
higher than the nmos.What determines the size of pmos wrt nmos. Though this is a
simple question try to list all the reasons possible?

In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons,
the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS
technology, nmos helps in pulling down the output to ground ann PMOS helps in pulling
up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes
long time to charge up the output node. If we have a larger PMOS than there will be more
carriers to charge the node quickly and overcome the slow nature of PMOS . Basically
we do all this to get equal rise and fall times for the output node.

22)Why PMOS and NMOS are sized equally in a Transmission Gates?

In Transmission Gate, PMOS and NMOS aid each other rather competing with each
other. That's the reason why we need not size them like in CMOS. In CMOS design we
have NMOS and PMOS competing which is the reason we try to size them proportional
to their mobility.

23)All of us know how an inverter works. What happens when the PMOS and
NMOS are interchanged with one another in an inverter?

I have seen similar Qs in some of the discussions. If the source & drain also connected
properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1
Similarly degraded 0;

24)A good question on Layouts. Give 5 important Design techniques you would
follow when doing a Layout for Digital Circuits?

a)In digital design, decide the height of standard cells you want to layout.It depends upon
how big your transistors will be.Have reasonable width for VDD and GND metal
paths.Maintaining uniform Height for all the cell is very important since this will help
you use place route tool easily and also incase you want to do manual connection of all
the blocks it saves on lot of area.
b)Use one metal in one direction only, This does not apply for metal 1. Say you are using
metal 2 to do horizontal connections, then use metal 3 for vertical connections, metal4 for
horizontal, metal 5 vertical etc...
c)Place as many substrate contact as possible in the empty spaces of the layout.
d)Do not use poly over long distances as it has huge resistances unless you have no other
choice.
e)Use fingered transistors as and when you feel necessary.
f)Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.

25)What is metastability? When/why it will occur?Different ways to avoid this?

Metastable state: A un-known state in between the two logical known states.This will
happen if the O/P cap is not allowed to charge/discharge fully to the required logical
levels.
One of the cases is: If there is a setup time violation, metastability will occur,To avoid
this, a series of FFs is used (normally 2 or 3) which will remove the intermediate states.

26)Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND
gate later than signal B. To optimize delay of the two series NMOS inputs A and B
which one would you place near to the output?

The late coming signals are to be placed closer to the output node ie A should go to the
nmos that is closer to the output.

1. Explain why & how a MOSFET works

2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with
increasing Vgs (b) with increasing transistor width (c) considering Channel
Length Modulation
3. Explain the various MOSFET Capacitances & their significance
4. Draw a CMOS Inverter. Explain its transfer characteristics
5. Explain sizing of the inverter
6. How do you size NMOS and PMOS transistors to increase the threshold voltage?
7. What is Noise Margin? Explain the procedure to determine Noise Margin
8. Give the expression for CMOS switching power dissipation
9. What is Body Effect?
10. Describe the various effects of scaling
11. Give the expression for calculating Delay in CMOS circuit
12. What happens to delay if you increase load capacitance?
13. What happens to delay if we include a resistance at the output of a CMOS circuit?
14. What are the limitations in increasing the power supply to reduce delay?
15. How does Resistance of the metal lines vary with increasing thickness and
increasing length?
16. You have three adjacent parallel metal lines. Two out of phase signals pass
through the outer two metal lines. Draw the waveforms in the center metal line
due to interference. Now, draw the signals if the signals in outer metal lines are in
phase with each other
17. What happens if we increase the number of contacts or via from one metal layer
to the next?
18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering
Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND
gate later than signal B. To optimize delay, of the two series NMOS inputs A &
B, which one would you place near the output?
20. Draw the stick diagram of a NOR gate. Optimize it
21. For CMOS logic, give the various techniques you know to minimize power
consumption
22. What is Charge Sharing? Explain the Charge Sharing problem while sampling
data from a Bus
23. Why do we gradually increase the size of inverters in buffer design? Why not give
the output of a circuit to one large inverter?
24. In the design of a large inverter, why do we prefer to connect small transistors in
parallel (thus increasing effective width) rather than lay out one transistor with
large width?
25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate
and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor level equivalent.
Draw its stick diagram
27. Why don't we use just one NMOS or PMOS transistor as a transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate is connected to
VDD, give the output for a square pulse input going from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write operations
30. Draw the Differential Sense Amplifier and explain its working. Any idea how to
size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential Sense Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the SRAM cell? How
did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect
SRAM's performance?
35. What's the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we delay the
enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your placements of
SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and
Buffers
38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit
Lines? Why?
39. How can you model a SRAM at RTL Level?
40. What’s the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-
At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with
some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter.
How do you avoid Latch Up?
Infineon:

43. How do you tackle coupling when design deep submicron SRAM memories?

44 . Power Optimization Techniques for deep sub micron?

Digital Design Interview Questions

1. Give two ways of converting a two input NAND gate to an inverter

2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random
Signal Generator; you can expect any sequential ckt)
3. What are set up time & hold time constraints? What do they signify? Which one
is critical for estimating maximum clock frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the
Clock)
6. Suppose you have a combinational circuit between two registers driven by a
clock. What will you do if the delay of the combinational circuit is greater than
your clock signal? (You can't resize the combinational circuit transistors)
7. The answer to the above question is breaking the combinational circuit and
pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
9. Give the truth table for a Half Adder. Give a gate level implementation of the
same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR?
(Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence of "1101" arriving serially from a signal line?
14. Design any FSM in VHDL or Verilog.
Posted in Interview Questions, Puzzles | 6 Comments »

Puzzle #9 - The Snail

September 10, 2007

It’s been a while since I posted a nice puzzle and since I know they are so popular, here is
a relatively simple one. It was used in job interviews btw (the last line will boost the
amount of views for this post…)

A snail leaves his warm house and takes a crawl through the forest leaving behind him on
the ground a trail of “0″s and “1″s. He takes a very complicated route crossing his path
several times. At one point he becomes tired and disoriented and wishes to go back home.
He sees his own path of “0″s and “1″s on the ground which he is about to cross (i.e. not
the trail ending in his tail) and wonders whether to follow the trail towards the left or
towards the right.
What is the shortest repeating code of “0″s and “1″s he should leave as he crawls in order
to easily and deterministically track the way back home? What is the minimum amount of
bits he needs to observe (or the sample length of the code)?

Posted in Interview Questions, Puzzles | 9 Comments »

Puzzle #8 - Clock Frequency Driver

August 13, 2007

Take the clock frequency circuit I posted about here. As I mentioned the XOR gate at the
output might cause some duty cycle distortion with some libraries, due to the fact that
most XOR gates are not built to be symmetrical with respect to transition delay.
Now, assume your library has a perfectly symmetrical NAND gate. Could you modify
the circuit so the XOR will be replaced by a NAND gate and still have a clock frequency
at the output (You are of course allowed to add more logic on other parts of the circuit).

If not, give a short explanation why not. If yes send a circuit description/diagram.

Posted in Interview Questions, Puzzles | 2 Comments »

Puzzle #7 - Transitions - Solution

August 3, 2007

This one was solved pretty quickly. Basically I was trying to trick you. The idea was to
try to create the impression an infinite amount of memory is necessary to hold all the 0–
>1 and 1–>0 transitions. In practice there cannot be 2 consecutive 0–>1 transitions (or
vice versa) since if the input goes from 0 to 1 before the next 0–>1 transition it must
change to a 0 and thus have a 1–>0 transition!
The FSM can have only three states: “exactly one more 0–>1″, “equal amount of 0–>1
and 1–>0″ or “exactly one more 1–>0″.

Posted in Interview Questions, Puzzles | No Comments »

Puzzle #7 - Transitions
July 17, 2007

It’s time for puzzle #7.

An FSM receives an endless stream of “0″s and “1″s. The stream can not be assumed to
have certain properties like randomness, transition density or the like.

Is it possible to build a state machine, which at any given moment outputs whether there
were more 0–>1 or 1–>0 transitions so far?

If yes, describe briefly the FSM. If no, give a short proof.

Posted in Interview Questions, Puzzles | 3 Comments »

The Ultimate Interview Question for Logic Design - A

Mini Challenge
July 9, 2007

I had countless interviews, with many different companies, large corporations and start
ups. For some reason in almost all interviews, which were done in Israel, a single
question popped up more often than others (maybe it is an Israeli High-Tech thing…).

Design a clock divide-by-3 circuit with 50% duty cycle

The solution should be easy enough even for a beginner designer. Since this is such a
popular question, and since I am getting a decent amount of readers lately, I thought why
not make a small challenge - try to find a solution to this problem with minimum
hardware.