FLASH MEMORY

Flash memory is a widely used, reliable, and flexible nonvolatile

memory to store software code and data in a microcontroller. Failing to
handle the flash according to data-sheet specifications may result in
unreliable operation of the application. This application report explains the
physics behind these specifications and also gives recommendations for
correct MSP430 flash handling. All examples are based on the flash memory
used in the MSP430F1xx, MSP430F2xx, and MSP430F4xx microcontroller
families
1.Introduction to Flash Memory
Today, flash memory is one of the most popular nonvolatile memories
to store program code and constant data values. Many microcontrollers, such
as the MSP430 family of microcontrollers, have integrated flash memory for
nonvolatile data storage. But there are big differences in behavior and
performance of flash memory cells. This report explains the parameters and
behavior of the ultra-low-power flash memory used in the MSP430F1xx,
MSP430F2xx, and MSP430F4xx families.
2.Simplified Flash Memory Cell
A flash memory cell is based on a transistor with a floating gate. Figure 1
shows a simplified schematic of a flash memory cell. The ultra-low-power
flash memory cell of a MSP430 is slightly modified, but the basic function is
the same.

Figure 1. Flash Memory Cell

Underneath the control gate is an additional floating gate. This floating
gate is either fully charged or discharged. Charging and discharging this
floating gate is done with high energy through the oxide. The amount of
charge in the floating gate influences the threshold of the transistor, which
generates a logical 1 or 0 when this flash cell is read.

Erasing a flash cell, as shown in Figure 2, is positive charging the

floating gate. A positive-charged floating gate results in reading a logical 1
from this erased memory cell. Negatively charging the floating cell, as shown
in Figure 3, means programming this cell. The CPU reads from a programmed
cell the logical value 0. For erasing and programming, high energy is needed
to transport the charge through the oxide by FN tunneling for erasure or
channel hot electron (CHE) injection for programming.

Figure 2. Erasure of Flash Memory Cell (Erased Cell Is on the Right)

Figure 3. Programming a Flash Memory Cell (Programmed Cell Is on the

Right)
The smallest unit that can be erased in a flash memory is a complete
flash segment. Erasing flash means generating logical 1s in the memory. The
MSP430 main flash memory has a segment size of 512 bytes.
All MSP430 devices also have some smaller 64-byte or 128-byte flash
segments. This area of the flash is called the information memory. In most
applications, the main memory stores program code and constant data
values, and the information memory is used for calibration data, serial
numbers, etc. Except for the segment size, there is no difference between
the main and the information memory. Hence, both can store

program code or constant data values or both. Programming flash memory

generates logical 0 values in the flash memory cell. Programming can be
performed bit, byte, or word wise. Flash segment size has no influence on
programming of flash cells.
Only logical 0 can be written as single bits, bytes, or words. Because
writing logical 1 in flash memory is only possible with erasing the memory,
1s can only be written segment-wise. A high voltage is needed to program
and erase flash memory. All MSP430 devices have an integrated charge
pump and automatically generate this high voltage, when necessary. Also, a
flash timing generator for automatic generation of erase and programming
sequences is integrated in every MSP430. Hence, MSP430 flash programming
is done without any external components. For programming and erasure, it
only is important to keep the supply voltage VCC within the data sheet limits
and to program the input clock frequency of the flash timing generator
according to data sheet requirements.
3. Flash Memory Parameters
3.1 Data Retention
3.1.1 Leakage Mechanism
Data retention is limited by leakage current through the insulating
oxide. Leakage can only occur if the floating gate is fully charged. Therefore,
leakage only can flip an erased cell with the logic level 1 to a programmed
cell with the logic level 0. there are several phenomena that cause leakage.
Conventional stress induced leakage current (SILC) (see Figure 4a)
explained by single trap-assisted tunneling conduction
Anomalous SILC explained by leakage path, hopping conduction
mechanism (HCM) large leak, little E-field dependence, intermittent (see
Figure 4b)
Trapped charges can block up the leak (see Figure 4c).

Figure 4. Leak Mechanism in Tunnel Oxides

Leakage behavior depends on temperature, program/erase cycles, lifetime,

and process. In an end application, the main influence on data retention is
temperature.
3.1.2 Data Retention Time
A common concern with nonvolatile erasable memories is data retention. As
explained in Section 3.1.1, over time, the floating gate charge is reduced due
to leakage introduced by oxide defects. With higher temperatures, leakage
current increases and, thus, the charge on the floating gate is reduced more
quickly than at lower temperatures. This temperatures dependence follows
the Arrhenius equation (see Equation 1):
AF=e

Ea 1
1
(

)
k T 1 T2

.(1)

Where
AF = Acceleration factor
Ea = 0.6 eV = Activation energy
k = 86.17

106

= Speed constant

T1 = Temperature 1 (K)
T2 = Temperature 2 (K)
The Arrhenius equation gives an acceleration factor (AF) for data
retention based on a temperature difference. Because it would take too long
to measure a data-retention time at 25C, these measurements are done at
a much higher temperature to accelerate the process. In the data sheets of

MSP430 devices, data retention is specified to exceed 100 years at 25C (see
Table 1). This value is industry accepted and all vendors specify 100 years as
the flash data retention duration at 25C, despite it being extremely
conservative.
Table 1. Data Retention Over Recommended Operating Temperature
in Data Sheets
PARAMETERS

MIN
MAX

TEST CONDITION

t Retention Data retention

T j=25 C

duration

100

UNIT
years

Further tests show the exact number of years at 25C is 1324 years.
Equation 2 is an example of using the Arrhenius equation to calculate
data retention for any ambient temperature:
T1 = 50C = 323K
T2 = 25C = 298K (data-sheet specification)
AF=e

Ea 1
1
(
)
k T 1 T2

=e

0.6 eV
1
1
(

)
6
86.1710 323 298

(2)

Stored data ages at 50C six times faster than at 25C.

In an application operating at 50C, 24 hours per day, 7 days per week,
the data retention time is reduced from 1324 years to 1324/6 220 years.
If the application is running 5 hours per day at 50C and the rest of the day
at 25C, the data retention is calculated as shown here:

5 hours/day at 50C is equivalent data aging at 25C: 5 hours 6 = 30

hours
19 hours/day at 25C is equivalent data aging at 25C: 19 hours
Total data aging per day is 30 hours + 19 hours = 49 hours 2 days at
25C.

In this scenario, data retention is 662 years.

Erased MSP430 flash memory bits have fully charged floating gates and read
back as logical 1s.
3.2 Flash Endurance
Like any other erasable memory, flash devices have a limited number
of erase/write cycles they can withstand without failure. The reason for the
limitation depends on either charge trapping characteristics or the dielectric

breakdown characteristics of the tunnel oxide. This introduces a term called

endurance.
Endurance is a measure of the number of erase/write cycles that a
flash array can achieve while retaining data integrity. Per IEEE Standard
Definitions and Characterization of Floating Gate Semiconductor Arrays,
endurance is defined as "The measure of the ability of a nonvolatile memory
device to meet its data-sheet specification as a function of accumulated
nonvolatile data changes." The flash endurance specified in MSP430 data
sheets is shown in Table 2.
Table 2. Flash Endurance in the Data Sheets
PARAMETER
MIN
NOM
MAX
UNIT
4
5
Program/erase
cycles
10
10
endurance
The data sheet specifies a minimum of 10 000 read/write cycles, while
the devices typically fulfill 100 000 read/write cycles.
MSP430 endurance testing shows that most devices easily achieve
more than 100 000 cycles at ambient or high temperature, while the number
of cycles at low temperature is in the range of a few ten thousands. Failures
are always a single bit failing erase.
Measurements show improvement in the number of cycles if a
quiescent period after erase operations is added. The most common problem
is stuck cells caused by charge trapping. Charge trapping occurs in the
insulating tunnel oxide during erase operations, causing the cell to read a
logic 0 although erased. This is a self-healing effect and usually detraps
automatically in the quiescent period after an erase cycle. During endurance
testing at Texas Instruments, the flash cells are continuously erased and
rewritten. With a
delay of at least one or two seconds between two erase/write cycles, the
flash endurance increases significantly during the tests.