Operating Systems (A) (Honor Track)

Lecture 20: Paging Mechanisms

Tao Wang
School of Electronics Engineering and Computer Science
http://ceca.pku.edu.cn/wangtao
Fall 2012

Acknowledgements: Prof. Xiangqun Chen at PKU and Prof. Yuanyuan Zhou at UCSD

Review
Memory

Management

Virtual Memory
The

abstraction that the OS will provide for managing

memory is virtual memory (VM)

Virtual memory enables a program to execute with less than its
complete data in physical memory
A program can run on a machine with less memory than it needs
Can also run on a machine with too much physical memory
Many programs do not need all of their code and data at once (or
ever) no need to allocate memory for it

OS will adjust amount of memory allocated to a process based upon

its behavior
VM requires hardware support and OS management algorithms to
pull it off

Virtual Addresses

physical
addresses

virtual
addresses

processor

Many

vmap

physical
memory

ways to do this translation

Start with old, simple ways, progress to current

techniques

Fixed Partitions
Physical

memory is broken up into fixed partitions

Hardware requirements: base register

Physical address = virtual address + base register
Base register loaded by OS when it switches to a process
Size of each partition is the same and fixed

How do we provide protection?

Advantages

Easy to implement, fast context switch

Why?
Problems

Internal fragmentation: memory in a partition not used by a process

is not available to other processes
Partition size: one size does not fit all (very large processes?)
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Variable Partitions
extension physical memory is broken up into
variable sized partitions

Natural

Hardware requirements: base register and limit register

Physical address = virtual address + base register
Why do we need the limit register? Protection
If (physical address > base + limit) then exception fault
Advantages

No internal fragmentation: allocate just enough for process

Problems

External fragmentation: job loading and unloading produces empty

holes scattered throughout memory

Compaction (Similar to Garbage Collection)

Assumes

programs are all relocatable

Processes must be suspended during compaction
Need be done only when fragmentation gets very bad

5 Monitor Job 7

Job 5

6 Monitor Job 7 Job 5

Job 3

Job 8

Free6
Job

Job 3

Job 8

Free6
Job

Job 8

Free6
Job

7 Monitor Job 7 Job 5 Job 3

8 Monitor Job 7 Job 5 Job 3

Job 8

9 Monitor Job 7 Job 5 Job 3

Job 8

Free6
Job

Job 6

Free
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Swapping
Move

a part of or the whole process to disk

Allows

several processes to share a fixed partition

Processes

that grow can be swapped out and swapped

back in a bigger partition

Third Way for Virtual to Physical Mapping

Paging
Paging

solves the external fragmentation problem

by using fixed sized units in both physical and

virtual memory
Virtual
Memory

Physical
Memory

Page 1
Page 2
Page 3
Page N

Paging
Translating

addresses

Virtual address has two parts: virtual page number and offset
Virtual page number (VPN) is an index into a page table
Page table determines page frame number (PFN)
Physical address is PFN::offset
Page

tables

Map virtual page number (VPN) to page frame number (PFN)

VPN is the index into the table that determines PFN
One page table entry (PTE) per page in virtual address space
Or, one PTE per VPN

10

Page Table Entries (PTEs)

1

Page

M R

Prot

20

Page Frame Number

table entries control mapping

The Modify bit says whether or not the page has been written
It is set when a write to the page occurs
The Reference bit says whether the page has been accessed
It is set when a read or write to the page occurs

The Valid bit says whether or not the PTE can be used
It is checked each time the virtual address is used
The Protection bits say what operations are allowed on page
Read, write, execute
The page frame number (PFN) determines physical page
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A variation of paging: Segmentation

Segmentation

is a technique that partitions memory into

logically related data units
Module, procedure, stack, data, file, etc.
Virtual addresses become <segment #, offset>
Units of memory from users perspective

Natural

extension of variable-sized partitions

Variable-sized partitions = 1 segment/process

Segmentation = many segments/process
Hardware

support

Multiple base/limit pairs, one per segment (segment table)

Segments named by #, used to index into table
Can

be combined with paging

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This Lecture

Paging Mechanisms

13

Page Mapping Hardware

Page Table
0
P 1
0
1 P-> F
1
0
1

Virtual Address (P,D)

P
D

Virtual Memory
P
Contents(P,D)

Physical Memory
F

Physical Address (F,D)

Contents(F,D)

14

Page Mapping Hardware

Page Table
0
4 1
0
1 4-> 5
1
0
1

Virtual Memory
Virtual Address (004006)
004 006

Contents(4006)

004
006

Physical Memory
005

006

005

Physical Address (F,D)

Page size 0x1000
Number of Possible Virtual Pages 0x1000

Contents(5006)

Number of Page Frames 8

15

006

Paging Issues
Page

size is 2n

usually 512, 1k, 2k, 4k, or 8k

E.g. 32 bit VM address may have 220 (1M) pages with 4k
(212 ) bytes per page
Page

table:

220 page entries take 222 bytes (4MB)

16

Managing Page Tables

The

page table for a 32-bit address space w/ 4K pages to be

4MB
This is far too much overhead for each process

How

can we reduce this overhead?

Observation: Only need to map the portion of the address space actually
being used (tiny fraction of entire addr space)
How

do we only map what is being used?

Can dynamically extend page table

Does not work if addr space is sparse (internal fragmentation), why?

So

now what?
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Discussion
How to reduce page table size if the virtual pages are
sparse?

18

Two-Level Page Tables

Two-level

page tables

Virtual addresses (VAs) have three parts:

Master page number, secondary page number, and offset
Master page table maps VAs to secondary page table
Secondary page table maps page number to physical page
Offset indicates where in physical page address is located
Example

4K pages, 4 bytes/PTE
How many bits in offset? 4K = 12 bits
Want master page table in one page: 4K/4 bytes = 1K entries
Hence, 1024 secondary page tables. How many bits?
Master (1K) = 10, offset = 12, secondary = 32 10 12 = 10 bits

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Two-Level Page Tables

Physical Memory
Virtual Address
Master page number

Secondary

Offset

Physical Address
Page table

Master Page Table

Page frame

Offset

Page frame

Secondary Page Table

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So what is the problem with two-level

page table?
Hints:

Programs only know virtual addresses

Each virtual address must be translated

So, each program memory access requires several actual

memory accesses

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Efficient Translations
Our

original page table scheme already doubled the cost of

doing memory lookups
One lookup into the page table, another to fetch the data

Now

two-level page tables triple the cost!

Two lookups into the page tables, a third to fetch the data

And this assumes the page table is in memory

How

can we use paging but also have lookups cost about the
same as fetching from memory?
Cache translations in hardware
Translation Lookaside Buffer (TLB)
TLB managed by Memory Management Unit (MMU)
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Translation Look-aside Buffer (TLB)

Virtual address
VPage #

offset

VPage#

PPage#

VPage#

PPage#

...
...

.
.
.
VPage#

Miss
Real

...

PPage#

page

TLB

table

Hit
PPage #

offset

Physical address

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TLBs
Translation

Lookaside Buffers

Translate virtual page #s into PTEs (not physical addrs)

Can be done in a single machine cycle
TLBs

implemented in hardware

Fully associative cache (all entries looked up in parallel)

Cache tags are virtual page numbers
Cache values are PTEs (entries from page tables)
With PTE + offset, can directly calculate physical address

TLBs

exploit locality

Processes only use a handful of pages at a time

16-48 entries/pages (64-192K)
Only need those pages to be mapped
Hit rates are therefore very important
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TLB Function
If

a virtual address is presented to MMU, the

hardware checks TLB by comparing all entries
simultaneously (in parallel).
If match is valid, the page is taken from TLB without
going through page table.
If match is not valid
MMU detects miss and does an ordinary page table lookup.
It then evicts one page out of TLB and replaces it with the
new entry, so that next time that page is found in TLB.

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Page Mapping Hardware

Page Table
0
P 1
0
1 P-> F
1
0
1

Virtual Memory Address (P,D)

P
D
Associative Look Up
P

First

Physical Address (F,D)

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Page Mapping Example

Virtual Memory Address (P,D)
Page Table
004 006
Associative Look Up
0
1
12
1
4
47
96
0
19
3
First
1 004-> 009
3
7
1
0
Table organized by
1
009 006
LRU
Physical Address (F,D)

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Page Mapping Example: next reference

Virtual Memory Address (P,D)
Page Table
004 00a
Associative Look Up
0
1
12
1
4
4
9
0
19
3
First
1 004-> 009
3
7
1
0
Table organized by
1
009 00a
LRU
Physical Address (F,D)

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Managing TLBs
Address

translations for most instructions are handled

using the TLB
>99% of translations, but there are misses (TLB miss)

Who

places translations into the TLB (loads the TLB)?

Hardware (Memory Management Unit) [x86]

Knows where page tables are in main memory
OS maintains tables, HW accesses them directly
Tables have to be in HW-defined format (inflexible)
Software loaded TLB (OS) [MIPS, Alpha, Sparc, PowerPC]
TLB faults to the OS, OS finds appropriate PTE, loads it in TLB
Must be fast (but still 20-200 cycles)
CPU ISA has instructions for manipulating TLB
Tables can be in any format convenient for OS (flexible)

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Managing TLBs (2)

OS

ensures that TLB and page tables are consistent

When it changes the protection bits of a PTE, it needs to invalidate the

PTE if it is in the TLB
Reload

TLB on a process context switch

Invalidate all entries

Why? What is one way to fix it?
When

the TLB misses and a new PTE has to be loaded, a

cached PTE must be evicted
Choosing PTE to evict is called the TLB replacement policy
If implemented in hardware, often simple (e.g., Last-Not-Used)

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Bits in a TLB Entry

Common

Virtual page number: match with the virtual address

Physical page number: translated address
Valid
Access bits: kernel and user (nil, read, write)

Optional

(necessary) bits

(useful) bits

Process tag
Reference
Modify
Cacheable

31

Paging Implementation Issues

Overhead

of TLB

Content-addressable memory/registers
TLB

hit ratio (Page address cache hit ratio)

Percentage of time page found in associative memory

32

Now we are switching gear

What

if not all virtual memory can fit into physical

memory
The physical memory is small
Too many running processes

33

Demand Paging
Real Memory

Request Page 3

Page Table
VM Frame
3 1
2
3
4

Memory

1
2

3
4

Virtual Memory Stored on Disk

Disk
1

8
34

Paging
Real Memory

Request Page 1

Page Table
VM Frame
3 1
1 2
3
4

Memory

1
2
3
4

Virtual Memory Stored on Disk

Disk
1

8
35

Paging
Real Memory

Request Page 6

Page Table
VM Frame
3 1
1 2
6 3
4

Memory

1
2
3
4

Virtual Memory Stored on Disk

Disk
1

8
36

Paging
Real Memory

Request Page 2

Page Table
VM Frame
3 1
1 2
6 3
2 4

Memory

1
2
3

Virtual Memory Stored on Disk

Disk

8
37

Paging
Real Memory

Request Page 8: Swap page 2

to disk first

Page Table
VM Frame
3 1
1 2
6 3
2 4

Memory

1
2
3
4

Virtual Memory Stored on Disk

Disk
1

8
38

Paging
Real Memory

Load Page 8 to Memory

Page Table
VM Frame
3 1
8 2
6 3
2 4

Memory

1
2
3

Virtual Memory Stored on Disk

Disk
1

8
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Summary
Paging mechanisms:
Optimizations

Managing page tables (space)

Efficient translations (TLBs) (time)
Demand paged virtual memory (space)

Next

lecture: Midterm Exam 2

Good Luck!

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