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Questions On Small Signal Model of Amp

This document contains a mid-semester test for a microelectronic circuits course. It includes 6 questions related to MOSFET circuit analysis and design. Key assumptions are provided for device parameters of NMOS and PMOS transistors. Questions involve analyzing small signal models, deriving output impedance, designing current mirrors, analyzing differential pairs, cascaded amplifier stages, and voltage gain calculations. Students are asked to sketch circuits, derive expressions, and design amplifiers meeting specified performance criteria.

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639 views

Questions On Small Signal Model of Amp

This document contains a mid-semester test for a microelectronic circuits course. It includes 6 questions related to MOSFET circuit analysis and design. Key assumptions are provided for device parameters of NMOS and PMOS transistors. Questions involve analyzing small signal models, deriving output impedance, designing current mirrors, analyzing differential pairs, cascaded amplifier stages, and voltage gain calculations. Students are asked to sketch circuits, derive expressions, and design amplifiers meeting specified performance criteria.

Uploaded by

devsrivastava
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Birla Institute of Technology and Science, Pilani

EEE C424 / INSTR C313 Microelectronic Circuits


Mid semester Test (closed book) I Semester 2012-2013
Max. Marks=90
Time: 90 min.

Date: 06-10-2012

Unless Given specifically


Take -- VDD = 3.3V,
For NMOS device
nCox = 140 A/V2, VT = 0.7 V , = 0.1 V-1 , Cox= 38pF/um2
For PMOS device
pCox = 40 A/V2, VT = - 0.8 V , = 0.2 V-1 , COX =38 pF/um2
NOTE:

If not specified in question, ignore , in drain current equation. .

Bulk of nmos connected to ground and bulk of pmos connected to Vdd.


assumptions. Justify your answers.

Unless specified, assume all MOSFET are biased in saturation region

Label your sketches properly.

All symbols have usual meaning

Q1.

Q2.

v1
Specify your

v2

For the circuit shown in Fig. 1, the bias current in all transistors (except
M1) is 100 A. Assume all MOSFETS are in saturation and VOV for all
transistors is 0.2 V. ,=0
a) Sketch low frequency small signal model. Calculate the low frequency small
signal voltage gain [vout/ vin] of circuit making valid approximations.
b) Derive impedance at nodes v1, v2
Vb4
15
Consider Fig 2, Assume all MOSFETS are biased in saturation with Vov=0.2V, ,=0
a) Derive Rout of the circuit intuitively using valid approximations
b) Design a current mirror circuit ( find w/L of all transistors) to generate bias
voltages Vb2, Vb4 using only one Iref= 100uA source.
15

Q3.

For the differential pair of fig.3, assume all the transistors are in saturation and the

Fig. 1

M4

I=100uA

Vb2
Rout
Fig. 2

circuit is symmetric. Take =0 and ron = rop, Vod= (Vo1-Vo2) , Vind= ( Vin1 Vin2), ,=0
a) Sketch and Justify the behavior of each plot
i.

Sketch (Vo1-Vo2) as ( Vin1 - Vin2) from 0 to VDD

ii.

Sketch Vo1 as Vin1 and Vin2 are equal and vary from 0 to VDD

b) Derive the input common mode range [ICMR]?


c) Also, derive the common mode gain for single ended output.

15
Q4.

For the Cascaded configuration given in fig. 4. Input voltage Vin is riding on a
Fig. 3
dc voltage of 3V, ,=0
Ibias current flowing through each stage is 0.5mA,
Take N Cox =134 A/V2, PCox=38 A/V2 , Vtn= 0.7V, Vtp= - 0.7V, N =P= =0, Vdd=3V, where ever required assume
current mirror load with Vov=0.3V.

Note: Design means determine the W/L of all transistors in that amplifier.

a) Draw the transistor level implementation of each stage by choosing correct topology and draw
the complete circuit
b) Design push-pull amplifier having Vov. of 0.3v for each transistor.
c) Now design stage-1 circuit/s as per the specifications given above, using current mirror load.
d) Design stage-3 (circuit-3) to get a total gain of 240 for stage2 and stage3 (A1A2).( N =0.2 & P
=0.4)
e) Qualitatively write the need for stage-4 and also design this stage to deliver maximum power to
load.
18

Vin

Current
mirror
Load
Stage-1

Push Pull
Amplifier
Stage -2

PMOS
CSA
Stage -3

Fig. 4

Stage -4

RL= 860

Q5. Consider the circuit shown in figure5. Assume all the transistors are in saturation
and =0, , 0.
(a) For second stage,
(i) Plot ID versus Vx when Rs = 0 and Rs
0 on
the one graph.
(ii) Again, Plot Gm versus Vx when Rs = 0 and Rs
0 on the single graph.
(b) Derive overall voltage gain (Vout/Vin) intuitively
with valid approximation by finding Gm, Rout of
each stage.
(c) If transistor M4 is replaced by an ideal current
source, then what will be the expression of
voltage gain (Vout/Vin).

Fig. 5

15
Q6. Consider the amplifier given in Fig 6. for the case.
Vov=0.2 V, (W/L) = 36 and RD = 20 K

a) Find the DC quantities ID and VDS of M1. Draw the ID vs. VDS characteristics of
M1. Draw the load line and locate Q point on it
b) Calculate the value of Gm, ro at the operating point.
c) Draw the voltage amplifier model.
Fig. 6

12

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