Logic Testing and Design for Testability

MIT Press Series in Computer Systems

Herb Schwetrnan, edito r

M etamodelinq: A St udy oj A pprox imations in Queueing M odels,

by Subha sh Ch an dra Agrawal, 1985
Lo gic T esting and Desiqn fo r Testability,
by Hid eo Fujiwara, 1985

Logic Testing and Design for Testability

Hideo Fujiwara

The MIT Press

Cambridge, Massachusetts
London, England

Second Printing, 1990

1985 by Th e Massachusett s Institute of Techno logy

All rights reserved. No pa rt of this book ma y be reproduced in a ny fo rm by any electronic
or mechanical mean s (includin g ph oto co pyin g. recording, o r informa tion sto rage an d
retriev a l) withou t perm ission in writing from th e publisher.
This book was set in Times New Roman by Asco Trade Typesetting Ltd., Ho ng Kong and
printed and bound by H alliday Lithograph in the United States of America
Library of Congress Cataloging in Publication D ata
Fujiwara, H ideo.
Lo gic testing and de sign for testability.
(M IT Press series in com pu ter systems)
Bibliography: p.
Includes ind ex.
1. Logic circuits- Testing. I. Title. II . Series.
TK 7868.L6F 85 1985
621.3815'37
85 84
ISBN ().262.()6096-5

M IT

P r85S

.~"~~_
0262060965
.i .]
t,~ :. : . :
r ,

FUJIWARA
LOGIC TESTING

~
\\\\\\\\\\\\\\

Contents

Foreword
Preface

VII

IX

I LOGIC TESTING
1 Introduction to Logic Testing
I.I
1.2
1.3
1.4

Logic Circuits
Fault Modeling
Testing Problems
Testing Schemes

8
12
18

2 Test Generation

24

2.1
2.2
2.3
2.4
2.5

24
30
45
53

Boolean Difference
The D-Algorithm
The POD EM Algorithm
The FAN Algorithm
Test Generation for Sequential Circuits

70

3 Fault Simulation

84

3.1
3.2
3.3
3.4
3.5

85
89
96

Simulation Methodology
Parallel Fault Simulation
Deductive Fault Simulation
Concurrent Fault Simulation
Hardware Simulators

84

102

4 The Complexity of Testing

109

4.1 NP-Completeness
4.2 Polynomial Time Class
4.3 Closedness under Faults

109
115
120

II DESIGN FOR TESTABILITY

5 Introduction to Design for Testability

133

5.1
5.2
5.3
5.4

133

Testability
Minimization of Testing Cost
Combinational Logic versus Sequential Logic
Ad Hoc Design and Structured Design

139
142
144

vi

Contents

6 D esign to Minimize the Cost of Test Application

150

6.1 EOR Embedding

6.2 Minimally Testable Design
6.3 D ual-M ode Logic
6.4 Testing with Fixed Reference Values

150
156
161
167

7 D esign to Minimize the Cost of Test G eneration

171

7.1 Partitioning and Exhaus tive Test ing

7.2 Syndrome-Testable Design
7.3 Reed- Muller Canonical Forms
7.4 Programma ble Logic Arrays

171
181
188
192

8 Scan Design for Sequential Logic Circuits

206

8.1 State-Shifta ble Machines

8.2 Scan Design Approaches
8.3 Vari at ions of Scan Design
8.4 Incomplete Scan Design and Enhanced Scan Design

206
213

232

9 Design for Built-in Self-Testing

238

9.1 Signature Analysis

9.2 Built-In Logic Block Observer
9.3 Self-Test with Scan Design

238
247

226

9.4 Self-Verification

259
267

Biblio graphy

272

Index

279

Series Foreword

This series is devoted to all aspects of computer systems. This means that
subjects ranging from circuit components and microprocessors to architecture to supercomputers and systems programming will be appropriate.
Analysis of systems will be important as well. System theories are developing, theories that permit deeper understandings of complex interrelationships and their effects on performance, reliability, and usefulness .
We expect to offer books that not only develop new material but also
describe projects and systems. In addition to understanding concepts, we
need to benefit from the decision making that goes into actual development
projects; selection from among alternatives can be crucial to success . We are
soliciting contributions in which several aspects of systems are classified
and compared. A better understanding of both the similarities and the
differences found in systems is needed.
It is an exciting time in the area of computer systems. New technologies
mean that architectures that were at one time interesting but infeasible are
now feasible. Better software engineering means that we can consider
several software alternatives, instead of "more of the same old thing," in
terms of operating systems and system software. Faster and cheaper communications mean that intercomponent distances are less important. We
hope that this series contributes to this excitement in the area of computer
systems by chronicling past achievements and publicizing new concepts.
The format allows publication oflengthy presentations that are of interest
to a select readership.
Herb Schwetman

Preface

With the great and growing use of computers (especially microcomputers) in many aspects of society, it is evident that the
computers must perform more and more reliably. The reliability of a
computer depends much on testing-that is, the determination
whether circuits have been manufactured properly and behave correctly. However, because of the rapidly increasing circuit density in
large-seale-integration and very-large-scale-integration technology,
testing is getting much more difficult. One approach to alleviating
this problem is embodied in "design for testability" techniques, by
which extra circuitry is added to a circuit or a chip to reduce the
complexity of testing. In the past, design problems were approached
with the idea of minimizing the complexity of the hardware. Testing
was considered only after the design of a circuit had been completed.
Recently, however, design for testability has attracted interest in
connection with LSI and VLSI designs, because the cost of hardware
has been decreasing while the cost of testing has been increasing.
There is now a growing interest in design for testability with the
increasing use of VLSI circuits.
This book is intended to provide insight into the theory and
practice of logic testing and design for testability. The book is
divided into two parts. Part I deals with logic testing and part II with
design for testability. Although an attempt is made to include topics
of general importance, many important techniques associated with
logic testing and design for testability are also dealt with . Related
topics include test generation, fault simulation, complexity of testing,
design techniques to minimize the cost of test application and test
generation, scan design, compact testing, built-in testing, and various design techniques for self-testable systems.
The book may be used as a text for a graduate-level course in
electrical engineering or computer science. It should also be helpful
to computer designers, logic designers, and test designers who want a
better understanding of the principles of logic testing and design for
testability and who may apply the techniques to their designs. Researchers who may be interested in going deeper into the study of
logic testing and design for testability will also find the book useful.
I wish to express deep gratitude to H . Ozaki of Osaka University
and K. Kinoshita of Hiroshima University for their encouragement
and support for this work. I am heavily indebted to various persons

Preface

for discussions, suggestions, and criticisms. I am especially grateful

to S. Toida of Old Dominion University, V. K. Agarwa l of McGill
Un iversity, T. Sasao of Osaka University, Y. T akamatsu of Saga
University, and A. Yamada, S. Funatsu, and T. Shimono of NEC
Corporation.
Hideo Fujiwara

Logie Testing and D esign for Test abilit y

LOGIC TESTING

Introduction to Logic Testing

The development of computers has been stimulated greatly by integratedcircuit technology. Circuit density has increased dramatically, and the cost
of devi ces has decre ased as their performance has improved. With these
developments, reliability has become increasingly important. Ho wever.
with the advent of very-large-scale integration (VLSI), test ing has come up
aga inst a wall of "intractability" and is at a standstill. Since the gate dens ity
of VLSI circuits is increasing much more rapidly than the number of access
terminals. the ability to generate test patterns and to process fault simulations is deteriorating. The difficulty can be reduced by the development of
faster and more efficient algorithms for test-pattern generation or by the use
of design techniques to enhance testability.
1.1 Logic Circuits

Logic circuits are constructed by interconnecting elements called gates

whose inputs and outputs represent only the values denoted by 0 and 1.
Some common gate s are AND, OR, NOT, NAND, NOR, and EOR
(Exclu sive-OR); their symbols are shown in figure 1.1. The output of each
gate can be represented by a logic function or a Boolean function of the
inputs. The terms logic and Boolean are often used to denote the same
meaning. A logic function can be specified by a truth table. a Karnaugh
map, or a set of cubes. Figure 1.2 demonstrates thes e three forms. The
Boolean (logic) operations '. +, and - correspond to AND, OR, and NOT,
respectively.
The output Z of an AND gate with inputs X l and X 2 is I if and only if both
of its inputs are 1 simultaneously, and can be expressed as

The output z of an OR gate with inputs Xl and X2 is 1 ifand only ifany of its
inputs are 1, and can be expressed as

The output z of a NOT gate or an inverter with input X is 1 if and only if its
input is 0, and can be expressed as
Z

= X.

The output z of a NAND gate with inputs X I and X2 is 1 if and only if any of
its inputs are 0, and can be expressed as

Logic Testing

AND

OR

NAND

NOR

NOT

EOR

Figure I.l
Sym b ols for ga tes

Xl

, ,
EEBB
0------0

(a)

0
0

0
I

x2

( b)

Karnaugh

0
0

1
0

,
,

Tr ut h tabl e

Figure 1.2
Represe ntat ion s for a logic fun cti on

X,

x2
0

(c)

--{)o- z=x

map

x3
0
1

A se t of cubes

] x3

Introduction to Logic Testing

The output z of a NOR gate with inputs XI and

its inputs are 0, and can be expressed as

X2

is 1 if and only if both of

The output z of an EO R ga te with inputs x I and X 2 is 1 if and only if its input

are not simultaneously equal, and can be expressed as

Logic circuits can be categorized as combinational or sequential. A combinational (logic) circuit consists of an interconnected set of gates with no
feedback loops. (A feedback loop is a directed path from the output of some
gate G to an input of gate G.) The output values of a combinational circuit
at a given time depend only on the present inputs. Hence, each output can
be specified by a logic function of its input variables. A block diagram for
combinational circuits is shown in figure 1.3, where XI"' " x, are the inputs
and z I ' ... , Zm are the outputs.
A sequential (logic) circuit contains feedback loops. The output values at
a given time depend not only on the present inputs but also on inputs
applied previously. The history of previous inputs is summarized in the
state of the circuit. Figure 1.4 shows a block diagram for sequential circuits.
A sequential circuit consists of two sections: a combinational circuit and a
memory circuit. The circuit of figure 1.4 has n primary inputs X I' ... , x,; m
primary outputs ZI'
, Zm; P feedback inputs YI' ... , YP ; and p feedback
outputs YI , , Yp- YI ,
, Yp are also inputs to the memory, and YI" ' " Yp
are outputs of the memory. The present state of the circuit is represented by
the variables YI, ... , Y p ' and the next state is determined by Y1 , , Yp
The mathematical model of a sequential circuit is called a sequential
machine or a finite-state machine. A sequential machine M is characterized
by the following:
a
a
a
a
a

finite set S of states,

finite set I of input symbols,
finite set 0 of output symbols,
mapping N of S x I into S (called the next-state function), and
mapping Z of S x I into 0 (called the output fun ct ion).

The sequential machine M is expressed by the 5-tuple

(5, 1,0, N, Z).

Logic Testin g

II

Xl

Combinati onal

lZ

Logi c
Circuit

xn

zm

Figure 1.3
Block diagram of combinat ional logic circuits

Combi nati ona 1

Logi c

Ci rcuit

~
Yl
,

Yl

. I Memory I ..,
,

Figure 1.4
Block d iagra m of sequent ial logic circu its

A sequential machine ca n be con venientl y represented either in ta bular

form by a state tab le (flow table) or in graph form by a state diagram . A state
ta ble, as illust ra ted in figure 1.5(a), lists the presen t states as row headin gs
an d the inp ut sym bols (also called input values or input states) as column
head ings. The entry in ro w S, an d colum n Ij represents the next sta te
N( Sj, Ij ) a nd the output Z (Sj, Ij ) . T he machine sh own in figure 1.5(a) has
fo ur sta tes (label ed 1, 2, 3,4) and a binary input and o utp ut. Fig ure 1.5(b)
shows the sta te diagram co rres po nd ing to the table of figure 1.5(a). A sta te
diagram is a directed graph whos e node s co rrespo nd to sta tes of the
machi ne an d whose arcs correspond to state transitions. Each arc is lab eled
with the input value separated by a slash from the ou tput value asso ciated
with the transition.
Sequen tial circuits a re categorized as either synchronous o r asynchronous,
depending upon whether or not the behavio r of the circuit is clocked at

Introduction to Logic Test ing

x
0

2. 0

3. D

3. D

2.

4, D

1,

1,

4, 0

( a)

1/1

1/ 0

(b)

St a te tab le

St a t e d ia gr am

Figure 1.5
Representat ions for a sequen tial machine

Xl

xl
X

Combina t ional
Logi c

zl

z2
zm

cl oc k

Figure 1.6
Block diagra m for a synch ronous seq uential lo gic circuit

Logic Testing

clock

~
CP

SR

\ I 0: I0: 11~ I l~

(a)

SR flip-flop

JK

=t]=

CP

(b )

CIITJ
00

11

10

J K flip-fl op

-ft-

LGJ

-tj(e)

01

T fli p-fl op

---fl-U(d)

Figure 1.7
Representations for flip-Oops

om
o

0 f li p-f l op

Introduction to Logic Testing

clock

R
Figure 1.8
Realization of the SR flip-flop

Combinational

Logic

,
Zm

Circuit

r
:

f-:~

.p
Figure 1.9
Block diagram for asynchronous sequential logic circuit

discrete instants of time. The operation of synchronous sequential circuits is

controlled by a synchronizing pulse signal called a clock pulse or simply a
clock. The clock is usually applied to the memory portion of the circuit.
Figure 1.6 is a block diagram for synchronous circuits. A series of bistable

memory elements called clocked flip-flops (FF) are used in synchronous

circuits. The most popular memory elements are the D (Delay), T (Trigger),
SR (Set-Reset), and JK flip-flops shown in figure 1.7. Figure 1.8 shows a
realization of the SR flip-flop. Other flip-flops can be similarly constructed

from cross-coupled NAND or NOR gates.

The behavior of an asynchronous circuit is not synchronized; it is un-

clocked. Each feedback line is assumed to have a finite, positive, pure delay,
as is shown in figure 1.9. Proper operation of such an asynchronous circuit

requires the following conditions.

Logic Testing

Because of delays, a combinational circuit may produce a transient error

or spike, called a hazard. Such an error, if applied to the input of an
unclocked flip-flop or latch, may result in a permanent incorrect state.
Hence the combinational logic portion of the circuit should be designed to
be hazard-free.
The inputs are constrained so as to change only when the memory
elements are all in stable conditions (Yi = Y; for all i). This is called the
fundamental mode operation.
A situation whereby more than one state variable must change in the
course of a transition is called a race condition. If correct behavior of the
circuit depends upon the outcome of the race, then it is called a critical race.
To ensure that the operation ofthe circuit is not affected by transients, the
critical race should be avoided by making the proper state assignment.

1.2 Fault Modeling

Logic gates are realized by transistors, which are classified into bipolar
transistors and metal oxide semiconductor field-effect transistors
(MOSFET, or simply MOS). The logic families based on bipolar transistors
are transistor-transistor logic (TIL), emitter-coupled logic (ECL), and so
forth. Some logic families based on MOSFET are p-channel MOSFET
(p-MOS). n-channel MOSFET (n-MOS), and complementary MOSFET
(CMOS). Although ECL and TIL are important for high-speed applications, their integration sizes are limited by the heat generated by their
heavy power consumption and by large gate sizes. In contrast, the MOS
logic families are well suited for LSI or VLSI, because larger integrations
can be obtained with them than with bipolar logic families. Most LSI and
VLSI circuits of today are implemented by MOS. However, the increasing
use of MOS technology for LSI and VLSI circuits has introduced new
testing problems, as will be seen later in this chapter.
A fault of a circuit is a physical defect of one or more components. Faults
can be classified as logical or parametric. A logical fault is one that causes
the logic function of a circuit element or an' input 'signal to be changed t6
some other ,logic function; a parametric jault alters the magnitude of a
circuit parameter, causing a change in some factor such as circuit speed,
current, or voltage.
Circuit malfunctions associated with timing are due mainly to circuit

Introduction to Logic Testing

Base

-{)o--

z ,

(a) Bipolar

re ~ l iz~ t1on

(b) l ogic symbol

Figure 1.10
Inverter

delays. Those faults that relate to circuit delays such as slow gat es are called
delay fa ults. Usually, delay faults only affect the timing operat ion of the
circuit, which may cause hazards or critical races.

Faults that are present in some intervals of time and ab sent in others are
intermitt ent faults . Faults that are always present and do not occur, disappear, or change their nature during testing a re called permanent fa ults or
solid faults. Although many intermittent faults eventually become solid,
the early detect ion of intermitt ent faults is very important to the reliable
operation of the circuit . H owever, there are no reliable mean s of detecting
their occurrence, since such a fault may disappear when a test is app lied. In
this book, we will con sider mainly logical a nd solid fault s.
Figure 1.1 0 shows an n-p -n tran sistor implementi ng an inverter. When
the input x is a high volt age, the outpu t z is a low voltage; when x is a low
voltage, z is a high voltage. An open collector or base of the transis to r would
cause the output z to be perma nently high, i.e., stuck at I (s-a-I) . O n the
oth er hand, a short circ uit between the collector a nd the emitt er would
cau se z to be permanently low, i.e., stuck at 0 (s-a-O). Th ese faults a re called
stuck-at fault s.
Faults in which two lines are shorted are called bridging faults. The
technology used will determine what effect the bridging will ha ve. Generally, either high or low will dominate. If two output lines are shorted and
low dominates, both are replaced by the AND gate of the two lines, as
shown in figure 1.11.This effect is the same as the Wired-AND usually used
in TTL gates. (Figure 1.1 2 shows the Wired-AND logic used in TTL gates.)

10

Logic Testing

f
9

z
w

(al
Figure 1.11
AND-type bridging fa ult

x
y

z
W

o----J

Figure 1.12
Wired-AND used in TTL gates

( b)

Introduction to Logic Testing

(a)

11

N - 16

toctc syrrbol

Voo

0y

'1

CD
'2

i(

M)S

Figure 1.13
CMOS two-input NAND gate

__ e-.1

C,',

C/

-,

z-"}.)"

I
realization

y\J UC-r

~\

!J\\

_'.~ __

',--,
(b)

i7

r~" u !-f

z--

:r\' L,

V dci

;' J1//'~ C ,_,

,

, J,i~
ra

}lLl.'-, ~~

/11';"",(. ",)

If high dominates, both of the lines are replaced by the OR gate of the two
lines. The ECL gate has the feature that the OR of the outputs can be
realized simply by tying together these outputs. Hence, in logic circuits
implemented by ECL gates, bridging faults cause the affected signals to be
ORed.
For most practical purposes, logical faults are successfully modeled by
stuck-at faults or bridging faults. However, not all faults can be modeled by
these classical faults. This is illustrated by the following examples. Figure
1.13 shows a CMOS two-input NAND gate with p-MOS and noMOS
FETs. The output z is a low voltage if and only if both inputs Xl and X 2 are
high. In figure 1.13, four possible open faults (numbered I through 4) are
indicated. The first fault, numbered I, is caused by an open, or missing, pchannel x,-input pull-up transistor. Under this fault, when the input x, is
low and the input X2 is high, the output z becomes an undesired, highimpedance state and retains the logic value of the previous output state. The
length of time the state is retained, however, is determined by the leakage
current at the node. (Table 1.1 is the truth table for the two-input CMOS
NAND gate for both the fault-free condition and the three faulted

Logic Testing

12

Table 1.1

Truth table for CMOS NAND gate

XI

0
0
I
1

x,

normal

open at <D

open at C!l

open at G) or @
I

0
I
0

1
1

Previous state

Previous state

1
1

Previous state

conditions.) Consequently, these open faults cause combinational circuits

to become sequential, and thus they cannot be modeled as classical (e.g.,
stuck-at) faults.
Crosspoint faults in programmable logic arrays (PLAs) also cannot be
modeled by the classical faults. Figure 1.14(a)shows an implementation of a
PLA in MOS technology. PLAs usually realize two-level AND-OR logic
circuits. Figure 1.14(b) shows the two-level AND-OR logic circuit equivalent to the PLA offigure 1.14(a).A PLA inherently has a device (a diode or a
transistor) at every crosspoint in the arrays, even ifit may not be used. The

connection of each device is programmed to realize the desired logic. A

crosspoint fault can be caused in a PLA by an extra or a missing device.
Although most of the crosspoint faults can be modeled by stuck-at faults,
there still exist some crosspoint faults that cannot be modeled by stuck-at
faults.
Consider an extra device at the crosspoint A shown in figure 1.14(a). In
the absence of a fault, the output realizes the logic function

If a transistor appears at A, the first product term

XIX2X,. Hence, the faulted function will be

X IX2

will shrink to

This function cannot be caused by any stuck-at fault in the equivalent

AND-OR logic circuit of figure 1.14(b).

1.3 Testing Problems

To ensure the proper operation of a system, we must be able to detect a
fault when one has occurred and to locate it or isolate it to a specific

Introduction to Logic T esting

(a)

-os

".1

13

J:
~~

- /
'~

xl
x2
~1
x2
x3
(b )

Equivalent AND-OR logi c

Figure 1.14
Programmable logic array

14

Logic Testing

s-d-1

A~D
o c

(a)

Fault-free AND Qate

::f)

(b) Faulty AND gate,

Figure 1.15
T est for stu ck-at fa ult

component-preferably an easily replaceable 'o\ne. The former procedure is

called [ault detection, and the latter is called fault location, [ault isolation,
or fault diagno sis. These tasks are accomplished with tests. A test is a
procedure to detect and/or locate faults . Tests are categorized as faultdet ecti on tests or fault diagnostic tests. A fault-d etection test tells onl y
whether a circuit is faulty or fault-free ; it tells nothing ab out the identity of a
fault if one is present. A fault diagno stic test provides the locat ion and the
type of a fa ult and other information. The qu antity of information provided
is ca lled th e diagn ost ic resolu tion of the test ; a fault-detection test is a fault
d iagno stic test of zero diagn ost ic resolution.
Logic circuits are tested by applying a sequence of input patterns that
produce erroneous responses when faults a re present and then comparing
the responses with the correct (expected) ones . Suc h an input pattern used
in testing is called a test patt ern. In general, a test for a logic cir cuit cons ists
of many test patterns. They are referr ed to as a test set or a test seque nce. The
latter term , which means a series of test patterns, is used if the test patterns
must be applied in a specific order. Test patterns, to gether with the output
responses, a re sometimes called test data.
Figure 1.I5(a) shows a fault-free AND gate. Figu re 1.15{b) shows a fault y
AND gate in which input A is stuck-at-!. The input pattern applied to the
fault-free AND gate has an output valu e ofO. In contrast, the output value
of the faulty AND gate is 1, since the stuck-at-I fault on A creates the
erroneo us resp onse. There is a definite difference between the faulty gate
a nd th e fault-free gate. Th erefore, the pattern 01 sho wn in figure 1.15 is a test
pattern for the A s-a -l fault.
If there exists only one fault in a circuit, it is called a sinqle fa ult. If there
exist two o r more faults at th e same time, then th e set of faults is called a
multiple[ault. For a circuit with k lines, th ere are at most 2k possible single

15

Introduction to Logic Testing

Figure 1.16

A/o

+ p/ )

Table 1.2

Allsingle stuck faults

X,

X,

z
I

~c>I )

'l-':

l"f ~ ' '''

:; '~

".1'-

r\J :~ J\"; S

A/O B/O c/O 0/0 E/O F/O A/I B/ l C/ I 0 / 1

o -0 . 0 I I
I
I
I
1
I
I
I
1
o 1 0 I I
I
I
I - 1. o
o -1 0 0 0 o . 1
1 -0
I
I - 0 -0
1
1
1
1 -

e/J

E/l F/ l
I

-I

c ","",Y' o f

ie

stuck-at faults. F or mu ltiple faults, the number of possible fauJts increa ses
k
~1<.~ 5 '......A- 1A-/'~ "' 1 ~ ,
dramatically to 3 - I,'smce any' line may be fault-free, s-a-O, or s-a-L A
circuit with 100 Jines would contain ap pro ximately 5 x 1047 faults. This
wou ld be far too many faults to assume, and hence test ing for mu ltiple faults
wou ld be impractical. H owever, for mo st a pproaches the model of a single
stuck-at fault has proved to provide the best practical basis. For example,
every co mplete single-fa ult-detection test set in any internal fanout-free
combinational circuit is known to cover at least 98 percent of a ll multiple
fau lts made up of six or fewerfaults (Agar wal and Fung 1981).
Since several differen t fa ults often may cau se a circu it to malfunction in
preci sely th e same way, it is convenient 10 gro up these equivalent f aults (or
indistinguishable f ault s) into equivalence classes. In the circuit sho wn in
figu re 1.1 6, the re are six signal lines (nets); hence, there are at most twelve
possible single stuck-a t fault s. Ta ble 1.2 illustr ates a tru th tabl e with
columns listing all possible single stuck-at fa ults and rows indicating all
inpu t patterns, wher e a line A stuck-at-O fau lt, for example, is den oted as
Aj O. As can be seen fro m table 1.2, the malfunction s caus ed by AjO, BjO, Ej O,
OJ!, and Fj l are all the same, so they a re grouped together in a fault
eq uivalence class. Similarly, CjO, D jO, an d Ejl a re gro uped to gether, as
shown in table 1.3. A fault is called redundant if its presence causes no
malfuncti on . In other words. the o utput function of a circ uit with a red un-

16

Logic Testing

Table 1.3
Fault equivalence classes

10
I,
I,
13
I.
I,

rJ~)j,/b/7J

z (fault-free), C/I

A/O, B/O, E/O, D/I, F/l

C/O, D/O, E/I
F/O

A/I
B/l

Table 1.4
Fault table for representative faults

x,

o
o

1
I

I,

x
x

x
x

I,

13

x
x

C)

I 0
/ I

dant fault is exactly the same as that of the fault-free circuit. In the circuit of
figure 1.16,fault ell is redundant, as table 1.3 shows.
In fault detection and location, only the faults that are picked out as
representative faults from each fault equivalence class need be considered,
since any two equivalent faults are indistinguishable from input-output
behavior only. Table 1.4, which is a fault table for five representative faults
of table 1.3, indicates precisely which test pattern will detect each fault.
Finding a fault-detection test set is simply a matter of defining a set of rows,
each indicating a test pattern, so that each column indicating a fault class
may have an "x" in one of the rows. For this example we obtain {OO, 10, II}
as a fault-detection test set. A fault diagnostic test set is obtained by defining
a set of rows so that no pair of column patterns corresponding to the rows
may be the same. From table 1.4 we have {00,01, 10, II} as the diagnostic
test set.
The testing of logic circuits is performed in two main stages: generating
test patterns for a circuit under test (the test generation stage) and applying
the test patterns to the circuit (the test application stage). Thus, the generation of test patterns is important; however, it is very difficult for large (e.g.

Introduction to Logic Testing

17

LSI and VLSI) circuits, so mo st of the effort of the past 20 years in this field
went into research and de velopment on efficient and economical testgeneration procedures.
The quality ofa test (a set or a sequence of test patterns) depends much on
the fault coverage as well as the size or length of the test. The fault coverage
(or test coverage) of a test is the fraction of faults that can be detected or
located with in the circu it under test. The fault coverage of a given test is
determined by a process called fault simulation, in which every given test
patterns is applied to a fault-free circuit and to each of the given faulty
circuits, each circuit behavior is simulated, and each circuit response is
analyzed to find what fault s are detected by the test pattern. Fault simulation is also used to produce fault dictionaries, in which the information
needed to identify a faulty element or component is gathered.
Summary
The test-generation process includes fault modeling and reduction, testpattern generation, fault simulation, fault-coverage evaluation, and the
production of a fault dictionary. The first step consists of developing a fault
dictionary for the circuit (that is, modeling the fault s th at are assumed) and
reducing the number of faults in terms of the fault equivalence relation.
Usually, the "single stuck-at fault" model is adopted, and the fault dictionary is generated directly from the logic-circuit description by arranging the
distinguishable faults for each gate in tabular form . Next, test patterns are
generated to test for the set of faults listed in the fault dictionary. The test
patterns are then simulated against the faulted circuits in the fault dictionary, and the fault coverage is evaluated from the results of the fault simulation (which include lists of tested and untested fault s). If the fault coverage
is inadequate, then the process of test-pattern generation and fault simulation is repeated for the untested faults until an adequate fault coverage is
achieved. Finally, the fault dictionary is completed by specifying enough
information to detect and locate the faults.
To be practical and cost-effective, the above test-generation process is
generally automated in the form of a collection of application software. In
particular, the test-pattern generation and the fault simulation should
interact effectively to give a high level of fault coverage at a low computation cost. The application of LSI and VLSI requires more efficient automatic test generation (ATG) systems.

Logic Testing

18

Fault Modeling and Reduction

Inadequate

Figure 1.17

Procedure for test generation

1.4 Testing Schemes

Logic testing is performed in various stages, including factory testing of
chips, boards, and systems and field testing of boards and systems during
periodic maintenance and repair. Usually, fault detection comes first. Hit is
determined that a fault is present, fault diagnosis is then used to isolate the
faulty node or component for repair. In the testing of LSI and VLSI chips it
is not necessary to locate faulty gates, since the entire chip must be discarded if any output value is faulty. However, fault diagnosis is required in
the testing of boards and systems, and diagnosis at the system level is very
important in factory testing and in field maintenance. After a fault has been
isolated at the system level, components or individual modules are replaced
until a repair is accomplished.
Testing approaches are distinguished by the techniques used to generate
and process test data, and can be divided into two categories: on-line and

Introduction to Logic Testing

19

off-line. Oll-lille tesrillg is execu ted duri ng system run time, con current with
norm al computer opera tio n. Data patterns from normal computat ion serve
as test patterns, an d a failure cau sed by some fault can be detected by builtin monitoring circuits. Since testing and no rmal computation ca n proceed

concurrently, on-line testing is also called concurrent testin g and is effective

against intermittent faults. Off- line testing is execut ed when th e system
unde r test is off line. In off-line testing, specific test pa tte rns are usua lly
pro vided; data pattern s from normal computation cannot serve as test
patterns.

Testin g approaches a re also di vided int o externa l testin g a nd bu ilt-in

testing. In external test inq the test equipment is extern al to the system und er
test; that is, test pattern s a re a pplied by the extern a l tester a nd the responses
are then evalu ated . In built-ill testinq the test equ ipment is built into the
syste m under test. As described below, on-line testing uses built-in mo nitoring circuits to detect a failure cau sed by some intermittent or solid fault, an d
thus it belongs to the ca tegory of built-in testing. Off-line testing encompasses both types of testing schemes, extern al and built-in.
On-line testin g schemes a re usually implemented by redundancy techIliqlle, : information redundancy a nd hard ware redundancy. Inform ationredundancy approaches include such pop ular coding schemes as parity,
cyclic redundancy checks, a nd err or-correcting codes; hardware-rcdu ndancy techniques include self-checking circuits at the gate level, duplication at the module level, a nd replicated co mpu ters a t the system level.
Th e most widely used linear codes are odd a nd even parity check code s
for single-bit fault detection a nd Ha mming codes for multiple-bit fault
detection. In those erro r-detecting codes, one or more red und ant bits are
simply appe nded to detect erro rs. For example, con sider a combi na tional
circuit with Ii inp uts an d III out pu ts. If on ly k < 2m output values ca n occur
during normal opera tion, the occu rrence of any of Z" - lc unallowable
values ind icat es a malfunction caused by a fault in the circu it. The output
values that do occur are called code words, a nd una llowable output values
are called noncode words. Error-detecting codes a re usually used to design
hard ware that ca n automa tica lly detect erro rs in the circu it (figure 1.18).
Self-checkinq circuits are thos e circuits in which the occur rence of a fault
can be recognized only by observing the outputs of the circu it. An important subclass of self-checking circuits is totally self-checkinq circuit s, defined
as follows. A circuit is [ault-secure for a set of faults F if, for any fault in F
and any allowable code input, the outpu t is a no ncode word or the correct

20

Logic Testin g

Error de tec t ing code )

Cir c ui t
Under

I nput s

Outputs

Test

Checker

Pass/Fa il

Figure U S
On-line testing using informa tion redundancy

Ci r cuit
Unde r

I nput s

r
I

Outputs

Tes t

L--.!-

Referenc e
Circu it

..
,

( compar e

Pass/Fail

Figure 1.19
On -line testing using ha rdware redunda ncy

code word, neve r an inco rre ct code word. In other words. the output of the
faulty circuit ca nnot be a code word and, at the same time, be different from
the correct output. T hus. as long as the ou tput is a code word, it ca n sa fely
he assumed to be correct. On the ot her han d, a cir cuit is self-testing for a set
of fau lts F if, for any fault fin F, th ere exists an allowable code inpu t th at
de tects f (i.e., th e resulting output is a non code word). In ot her words, the
inpu t set co ntains at leas t one test for every faul t in th e prescribed set. A
totally self-checki ng circuit is bo t h fault-secure and self-testing for all fau lts
und er consideration. He nce, a tota lly self-checking circui t ca n gua rantee
t hat any fault in the circuit cannot cause an error in the o utp ut without
det ection of the fault.
O ne of the most effective approaches to on-line testing using hardware
redundancy is dua l redundancy; t hat is, straightforward d uplica tio n of t he
resource being tested . Figure 1.19 shows this d up licatio n scheme for built-in

21

Introduction to Logic Testing

Reference va l ue

Test

Circuit

Pattern

Under

Source

Test

IComparator I

Good/Faulty

Figure 1.20
General test ing scheme

testing. Although full duplication is the upper bound on hardware redundancy for fault detection and thus requires more hardware than other
hardware-redundancy approaches, the duplication scheme can eas ily be
adopted at any part of the computer system and at any level within the
computer hierarchy.
In the external-testing approaches, the circuit under test (CUT) is tested
with automatic test equipment (ATE) in which a sequence of test patterns are
applied to the CUT and the responses of the CUT are compared against
reference values (correct responses). Figure 1.20 shows the general scheme
of testing. Test patterns and reference values are produced by either
software-based or hardware-based methods. In the software-based scheme,
test patterns and correct responses are generated in advance and stored in
memory. Test patterns are produced either manually, by a design or test
engineer, or automatically, by test-generation programs. In contrast, both
test patterns and reference values can be produced each time a CUT is
tested by hardware-implemented algorithms. In these hardware-based
schemes, test patterns are usually generated randomly or pseudorandomly
and simultaneously applied to the CUT and a known good circuit, called a
gold circuit. The output responses of the CUT are then compared with those
of the gold circuit. This type oftesting method (figure 1.21)is called random
testing, and in contrast the former software-based testing is called deterministic testing. Deterministic testing requires costly or time-consuming test
generation and memory to store huge amounts of test data, where as
random testing eliminates the cost and the time requirement of generating
or storing test data. However, random testing has disadvantages: The need
for a gold circuit may be bothersome, and the reliability of the gold circuit is
not guaranteed. Synchronization of the two circuits and fault coverage of
random test patterns may also cause problems.
In the above-mentioned testing schemes, the total responses are com-

Logic Testing

22

Circu it
Under

Test

Random
Good/ Faul ty

Pattern
Ge ner a to r

Gold
Ci rc uit
Figure 1.21
Random testi ng

Refe re nce ve1ue

Test

Circuit

Patternr----~~

Under

Source

Test

Data

Good/Fau1 ty

Compressor

Figure 1.22
Co mpact testin g

From
CUT

Figure 1.23
A 16-bit linear feedback shi ft register (Fr ohw erk 1977). Cop yright 1977 Hewlett-P ackard
Co mp any . Repr oduced with per mission .

Introduction to Logic Testing

23

pared with the correct reference values, which are usually high volumes.
This difficulty of analysis and storage of huge amounts of response data can
be avoided through an approach called compact testing, in which, rather
than the total responses, compressed response data are used for com-

parison. Figure 1.22 shows the general scheme for compact testing. The
model of figure 1.22 allows wide variations in the methods for test-pattern
generation and data compression. In a global sense, compact testing
methods may be classified as either deterministic or random in connection

with the techniques used to generate test patterns. The data compressor can
be implemented with simple circuitry, such as counters and linear-feedback
shift registers. Since compact testing requires little test equipment, it is

suited for built-in testing. A widely used method of compact testing is

signature analysis, which compresses the output response through a 16-bit
linear feedback shift register whose contents are called the signature. Figure
1.23 shows a 16-bit linear-feedback shift register.

Test Generation

In this chapter we consider the problem of test generation and examine

several algorithms for the computation of tests. In the first four sections, we
restrict our attention to test generation for combinational circuits. In the
last section, we consider the problem of generating tests for sequential
circuits.
Many algorithms for test generation have been proposed over the years.
Most of those approaches were of more theoretical than practical significance and consequently have not been put to practical use. Only a few
approaches are of practical use. The most widely used algorithm is the Dalgorithm (Roth 1966). This is a complete algorithm in the sense that it will
generate a test for any logical fault if such a test exists. However, it has been
pointed out that the D-algorithm is inefficient in generating tests for circuits
with many EOR gates. To improve this defect of the D-algorithm, another
test-generation algorithm called ' P O D EM (Path-Oriented DEcision
Making) was proposed (Goel 1981a). However, a fanout-oriented testgeneration algorithm (called FAN) has recently been developed (Fujiwara
and Shimono 1983a,b) that generates tests much more efficiently than the
D-algorithm or POD EM. These three algorithms are described in detail
below.
The generation of tests is usually much more difficult for sequential
circuits than for combinational ones. This is due mainly to the poor controllability and observability of sequential logic. However, the controllability and observability of sequential circuits-that is. their testabilitycan be raised to the level of combinational ones by some techniques known
as "design for testability." Those techniques allow tests for sequential
circuits to be reduced to tests of the same sort that are used for combinational circuits. Hence, if we assume that sequential circuits under tests are
always implemented by those design techniques, it is sufficient to develop
efficient test-generation algorithms only for combinational circuits. For
this reason, this chapter emphasizes test-generation algorithms for combinational circuits and treats those for sequential circuits only briefly.

2.1 Boolean Difference

Each output of a combinational logic circuit realizes a logic (Boolean)
function. Let F(X 1,X2""'Xn) be a logic function of the input Boolean
variables Xl' X 2, , X n The Boolean difference of F(X) with respect to an
input Xi is defined as

Test Generati on

25

and is denot ed by

dF(X)
~o

It can also be represented as

dF(X) = Fi(O) Ej) Fi(1)

dx,
whe re

F,(1)

F(x , . . . x, _,. I'X'+I . . ... X.).

In general. a logic function is co mposed of some component functions

using logic opera tions. such as complement, p roduct. and sum. T hus, the
formulas that express the Boolean difference of those ope rations in terms of
the Boolean differences of the comp on ent functions are useful in calc ulating
the Boolean difference. On the ba sis of the definition of the Boolean
difference. those formulas can be deriv ed as follows:

(I)
dF(X)

d;;-

dF(X)
= dXj

(2)

d dF(X) . d dF(X)
dXi

dXj

'- dXj

dX j

(3)
,

d [F(X)G(X)] = F(X)dG(X) @G(X)dF(X) @ dF(X) dG(X) ,

dx,
dx,
dx ,
dx, dx,

(4)

d [F(Xl + G(X)]
dx,

F(X) dG(X) Ell G(X) dF(X) Ell dF(X) dG(X)

dx ,
dx,
dx, dx ,

(5)

-..:d[::.. .f-,--(X-,-;lE=--%l G,-(X.!C:

)]
dx,

_dF(_X) Ei1 _
dG(_X) .

(6)

Ex ample 2.1
=

X 1X 2

dx,

dx,

Cons ider the circuit show n in figure 2.1. The output is F(X)

+ X2 X3 0 From the definiti on of the Boolean d ifference,

Logic Testing

26

Using Boolean algebra,

dF
dX 1

d(G) + G2 )
dX 1
[by eq. 5]

.
dG2
[ SInce dX

[by eq. 4]

.
dX 1
dX2
]
[ since -dX1 = 1 and -dX 1 = 0

= x2
Consider F(x I ' . x n) as an output function of a combinational circuit.
Let 0: be a fault in wh ich input Xi is s-a-O. The function realized by the faulty
circ uit is

= F;(O).
The test pattern th at detects the fault ex is an input combination or vector X
th at satisfies

F(X) EEl F,(X)

= 1.

Us ing some arithmetic. we ob tain

F(X) EB F,(X) = (xiF;(O) EEl XiF;( 1)) EB Fi(O)

= xjFj(O) EEl x;F;(I) EB (x; EEl xi)Fi(O)

27

Test Generation

Figure 2.1

= xjFi(O) EB xjFi(O) EB XiFi(l) EB x;Fj(O)

=

x j ( Fj (1 ) EB Fi(O))

dF(X)
-
dXi

=X i -

Thus the set of all tests that detect the fault

=
{ x. x. dF(X)
dx,
,

Xi

s-a-O is

l}

and is defined by the Boolean expression

This expression implies that Xi = land dF[dx, = 1. Since Xi = 1, then Xi

applies the opposite value on the faulty input. The factor dF/dx j ensures
that this erroneous signal affects the value of F. Similarly, the set of all tests
that detect the fault Xi s-a-l is defined by the Boolean expression

_ dF

<z:
Xj

Example 2.2 Consider the circuit of figure 2.1. The output is F(X) =

X I X2

+ X2XJ' The set of tests that detect the fault Xl s-a-O is calculated as follows:

Thus, the set of all tests that detect this fault is defined by the Boolean
expression

28

Logic Testing

Figure 2.2
Internal sign al line

This means that the fault Xl s-a-O causes an erroneou s signal Xl and this
erroneous signal affects the output value of F only if X I X 2 = 1, that is, only
if X t = 1 and X2 = 1.
In general, faults can exist not only on external or primary inputs but also
on signal lines that are internal to the circuit. The Boolean difference can
also be used to derive tests for stuck-at faults on internal signal lines. For the
clfcuit of figure 2.2, let F(X) be the output function of the circuit and let h be
an internal signal line. We can express h as a function of X: h(X). We can
express the output function F as a function of X and It by considering It as an
input. Let this function be F*; that is,

F*(X, It) = F(X).

To detect the fault It s-a-O, it is necessary to propagate the opposite value I
to It and to propagate the difference of normal and erroneous signal values
to the output of the circuit. Thus, the set of all tests that detect the fault It s-ais defined by the Boolean expression

Similarly, the set of all tests that detect the fault It s-a-l is defined by the
Boolean expression
J (X).
1

dF*(X. Ii)

dlt'

Example 2.3

For the circuit offigure 2.1, consider the fault h s-a-I, where It
is an input of Gz . The output function

Test G eneration

29

Figure 2.3

will be expressed as a function o f Xl ~

F*(X,h) ~

X,X ,

X2' x 3

and II:

+ hx ,

where h(X) = x, . Thus, we have

dF*(X,h)
dh

= XI X,
=

Ell (x , x, + x, )

{'ii , + x,)x, .

The set of all tests that detect the fault h s-a-l is defined by the Boolean
expression
-( I) . dF*(X, h)
,X
dh
(

Hence, the fault h s-a-I is detected if and only if x , = 0 a nd x ,

= x, = 1.

Example 2.4 Con sider the circu it of figure 2.3. The output is F(X) = x,
+ X, X , = x, + X , . Compute the set of all tests that det ect thefaul t h s-a- L
where h is an input of G, as show n in figure 2.3. F can be expressed as a
function F* of X and 1J:
F*(X,h ) = x , + hx"
where h(X) = x, , Th us,

dF*(X, h) _
_
dh
= x, Ell(x ,+x,)

Logic Testing

30

The set of a ll tests tha t detect the fault Iz s-a- I is defined by Boolean
exp ression

- . dF*(X, Iz)
Iz(X)'

dlz

=xtx ,x,
= 0.

This mean s that no test patterns exist for the fault Iz s-a-I ; tha t is, the fault h
s-a- l is redun dant.

Th e effect of two fau lts a t the inpu t of a logic circuit on its o utput can be
a na lyzed by defining the doubl e Boolean d ifference as

Thus, test generation for multiple stuck -at faults ca n be generalized by

using multiple Boolea n d ifferences (Ku and Masson 1975).
T he test-genera tion me thod using the Boo lean differe nce was develo ped

by Sellers et al. (I968a). T he Boolean -difference ap proach can be cha racterized as algebraic in tha t it manipula tes circu it equa tions to gene rate

tests. Several ot her algebraic test-generation methods have been developed.

These inclu de the pro positional method of Poage (1963), the equivalent
normal for m of Armstrong (1966), th e cause-effect equat ion of Bossen and
Hong (1971), the SPOOF procedure of Clegg (1973), an d the structure
descript ion function of K inoshita et al. (1 980).
T hese approaches a ll generate equa tions for a fault-free circuit a nd
manipulate those equation s to generate tests. However, in general. it is a
difficult task to man ipulat e algeb raic equa tions. For large circuits, a great
amount of algebra ic mani pula tion may be required to derive tests fo r a
given fault. Moreover, because these algeb raic meth ods generate all the

tests for a given fault, they ha ve the disad van tage of requiri ng a la rge
quantity of time and memory. which may make them imp ractical for large

circuits.

2.2 The D-Algorithm

There are other test-generation methods that use the top ological gate-level
description of a circui t instead of man ipulating Boolean equation s. Those

Test Gene ration

31

Figure 2.4
Single-path sensitizat ion

methods all involve path sensitization and signal propagation using a

backtracking mechanism.
One-dimensional path sensitization or single-path sensitization is one of
the simplest approaches to test generation. The basic idea of the method is
to select a path from the site of the fault, say gate Go, through a sequence Gl ,
... , Gil of gates leading to an output of the circuit. First, inputs of Go are
specified so as to generate the opposite value of the faulty value (0 for s-a-l
and I for s-a-O) at the site of the fault. Then, the inputs to Gl , ... , Gn are
determined so as to propagate the fault signal along this path to the primary
output of the circuit. The technique for doing so is illustrated in figure 2.4.
All inputs to Gj except an input on th e path are set to I for an AND/NAND
gate and 0 for an OR/NOR gate. In this figure, the symbol 0/1 represents a
signal that has value 0 in the normal or good circuit and I in the faulty
circuit, and 1/0 represents a symbol that has value 1 in the normal circuit
and 0 in the faulty circuit. This process is called the forward-trace or errorpropagation phase of the method. The path is called a sensitized path.
Finally, we must find a primary input pattern that will realize all the
necessary gate input values. This is done by tracing backward from the
inputs of Go, . . . , G; to the primary inputs of the circuit. This process is
called the backward-trace or line-justification phase of the method.

Example 2.5 For the circuit of figure 2.5, in order for the fault Xl s-a-Oto be
detected, Xl must be 1 and the error signal must be propagated along some
path. We have a choice of propagating the error signal to the output Zl via a
path through G l , Gs and G7 or through Gl , G4 , G6 , and G7 To propagate
through G l requires that X 2 be I. To propagate through Gs and G7 requires
the output of G3 to be I and the output of G6 to be O. This implies that the
output of G2 must be 0, and thus X3 = 0 or X 4 = O. Consequently, we have
two tests: X lX 2 X3 and XlX2X4' In these tests a difference between normal

LogicTesting

32

x1 _ _--r-__..

x2 - -

,,---

)---,...------1----..

3 _ _r--......

x4

--""'----~

r-~----L-----'

Figure 2.5

. . - - - - - - - - - - - - - - 1 -.. . .

X2

G
4

--+---I--..--r-----

x4 --+-~~-+--------;

Figure 2.6

and faulty signals propagates along the path

path is a sensitized path.

Xl

G1 GS G7 Z l' and hence this

The single-path sensitization method has a fatal flaw. In general, there

Canexist testable faults in a circuit for which it is impossible to generate tests
if only one path is allowed to be sensitized at a time . A simple example was
reported by Schneider (1967). The circuit is shown in figure 2.6, and the fault
in question is G2 output s-a-L To generate the value 0 at the output of G2
requires the input X 2 = X 3 = 1. Any single path from G2 to Zl must pass
through Gs or G6 If only a single path through Gs and Gs is selected to be
sensitized, it requires XI = 1 and G4 = G6 = G7 = 1. Furthermore, G6 = 1
requires X 4 = O. However, X 2 = X 3 = 1 and X 4 = 0 implies G7 = 0, which is
an inconsistency. By symmetry of the circuit, another sensitization along

Test Generation

33

o
Xl

x, -o-4-- - h -r-----,
x ":'---t-- -4-L---I
3

x4

...:1-4_ .-_ !-

--i.---I

o
Figure 2.7

Multiple-path sensitizatio n

pa th G. G, must also fail. This incon sisten cy seems to imply th at the fau lt
cannot be detected. However, th e input pattern x, = X , = x, = x. = 1
provides a test for the fault in qu estion. Figur e 2.7 shows the behavior of
bot h normal and fault y circu its for this inp ut. In this figure, we notice that
the effect of the fault has been propagate d simultaneou sly along two paths.
The single-path sensitizat ion method failed to derive the test because it
allowed only one path to be sensitized at a time. Therefore, in order to
guarantee finding a test for a fault if one exists, we must con sider the
sensitization of all possible paths from the site of the fault to the circuit
outputs simultaneously. This mult iple-path sensitization approach, called
the D-algorithm, was first formu lat ed by Roth (1966; see also Roth et al.
1967).T he D-algorit hm is formalized in terms ofa cubica l algebra ca lled the
D-calculus. Before describing the algorithm, I will introduce three types of
cube s a nd the D-ca leulus.
For a gate G which realizes the logicfunction f, the singular cover of G is
a set of the prime implicant s off and 1 Each pri me implica nt of the singular
cover is called a singular cube. For example, cons ider the two-input AND
gate sho wn in figure 2.8. The prime implica nt of f is x , x" a nd the prime
impl ican ts of J are X, a nd x,. Thus, the singula r cover of the AN D gate is
th at shown in figure 2.8.
A primitive D-cube of a f ault (pdcf) is used to expre ss tests for a fault in
terms of the input and output lines of the fau lty ga te. As an example,

34

Logic Testing

Xl

X -r\

~f

2~

3
1

Figure 2.8
A two-in put AND gate and its singula r cover

s-a- O

o
Figure 2.9
A fault and its pr imitive D-cube

consider the AND gate with an output s-a-O fault shown in figure 2.9. To
test the fault it is necessary to set 1 on the output line, and thus lines 1 and 2
must be forced to value 1. Then line 3 will ha ve value 0 if the fa ult is present
and value I ifit is absent. Hence, the corresponding primiti ve D-cube of the
fault is
2

where D mean s value 1 in the normal circuit and valu e 0 in the fault y circuit.
Similarl y, D will be used to represent a signal that has th e value 0 in the
normal circuit and I in the faulty circu it. Note that all appearances of D in a
cube ar e con strained to take the sam e value. Thus, the cub e DOD represents
the two cubes 001 and 100. On the contrary, the symbol X indicates "don't
care" and ma y take th e values 0 and 1 independent of other values. Thus,
the cube XOX represents the four values 000, 001, 100, and 101.
The primitive D-cubes of a fault are constructed by intersecting pairs of
singular cubes from the singular covers of the faulty and fault-free gat es. Let
the singular cubes for which the output of the fault-free ga te is 1 (0) be
denoted by (Xl (eto). Let the singular cubes for which the output of the faulty
gate is 1 (0) be denoted by PI (Po). The primitive D-cubes of the fault that
result in output D can be obtained by intersecting the inputs of eac h cube in
~ I with those for each cube in Po . Similarly, th e prim itive D- cub es of the
fault resulting in output D can be obtained by intersecting cubes in eto and

PI.

35

Test Generat ion

(.)

"I

"0

( b)

;]

'1

ii
ii

1 0.0 n 61

'0

(e)

( d)

FiCure2.10
A fault and its primitive D-cubes

Example 2.6 Suppose there is a fault that transforms an AND gate into an
OR gate. T he singular covers of the fault-free and faulty gates a re shown in
figure 2.10. By intersecting each pair of cubes from ~, and Po. and ~o and P"
we obtain the primitive D-cubes of the fault as shown in figure 2.IO(d). The
first cube is derived by intersecting the inputs of the first cubes of ~o and P,
and placing i5 at the output. The second cube is obtained similar ly from the
second cubes of ~o and PI . The inte rsection of the inp uts of ~I and Po is
empty.

For the purpose of generating tests for faults that can be detected by
primary outputs of the circuit. there arc propagation D'-cubes of a gate,
which specify the minimal input co nditions to the gate that arc required to
propagate an error signal on an input (or inputs) to the output of that gate.
Roth (1966)calls these cubes "primitive D-eubes of a logical block ." Pro pagat ion D-eubes can be derived from the singular cover as follows. For each
pair of cubes in the singular cover that have different output values,
intersect them by the following rules:

ono = onx = xno = 0,

l It l = Inx = x n l = I,
xnx = X,
mo o. oru = 0 .
s

36

Logic Testing

~~
AND

(a)

2
a,

0
0

(c)

(b)

Figure1.11
A two-input AND gate and its singular cover and propagation D-cubes

The propagation D-cubes for a two-input AND gate are given in figure
2.11(c). The D-cube DID represents the two cu bes III in the normal circuit
and 010 in the faulty circuit. Thus, the D-cube speci fies an input condition
to propagate an error signal on line I through the gate to line 3.
Propagation D-cubes for multiple input errors can be obtained similarly.
For example, consider the propagation of double error sign als on input
lines 1 and 2 of the AND gate in figure 2.11. When both lines 1 and 2 have
value 1 in the normal circuit and 0 in the faulty circuit, output line 3 will take
1 in the normal circuit and a in the faulty circuit. Thus, the pr opagati on Dcube becomes
1

D D D
This D-cube can be obtained by intersecting the cubes 111 and OOO,just as is
done for single-error propagation D-cubes. Similarly, by intersecting 000
with III we obtain

D fj

15

Test Generation

37

Table 2.1
Coordinate D-intersection

0
1

D
[j

>j;
>j;

1
I
>j;
>j;

>j;
>j;

D
[j

>j;

[j

>j;
>j;
[j
>j;
[j

o~ empty, >j; ~ undefined

For a three-input AND gate, we obtain the following multiple D-cubes:

1
D
D
1
D

D
1
D
D

D
D
D
D

D
1

I
D
D
D
I
D
D

D
1
D

D
D
D

Let C( and j3 be two D-cubes. The Ir-intersection C( (') j3 is defined using the
coordinate D-intersection in table 2.1 and the following rules:
C(

n j3

0 (empty) if any coordinate intersection is 0.

C(

n j3

IjJ (undefined) if any coordinate intersection is 1jJ.

n j3 = the cube formed from the respective coordinate intersections if

neither 1 nor 2 holds.

C(

For example,
OXDlxnXDDll ~ ODDll,
OXDIXnlODXX=0,
OXDlX nOODDX = 1jJ.

The D-intersection is used to generate a sensitized path. For example,

consider the circuit of figure 2.12. To generate a sensitized path from line 1

Logic Testing

38

2
Figure 2.12

to line 5, we D-intersect the rele vant propagation Dvcubes for the two
NAND gates as follows :

D D

D 1

D D

This cube represents a test sen sitizing a path from line [ to line 5.
Now we can specify the D-algorithm, since the necessary preliminaries
have been defined. The flowchart of the D-algorithm is given in figure 2.13.
Each box in the flowchart will be explained in the followin g.
We begin by initializin g a test cube to be completely unspecified. We label
th is test cube 0 (tcO). Then, we select a primiti ve D- cube of the fault in
quest ion . For example, consider the circuit offigure 2.14 a nd the line 6 s-a-l
fault. The primitive D-cube of the fault is
2

36
D

Usually a choice exists , since more than one primiti ve D-cube of the fault
exist. For example, for the line 6 s-a-Ofault we have two primitive D -cubes:
236

In such a case we select a cube a rbitra rily, but we may need during the
execution of the algorithm to return and consider another possible choice.
This is called backtrackin g. Backtracking may have to be iterated un til all
choices have been considered.
In box 3 of figure 2.13 the selected D-cube is D-intersect ed with the test
cube tc'', In our example, the D-intersection of tc? with the pr imitive Dcube of the line 6 s-a-l fault is
2

36
D

Test Generation

39

( Start

Initialize test cube (te)

Select a primi ti ve D-cube

of the fault as c

t
i nconsi stent

I
none

ex; s ts

/ No test
exists

D-intersect c with previous

test cube tc and per-term
implication
consistent

Is there a o or 0
on any primary
output?
no

yes

illJ;)ossible

Backtrack to the
last point a choice
ext sted

none
exists

Figure 2.13
Flowchart for D-algorithm

I line justification
done

Test has been

generated

I)

Select a gate from O-frontier

and a propagation O-cube of
the selected gate as c

Lo gic Testing

40

G4
8

GS
2

12

11

Figure 2.14

Next, the implicat ion is performed. The implication procedure is to specify

all gates, inputs, and outputs that wili be determined uniquely or implied by
other line values in the current test cube. These implied line values can be
determined by intersecting the test cube with the singular cubes for the
associated gate. For example, for an AND gate, if one input has value 0 and
the output is unspecified, then the output of the AND gate will be specified
to be O. If the output value is 1 but all inputs are unspecified, then all input
values will be imp lied to be 1. As a complicated case, the output of an AND
gate is implied to be D (D) if some input(s) is (are) D (D) and all other inputs
are 1. Moreover, if one input value is D and another input value is D, the
output is implied to be O.
An inconsistency occurs when the value implied on a line is d ifferent from
the value that has already been specified on the line. If an inconsistency
occurs, we must backtrack to the last point at which a choice existed, reset
all lines to their values at this point, and start again with the next choice.
The implication operation completely traces such signal determination
both forward and backward through the circuit. If the faulty signal D or 15
has been propagated to a primary output, then line justification (called
consistency operation in Roth 1966) will be performed. This process will be
explained later.
In box 3 of figure 2.13, the process of propagating the faulty signal D or 15
is performed one step further toward primary output. This process is called

Test Generation

41

D-drice. The set of all gates who se ou tput values are unspecified but whose
inpu t has some signa l D or 15 is called the Ir-frontier. For our example, the
D-frontier of the test cube tc? is {G s , G6 } . D-drive first selects a gate in the
D-frontier. Then D-intersection of the current test cube with a propagation
D-cube of the selected gate is perfo rmed. For our example, suppose we
select gate Gs in the D-fron tier and a propagation D-cube

pdc '

15

The D-intersection of tc'' with the propagation D-cube is as follows.

2
tc ?

=X

pdc' = 1
tc ' = tcOnpdc l = 1

10 11

12

If such D-intersection is imp ossib le with all the propagatio n D-cubes of

the selected gate, a new gate in the D-frontier is selected . If D-intersection
cannot be accomplished for any gate in the D-frontier, we backtrack to the
last point at which a choice existed, reset all line to their values at that point,
and begin with the next choice.
After D-d rive, implication for the new test cube is performed. For our
example, the D-intersection of tel with a singular eube (sc] of gate G1 is

tc '
SCi

tel

= tel n SCi

=I
=1
=1

10

II

12

1
1

Moreover, by D-intersecting tel with a singular cube of gate G4 we obtain

2
l

tc 3

sc =
= tel n sc? = 1

5
0

10 11

12

At this point, the D-frontier of tc 3 is {G6 , Ga}. Suppose we select Gs to

execute the D-drive. The D-intersection of tc 3 with a propagation D-cube
of Gs is

42

Logic Testing

pdc' =
tc"

tc' n pdc?

X 0

10 II

12

D 1

The implications for this test cube proceed as follows: The value I on line II
forces value 0 on line 7 since line 3 is fixed at value 1, and the value I on line
10 forces value 0 on line 4 since line 6 is currently value D. When gate G, is
examined for implications it is found to be inconsistent; the NAND gate
cannot have an input value 0 and an output value 0 simultaneously.
Hence, we backtrack to the last point at which a choice existed. In this
case, we reset the text cube to tc', whose D-frontier is {G 6 , G8 l. Since we
selected G8 1ast time, this time we select G6 The D-intersection oftc' with
a propagation D-cube of G6 is

tc' = 1

tc' = tc' n pdc' = 1

9
D

pdc' =

10 11 12

D X

This implication for tc" is as follows: the ones on lines 2 and 4 imply value 0
on line 7, which implies value 1 on line 11. At this point, lines 9 ad 10 are D,
and lines 8 and II are 0, thereby forcing value D on the primary output line
12. Thus we have

2
tc' = 1

678

10 11 12

DOl

Since the faulty signal D has reached the primary output, the line justification (consistency operation) would normally be started. The execution of
D-drive and implication may result in specifying the output of a gate G but
leaving the inputs of G unspecified. This type of output line is called an
unjustified line. It is necessary to specify input values so as to produce the
specified output values. This process is called line justification or consistency operation in box 5 of figure 2.13. Figure 2.15 is the flowchart of the
line-justification procedure. For our example. however, in the test cube te S
all gates with outputs 0 or 1 have their signals already accounted for by their
inputs. Thus, tc' is a test for the fault in question, line 6 s-a-L The test
pattern is T ~ 1111.

Test Generation

43

<i

Is there any line

tc whi ch are not
justified?
yes

S~lect an unjustified line

and a singular cube c to
justify the line

prevt ous

inconsistent
Backtrack to the last point
a choice existed
none
exists

line justification
impossible

Figure 2.15
Line justification (consistency operation)

no

44

Logic Testing

P--

-8

2 _ _...

3 ----1

---J

F igure 2.16

As an illustrat ion oflinej ustification, consider the line 1 s-a-Ofau lt for the
circuit in figure 2.16. After D-d rive we obtain the test cube

jj

8
D

In this test cube, line 7 is unjustified. The singular cover of gate G3 is

46

X
0

Suppose that we select the second singular cube and intersect it with tc' to
justify line 7. The D-intersection is
3

tc' = D
sc" =

= tc' n sc 2 = D

X
X
X

X
0
0

tc 2

8
D
D

At this point, line 6 becomes an unjustified line. Thus, the D-intersection of

te 2 with a singular cube of gate G2 must be performed as follows:

tc 3

= tc 2 n

tc
se 3
sc 3

=D
=
=D

1
1
1

jj

1
1

jj

0
0
0

Since all lines in tc 3 are justified, the test generation for the line 1 s-a-O is
completed.

Test Generation

45

there is more than one choice available at each decision node. Through an
implicit enumeration process, all alternatives at each decision node are
examined until a test is found. Thus, we can see intuitively that the Dalgorithm will derive a test for any logical fault if such a test exists. This has
been proved by Roth (1966).
In the D-algorithm the computation of a test for a fault proceeds in two
stages: first the D-drive from the site of the fault to the primary output, then
consistency or line justification backward to the primary inputs. Roth
(1980) extended the original D-algorithm by mixing D-drive and linejustification processes. In that algorithm, at each stage the D-frontier (gates
with an X on their output and a D or a Don theirinputs) and the Ccfrontier
(gates whose output line is unjustified) are computed. A gate is said to be
"on the frontier" if it is on the D-frontier or the C-frontier. At each step, the
gate on the frontier is selected, whether on the D-frontier or the C-frontier,
that has the smallest distance. (The distance of a gate on the D-frontier is
measured in terms of the number of gates to the primary outputs. Similarly,
the distance of a gate on the C-frontier is measured in terms of the number
of gates to the primary inputs.) In the original D-algorithm, first each gate is
selected from the D-frontier to D-drive, and then after the faulty signal D or
D has reached the primary output each gate from the C-frontier is chosen
successively to perform the consistency operation. Hence, this algorithm
mixing the D-frontier and the C-frontier is an extended version of the 0algorithm.
There is another variation of the D-algorithm. The D-algorithm uses a
calculus based on five values: 0, I, D, D, and X. Cha et al, (1978) reported
another test-generation algorithm for combinational circuits using nine
values: 0, I, D, D, DID, DID, liD, liD, and X. Here, alb(a = 0 or I; b = D or D)
means that the value of the line is not completely specified yet and can be a
or b.
Akers (1976) presented a test-generation algorithm using a 16-value
calculus. Takamatsu et al. (1983) extended the nine-value algorithm of Cha
et al. to an algorithm using ten values: 0, I, D, D, DID, DID, ito, liD, X, and

DID.
2.3 The PODEM Algorithm
A test-generation algorithm called the PODEM (Path Oriented DEcision
Making) algorithm was reported by Goel (198Ia) and shown to be more

46

LogicTesting

c
F
G

Figure 2.17
ECAT circuit

efficient than the D-algorithm. The D-algorithm has been pointed out to
be ineffective for the class of combinational circuits used to implement
error-correction-and-translation (ECA T) functions. ECA T-type circuits
are characterized by consisting of some number of EOR trees with
reconvergence.
Consider figure 2.17, whic h shows an ECAT circuit. Fo r the fau lt H s-a-O,
the D-algorithm may go through the following steps. First, the primitive Dcube of the fault is chosen. In this case, A = B = 1 and H = D. To propagate the faulty signal to the primary output R, D-d rive operations are
performed by D -intersecting the test cube with the propagation D-cubes of
gates along the path. After D -d rive, N = 1, P = D, Q = 1, and R = D may
be obtained. Next, the D-algorithm begins to justify lines Nand Q. However, since lines Nand Q realize the complementary functions with each
other, no justification is possible for the concurrent assignment N = 1 and
Q = 1. Thus, the D-algorithm must enumerate input values exhaustively
until the ab sence of the justification will be confirmed. In this enumeration
process, the D-algorithm creates a decision tree and examines all alternatives at each decision node, as shown in figure 2.18. In thi s figure, the Dalgorithm backtracks tediously many time s until it reaches the assignment
N = 1 and Q = O.
In the D-algorithm, since the assignment of values is allowed to internal
lines, more than one choice is available at each internal line or gate and

Test Generation

47

START

INCONSISTENCY
BACKTRACK
Figure 2.18
Decisio n tree in D-algo rith m

backtracking could occur at each gate. In contrast, the PODEM algorithm

allows assigning values only to primary inputs. The values assigned to
primary inputs are then propagated toward internal lines by the implicati on . Thus, in the PODEM algorithm, ba cktracking can occur only at the
primary inputs. The PODEM algorithm examines all possible primary
input patterns implicitly but exhaustively as tests for a given fault. Of
course, the examination of primary input patterns is terminated as soon as a
test is found. If it is determined that no primary input pattern can be a test,
the fault is undetectable or redundant. Figure 2.19 is the flowchart of the
PODEM algorithm.
For th e H s-a-O fault of the circuit in figure 2.17, the PODEM algorithm
is carried out as follows . First, a binary value is assigned to an unassigned
primary input in order to provide a faulty signal at the site of the fault. (The
procedure for determining a primary input and a value to be assigned will
be described later.) Suppose we assign A = 1. Next, we determine the
implications of all primary inputs. The implication is identical to the
forward implication process in the D- algorithm. Since assignments occur

48

Logic Testing

Te s t

possible with
additional assigned
primary inputs?

maybe

s
untried conblnatlon of
values on assigned ~
primary inputs?

Set untried combination of

values on assigned primary
inputs

Figure 2.19
Flowchart for PODEM algorithm (from Goe11981a; 1981 IEEE)

Test Generation

49

START

c-o

C- 1

\l

Test has
been generated
Figure 2.20
Decisio n tree in PODEM algo rithm

only at th e primary inpu ts, we need not consider the ba ckward implication.
For our example, since A = 1 causes no implication, we again choose a
primary input B and assign B ~ 1 to provide a faulty signa l. Th en, A = 1
and B = I imply H = D.
O nce the faul ty signal has been provided, the objective is to propagate a
D or a D one level of gate closer to a primary out put than before. For our
example, to propagate the val ue D on H to P we assign C = I, which is
followed by the assignmen t E = O. At this point, C = 1 a nd E = 0 imply J
= 1 and L = O. Continuing the assignment and implication. we have F = 0
and G = O. At this point, the implic ations of primary inputs force K = 0, M
= I, N = I, and Q = O. Moreover, H = D and N = 1 imply P = D, an d P
= Dand Q = 0 imply R = D. Thi s com pletes the genera tion of a test for the
fault H s-a-O.
In these proc esses, the PODEM algorit hm creat es a decision tree as
shown in figure 2.20. The deci sion tree is an order ed list of nod es with each

node identifying a curre nt assignment of either a 0 or a I to one prim ary

inpu t, an d the o rdering reflects the seque nce in which the cu rren t assign-

50

LogicTesting

ments were made. The decision tree can be implemented as a LIFO (last in
first out) stack. The above-mentioned example suggests that the PODEM
algorithm is more efficient than the D-algorithm for ECAT-type circuits.
While the D-algorithm backtracks many times to generate a test for the
fault H s-a-O, as shown in figure 2.18, the PODEM algorithm generates the
test without backtracking.
The process of choosing a primary input and a logic value for initial
assignment is performed in two steps:
(1) An initial objective is determined. An objective is defined by a pair (v,s)
where v is a logic value 0 or 1 (called the objective value) and s is an objective
line (the line at which the objective value is desired). If a faulty signal D or i5
has not yet appeared at the site of the fault, the initial objective is directed
toward providing the faulty signal on the associated line. For an s-a-O
(s-a-l) fault on line L, the objective line is L and the objective value is 1 (0).
If a faulty signal has already been provided, the initial objective is directed
toward propagating a D ori5 to a primary output. In this case, PODEM
uses a look-ahead technique called X-path check: It checks whether there is
any path from a gate in the D-frontier to a primary output such that all lines
along the path are at X. In the case when there exists no D-frontier with
such a path, backtracking occurs.
(2) Given the initial objective, a primary input and a logic value are chosen
such that the chosen logic value assigned to the chosen primary input has a
good likelihood of helping to meet the initial objective. This process is
called backtrace by Goel (1981a). The flowchart of the back trace procedure
is shown in figure 2.21. The back trace procedure searches a path from the
objective line backward to a primary input. During the process, the next
objective is chosen from the current objective by the following heuristics:
When the current objective value is such that it can be obtained by setting
anyone input of the gate to a controlling state (for example, 0 for an
AND/NAND gate or 1 for an OR/NOR gate), we choose the input that can
be most easily set. When the current objective value can be obtained only by
setting all inputs of the gate to a noncontrollinqstate (for example, 1 for an
AND/NAND gate or 0 for an OR/NOR gate), we choose the input that is
hardest to set, since an early determination of the inability to set the chosen
input will save the time that would be wasted in attempting to set the
remaining inputs of the gate. In these heuristics (i.e., the choice of the
"easiest to control" input or the "hardest to control" input), several mea-

Test Generation

51

yes

,----<Jine
Found primary input
initial assignemt
is the current
objective value

no (fed by gate G)
Current objectiv
value v and type of gatee;o
driving objectiv
1ine ?

OR/NAND with v:O

ANO/NOR with v ~l
Next objective line is
that input of G which
is at X and is the
hardest to control

no

r--<

Next objective line is

that input of G which
is at X and is the
easiest to control

Is G a NAND/ :::_NOR gate? ~

Next objective value

is the same as the
current objective
velue

OR/"lANO with v-t

AND/NOR with v"O

yes

-,

Next objective value

is the complement of
the current objective
value

Figure 2.21
Flowchart of back trace (from Goel198la; 1981 IEEE)

Logic Testing

52

GS

'1

'2

G
2
'1

'3

"
G]

Figure 2.22

sures of controllability for the inputs of th e gates could be used. Vario us

types of testabil ity measures that include controllability and observability
of internal lines of circuits will be discussed in section 5.1.
Ex ample 2.7 Consider th e circuit of figure 2.22 and the fault G, ou tpu t
s-a- l . T o provid e a faulty signal on the output of 0 " the initial objective is
determined to be (0,0,). Th e back tr ace cau ses the assignment x, = I.
Again, the initial object ive is set to (0,0,), and the back trace causes the
assignment x J = I. By implicat ion, we have G, = D and the D-frontier
{Gs , G_}. To propagate the faulty signal thro ugh gate Gs, the initial objective is set to (0, Gs) a nd th en the backtrace selects th e assignment x, = 1. By
implica tion, we have G, = 0, G. = I, a nd Gs = D, and hence the D-fro ntier
has changed to {G_,G.}. To propagate the fault y signal furthe r through
gate G. , the back trace begins with the initial objective{O, G.) and ends in the
assignme nt x. = O. H owever, by impl ication we ob tain G, = 1, G, = 0, and
G. = 1, and thu s the pro paga tion of the faulty signal through gate G. has
failed. Since no test exists under the assignment x I = x, = x, = 1 an d x.
= 0, we backtrack to the last node a t which a choice existed. This is
illustrated as a decision tree in figure 2.23. The last primar y input assignment was x. ~ 0, and so the alterna tive is assigned this time. Performing
the implica tion of x, = X, ~ x, = X. = 1 at this stage results in G, = G,
= 0, G, ~ D, G. = G, = I, Gs = G_ = D, and G. = D.

53

Test Gen eration

START

TEST HAS
BEE N GENERATED

BACKTRACK
NO TEST

Figure 2.23
Decision tree for example 2.7

2.4 The FAN Algorithm

The PODEM algorithm has indeed succeeded in reducing the occurrences
of backtracks in comparison with the D-algorithm. However, there still
remain many possibilities of reducing the number of backtracks in the
algorithm. This section discusses several techniques to accelerate testgeneration algorithms and presents a new test-generation algorithm: the
fanout-oriented test-generation algorithm FAN, which was developed by
Fujiwara and Shimono (1983a,b).
With respect to the acceleration of test generation, the PODEM algorithm has some defects. Let us consider several effective techniques to
eliminate these disadvantages.
In generating a test, the PODEM algorithm creates a decision tree with
more than one choice available at each decision node. The initial choice is
arbitrary, but it may be necessary during the execution of the algorithm to
return and try another possible choice. In order to accelerate the algorithm,
it is necessary to reduce the number of these backtracks and to shorten the
proce ssing time between backtracks. The reduction of the number of backtracks is particularly important.

54

Logic Testing

In order to reduce the number of backtracks, it is important to find the

nonexistence of the solution as soon as possible. In the "branch and bound"
algorithm, when we find that there exists no solution below the current
node in the decision tree we should backtrack immediately to avoid the
subsequent unnecessary search. The PODEM algorithm lacks careful consideration in this regard.
The following strategies are used in the FAN algorithm.
Strategy 1 In each step of the algorithm, determine as many signal values
as possible that can be uniquely implied.

To do this we take the implication operation that completely traces such

signal determination both forward and backward through the circuit.
Moreover, we carry out the following process.
Strategy 2 Assign a faulty signal D or
implied by the fault in question.

D that is uniquely determined

or

Example 2.8 Consider the circuit of figure 2.24. For the fault L s-a-l, we
assign the value D to the line L and the value 1 to each ofthe inputs J, K, and
E. Then, after the implication, we have a test for the fault without backtracks as shown in figure 2.24(a). On the other hand, in PODEM, the initial
objective (0, L) is determined to set up the faulty signal D to L, and
backtrace starts. As shown in figure 2.24(b), the back trace causes a path
from L backward to a primary input B. The assignment B = implies
L = 1 and fails to provide the faulty signal on L. As seen in this example, by
assigning uniquely determined values we can avoid the unnecessary choice .

Consider the circuit of figure 2.25(a). Supposing that the D-frontier

consists of a single gate, we often have specific paths such that every path
from the site of the D-frontier to a primary output always goes through
those paths. In this example, every path from gate G2 to a primary output
passes through the paths F-R and K-M. In order to propagate the value D
or D to a primary output, we have to propagate the faulty signal along both
F-R and K-M. Therefore, if there exists a test at this point, paths F-R and
K-M should be sensitized. Then we have the assignment C = 1, G = 1,
J = 1, and L = 1 to sensitize them. This partial sensitization, which is
uniquely determined, is called a unique sensitization. In figure 2.25(a), after
the implication of this assignment we have A = 1, B = 0, F = D, and R = D
without backtracking. On the other hand, PODEM sets the initial objec-

55

Test Generation

J=l
B"

K=l

c=o
E=l

(a)

Fault signal assignment and implication

a -----. ,
"-0""

(b)

POOEM

Figure 2.24
Effect of fault signal assignment

.----.~

,~---0

56

Logic Testin g

..

A-l-=~~~ ~:.~.,l

,oQc..
c-- - -LJ

(a)

: '

-"

.' .

Unique sensiti zat i on and implication

-,
....

( bl

POOCH

Fig ure 2.25

Elfect of unique sensitization

live (0, F) to propagate the faulty signal to line F an d performs the backtrace proc edure. !fthe back trace performs along the path as shown in figure
2.25(b), we ha ve the assignment A = 0, which implies J = 0 an d K = L
Th ough no inconsistency appears at this point, an inconsisten cy or the
disap pearance of the D-frontier will occur in the future when the faulty

signal propagat es from H to K . Although the POD EM algorithm can find

such an inconsistency by using X-path check, backtracking from A = to
A = I is unav oidab le.

Strat egy 3 When the D-frontier consists of a single gate, app ly a uniq ue
se nsit ization.

As seen in the above exam ple, in orde r to reduce the numbe r of backtracks it is very effective to find as many uniq uely determined values as we
can in each step of the algori thm. This is because the assignment of the
uniquely det ermined values could decrease the number of possible cho ices.
The execution of the techniques mentioned ab ove may specify the output
of a gate G bu t leave the inputs of G unsp ecified. It is necessary to specify
input values so as to prod uce the specified output values for these unjustified lines. In PO DEM, since all the lines a re first assigned only to the

Test Generation

57

A
B

c
(a)

(b)

PODEM

Illustrative circuit

(cl

Backtracking at head lines

Figure 2.26
Effect or head lines

primary inputs and only the forward implication is performed, unjustified

lines never appear. However, if we employ the techniques mentioned above,
the unjustified lines may appear. Thus, in this case some initial objectives
will be produced simultaneously so as to justify them. We will manage this
by introducing a multiple backtrace procedure that is an extension of the
back trace procedure of PODEM.
When a signal line L is reachable from some fanout point (that is, when
there exists a path from some fanout point forward to L), we say that L is
bound. A signal line that is not bound is said to be free. When a free line L is
adjacent to some bound line, we say that L is a head line. As an example,
consider the circuit of figure 2.26(a). Lines A, B, C, E, F, G, P, and J are all
free, and lines K, L, and M are bound. Among the free lines, J and Hare

58

LogicTesting

head lines ofthe circuit since J and H are adjacent to the bound lines Land
M, respectively.

The back trace procedure in PODEM traces a single path backward to a

primary input. However, it suffices to stop the back trace at a head line for
the following reasons. The subcircuit composed of only free lines and the
associated gates is a fanout-free circuit, since it contains no fanout point.
For fanout-free circuits, line justification can be performed without backtracking. Hence, we can find the values on the primary inputs that justify all
values on the head lines without backtracking. It is sufficient to let the line
justification for head lines wait until the last stage of test generation.
Strategy 4 Stop the backtrace at a head line, and postpone the line
justification for the head line to later.

As an illustration of strategy 4, consider the circuit of figure 2.26(a).

Suppose that we want to set J = 0 but do not yet know that there exists no
test under the condition J = O. In PODEM, the initial objective is set to
(0,1) and the back trace may result in the assignment A = 1. Since the value
of J is not determined yet, PODEM starts the backtrace procedure again
arid gets the assignment B = O. A = I and B = 0 imply J = O. Now, suppose that there exists no test under J = 0, and thus an inconsistency occurs

for the current assignment and PODEM backtracks to change the assignment on B as shown in figure 2.26(b). In this case, if we stop the back trace at
the head line J we can decrease the number of backtracks, as shown in figure
2.26(c).
In performing a unique sensitization, we need to identify the paths that
would be uniquely sensitized. Also, we need to identify all the head lines in
the circuit. These must be identified, and this topological information
should be stored somehow, before the test generation starts. The computation time of these preprocesses can be, however, as small as negligible
compared with the total computation time for test generation.
Strategy 5 Multiple backtracing (concurrent backtracing of more than
one path) is more efficient than back tracing along a single path.

Consider the circuit of figure 2.27. For the objective to set C = 0,

PODEM back traces three times along the same path C-B-A and also along
the same path C-F-E before the value 0 is specified on C by the implication.
Backtracing along a single path wastes time. This could be avoided by
multiple back tracing along plural paths.

59

Test Generation

' \D.....-- _.
B

... :"-

~; ,

.---

<W
'0

-'@ - --- -E

,,

--- -0

Figu re 2.27
R:!c k ,,, ,,c("

In the backtrace of PODEM, an obj ective is defined by a pair of a

objective value and an objective line. An objective that will be used in the
multiple back trace in FAN is defined by the tr iplet

(s, no(s), n, (s))

wher e s is a n objective line, no(s) is the number of times the object value 0 is
required to be set on 5, and n1 (s) is the number of times the o bject value 1 is
requ ired to be set o n s.

Th e computa tion of no(s) and n,(s) will be described lat er. The mu ltiple
backtrace sta rts with mo re than one initial objective. that is, a set of initial
objectives. Beginn ing with the set of initia l object ives, a set of object ives that
appea r during the proced ure is called a set of current objectives. A set of
objectives that will be obtained at head lines iscalled a set of headobjectives.
A set of objectives on fanout points is called a set of fa nout-point objectives.
An initial objectiv e req uired to set 0 to line s is

(5,no(s),n, (s)) ~ (5, 1,0),

and an initial objective requ ired to set 1 to s is

(5, no(5), n,( s)) = (5,0. 1).

Wor king brea dth-first from these initial objectives backward to head
lines, we determine the next obje ctives from the cu rrent objec tives succes-

sively as follows:

Logic Testing

60

(A. l .O)

rs.c .u
8

~. n

( N. l , O)

tc .e.n

(K.O .l )

(H,O,2)

(0 .1 .0)

u .c.i )
(E.0. 1)

(M.O. n

o.e.n

(R.I. O)

Figure 2.28
Comp utation of no(s) and "I (S)

AND gate: Let X be an input that is the easiest to set to O. Then

", (X) =

", (Y)

and for othe r inputs X,

where Y is the output of the AND gate.

OR gate: Let X be an input which is the easiest to set to I. Then

", (X) = " , (Y)

and for other inputs X,

"o(X,) =

no(Y~

" ,(X,) = O.

NOT gate:

"o(X) = " , (Y~

", (X ) = "o(Y~

Fan out point:

where line X fans out to Xl' ... , Xi"

Example 2.9 Figure 2.28 shows an example of the computation of "o(s)
and", (s). The initial objectives are (Q,O, I) and (R, 1,0);that is, Q and Rare

Test Generat ion

61

first required to be set to I and 0, respectively. At the fanout point ll, n, (H)
is obtained by summin g n,(K ) and n,(L).
Figure 2.29 is a flowchart of the multiple-back trace proced ure. Each
curre nt objective is backtraced unt il either a fanout point or a head line is
reached. At that point, the o bjective becomes, respect ively, a fanou t-po int
objective or a head-line objective. After the set of current objectives
becomes empty, the fanout -point objecti ve closest to a primary output is
take n out, if one exists. If the fa nout-point objective satisfies the following
condition, the objective becomes the final objective in the back trace process
and the procedure ends at exit D in fi gure 2.29. T he condition is th at the
fanout point p is not reachable from the site of the fault and both no(p) and
n,(p) are nonzero. In this case, we assign a value [0 if no(p) > n,(p) or I if
no(p) < n,(p)] to the fanout point and perform the implica tions. Th e first
part of the co ndition is necessa ry to guarantee th at the value assigned is
binar y, tha t is, neither D nor D.
In POD EM , the assignment of a binar y value is allowed only to the
prima ry inputs. In th e FAN algorithm, a binary val ue may be assigned to
fanout points as well as to head lines, a nd thus back tracking occurs only a t
fanout points and head lines but not at primary inpu t. Th e reason we assign
a value to a fanout point p is that th ere might exist a great possibility of an
inconsistency when th e objective in backtracing has an inconsistent requir ement such that bot h no(p) and n,(p) are nonzero. To avoid fruitless
compu tat ion, we assign a bina ry value to the fanout point as soo n as the
objective involves a cont radicto ry requirement. T his leads to the early
detection of inconsis tency, which decreases the number of backtracks.
In the multiple backtrace, ifan objective at a fanout point p has
no(p) and n l (p) are nonzero.
stop the backtra ce so as to assign a binary value to the fanout point.
Strategy 6

a con tradicto ry requiremen t, that is. if both

When an objective at a fanout point p has no cont radiction, that is, when
either no(p) or n,(p) is zero, the backtrace continu es from the fanout po int.
If all the objectives a rrive a t head lines, that is, if both sets of curren t
objectives and fanou t-poin t objectives a re empty, then the multi plebacktrace proc edu re terminates at exit C in fi gure 2.29. After this, taki ng
ou t head lines one by one from the set of head object ives, we assign the
relevan t value to the head line and perform the implication .
T he flowchart of the FAN algorithm is given in figure 2.30. Each box in
the fl owchart is explained in the list o n pages 64-66.

Logic Testing

62

l et t l'le set of infttal objectives be

the set of current obJe<: t1ves

<,

. . . . . Is the se t of
current objectives
ty ?

.>--_..,
yes

no

Take out I fanoot -potn t obj ect he p cl oses t

to a pr tlllry

output
yes
yes

Is p reachabl e
frm the faul t 11ne
?

no

yes

8y th e r ules (l)-(3)
detennfne next obfectf Yes and add them to

the set of cur rent

ob ecttves

figure 2.29
Flowcha rt of multiple backt race

Add "0 and ",

to the corresponding fanoutpot nt objectfve

by rule (4)

".

re bot h

'---<"0(') aod ",(,)

nzero 1

Add the current

obj ec t i ve t o
the set of

head obj ect f ves

63

T est Ge neration

Incons t stency

Il'Clltcatt Qn

no

yes

'""

zero

The numer
--(10f gates t" Dfrontier

plural

>----0-1

Is t here an
untried contJtnation
of value s on as sl gr.ed
head 1t nes or fan

ut.potn/

r,....,--~--,
Set uwtrt~
combl tton
of n lueSi

and set back-

trace flag

F igure 2.30
Flowcha rt of FAN algo rithm

Detennlne a
ftnal objectfve to
as si gn a
val ue

Asstgn a value to the

final object1ve line

64

Logic Testing

Assignment of fault y signa l: In box 1, a uniquely determined fau lty signal

D o r jj is assigned.
Backtrace flag: Th e multiple backtrace procedure of figure 2.29 has two
ent ries. One entry is (A), where the multiple backtrace sta rts from a set of
initial objectives, an d the other entry is (B), where the multi ple back trace
starts with a fan out-p oint objective to continue the last multiple backtrace
that terminated at a fanout point. Th e back trace flag is used to distinguish
the above two modes.
Implicati on : We determine as ma ny values as possible that can be
uniqu ely impl ied. To do this we take the implicat ion o pera tion that co mpletely traces such signal det ermination both forward and backward
throu gh the circ uit. In PODEM , since all the values are assigned only to the
pr imary inputs and only forwa rd implica tion is performed, unjustified lines
never appear. However, in FA N, since both forwa rd and backward implica tions are performe d, unjustified lines might appear. T hus, so as to justify
those lines, the mul tiple bac ktrace is necessary not on ly to propagate the
faulty signa l but a lso to justify unjustified lines.
Continu ati on check for mult iple back trace: In box 4, we check whether it
is meaningful to continue the backtr ace or not. We con sider that it is not
meaningful to continue the back tr ace if the last objective was to propagate
D or fj and the Dvfrontier has changed, or if the last objective was to justify
unjustified lines and all the unjustified lines have been justified. Wh en it is
not mean ingful to con tinu e, the back trace flag is set so as to sta rt the
multiple backtrace with new initial objec tives aga in.
Unique sensitiza tio n: The un ique sensitization is perfor med in the manner mentioned a bove (see figure 2.25). Althou gh the unique sensitization
migh t lea ve some lines unju stified, those lines will be ju stified by the
multiple backtrace.
D etermination of a fina l objec tive: The detailed flowchar t of box 6 is
described in figure 2.31. By using the multiple backtrace procedure, we
determine a fina l objective; that is, we choose a value and a line such that the
chosen value assig ned to the chosen line has a good likelihood of helpin g to
meet the initial objectives.
Backtracking: Th e decision tree is identi cal to that of POD EM (that is, an
ordered list of nodes with each nod e identifying a current assignment of
either 0 or 1 to one head line or one fanout point), and the ordering reflects
the sequence in which the cur rent assignm ents were made. A node is flagged
if the initial assignm ent has been rejected and the alternative is being tried.

Test Generat ion

65

yes
~ se t bad:t race fla g and let
a11 t he sets of obj ectt ves be

empt y

1M se
of fanout -pOint

In

no

eefeet fves
_

t y?

yes

Let all the Imjust tfted

1t nes be the set of
tntth l objecttves

no

faul ty S1g"il
l"OPl gl ted to a
pdllllry output
1

Add II gate in 0-

yes

........

frontier to the
set of init1a1
object ives

Multiple backtrece
from the set of
1nt ti II1 obfectt yes

,.
'"

yes

Figure 2..31

or fina l object ive

Hul tt ple backt race

l et the h nout- pO tn t obj ective

be f tNl obj~ ttve to assi gn a val ue

Deter mina tion

Multiple backtnce
from a fanout-pot nt
objective

66

Xl

Logic Testing

-+---4>--+---------1--

x2
x

x4

-+-_--+-------IL...-

Figure 2.32

When both assignment choices at a node are rejected, then it is removed and
the predecessor node's current assignment is rejected. The backtracking
done by PODEM does not require saving and restoring of status because at
each point the status could be revived only by forward implications of all
primary inputs. The same backtracking can be done in FAN, which does
not require saving and restoring of status, by implications of all associated
head lines and fanout points. However, to avoid the unnecessary repetition

of implications, FAN uses saving and restoring of status to some extent.

Line justification of free lines: We can find the values on the primary
inputs that justify all the values on the head lines without backtracking.
This can be done by an operation identical to the consistency operation of
the D-algorithm.
To compare the FAN algorithm with the D-algorithm and
the PODEM algorithm, consider again the Schneider circuit (figure 2.32).
For the fault G, output s-a-l. FAN first assigns x, ~ x, = I and G, = D
Example 2.10

uniquely. At this point, the unique sensitization causes the assignment G4

= G, = 1. To justify the unjustified output lines of gates G. and G" the

initial objectives are set to (G.,0, I) and (G" 0, I). By the multiple back trace,
we have the final objectives (Xl' 0, I) and (x., 0, I). Selecting the first assignment Xl = I, we obtain GI = 0, G. = I, and G, = D by implication. Successively, the second assignment x. = I implies G, = 0, G6 = D, G, ~ I,
and G8 = D. Consequently, FAN has generated a test for the fault in

Test Generation

67

question without backtracking, whereas the D-algorithm and the PODEM

backtrack in generating the test.
Three programs-SPS (single-path sensitization), PODEM, and FAN
test-generation algorithms-were implemented in FORTRAN on an NEC
System ACOS-IOOO (15 MIPS) (Fujiwara and Shimono 1983a,b). These
programs were applied to a number of combinational circuits, shown in
table 2.2.The results are given in tables 2.3,2.4,and 2.5.To obtain the data,
three programs were executed to generate a test for each stuck-at fault. The

number of times a backtrack occurs during the generation of each test

pattern was calculated by the programs, and the average number of backtracks is shown in table 2.3. Since PODEM and FAN are complete algorithms, given enough time, both will generate tests for each testable fault.
However, being limited in computing time, the programs discontinued test
generation for those fault for which the number of backtracks exceeded
1,000. (Such faults are called aborted faults.) The results shown in tables 2.3
and 2.4demonstrate that, though PODEM is faster than SPS, FAN is more
efficient and faster than PODEM and SPS. The average number of backtracks in FAN is much smaller than the number in POD EM and SPS.
An automatic test-generation system composed of the FAN and the
concurrent fault simulation was also reported by Fujiwara and Shimono
(1983a,b). In this system, the fault simulator is used after each test pattern is
generated to find what other faults are detected by the tests. The results of
this system are given in table 2.5.
2.5 Test Generation for Sequential Circuits
For sequential circuits, there are few test-generation algorithms that are of
practical significance. Known procedures that are good for use are the
extended D-algorithm ofKubo (1968) and Putzolu and Roth (1971) and the
nine-valued model ofMuth (1976). This section describes these algorithms.
We consider synchronous sequential circuits and then asynchronous sequential circuits.
A synchronous sequential circuit M can be modeled as shown in figure

2.33. Cutting the feedback loops where the clocked flip-flops are, we can
form the iterative combinational circuit M P of figure 2.34. The combinational circuits C(i), where i = I, ... , p, are all identical to the combinational portion C of the original sequential circuit M. In this transfer-

Table 2.2
Characteristics of circ uits
Circui t
1 Error-correcti ng
circuit
2 Arithmetic logic
unit (ALU)
3 ALU
4 ALU a nd
selector
5 ALU

Numbcrof
gates

Numbe r of
lines

Numbe r of
inputs

Number of
outputs

718

1,925

33

25

1,003

2,782

233

140

1,456
2,002

3,572
5,429

50
178

22
123

2,982

7,618

207

108

Source: F ujiwa ra a nd Sh imono 1983a, b. Copyright

1983 IEEE.

Test Generation

69

Table 2.3

Normalized computing time and average numberof backtracks

Normalized computing time
Average number of backt racks

(sec)

Circuit

SPS

PO D EM

FA N

SPS

PODEM

FAN

1
2
3
4

5.2
4.5
14.5

1.3
3.6
5.6
1.9
4.8

31.2
51.7
189.7
1.5
38.1

4.9
42.3
6 1.9
5.0
53.0

1.2
15.2
0.6
0.2
23.2

3.1
3.4

1
1
1

Sou rce: Fujiwara an d Shimono 1983a, b. Copyright

1983 IEEE.

marion , the clocked flip-flops of 111 a re modeled as co mbinational element s

F(i ), where i = I, .. . , p. These are referred to as pseudo fl ip-flops. Fo r
examp le, the pseud o flip-flops cor respo nding to a D flip-flop and an SR flipflop will be represented as shown in figure 2.35. In this figure the pseudo SR
flip-flop has two excitation input s Sand R plus an additiona l input representing the present state of the flip-flop.
In figure 2.34, C(i) and F(i) correspond to time frame i. Suppose tha t a n
input sequence x(I) , x(2), ... , x(p) is applied to the sequential circuit 111 of
figure 2.33 in initial sta te y(l) and that 111 genera tes the outpu t sequence
z(1~ z(2), .. ., zIp) with the sta te seque nce y(I), y(2), .. ., y(p + 1). Then, the
iter ative combinational circuit 111' obt ained from the sequential circuit M
will respond as shown in figur e 2.34. The time-domain response of the
sequentia l circuit is mapped int o a space-domain response of th e iterat ive
combination al circuit. In this sense, the iterative comb inational circuit At P
is logically equivalent to the sequential circui t M whose input/output
response is of length p.

Suppose that we wish to find a test sequence of length p for a single fault
in a sequential circuit M . For this pu rpose we cons truct the itera tive com binational circuit with p identica l comb inat ional circuit s. A test sequence of
length p will be mapped into the test pattern as shown in figure 2.36. In this
figure, each cell M(i) consists of th e combinati ona l po rtion C a nd pseud o
flip-flops of the original sequential circuit M . States y(i) and y(i + I) are
called pseudo-inputs and pseudo-outputs of cell M(i ), respectively. The
iterative circuit AlP is combinational; thus, most of the test-generatio n
algorithms for comb inational circuits ca n be ap plied to this mod el. However, we ha ve to note the following points.

Ta ble 2.4
Test coverage
Percentage of aborted faul ts

Percentage of tested faults

Circuit

SPS

pn OEM

99.04
9 US
66.25
98.77
94.73

99.20
94.25
92.53
98.75
94.38

2
3
4

FAN

SPS

PODEM

FA N

SP

99.52
95.49
96.00
98.90
96.81

0.48
4.70
16.25
0.07
3.54

0.48
3.49
5.05
0.26
4.79

0.11
1.38
0
0
2.17

Source: Fujiwara and Shimono 1983a, b. Copyright

19S3 IEEE.

Tab[e 2.5

Experimental results from FAN with concurrent simul ator

Compu ting time (sec)
Circuit

FAN

Concurrent
simulator

I
2
3
4

3.8

4.6

34.6
7.4
4.0

76.5

3.7
9.5
10.5
18.9

So urce: F ujiwa ra and Shimono 1983a , b. Copyright

Tota l
8.4
38.3
16.9
14.5
95.4

1983 IEEE.

Pe rcentage
of tested
fault s
99.52
95.74
96.00
98.90
98.20

72

Logic Testing

cloc k
Flgure 2.33
Synch rono us seq uentia l circui t

( Il l

)'l lJ

y I p)

uu

,
,

t ime fraone 2

,....
,

-,,,

time f rame p

Figure 2.J.t
Co rresponding iterat ive com bina tio nal circuit M"

present
5 t e te

:...
TCI

..

, - - - - - - "1

..

... . . -. . .. _..

( 4)

Pse udo 0 f li p-fl o p

fi gure 2.35
Pseud o I li p-flc ps

..,.- _. _

..

_-- ----.

R
L. _ _

(b)

Pseu do SR fl f p fl cp

.1

73

Test Generation

xO)

y(1)

x(p)

x(2)

y(2)
M(1)

yep)

M(2)

'0)

M(p)

,(2)

zIp)

Figure 2.36

0,1/0

1/0'0

=D*-

s-a-O

(a)

0'0/1

0/0

DJ*s-a-O

(b)

Figure 2.37

A single fault J in M corresponds to the multiple fault f' consisting of the

same fault J in every cell M(i) of the iterative circuit MP. In a combinational
circuit with a multiple fault, a faulty signal D or D may be propagated onto a
line that is itselffaulty. Figure 2.37 shows the signal that results when a D or
a Dpropagates onto a faulty line. For example, if a D propagates onto a line
that is s-a-O, then the line has value 1 in the normal circuit and value 0 in the
faulty circuit, and thus the resultant signal on the line is D. This is shown in
figure 2.37(a). If a D propagates onto a faulty line that is s-a-O, both the
normal and the faulty circuit will have value 0 on the line; that is, the effects
of the multiple faults cancel each other. This is illustrated in figure 2.37(b).
In general, the initial state of M is unknown, and hence the pseudo-inputs
y(l) of MP are unknown. Thus, their values must remain at the indeterminate X.
The distinction between the outputs from the test for normal and faulty
circuits must appear on at least one of the primary outputs z(I), ... , z(p);
that is, at least one of these primary outputs must have the value D or D. If
no test is found, we have to increment p by 1 and repeat generating a test for
MP.
The algorithm for generating a test for the multiple fault f' in MP can be

74

Logic Testing

obtained by modifying the con bi national D -al go rit hm, with speci al attention to pse ud o-inputs and fault mu ltiplicity, as ind ica ted abo ve. T he proced ure is as follow s.

The Extended Dcalgor tthm for Synchronous Circuits

Step I D ecide th e maximum value P for p, i.e., P is the maximum number
of time frames allowed for test genera tion .
Step 2 Select an initial value fo r p and con struct the iterative combinational circuit At P of figure 2.36.
Step 3 By choosing the time fram e q from which t he D -drive must be
organized , ap ply the combinationa l D- algorit hm (sectio n 2.2) to find a test
for the mu ltiple fa ul t JP in MP, ensuring that the pseudo-inp ut s of fra m e 1
reta in only X valu es, i.e., y(1 ) = (X, ... , X). If a te st is found, exit; o therwise,
continue.

Step 4 If pos sible, increment p by I and return to step 3; o therwise, exit

with no tes t,
Ex ample 2.11 C on sid er t he synchronous sequen tial circuit of figure 2.38
and th e fault a s-a - I on G, . We firs t select p = 3 and construc t At' as sho wn
in figure 2.39(a). C hoosing the tim e frame 2, we begin the D -d rive from the
site ofthefa ult in At(2). First we set y,( 2) = 0 to provide a D on line u. Since
it is im pos sible to p ropaga te the faulty signal on to t he primary o utp ut z(2),
we try to pro pagate it towa rd z(3). Set ting x(2) = I, y, (2) = 0, and x(3) = 1
allo ws the fa ult y signal D to pr opaga te o nto z(3), and the D -drive is
su ccessfully completed. At this point, since y, (2) = 0 and y, (2) = 0 are
unjustified, the lin e j usti fica tio n begins. Ho wever, we cann ot set y,(2)
~ y,(2) = 0, ensuring y, (l) ~ y, (1 ) = X . Whenever a n incon sistency is
di scover ed , the pr ocess mu st back t rack to the last d ecision point and make

an alternative selection. In this case there are no alternatives, and hence we

inc remen t the number of frames bv I, i.e., D = 4. F or the iterative combi-

national circuit /'v1 4 , we can find a test successfully, as shown in figure

2.39(b).
When the logi c circuit is combinational, the D -a lgori thm gu arantees to

generate a test if one exists. However. for sequential circuits, the extended
D -al gorithm ment ioned abo ve d oes not gu arantee a test seq uence for a
fault even if one exist s. C onsider t he circ uit of figure 2.40. Suppose we wish
t o find a n inp ut co mbin ati on (x" x , ) th at forc es J = 1 by ret ain ing y = X .

75

Test Generation

Figure 2.38
Synchron ous circuit

.m-e

z(l)-fi"

K( 2)

" ll )

(. )

M(l)

M( 3)

M{ 2)

Ib)

Figun 2.39
Itera tive combinat iona l circuits

M( 4 )

76

Logic Testing

Xl

a
b

Figure 2.40

First,f = 1 requires c = 1 or d = 1. Ifc = 1 is chosen, then it implies Xl = 1

and a = 1, and thus y = 1. If d = 1 is chosen, then it causes Xl = 1, b = 1,
and y = O. Both cases contradict y = X, and this seems to imply that no
input combination forces f = 1 by ensuring y = X. However, f{X l,X2, y)
= Xl Y + X 2 Y and 1(1, 1, y) = y + Y = 1. Thus, 1 has the value 1 independent of the value of y if Xl = X2 = 1.
If the circuit M has a synchronizi ng sequence (an input sequence that
when applied to M results in a unique final state independent of the initial
state), then the above problem may be settled. However, the extended 0algorithm still cannot guarantee the generation of a test sequence when one
exists. For example, consider the circuit offigure 2.41(a) and the fault d s-a-l.
The extended D-algorithm fails to generate a test sequence for the fault, as
shown in figure 2.41(b). In this figure, trying line justification ends with the
contradiction that d( 1) must be 0 while d is stuck-at-I because of the fault.
Further, it can be shown that there is no way to generate a test for the
iterative combinational circuit, even if more than two copies of the circuit
are consid ered. However, we can find a test sequence for the fault if we apply
a test-generation procedure using a nine-value model.
A nine-value circuit model for test generation of seq uential circuits was
presented by Muth (1976). The nine-value algorithm guarantees the generation of a test sequence, if one exists, for every stuck-at fault in a synchronous sequential circuit having a synchronizing sequence.
The nine values of the model are derived by distinguishing between a
normal and a faulty circuit. Each of the nine values Il j , where i = 1, ... ,9, is
defined by an ordered pair of binary values:

where a, is a value in the normal circuit, b j is a value in the faulty circuit, and
a, and b, are 0, 1, or X (unspecified binary value). Values 0/0, 1/1, 1/0, and 0/1

Test Generation

c o. t r ~ d i c t lo n

77

,.)

H~ )'~~~
. 111
bil l -

f 12 1_0

'0'
Flgure 2.41
Test generation for fault d s-a- l

are fully specified and identical to the value s 0, 1, D, and D, respectively, of

th e D-algorithm. Valu e X/ X is identical to X, which is an unspecified value
in both the no rmal a nd the faulty circuit. If a bina ry value need be sp ecified
o n ly in the nor mal circui t, we ha ve O/X a nd l/X ; if it need be specified o n ly
in the faulty circuit, we have X/O a nd X/I. The calculus for th e nin e- val ue
mode l is as sho wn in ta ble 2.6. F o r exam ple, co nsider a th ree-input AN D
gat e. If o ne in pu t has I/O = D and the other two inputs ha ve I / X , then t he
o utput o f the AN D gate will have I/O = D.
Th e test-generation proced ure based o n the nine-val ue model is simi lar
to that of the ex tended D-al gorith m. To derive a test sequence for a fault f
in a synch ro nous seq uenti al circuit M , we co nst ru ct the corresponding
iterative combinational circuit ""1 P and then try to generate a test for the
multiple fault l' in the iterative com bination al circuit M ".
A pri mitive Dvcube ofa fault in the nine -value mod el is defined as a cube
th at specifies a minimal inp ut condition to the ga te, requi red to pr ovide a

78

Logic Testi ng

Table 2.6
Calculus of nine values

AND

a
a/x
fj

x/O
x
x/I

a
a
a
a
a

a/x
a

x/a

x/I

I/x

O/x

a/x

0
0

O/x

0
0

O/x

O/x

a/x

a/x

fj

a/x

fj

a/x

fj

O/x
O/x

O/x

x/a
x
x

x/a

x/O
x
x/I

D
D

x
x

x
x/I
x/a
x
x/l

x/O
x
x

fj

x/O
x/O
x/O
x/O
x/O
x/O

a
x/a
x/a
x/a

I/x
I/x

I/x
I

O/x

jj

x/O

x/I

I/x

x/O
x
x/I
x/a
x
x/I

x/I
x/I
x/I
x/I

x/t

I/x
I

l/x
I

I/x
I/x
I
l/x
l/x
I
l/x
I/x

x
x
x/I
x
x
x/I
I/x
l/x
I

jj

l/x
I

O/x
O/x

OR

a
a/x

O/x
a/x

fj

a/x
jj

jj

jj

fj

x/O
x
x/I

x/O
x
x/I

O/x
jj

x/a

I/x
I

l/x

l/x

x
x
x/I
I/x
I/x

x/I
x/I
x/I
I
I
I

a/x

t5

x/O

x/ I

l/x

!/x

x/ I

x/a

fj

a/x

NOT

l/x

x/I
I
I

faulty signa l on its out put. Fo r examp le, consider a th ree-in put AND ga te
and th e s-a -O fault on th e output. To pro vid e th e faulty signa l D on the
o utpu t, all th e inp ut s of the ga te need to tak e value I only in the normal
circuit. Hence, t he prim itive D -cube of the fa ult is

l /X

I jX

l /X

In th e D -al gorithm, the primitive D -cub e of the fau lt is

2

79

Test Generat ion

This cube 111D includes the unnecessary condition th at all the inputs of the
gate take the value 1 even in the faulty circuit. In the nine-value model we can
describe the minimal conditions precisely, since behaviors of the normal
and the fa ulty circuit are distinguished by using nine values. F or the s-a-l
fault on input 1 of the three-input AND gate, the primitive D-cube is
2
O/X X /I

X /I

fj

For the s-a-l fault on the output of the AND gate, the pr imitive D-cubes a re

a/x X

Q/X

D
fj

o/x

A propagation D-cube ofa gate in the nine-value mod el is similar to that

of the D-alg orithm. Suppose that a faulty signal D or jj is o n input line 1 ofa
three-input AND gate. Then the propagation D-cubes for this fault are

34
- _2
..
D

l/X l/X D

fj

X /I

X /I

In the D-algorithm th e corresponding propagation D-cubes are

234
DID

jj

Similarly to the D- al gorithm, after the D-drive, line justification or

consi stency operation is performed. For example, consider a three-input
AND gate whose inputs are all unspecified but whose output has value a/x.
Line justification will choose one of the following cubes to justify the
required value a/x .

234
Q/X X

Q/X

Q/X X

ci x

o/x

Q/X

Logic Testing

80

When the inputs are all unspecified but the output has value X/I, line
justification assigns the following cube.

234

X/I

X/I

X/I

X/I

In circuits with reconvergent fanout, line justification may result in two

or more values being required simultaneously at a branching point. In such
cases, the consistency of the required values has to be checked by means of
an intersection operation in the nine-value model. Nine-value intersection
is defined by the intersection of the set of binary values for the normal and
the faulty circuit. If either of these intersections is empty, the required values
are inconsistent. For example, suppose that a line L fans out to lines M and
N and values M = I/X and N = X/O are required at the same time. Binary
intersection is nonempty in both the normal and the faulty circuit, and we
have L = I/O, that is, L = D.
Line justification always ends at the primary inputs of the circuit, where
values O/X and X /0 are replaced by 0, and I/X and X/I by L Values D and
i5 must not occur at primary inputs unless faults in these inputs are to be
tested. Value D is replaced by I, and i5 by O. Having thus completed line
justification, we have test patterns consisting of values 0, I, and X .
Example 2.12

Consider the circuit of figure 2.41(a) and the fault d s-a-l. As

previously stated, the extended D-algorithm cannot find a test sequence for
this fault . We will now try to find a test sequence for the fault by the
procedure using the nine-value model. Here, we consider two copies of the
circuit, that is, the iterative combinational circuit M P with p = 2. The first
step in test generation is to assign the value X/I to the corresponding lines,
d(l) and d(2), since in the faulty circuit both lines d will take the value 1.
Arbitrarily, we start the D-drive at the second copy M(2) of the circuit. The
primitive D-cube of the fault is a(2) = I/X and d(2) = 0/1. Driving the
faulty signal from d(2) to the output z(2) through f(2) requires e(2) = O/X
and k(2) = I/X. Line justification of these will yield the values shown in
figure 2.42. At this point, the value I/X is assigned to the pseudo-input y(2).
Thus the line justification is continued backward into M(1) along the lines
k(1), 11(1), g( 1),and d(I). In this case, as shown in figure 2.42, the intersection
of X/I and O/X on line d(1) is performed successfully, and thus a test has
been derived.
Most of the advantages of the nine-value model are due to the higher

Test Generation

81

yO I=X

'/I
a(2)=1 X

b(2)=l/X
c(2)=1/X

z{T)

D/X

Figure 2.42
Test generation for fault d s-a-I using nine-value model

degree offreedom afforded by the partly specified values O/X, I/X, X/O, and
X/I as compared with the values 0, I, D, and fj of the D-algorithm. The Dalgorithm does nol take into accounl correclly the repeated effects offaults
on the internal state of a circuit; the test-generation procedure using the
nine-value model does take them into account precisely. Moreover, the Ddrive along any path using the nine-value model simultaneously takes
account of all the possibilities of sensitizing this path as part of a multiplepath sensitization. Thus, at a fanout point having a fanout of N, at most N
attempts have to be made at sensitizing a path. However, in the 0algorithm it may be necessary to try all 2" - I possible selections of one or
more of the N branches to sensitize all possible single or multiple paths.
Although the nine-value model has these advantages, it also has some
disadvantages. One is the natural increase of computing time due to the
greater complexity of its calculus in comparison with that of the five-value
model of the D-algorithm.
Up to now we have considered the generation of tests for synchronous
sequential circuits only. Test generation is much more difficult for asynchronous circuits than for synchronous circuits because of races, hazards, or
oscillations. We will next briefly consider asynchronous circuits. In an
approach that is analogous to that taken for synchronous circuits, an
iterative combinational circuit model will be adopted for asynchronous
circuits in order to utilize test-generation procedures for combinational
circuits. Test generation for asynchronous circuits is performed in two
steps. First, a potential test is generated for the multiple fault in the iterative
combinational circuit that corresponds to a given fault in the original
asynchronous circuit. This potential test is then simulated for both the
normal and the faulty circuit to check its validity. In the real asynchronous
circuit the potential test might be invalid because of races, hazards, or
oscillations.

82

Logic Testing

z
C
y

(al

x \l)

y ( l)

x( 2)

x ( p)

C(l)

C(2)

C(p)

z(l}

z( 2)

z (pl

t----y(p)

(b)

Figure 2.43
Asynchronous circuit

Figure 2.43(a} shows a model of an asynchronous circuit M, and figure

2.43(b) shows the corresponding iterative combinati onal circuit M.". For
the circuit MP and a corresponding multiple fault JP, the extended Dalgorithm or the test-gene ration algorithm based on the nine-value model
might be used to gen erate a test. Havin g obtained a potential test, we
perform a simulation to check that the test is valid. For the test simul ation, a
three-value simulator of Eichelberger (1965), or other multivalue simulators for hazard detection, such as the mod el of Fantauzzi (1974), might be
used by simulating the test on both the normal and the faulty circuit and
comparing the values on prim ar y outputs. Eichelberger's approach first
modifies the seq uence of patterns by inserting between each pair of adjacent
patterns a new pattern having X values corresponding to changing variabIes and values as in the adjacent patterns for the nonchanging variables.
For example, consider a circuit with three inputs x t, X2' and X 3 and the
input sequence

83

Test Generation

XI

X2

0
0

X3

0
1
0

Then, the modified input sequence is

Xl

X2

X3

This modified inpu t seq uence is then simulated using three -value logic. The
simulator due to Eichelberger (1965) will detect any possible race, hazard,
or oscilla tion.

Fault Simulation

Fault simulation oflogic circuits is an important part of the test-generation

process. It is used for the purpose of generating fault dictionaries and for
verifying the adequacy of tests (test patterns or test sequences) intended to
detect and locate logic faults. Moreover, fault simulation is often necessary
to determine the fault coverage of a given test, that is, to find all the faults
detected by the test.
Fault simulation is also employed for analyzing the operation of a circuit
under various fault conditions in order to detect circuit behavior not
considered by the designer. For example, faults can create races and hazards that did not exist in the fault-free circuit, or change a combinational
circuit into a seq uential one. To analyze these faults it is desirable to employ
timing analysis of circuits, which requires the simulation of timing (delay)
faults.
This chapter introduces three typical methods offault simulation: parallel, deductive, and concurrent fault simulation. These methods are compared, and concurrent fault simulation is shown to be the most effective.
For very large circuits, these fault-simulation methods based on software
are all very time-consuming and costly. A new approach to this problem
has been reported. The proposed solution involves hardware simulatorsspecial-purpose, highly parallel, programmable computers, with a capacity
and speed hundreds or thousands of times that of existing software simulators. In section 3.4 we consider these hardware simulators.

3.1 Simulation Methodology

In general, simulators can be separated into two classes: compiler-driven
simulators and table-driven event-directed simulators. In table-driven simulators, the description of the logic circuit to be simulated is stored in tables
in the host computer. The tables are accessed by the simulation program as
necessary. The simulation program is circuit-independent, but a new set of
tables is required for each distinct circuit to be simulated. In contrast,
compiler-driven simulators have the circuit implicitly described in the
program, as compiled code.
The first step in compiler-driven simulation is leoelizinq. We define the
logic level of element i by level(i) recursively as follows:
level (i) = 0 for all primary input lines and feedback lines.
level[r] = n + 1 if level (j) < n + 1 for all immediate predecessors j of i;
level(k) = n for some immediate predecessor k of i.

Fault Simulation

85

If circuit elements (gates or flip-flops) are simulated in the order of

ascending value of their logic level, the logic value of each element can be
determined properly, since whenever an element at logic level k is evaluated
the logic value of each of its inputs has already been evaluated. After
levelizing, the compiler-driven simulation translates the description of the
circuit into a machine-executable code, such as an assembly-language
program. Simulation of a logic circuit is performed by executing the compiled code in the order of ascending value of logic level.
Compiler-driven simulators are usually employed for simulating logic
circuits in a zero-delay model, and hence they handle only synchronous
logic circuits, where race and hazard conditions are often ignored. A
more accurate simulation is obtained with table-driven event-directed
simulators.
A table-driven event-directed simulator models the dynamic behavior of
the simulated circuit, updating its computations at successive, uniform
intervals of simulated time, 1 T, 2T, 3 T, . .. , where the time interval Tis
chosen equal to the average gate delay . An event is a change in value of a
signal line. The output of a logic elem ent will change value only when one or
more of its inputs have changed in the preceding tim e interval. Hence, an
element need be simulated only when an event occurs at one of its inputs.
When an event occurs, every element to which this line fans out has the
possibility of a new event. We need only to simulate those potentially active
elements that are successors of a signal line where an event occurred. The
technique based on this observation is called event-directed (selecti ve trace)
simulation. Deductive and concurrent fault simulators are table-driven
event-directed simulators. In contrast, almost all compiler-driven simulators are parallel fault simulators (although parallel fault simulation can
also be carried out by table-driven event-directed simulators).

3.2 Parallel Fault Simulation

A computer has several bit-oriented instructions, including logical instructions such as the AND, OR, Exclusive OR, and NOT operations. During
execution of instructions from this group the several bits of a single computer word are manipulated identically and independently. The AND, OR,
and Exclusive OR instructions each operate on a pair of operands; the ith
bits of each operand are combined to give the ith bit of the result. For

86

Logic Testing

example, the AND operation of 4-bit words is processed as follows:

[lOlOJ .AN D . [1100J = [1000J
Each ith bit of two words is simultaneously ANDed, and the resultant value
is stored in the ith bit of the third word. Several advantages accrue from
adopting a bit-oriented view of the contents of computer words instead of
the one-symbol-per-word view. One advantage is that memory can be used
with great efficiency ifmany items per word, instead of just one, are stored.
Another advantage is that parallel computation is possible because there
are instructions that operate on all the bits of a word concurrently.
Fault simulation based on this parallel process of bit-oriented operations
is called parallel fault simulation. Parallel fault simulation is an old method,
and it has been widely accepted in automated test-generation systems.
Representative of this approach are the Sequential Analyzer (Seshu 1965),
the IBM simulator used in the design ofthe Saturn computer (Hardie and
Suhocki 1967), and the TEGAS simulator (Szygenda et al. 1970).
In parallel fault simulation, if a word or a string has n bits, then n different
problems can be processed in parallel.lfwe want to simulate a circuit for m
different faults, then rm/nl passes must be made with n faults being simulated during each pass, when x 1 is the smallest integer equal to or greater
than x.
In the fault simulation, a logical effect of a fault is injected into the
computation of the faulted element. This procedure is called fault injection.
Two masks mask(S) and fvalue(S) associated with each signal line S are
used to inject faults. Each fault injected on S corresponds to a unique bit
position i in mask(S) and fvalue(S). This bit position must be different from
the bit positions in the corresponding masks of any other remaining n - 1
faults being simulated in parallel with the fault on S. These masks are
defined as follows: mask (S)i = 1 if a fault exists on the signal line S when the
ith bit of the computer word is simulated, masL(S); = 0 otherwise;
fvaluefS], = 1 if the fault on S is stuck-at-I, fvalue(S); = 0 if the fault on S is
stuck-at-O, where the subscript i denotes the bit position.
These two masks are used to inject faults into each bit of the word S, and
the masked word Sf is formed as follows (figure 3.1):

Sf = S mask(S)

+ mask(S)' fvalue(S)

where ., +, and mean bit-oriented logical operations AND, OR, and

NOT, respectively.

Fa ult Simulat ion

87

r- --,
,

M I
A
S :11 ----

$'
_

'

oJ

Figure 3.1
Model of fault injection

Bit Positio n

Faul t

Line

Mask

Fva1ue

[ 01000 ]
[ 00100 ]
[ 00011 ]

[ 00000 ]
[ 00100 ]
[ 00001 ]

Fault - Fr ee

A 5-a-0

B s-a- 1

C s-a -O

C s -a- 1

(b)

(al
A=[l1l1l]

A'=[10111]

8=[00000] ,,... . ..:

8' =[001 00]

~C=[11011J

---~

(cl
Figure 3.2
Parallel fau lt simulation

The masks used for fault injectio n a re gene rated during the preprocessing
of th e circ uit for fault simulatio n. Except for th e overh ead required to
generate the mask s an d carry o uut fault injection, n faults can be pro cessed
almost as rapidly as one fault.
Consider a two -input N AND gate and the four faults associated with the
gate (figure 3.2). The four fault s a re specified in figure 3.2(a), a nd the values
of th e ma sks associat ed with signal lines A, B, and C are defined as shown in
figure 3.2(b). For exa mple, mask (B) = [00100J since the bit position of th e
fault as sociated with line B is bit 3, and fvalu e(B) = [00100J because the
fault is stuck-ai-l and is processed in bit 3. Similarl y, since two faults

88

Logic Tes ting

associated with line C (C s-a-Oa nd C s-a-l) must be injected into bits 4 and 5
of wo rd C, mask(C) = [00011] and fvalue(C)4 = 0 and fvalu etC] , = 1.
After the masks for fault injecti on have been gener at ed, parallel fault
simul ation is carried ou t. Suppose we want to simula te an input pattern
wit h A = 1 and B = O. First the words A and B are initialized to A
= [11111] and B = [00000]. The simulation is carried ou t from pri mary
inputs toward primary outputs. To evaluate properly the logic value of each
element, all element s of th e circuit should be ordered or levelized. The
details of levelizati on will be described later. In figure 3.2(c), A and Bare
masked to form A' and B':

A'

= A-mask(A) + ma sk(A)'fvalue(A}
= [11111]'[01000] + [01000] '[00000]
= [11111]' [10111] + [00000]
= [10111] ,

B' = B mask(B)

+ mask(B) ' fvalue(B)

= [00 000] -[00100]

= [00000]

+ [00100] ' [00100]

+ [ 00100]

= [001 00].

Nex t the NAND gat e is simul ated:

C=A' B'

= [10111]-[001 00]
= [00100]
= [11011].

Th en C is ma sked:
C' = C mask(C)

+ mask(C) 'fva1ue(C)

= [11011]' [00011]

= [11000]-[00001]
= [11001].

+ [00011]' [00001]

Fault Simulation

89

O n the ou tput C, bits 3 an d 4 are different from hit 1 o r the fault -free value,
and hence the fault s corresponding to the bits 3 an d 4, that is, B s-a- I and C
s-a-O, are detectable.
3.3 D eductive Fault S imulation
Deductioefau lt simulatioll was de veloped by Armstro ng (1972) and has been
used in the LAM P system (Cha ppell et a l. 1974b). T his metho d co nsists in
explicitly simulating the behavior of the fau lt-free logic circuit o nly, and
simultan eou sly deducing from the curr ent "good" state of the circu it a ll
fault s that are dete ctable at any int ernal o r output line while in the curr ent
state. Using the concept of ded uct ive simula tion, we can co mp ute all
detectable faults at the same time, and th us we need perform only a one pass
simulation for ea ch applied test pa tt ern . In pa ra llel fault simula tio n, if m is
the tot al number of faults to be sim ulated and Ii fau lts are simulated du ring
each pass, then rm/1l1 pas ses are requi red. T he simu lation time per pass for
ded uctive fa ult simulation is likely to be m uch longe r than the time per pass
for pa rallel fault sim ulation. Ho wever, it is expected to be less th an the time
for th e rm/1l1 passes requ ired by par allel fault simula tion to accomplish
eq uivalent results . Indeed, Ch an g et al. (1974) have show n experimentally
that deductive fault simulation is fast er than parallel simulation when a
lar ge circuit with a large n umber of fault s is to be simula ted, P arallel fault
simu lat ion is faste r tha n dedu ctive simula tion o nly for small (e.g., < 500
ga tes), hig hly seq uential cir cuits. However, com parison indica tes that a
pa rall el fau lt sim ulato r can be designed to requ ire less storage than a
deductive fault simu lato r.
A deductive fault simu la tor simula tes the fault-free circuit a nd co mputes
lists of faults. A list offa ults LA associa ted with line A co ntains the name o r
index ofevery fault that prod uces a n err o r on line A when th e circ uit is in its
cu rr ent logic state. Th at is, each fau lt in a list, ifi nserte d singly in the cir cuit,
woul d ca use complementation of the good state of the associ at ed signal
line. Th ese fault lists are pro paga ted fro m pri mary inputs toward prim ary
o utputs, level by level, th rou gh the circ uit. In this man ner, a fau lt list is
generated for eac h signal line, a nd it is updated as necessary with every
change in the logic state of the circuit.
A ded uctive simulato r employs the event-directed o r selecti ve trace
procedure; the out put stale of a log ic element is com puted o nly when an
event occ urs at one of its inpu ts. In ded uctive faul t simula tion there are two

90

Logic Testin g

E=O

Figure 3.3
Fa ult lists associated with NOR gate

typ es of events: logic events, which occur when a signal line takes on a new
logic value , and list events, which occur when a fault list changes. The
simula tor must recompute a fault list associated with the ou tput of an
element when a list event occurs at one of its inputs, even if no logic event
occurs at any of its inputs.
Let me first illustrate the procedure for computing fault lists in the case of
logic gates . Consider a NOR gate having inputs A = 0, B = 0, C = 1, and
D = 1. Suppose that inputs A, B, C, and D already have the fault lists shown
in figure 3.3. These are the lists currently associated with the logic elements
that feed these inputs. Several of the faults appear in more than one input
list because of the effects of reconvergent paths in the circuit.
Let a list offaults associated with line X be denoted Lx. In figure 3.3, the
fault lists are

LA = {a,e},

L B = {b,c},
L c = {a,b,c,d},
LD

= {a, d,f} .

Consider fa ult a in figure 3.3. Since fault a appears in LA' L c , and L D , it

cau ses the states of A, C, and D to be complemented (that is, A = I and C
= D = 0) and the output E to be 0. This implies that fault a causes no error
at E and hence is not contained in L. Next, consider fault d. Since fault d

91

Fault Simulat ion

a ppears in both L c and L D , it caus es C = D = 0 and thus E = 1. Th is

imp lies th at fault d causes a n error at E and thus is con tained in L E The
faults th at propagate to E are the faults th at cau se th e good output of E to
be comp lemented. Th erefore, to ca use a I on E, a fault must cau se all ones
on E's inputs to change to zeros, and at the same time must not cau se any
zeros on E's inputs to cha nge to o nes. In th is example, the fault-free inputs
ar e A = B = 0 and C = D = 1.Therefore we have

where U, n, and
denote set umon , intersection, and complement,
respectively.
For the faults that propagate to the inputs of a logic element, we can
compute the list of faults pr op agat ing to the output by the abo ve computat ion using set operations. Ho wever, we also have to cons ider th ose faults
int ern al to the associ ated logic element th at produce the incorrect o utput
for the current good inputs. In figu re 3.3, we have the fault E s-a-l under the
single stuck-at fault assu mption. Hence, we have a complete list of faults
associa ted with E in the example of figure 3.3:

LE

((LA U LB)

n Lc n Lo ) U {E/l}

= {d,E/l} .
For the same 4-input NOR gat e of figure 3.3, if we co nsider A
= 0, and hence E = 1, then we ha ve

=B =C

= D

because in this case an y fault that cau ses a 1 on any inp ut line or a 0 on the
output will produce the incorrect logical output.
The pr ocedures for computing fault lists for other types of logic gates are
straightforward and involve the same considerations as above.
Fault propagation through memory elements is more complicated. Consider the SR latch realized by cro ss-connected NOR ga tes shown in figure
3.4. Suppose that the state at time 1 is (Ql,Q2) = (1,0), and the input is
(S, R) = (0, 1). If at time 2 R changes to 0 (that is, if a non enabl ing input is
applied at t 2), th en th e latch will remain in the same state, as show n in figure
3.4. Let Lb, and Lb2 be the fault lists pr esent at QI and Q2 at time 1'
respectively, and let L~, L~ , L~ " and L~ 2 be the fault lists ass ocia ted with
lines S, R, Ql ' and Q 2 a t time 2' respect ively.

92

Logic Testing

1
o
1

Figure 3.4
Propagation of fault lists through SR latch

The computation of the new lists depends on the previous logic state of
the latch at time t 1 and the new logic inputs to the latch at time t z, as well as

on the associated fault lists. That is, L~, and L~, can be expressed as a
function of Lbl' Lb2' L~, and L~. In other words, L~l and L&z may be
expressed as the union of appropriate subsets of the 16 fundamental
products:
LblnLb2nL~nL~,
LblnLb2nL~nL~,

... ,
Lb,nLb,nL~nL1,

In the following, we will compute the lists L~, and L~, by examining each
of the 16 fundamental products in turn to see if it is included in L~, or L~,.
To keep the discussion simple. we will first consider only faults external to
the latch.
Any fault in Lb, n Lb, n L~ n L1 causes both lines Q, and Q2 to be
incorrect at time t 1 and both inputs to be incorrect at time [2' That is, it
would cause Q, = 0, Q2 = I at t, and S = R = I at (2' This also causes
Q, = Q2 = 0 at (2' and an error is detected on Q, at (2' Consequently,
the product q, n Lb, n L~ n L1 is included in L~, but not in q,.
Next, consider the product Lb, n Lb, n L~ n L~. Any fault in this set
causes Q, = 0, Q2 = I at time (, and S = I, R = 0 at time (2' Therefore we
have Q, = 0, Q2 = I at time (2. which implies that this fault can be detected
on both outputs Q, and Q2 at time t 2 . Hence, Lb, n Lb, nL~ n L1 is
included in both q, and q,.

Fault Simulation

93

We can process the remaining 14 products in a similar manner and

determine whether each product should be included in L~, or L~,. However, we have to pay special attention to the following cases:

Any fault in Lb, n Lb, n Li n L~ causes Q. = Qz = 0 at time i.. This

implies that both inputs Sand R must be 1 at time , because of the fault.
Since such a fault does not affect either input at time z, both will be 0 at this
time. Hence, both inputs Sand R will change from 1 to O. However, it is not
predictable which input changes first, and so it is not known whether the
state of the latch will be (Q" Qz) ~ (1,0) or (0,1). If and only if the latch goes
to the state (Q"Qz) ~ (0, I) as a result of the race, the fault can be detected
on both outputs at z. Owing to this race condition, any fault in

Lb, n Lb, n Li n L~ mayor may not be detected by the current test.

. There is no fault external to the latch that can cause both outputs Ql and
Qz to be 1 simultaneously. This condition can appear only in the four
products containing Lb, n Lb,. Therefore, we can treat these four products
as don't care" to reduce the expressions for L~l and L~2'
in

Having examined whether each of 16 fundamental products is included

Lbl and L~2' we can now specify the expressions for L~I and L~l

L~, =

(Lb, n Lb, n Li n L~) U(Lb, n Lb, n Li n L~) U

(Lb, n Lb, n Li n L~)U (Lb, n Lb, n Li n L~) U

(Lb, nLb, nLi nL~)U(Lb, n Lb, nLi n L~)U

(Lb, n Lb, n Li n LMU(Lb, n Lb, n Li n L~) U
(Lb, n Lb, n Li nL~)U(Lb, nLb, nLi nL~)U
(Lb, n Lb, n Li n L~),
L~, ~

(Lb, n Lb, n Li n L~) U(Lb, n Lb, n Li n L~) U

(Lb, n Lb, n Li n L~) U(Lb, n Lb, n Li n L~) U
(Lb, n Lb, n Li n LM U(Lb, n Lb, n Li n L~) U
(Lb, n Lb, n Li n L~).

The above expressions can be simplified by using "don't care" products

containing

Lbl nLb2' The simplification is performed on all the products

Logic Testing

94

c
o
Figure 3.5
D eductive fault simula tio n

except

Lb. n Lb2 n L~ n L~ . Consequently, we have

q ,=

(Lb . n Lb, n L~ n L~) U Lg U (Lb2n L~),

L~, = (Lb.

n Lb, n L~ n L~) U (L~ n L~) U (Lb, n Lf).

Up to now we have not considered the faults internal to the latch. Any
internal fault causes (Q),Qz) to be either (1,0) or (0,1) . Hence, in the
example of figure 3.4, all internal faults causing (Ql' Qz) = (0, I) should be
included in the lists La. and L~, .
Example 3.1 The propagation of fault lists is illustrated by the circuit of
figure 3.5. This example shows how a deductive fault simula tor propagates
lists of sin gle stuck-at faults on each signal line under the input pattern
shown in the figure. The propa gation of fault lists is performed from
prim ary inputs to ward primary outputs in the order of ascending value of
logic level. First, the fault lists associ at ed with inputs A, B, C, and Dare
obtained as follows :

LA = {A/ I} ,

L o = {BIO},

Lc = {C/O},
L D = {D/O }.
F or gate G(, we have the fault list associated with the output E in

LF; = (LAnLB)U {E/ I} = {A/I, E/ I}.

95

Fault Simulation

For gate G2 , L F is obtained from

L F = LcULDU {F/O}

{C/O,D/O,F/O}.

Similarly, we have

L H = LFU{H/O} = {C/O,D/O,F/O,HIO},
LN

LFU{NjO} = {C/O,D/O,FjO,NjO},

L J = LEU {J/l} = {A/l,E/l,J/l},

L K = LEU{K/I}

= {AII,EII,K/I},
LL = LHU {L/I} = {C/O,D/O,F/O,H/O,L/l},

L M = LJU{M/O} = {A/I,Ejl ,J/l,M/O},

L; = (LKnLdU{P/l}

= {Pj!} ,

La = LMULNU{Q/O}
=

{A/I, C/O, DIO, E/I, F/O, J/1, M/O, N/O, Q/O}

L R = (Lp n LQ)U {RIO}

=

{A/I, C/O, D/O, E/l, F/O,JII, M/O, NjO, Q/O, R/O}.

Consequently, all faults in L R can be detected by the current test pattern.

Next, suppose that the input B changes to 0. The logic event (B changes
from 1 to 0) indu ces a list event on input B by which La = {BIO} changes to
{B/l }. Simulating gat e G1 produces no logic event, but now L E = {E/l} and
thus a list event has occurred. The simulator must recompute a fault list
associated with the output of a gate when a list event occurs at one of its
inputs even if no logic event occurs at any of its inputs. Therefore, we have to
continue the fault list propagation. The list event on E causes the lists L K
and LJ to change to {Ell, K/l} and {E/ l , JIl}, respectively . We still have

Lp={P/l},
but now

Lf>{ = {E/l, JI I, M/O}.

Thus, a new list event has occurred on M, and so L Q is reevaluated to

LQ = {C/O,DIO, Ell, FIO,J/l,MIO,N/O,Q/O}

96

Logic Testing

and L R to

L R = {C/O, DIO, Ell, FlO, 1/1, MIO, NIO, QIO, RIO}.

Up to now we have considered fault simulation at the gate level. However, when the size of the circuit is too large (as in LSI or VLSI circuits), it is
often more cost-effective to simulate parts of the circuit, such as memories,
registers, and decoders, at a functional level. In functional simulation, only
input/output behavior is specified for each functional block for which the
actual gate-level realization is unknown. This approach makes the simulation of larger circuits feasible, since large functional blocks wiII usually
make lesser requirements of the host computer's resources than the corresponding gate-level circuits. A method developed by Menon and Chappell
(1978) for propagating the effects of faults through functional blocks by a
deductive technique was used to implement the functional simulator in the
LAMP system.

3.4 Concurrent Fault Simulation

There is another fault-simulation method that like deductive fault simulation, can perform only one pass simulation to compute all detectable
faults for each applied test. This method, known as concurrent fa ult simulation, was developed by Ulrich and Baker (I 973). Usually, the behavior ofa
faulty circuit is only slightly dissimilar from the fault -free circuit. Activities
in fault-free and faulty circuits are sometimes identical, most of the time
almost identical, and only rarely substantially different. Concurrent fault
simulation, which is bas ed on this similarity between fault-free and faulty
circuits, consists of simulating the fault-free circuit, and concurrently
simulating the faulty circuit only if the faulty circuit's activity actually
differs from that of the fault-free circuit. There are some similarities between
deductive and concurrent simulation. The difference between them wiII be
clarified after the concept and the fundamental operations of concurrent
fault simulation have been illustrated.
Figure 3.6 shows an example of a fault list associated with an AND gate.
Each entry in the fault list consists of the name or index of every fault that
produces an error either at an input or the output of the gate, and of its
input and output values. The first entry in the fault list of figure 3.6 is

AIO; 010; 0

97

Fault Simulati on

A
B
C

Figure 3.6
Fa ult list associated with AND gate

which means that fault A/O cau ses inputs (0, 1,0) and output O. (This fault
A/O is contained in the list associated with line D although it causes no error
on D.) To facilitate fast processing, the entries are sorted by fault index and
are stored in the order of their indices in a list structure.
In deductive fault simulation, a fault list Lv associated with line D
contains only the names or indices offaults that produce an error on the line
D. In the example of figure 3.6, the fault list Lv would be

L D = {Cfl ,D/l}.
Hence, the deductive fault list is a subset of the concurrent fault list, and
concurrent fault simulation requires more storage than deductive fault
simulation.
How fault lists are propagated in concurrent simulation is illustrated in
figure 3.7 by a situation wherein input A = B = C = 0 is first applied and
then input line A changes to a I. In concurrent simulation, only the gates in
the faulty circuit that do not agree , in terms of their input and/or output

98

Logic Testing

o
E

c
All; 10; 0
BIl ; 01 ; 0
0/1; 00; 1

C/1 ; 01; 1

DIl i 10 ; 1
E/1; 00; 1

(al

E
0)--....--C --__!.___

* AIO;

00; 0

8/1 ;
C/1 ;
Oil;
E/l;

* BIl; 11; 1
* Oil; 10; 1

10; 1

01; 1
10; 1
00; 1

(b )

Figure 3.7
Pr op aga tion of faul t lists

values , with the corresponding gate in the fault-free circuit are explicitly
simulated. For gate D, in figure 3.7(a), faults A/I, B/l, and D/l produce an
error at an input and at the output of the gate. Hence, for each of these faults
gate D is simulated separately, and the associated fault list is obtained as
sh own in figure 3.7(a). For example, the first entry (A/I; 10; 0) in the list
implies that if A is s-a-l , the input to the gate will be A = I, B = 0 rather
than A = 0, B = 0, and the output is O. Here, only fault D/1 is propagated to
th e input of gate E, since the output value of D in the faulty circuit differs
from the fault-free value. For gate E, faults Cl1, D/1, and E/l are simulated
to evaluate their output values , and the gate's associated fault list is obtained as shown in figure 3.7(a). All the output values for Cl), D/l, and E/l
are ones and differ from the fault-free value, and hence these faults are
detectable at E.
Next, suppose that line A changes to 1.Since a logic event has occurred at
an input of gate D, the entire fault list associated with D mu st be processed.
For the entry (A/I ; 10;0), since A = I, this term is deleted and the term (A/O;
00; 0) is added to the list. Similarly, (B/l; 01; 0) changes to (B/1; 11; 1), and

Fault Simulation

99

(D/I; 00; 1) changes to (D/I; 10; 1),as shown in figure 3.7(b). Those gates and
entries in fault lists that have been processed are flagged by an asterisk in
figure 3.7(b). The fault list associated with D has three entries, all of which
have asterisks. Among these, only entry BII qualifies for further processing,
since this fault causes a change in the logic value ofline D. Hence, fault BII is
propagated to gate E. The fault list associated with E is then recomputed
only for the new fault Bl]; It is not necessary to reevaluate the other entries,
CII, D/I , and Ell, since their input values do not differ from their previous
status.
In this way, concurrent fault simulation simulates only the gates in the
faulty circuit that have an error at either an input or the output. If gate G has
some activity or event due to faults!lJ2,'" In, then these n faulty circuits
are simulated separately and these entries are placed in the fault list
associated with gate G. In concurrent fault simulation, the faulty circuits
and the fault-free circuit are simulated explicitly. In deductive fault simulation, only the fault-free circuit is simulated explicitly; the faulty circuits are
simulated deductively. Another significant difference between deductive
and concurrent fault simulation is related to the fact that a concurrent
simulator processes only the active circuits. In deductive simulation, if a list
event occurs, it is necessary to reevaluate all faults in the list because of the
complex process of set operations. In contrast, concurrent simulation need
not reevaluate a fault whose status has not changed, but need only resimulate the active faulty circuits. Furthermore, in concurrent simulation, since
each fault in a list is processed separately, fast processing is possible
throught techniques such as table lookup.
The disadvantages of concurrent fault simulation are that it requires
more memory space than does deductive fault simulation. Also, as in
deductive simulation, the amount of memory needed by concurrent simulation cannot be predicted accurately before a run. This can become serious
for large circuits such as VLSI circuits, and so dynamic memory allocation
is desirable.
Example 3.2 The differences between concurrent and deductive fault
simulation are clarified by fault simulations for the circuit of figures 3.8 and
3.9 using concurrent and deductive techniques, respectively. Suppose that
the input to the circuit is first A = B = C = 0, D = 1, and then input A
changes to 1. We begin with concurrent fault simulation in figure 3.8. For
gate E, faults All, BII, and 10 are simulated to form the fault list

re/ l; 11;
E/O ; 00:
F/O; 00;
H/ l : OJ ;

==lLY7
a

1
0

..

0
1

,,

c/i, "10: 1

"
""

0/ 0; 01: 1
E/O : 01; 1
G/O: 01: 1

A/ l; 10 : 1

BIl: 01: 1
E/ O: 00: 0

0
0/ 0; 10:
E/ O: 01:
G/O: 01:
J/ l: 11:
( a)

F igure 3.8
Co ncu rrent fa ult simu lat ion

HIl : 10: 1
JIl : 01: 1
K/l: 00 ; 1

A~

~"

,,

* A/O; 00; 1
* B/l : 11: 0
.. E/O: 10; 0

o~

1
1
(b)

Fault Simulation

All;

10;

B11 ;

01;

101

Ell ; 00; O.
Among these faults, on ly EIO is propagated further since it is the only
o utput value of the ga te in the faulty circuit that d iffers from th e fault-free
value. For gate H, faults ClI, EIO, FlO, and HII are simu lated; the resulting
fault list ass ociated with H is
Cl I;

II ;

10; 00; 0

FlO;

00; 0

nn,

01;

1.

Similarly, we ha ve the fault lists associa ted wit h J a nd K as shown in figu re

3.8(a). Conseq uent ly, fault s ClI , DIO, EIO, GIO, HII , J/1 , and K f! a re all
detecta b le o n the o utp ut K .
Ne xt, consider th e case whe re inpu t A changes to 1. Previously the fault
list associated with E co n tai ned the foll owing faults.

All ; 10;
BII ; 01;
EIO; 00; 0
Since A is no w I, the first entry, (Al l; 10; I), is deleted a nd (AIO; 00; I) is
ad ded. Since a logic even t ha s occurred at an input of gate E, th e remaining
entries, (Bf! ; 0 1; I) and (10; 00; 0), are reev aluated. T he resulting faul t list is

Al l ; 00;
BI I; 11; 0
EIO; 10;

o.

Now, since gate E in th e fault-free cir cu it d oes not alter its output in spite of
the change in input A, no logic events occur after this. On ly fault B/1 causes
a change in the logic value of E as compared with the previ ou s status and
hen ce qualifies for further processing. Similar ly, only BII is sim ula ted after

102

Logic Testing

this, as shown in figure 3.8(b). In this way, a concurr ent fault simulator can
simulate each fau lt sepa rately an d thus process only the active circuits. This
leads to a significant redu ction in computing time.
Fo r the sa me circuit with the same tests, if we consider deductive fa ult
simulation, we can ob tain the result s shown in figure 3.9. T he result of the
simulation with A = B = C = 0 an d D = I is sho wn in figure 3.9(a). Comparing figure 3.9(a) with figure 3.8(a) makes it obvious that concurre nt fault
simula tion requires more memory than dedu ctive simulat ion. Figure 3.9(b)
shows the result of simulation afterinput A changes to 1. First, since a logic
event has occurred at A, the fault list associa ted with E must be recomp uted
by set operations, resulting in the fault list (B/ I, E/O}. T his new fa ult list is
different from the previous list associate d with E, which implies a n occurrence of a list event on E. Hence,furt her compu ta tions offault lists must be
continued at the following gates, H and J. For gate K , deduc tive simulation
must resimulate all fa ults B/I , en, D/O, E/O, G/O, un, J/ I, and K/ I, which
are flagged by an asterisk in figure 3.9(b). In concurrent simulat ion, only the
single fault B/I is processed, as show n in figure 3.8(b). The main reason
that dedu ctive simulation must process more faults than co ncu rrent simulat ion is that the deduc tive technique canno t simulate each offa ulty circuits
separately.
3.5 Hardware Simulators
T he development of increasingiy complex logic circuits has creat ed difficult
problems in logic design, verifica tion, an d testing. The complexity of circuits has led to significantly greater use of CAD (computer-aided design).
For examp le, 1,800 hou rs of IBM System/ 370 model 168 CP U time were
required to verify the logic design of one-fourth of a medium -range System/370 CPU (Pfister 1982). T his fact seems to indica te the limits of
current technology supported by genera l-purpose computers. Recently,
attempts to ov ercome these limits by using special-purpose processors that
utilize the parallelism/con curre ncy in CAD algorithms ha ve received a
great deal of attent ion. T he present commercial products ar e the Logic
Evalua tor and the Tagas accelerat or (Lineback 1982). The othe r systems,
discussed in th is section, are a logic-simulation machine pro posed by
Abramovici et al. (1982), the Yorkt own Simulation Engine (Pfister 1982;
Denneau 1982; Kr onstadt an d Pfister 1982), an d the Hardwa re Logic
Simulat or (Sasak i et a1. 1983). The se are all special-pur pose par allel com-

Fault Simulation

103

,,

-, ;c- :::: , "'- ;, :::: :::: ::::

0

00

,,
0

,,

:::: ,
~

,,
0

"

,0 ,0

= ;;

::::
~

n
0

::::

104

Logic Testing

EVENT
LIST
MEMORY
FROM
INPUT
FILE

EVENT
LIST
MANAGER

SCHEDULER

CURRENT
TO
EVENT
- - RESULT
FILE
PROCESSOR

I
CONFIGURATlON
EVALUATOR I-- PROCESSOR

MOOEL
ACCESSING
UNlT

..-

Figure 3.10
O verall a rchitecture of logic-simulation mach ine (Abramovici et a!. 1982; IEEE 1982)

puters that might be called hardware simulators (in contrast with conventional software simulators hosted by general-purpose computers).
Although all these hardware simulators are designed primarily for logic
simulation, they can be used for fault simulation. By simulating faulty
circuits as well as a normal circuit, they can perform fault simulatio n at high
speed.
T he basic structure of the logic-sim ulation machine of Abramovici et al.
(1982) is shown in figure 3.10. T he machine is organized in a distributed
processing architecture in which separate processing units are dedicated to
specific tasks of the simulation algorithm. The algo rithm adopted here is
base d on tab le-driven event-di rected sim ula tion. Usually, event-directed
simu lation perfo rms the following main processes (tasks): The first step is
retrieving an event from the event list. T he second is upda ting the configuration of the sou rce element tha t has generated that event, wher e the
configuration of an element consists of the values of its inputs, outputs, and
internal state variables. The fanout elemen ts to which the event propagates
are determined to update thei r configuratio n. After updating the configuration of all the elements associated with the event, the simulator determines
(that is, evaluates) the new values of their outputs and state variables. T he
evaluation of an element may result in events on its outputs and/or state

Fault Simulation

105

variables. Delays are usually associated with the operation of elements.

Hence, the resulting events are scheduled to occur at some time in the future
by computing their times of occurrence. These events are inserted in the
event list, and the simulation time is advanced. Each processing unit is
dedicated to some task of simulation and works concurrently and cooperatively with the other processing units. The execution of a task is initiated by
the arrival of the data required for the task, and the data flow between
processing units is organized in a pipeline fashion. The tasks of the different
processing units are as follows:
The Event List Manager receives the future events and their times of
occurrence from the Scheduler and inserts them in the Event List Memory.
It also transfers events of the primary inputs from a file containing the
applied input sequence into the Event List Memory periodically.
The Current Event Processor retrieves the events associated with the
current time from the Event List Memory and sends them to both the
Model Accessing Unit and the Configuration Processor. It also records in
the output file the events occurring at the monitored points.
The Model Accessing Unit determines the fanout elements to which the
current event propagates and sends them to Configuration Processor.
The Configuration Processor updates the configuration (i.e.,all the values
of inputs, outputs, and internal states of the source element and its fanout
elements affected by the current event).
The Evaluator receives the configurations of the elements from the Configuration Processor and evaluates them. The evaluation of an element may
result in new events or may cancel a previously scheduled event. Depending
on the results, it sends the new events or a "cancel event message" to the
Scheduler.
The Scheduler receives the new events and computes the times of occurrence of the events. The new events and their occurrence times or the
"cancel event message" are sent to the Event List Manager.
The simulation machine of Abramovici et al. also contains parallel
processors, referred to as Functional Evaluators, which concurrently perform functional evaluations as shown in figure 3.11.
Abramovici et al. also proposed to use a microprogram mabIe processor
and to implement all the tasks directly in microcode in order to avoid the
substantial software overhead involved in fetching and decoding macroinstructions. They estimated that hardware-based simulation would be between 10 and 60 times as fast as software-based simulation.

106

Logic Testing

rROM CURRENT EVENT PROCESSOR

TO SCI1EDULEIl

AND

~OD E l

ACCESSINGUNIT

SIM.P LE
CONFIGURATION
PR) CESSOR

FUNCTI ONAL

CONFIGURATION
PROCESSOR

Figure 3.11

Simple and functional evaluations {Abra m c vici et al. 1982; IEEE 1982)

In co ntrast with the lo w parall elism o f the mach ine o f Abramo vici et al.,

the Yorktown Simulati on Engine (YSE) (Pfister 1982) exploi ts the high
paralleli sm of 256 proce ssors. T he YSE differs from the machine of Abramovici et al, in that it is designed to execute unit -delay a nd level-ord er
simulation rather th an event-directed simulation. Th e unit-delay model
assumes that every gate has the same delay an d that external input changes
occu r only on integral unit-delay time boundaries. Level-order simulatio n
is a technique used in parallel fault simulation where in all gates are first
so rted in ascending order of levels and simula ted in the order of ascendi ng
value of logic level. The YSE uses these two simula tion techn iques at the
gate level, but not at the functional level. It was built to simulate the logic
o peratio n of circuits composed of up to a million gates at a rate exceedin g 2
billion gat e comp utat ions per second .
Figure 3.12 shows the overall a rchitecture of the YSE. It is basically an
array of parallel processors. In addition, it has a n interprocessor switch and
a control processor. A la rge circuit to be simula ted is partitioned into
subcircuits, and each subcircuit is assigned to a logic processor prior to
simulation by the control processor. Each logic pro cessor contains an
instruction memory, which stores the interconnection and function information for the logic circuit;a data memory. which maintains configurations
(i.e., logic values for signal lines in the circuit); an d a function unit, which
evaulates logic function. During simulati on, the logic processors concurrentl y fetch the inform ati on from their instruction memories to access and

107

Fault Simulation

l
0
G
1
C

l
0
G
1
C

l
0
G

1
C

A
R
R
A
Y

A
R
R
A
Y

TO

I FROM

HOST
p

R
0
C

R
0
C

R
0
C

R
0
C

P
R
0
C

COMPUTER

CONTROL
PROC

Fig ure 3.12

Ove rall architecture of Yorktown Simulation Engine (Pfister 1982; IEEE 1982)

upd a te values for signa l lines stored in their data memories. Each function
unit of the logic processors accepts a function code and some opera nds fro m
the instruction memory and the data memory, respectively; computes the
logic function; and finally sto res the resulta nt value back into the data
memory. Array processors are used to simula te rando m-access memories
(RAMs) an d read-only memo ries (ROMs).
T he interprocesso r switch provides communication among up to
256 logic and array processor s du ring simulatio n. Logic an d array processo rs ha ve to tran sfer signal value s betwee n their data memories. The
switch accom modates th e requi red communica tion introd uced by the
partitioning.
The control processor takes charge of co mmunication between the hos t
computer and the YSE, including initializing, interrupt handling, and
diagnostics of the YSE. T he par titioning of the circuit into subci rcuits and
the sequence of switc h routi ng configurations are all determined and fixed
prior to simula tion, and affect the initialization of the YSE by the co ntrol
processor.
T he thi rd type of hardware simulator is the Ha rdware Logic Simulator
" HAL" developed by Sasaki et al. (1983). T he overa ll architecture of t he
HA L, show n in figure 3.13, is simi lar to that of the YSE. It is also basica lly
an array of parallel processors that contains logic processors, memory
processors, a control processor, a nd an interprocessor network. However,

Logic Testing

108

LOGIC PROCESSOR

INTERPROCESSOR
NETWORK

LOGIC PROCESSOR

LOGIC PROCESSOR

29
30
31

32

Figure 3.13
Overall arch itecture of HAL (Sasaki et a!' 1983; IEEE 1983)

the HAL differs in some resp ects from the YSE. It contains only 32 processors, and thus its parallelism is lower than that of the YSE. It performs
table-driven event-directed simulation at the functional level as well as at
the gate level. It uses a technique called block-oriented simulation, where
"block" means a logic collection ranging from several gates to several
hundred gate s or a memory element in a range from one RAM chip to
several hundred RAM chips. The block-level simulator supports LSI-level,
functi onal macro-level, gate-l evel, and mixed-level simulation.
The hardware of each processor is made up of two parts: an interblockconnection simulator and a block-behavior simulator. The interblock
simulator has a block-status memory and a block-interconnection list
memory. It reads (in turn) block input valu es and block type information
from the block-status memory, send s th em to the block-behavior simulator,
receives the resulting o utput values of the block from the block-behavior
simulator, and updates the block-status memory. The block-behavior
simulator has a block-function memory. It receives block-input values and
block type information from the interblock simulator, evaluates the output
values of the block, and sends the result to the int erblock simulator.
The HAL ha s 29 logic proces sors and two memory processors. Each
logic processor can simulate up to 1,024 logic blocks. Each memory processor can also simulate up to 1,024 memory blocks. It was estimated th at
the HAL can simulate up to 1.5 million gates and 2M byte RAM ICs at a 5millisecond clock speed .

The Complexity of Testing

Testing has two main stages: the generation of tests for a given circuit and
the application of these tests to the circuit. Hence, the complexity of testing
can be classified into the complexity of test generation and the complexity
of test application.
The computational complexity of the algorithms used to generate a test is
used to estimate the complexity of test generation. The size of a test set or
the length of a test sequence is adopted as a measure of the complexity of
test application.

4.1 NP-Completeness
The time complexity of an algorithm (that is, the time needed by the
algorithm) can be expressed as a function of the size of the problem. If an
algorithm processes inputs of size n in time cn2 for some constant c, then we
say that the time complexity of that algorithm is of order n 2 More precisely,
a functionf(n) is of order g(n) whenever there exists a constant c such that
f(n) ~ c- g(n) for all values of n ~ O. An algorithm whose time complexity is
of order p(n) for some polynomial function p is called a polynomial time
algorithm. Similarly, an algorithm whose time complexity is of order k" for
some constant k is called an exponential time algorithm.
In the theory of computation, there is general agreement that a problem
should be considered intractable if it cannot be solved in less than exponential time. That is, exponential time algorithms are "too inefficient."
To illustrate this, suppose that we have three algorithms whose time
complexities are 11, 113, and Z", Assuming that time complexity expresses
execution time in microseconds, the n, n 3 , and 2n algorithms can solve a
problem of size 10 instantly in 0.00001, 0.001, and 0.001 second, respectively. However, the apparent distinction between polynomial time algorithms and exponential time algorithms exists in larger problems. For
example, to solve a problem of only size 60, the 2n algorithm requires 366
centuries whereas the nand n 3 algorithms require only 0.00006 and 0.216
second, respectively.
From this example it is obvious that exponential time algorithms are
unsuited for practical use in large problems, and that polynomial time
algorithms are much more desirable. Hence, a problem is regarded as
intractable if it is so hard that no polynomial time algorithm can possibly
solve it. Many intractable problems are known to constitute an equivalent
class called the class of NP-complete problems. Major fault-detection prob-

Logic Testing

110

lems are NP-complete, and thus it appears very unlikely that faultdetection problems can be solved by a polynomial time algorithm in
gen eral.
More detailed and preci se discussions ofNP-completeness may be found
in both Aho et a!. 1976 and Garey and Johnson 1979. A problem A is said to
belong to class P (class NP) ifany instance of A is solved in time bounded by
a polynomial of the problem size by a deterministic (nondeterministic)
computation. (In our problems, the number of gates and lines in a circuit
may be regarded as the problem size.)
Problem A is said to be polynomially transformable to B if the existence of
a deterministic polynomial time algorithm for B implies the existence of a
deterministic polynomial time algorithm for A. For decision problems, we
say that A is polynomially transformable to B if any instance of A can be
transformed in polynomial time of the deterministic computation to an
instance of B such that the former has an answer "yes" if and only if the
latter has an answer "yes." Now we can define NP-completeness as follows:
A problem B is said to be NP-complete if(l) it belongs to NP and if(2) every
pr.oblem A in NP is polynomially transformable to B. Ifsome problems are
already known to be NP-complete, condition 2 is rather easily checked: It is
sufficient to show that (2') at least one problem A, which is known to be NPcomplete, is polynomially transformable to B.
"Is P = NPT is a long-standing open problem in complexity theory. If
for at least one NP-complete problem A any instance of A is solved in
polynomial time, th en P = NP. However, it appears very unlikely that
P = N P, and hence NP-complete problems are regarded as intractable in
the sense mentioned above.
The first NP-complete problem, usually referred to as the satisfiability
(SAT) problem, was reported by Cook (1971). A brief description of this
problem follows; we need it in our discussion of the NP-completeness of
fault-detection problems.
A literal is either x or x for some variable x, and a clause is a sum of
literals. A Boolean expression is said to be in conjunctive normalform (CNF)
if it is a product of clauses. For example, (XI + X2)'(X 1 + X3 + x 4 ) is in
CNF, but Xl + X2X 3 is not. A Boolean expression is satisfi able if and only if
there exists some assignment of zeros and ones to the variables that gives
the expression the value 1. Then the SAT problem is specified as follows .
Sat isfiability (SAT)

Is a Boolean expression satisfiable?

THEOREM 4.1 (Cook 1971) The satisfiability problem is NP-complete.

The Comp lexity of Testing

111

It is know n that, even with a more strin gent condi tion, the satisfia bility
p roblem is NP-com plet e. An expression is said to be in k-co njun ctive
normal for m (k-CNF) if it is a prod uct o f sums of at most k litera ls. The ksat isfia bility probl em (k-SAT) is to determine whe ther a n ex press ion in kCNF is sat isfiable. For k = I or 2 th ere exist po lynom ial algo rithms to test
k-sa tisfiab ility. However, 3-SAT is known to be NP-complete .
THEO REM4.2 (Co ok 1971)

3-SAT is NP-complete.

An express ion is said to be clause-monotone if ea ch cla use contains either

on ly nega ted va ria bles or onl y unnegated va riables. The sa tisfiability for
clau se-monotone expressions (CM-SAT, for short) is a lso kn own to be NPcom plet e (Gold 1974). Since th is is the ke y NP-complete problem for the
following discu ssions, a proof is given here.
T HEO REM4.3

CM -SAT is NP-complete.

Proof It is ea sy to see that CM-SAT is in N P. We tr an sform 3-SAT to

CM -SAT. Gi ven a 3-C N F of a Boolean expression F = C j C2 ' C,
where each clau se Ci (1 ::::;; i ::::;; k) is composed of exactly three literals, we
shall co nstruct a clau se-mon oto ne expression F' su ch th at F' is satisfiabl e if
a nd only if F is sat isfiabl e.
T o construct F' we merely repl ace each indiv id ua l clause Cj(1 ::::;; j ::::;; k) by
a clau se C; or a pr oduct of two cla uses C
;C;' as follows:
Case 1

C, = a + b + c,

Case 2 C, = a +
Case 3

C, = a

b + c,

+ b + c,

C; = C
C; = C
C;. Cj' = (a + b + Vj) ' (Vj + c)
j'

j'

where vj is a new varia ble for Cj

Case 4

Cj =

a + b + c,

C; Cj' = (a + b + v

j) ,

(Vj + c).

O bviously, thi s transformati on can be performed in polynomi al time. To

pro ve th at th is is indeed a tr ansformat ion, we must sh ow that F' is sa tisfia ble if an d only if F is satisfiable. However, on e can ea sily pro ve th at. _
Although SAT , 3-SAT, and CM-SAT a re all N P -co mplete, the satisfiabil ity probl em is solva ble in polynomial time if a Boolea n expression is
monotone or unate. An expression is sa id to be monotone ifi t contains onl y
unnega ted va ria bles. An exp ression is said to be unate if each variable is

Logic Testing

112

either only negated or only unnegated. A negated (unnegated) variable in a

un ate expression is called to be negative (positive) unate.
One can easily see that if an expression is monotone then it is unate and
also clause-monotone. However, every unate expression is not always
clause-monotone. For example, (Xl + x1}'(X Z + x3) is unate but not
clause-monotone. In this expression, Xl and Xl are positive un ate and X3 is
negative unate. Moreover, (Xl + Xl)' (x2+ x3) is clause-monotone but not
unate.

The satisfiability problem for unate expressions (V-SAT, for short) is

shown to be solvable in time OIL), where Lis the length of an expression, in
the following theorem.
THEOREM 4.4 V-SAT is solvable in time O(L) where L is the length of an
expression.

Proof Let E(x1 , Xl"'" X p } be a unate expression. Let (at, Qz, ... , Qp ) be an
assignmentsuch that Q j = 0 if Xi is negativeunate and a, = 1 if Xi is positive
un ate. Since the expression E is unate, if E(a 1 a z ... , ap ) = 0 then E(x 1 Xl'
... , Xp } = 0 for any assignment. This implies that E(a l, a2"'" ap ) = 1 if E is
satisfiable. Hence, E is satisfiable if and only if E(a[, G 2, .. , ap) = I. We can

determine whether E(a[, a 2 ,

solvable in time O(L).

.. ,

apl = 1 in time O(L) and so that V-SAT is

The satisfiability of a monotone expression (M-SAT, for short) is also

solvable in time

O(L). since a monotone expression is also

unate. Thus we

have the following corollary.

COROLLARY 4.1

M-SAT is solvable in time O(L) where L is the length of an

expression.

Now we shall consider the following fault-detection problem:

Fault detection (FD)

Is a given single struck-at fault detectable?

Ibarra and Sahni (1975) reported that the FD problem is NP-complete.

However, their proof is rather long and complicated. The much simpler
proof given by Fujiwara and Toida (1982a, b) showed that the FD problem
is still NP-complete even for k-Ievel (k )0 3) monotone/unate circuits
though it is solvable in polynomial time for 2-level monotone/unate
circuits.

In this section, NP-completeness proof offault-detection problems given

The Complexity of Test ing

113

"

,,

,,

Figure 4.1
A 3-level mo notone circuit Q I

by Fujiwara and Toida (1982a,b) will be described. The following expressions will be used:
kM-FD fault-detection problem for k-Ievel monotone circuits
kU-FD fault-detection problem for k-Ievel unate circuits.
Let us begin with the following theorem.
THEOREM 4.5

3M-FD is NP-complete.

Proof Obviously 3M-FD is in NP. Hence, it suffices to show that some

NP-complete problem is polynomially transformable to 3M-FD. We shall
transform eM-SAT to 3M-FD.
Given any clause-monotone expression E with variables x., X 2, , x p
and clauses C 1, C2 , ... , Cq , we construct a 3-level monotone circuit Ql as
folows (figure 4.1).
Without loss of generality, we assume that C l , C 2 , , Ck are the clauses
with negated variables and CHI' C H 2 , .. . , Cq are the clauses with unnegated variables.
Step 1: Construct AND gates AI, A 2 , , A k from clauses C l , C2 , , Ck
with negated variables so that each AND gate Ai has the input variables of

Logic Testing

114

Cj For example, suppo se a clause C j is equal to a + b + c; then the output

of A j is a' b . c.
Step 2: Construct the above AND gates to OR gate G 1 as shown in figure
4.1.
Step 3: Construct OR gates 1 , 0z, ... , Oq-k from clauses Ck + 1 , Ck+Z' . . . ,
Cq with unnegated variables. For example, the output of OJis a + b + c if
the clauses Cj is equal to a + b + c.
Step 4: Connect all the OR gates 1 , 0z, .. . , 0q-k and G[ to AND gate Gz
a s sh own in figure 4.1.
In this circ uit Ql, a stuck-at-I fault on the output of gate G1 is detectable
if and only if there exists a test such that all the outputs of AND gates AI'
A z, ... , A k are 0 and all the outputs of OR gates 0[, 0z, ... , Oq-k are 1.
Suppose that AND gate A j corresponds to a clause C, = a + b + c. Then
the output of A j isO ifand only if C, = Lsince c b c = Oif and only if a + b
+ C = 1. Hence, the fault G1 s-a-l is detectable if and only if the given
expression E is satisfia ble.
The above construction can be carried out in an amount of time linear in
p and q. Therefore, CM-SAT is polynomially transformable to 3M-FD.

Since monotone circuits are also unate, we can see from theorem 4.5 that
3U-FD is also NP-complete.
COROLLARY 4.2

3U-FD is NP-complete.

Now we have seen that the fault-detection problem is NP-complete even

for 3-1evel monotone/unate circuits. These results also imply that the faultdetection problem is in general NP-complete. Hence, we have the following
corollary from theorem 4.5.
COROLLARY 4.3

FD is NP-complete.

Next we consider the following test-generation problem with a more

stringent condition. Suppose we know that a circuit C is not only monotone
but also irredundant and we wish to know how long it will take to find a test
for a given fault in C. The following theorem shows that this problem is still
NP-complete.
THEOREM 4.6 The problem of findi ng a test to detect a given fault
arbitrary monotone and irredundant circuit C is NP-complete.

in an

Proof It suffices to show that a polynomial time algorithm for finding a

The Complexity or Testing

115

test for f in C can be used to develop a polynomial time algori thm for
solving 3M-FD.
Assume that we ha ve a polynomial time algo rithm A that finds a test for a
given fault f in a n a rbitra ry mon ot one a nd irred unda nt circuit C. Using
this algorith m, we can construct a polyno mial time algorithm that solves
3M-FD as follows:
Algorithm A :
Input: an irred undant mo no tone circuit C and a single stu ck-at fault f.
Output: a test to detect f in C.
Let p(. ) be the polynom ial time bou nd of A.
Algorit hm B:
Input: a 3-le vel mo not on e ci rcuit C' and a single stuck-at fault [' ,

O utp ut: "yes" if there is a test to det ect J';"no" o therwise.

Method:
Apply algorithm A to J' a nd C.
lf A does not halt on I' and C after p(. ) steps, then there is no test for I' an d
the answer is uno."
lf A halts on I' an d C in p(.) or fewer steps, then check whether o r not the
outpu t is a test for J'. lfit is a test for 1', then the answer is "yes." O therwise,
the re is no test for J', and the answer is "no." _
4.2 Polynomial Time Class
T he choice has been made to show tha t the fau lt-detection pr oblem is NPcomplete. However, there a re many circuits for which the fault-detection
problem ca n be solved in polyno mial time-for example, linea r circuits,
decoder circuits, a nd parallel adders.This section presents a class of circuits
that contains the abov e circuits and for which the fault-detection problem
can be solved in polynomial time (Fujiwara and Toida 1982a, b).
First, we int rod uce an extended opera tion of implicat ion , called an
ex tended implication.
Co nside r a combinat iona l circuit C in which the values 0, I, D, an d 15 may
be assigned at so me lines. Let V(Si) be a subset of {O, I, D, 15} with respect to
line s, in C. We construct each set V(Si) working breadth-first from primary
inputs to primary outputs as follows: For each primary input x,(1 .;; i .;; n),
we let V(x,) = {a} if the value a is alread y assigned at Xi' where a is 0,1 , D, or
15, and let V(x,l = {D, I} otherwise.

116

Logic Testing

For an AND ga te with inputs X " X, . .. Xp and o utput Y, we construct

V(Y) in th e follo wing steps:

If 0 is in V(X i) for some Xi. then 0 is in V(Y).

If D is in V(Xi) and i5 is in V(Xj ) for some Xi and Xj ' then 0 is in V(Y).
If 1 is in V(X') for all X" then 1 is in V(Y).
If D is in V(X ,) for so me X , and D or I is in V(X j ) for all ot her X j (j # i), then
D is in V(Y) . If i5 is in V(X,) for so me Xi and i5 o r 1 is in V(X j ) for all other X,
(j # i). the n 15 is in V( Y).
We can construct V(Y) simila rly for other types of gates (OR. NAND,
NOR, NOT).
When we encounter a line 5, on which a value V is already assig ned, we
check whether or not V(Sj) contains v. If it does no I, then an incon sistency
occ urs . Otherwise, we redefine V(s,) = {v) and continue the computation.
When we enco unter a line L wit h a fa ult, we check whether o r n ot V(L)
co n ta ins 1 (0) if the fault is s-a -o (s-a-I). If it does not. then an inco nsistency
occu rs. Otherwise. we red efine V(L) = {D} for a s-a-O fault and V(L) = {V}
for a s-a-I fault and con tinue t he co mpu tation.

Obviously, theabove computation requiresat most O(m) time,wheremis

the num ber of lines in C.
A set S of poi nt s in a circuit C is called a head-point set of C if for any
reconvergent fanou t point p, either p belongs to S o r any path from eac h
pr imary in put to p contains at least one point in S.
4.7 Let C be a circuit and let S be a head-po int set with k head
points. Then there is an algorithm of time complexity 0(4*. Ill) to find a test
for a single stuck-a t fa ult in C. whe re In is the num be r o f lines in C.

THEOREM

Pr oof T he test generati on for a fau lt on line L can be perfor med in the
foll owing steps:

(I) Fix a value of L to D (15) ifa fau lt is a st uck-a t-O fs-a- t]. Assign a value O. I,
D. or 15 to each head poi n t in C to do t he following steps for each
combination of values on the head points. If there is no untried combination remaining and no test has been found, the n there exists no test, so
sto p.
(2) For ea ch assignment. determine the imp lications, th at is. determine all
the line va lue s tha t are implied uniquely by the values assi gned on t he head

The Complexity of Testing

117

points. If any inconsistency occurs, then go back to step 1. If no inconsistency occurs, the values of all (head a nd nonhead) reconvergen t fanou t
points a re determined uniquely.
(3) Perform extended implications. wor king breadth-first from prima ry
inpu ts to primary outputs; that is, compute VIs,) for all lines s,: If any
inconsistency occurs, then go back to step 1.
(4)Check whether or not every D-path sta rts at the line L under test, where
a D-path is a path such that VIs,) contai ns either D or 15 for all lines s, on the
path. If not, the n go back to step 1.
(5) Check whether or not there is at least one D-path endin g at a primary
output. If not, then go back to step 1. Otherwise, you have foun d a test, so
stop.
The abov e alg orithm requires the enumera tion of at most 4.1: combi -

nations of values on head points. We can see that steps 2, 3, and 5 can be
performed in time O(m), where m is the number of lines. Hence, the above
algorithm can be carried out in 0 (4.1: m) time. _
The algo rithm shown in the proof of theorem 4.7 generates all the
combination s of values 0, 1, D, or 15 on all head points, i.e., 4' assignments
from the beginning. Th is can be impr oved by an implicit enumeration
technique. In generating a test, the algorithm creates a decision tree in
which at each decision node the value of a line is chosen from among a
number of possible values. The initial choice is arbitrary, but it may be
necessar y dur ing the execution of the algorith m to return to the same node
and consider ano ther possible cho ice. Th is is called a backtrack. In o rder to
guarantee the time com plexity 0 (4" m), we have to make sure that back tracks occur only at k head points.
Next, consider a combinational circuit C, which is partitioned into
subcircuits called blocks : B 1 , B 2 , ... , B,. A fanout point p in a block B , is
called a reconvergentfanout point with respect to Bj if there exist two paths,
both of which start from p and either recon verge within B, or arri ve at an
adjacent block BJ (j # i). A non primar y input of Bi is a signal line coming
into Bi from another block.
A head-point set 5, ofa blo ck B, is a set of points such that all nonp rimary
inputs of Bi are cont ained in Sj and such that. for any reconvergent fanout
point p with respect to B" either p belongs to 5, or any path from each
primary input to p cont ains at least one point in 5i
For a combinat ional circuit C parti tioned into blocks, we defi ne a

11 8

Logic Testing

Pri ma ry Input s

(a)

Circuit C parti t ioned i nto bl ocks

(b) Gra ph Gc
Fi gure 4.2
A k-hea d- bou nded circuit

directed graph Gc with respect to the circuit C and its blocks such th at each
vertex represents a block a nd each a rc represents a connection between
blocks (figure 4.2).
A combinational circuit C is said to be k-head-bounded if C can be
partitioned into block s B, (i = 1,2, . . . , t) such that the graph G, with respect
to C and B, is acyclic and has no reconvergent path and such th at, for each
bloc k B, (1 ~ i ~ t), there is a head-point set Sj with at most k head points.
Exa mple 4.1 Con sider a par allel binary adder of p bits con structed by
cascading p stages of one-bit full adders called rippl e-carry adders. Figure
4.3 sho ws p-sta ge ripple-ca rry adder. If we partition thi s adder so that each

The Complexity of Testing

119

Co

Figure 4.3
Ripp le-carry add er

Co

Fig ure 4.4

G ate-m inimum p-bit add er

block corresponds to a full adder, we see that the ripple-carry adder is a 3head-bounded circuit.
Example 4.2 The gate-minimum p-bit parallel adder (Lai and Muroga
1979) diagrammed in figure 4.4 is e-head-bounded.
Example 4.3 The exclusive-OR tree realization of a linear function is a 2head-bounded circuit.

Example 4.4 A p-bit decoder ca n be realized by a circu it with p nonreconverge nt fanout poin ts and 2P AN D ga tes. Hen ce, it is a O-hea d-bo unded
circuit.
In theorem 4.7 it was shown that for a circuit wit h k head poin ts th ere
exists an algorithm oftime complexity
m) to find a test for a given fault
of the circuit. We can easily exten d th e result to a class of k-head-bo unded
circu its as in the follow ing theorem.

oW'

Logic Testing

120

THEOREM 4.8 Let C be a k-head-bounded circuit. Then there is an algorithm of time complexity O(16k m) to find a test for a single st uck-a t fault
in C, where m is the number of lines in C.
In the proof of theorem 4.8, we consider 4k po ssible values for each block
and 4k x 4k possible tests for each pair of adjacent blocks. Hence, the time
complexity becomes O(16k m) instead of the
m) of theorem 4.7. The
proof is omitted. For details, see the proof of theorem 11 in Fujiwara and
Toida 1981c. Notice that k-head bounded circuit will have more than k
head points.
From Theorem 4.8 we have the following corollary.

OW '

COROLLARY 4.4
Let C be a k-head-bounded circuit such that k = log2P(m)
for some polynomial p(m), where m is the number of lines in C. Then the
fault-detection problem for C is solvable in time complexity O(p(m)4. m).

For a k-head-bounded circuit, in order to solve the fault-detection problem in polynomial time it is sufficient that k = logp(m). As mentioned
earlier, parallel adders, linear circuits, and decoder circuits are all kheadbounded for some constant k. Hence, the fault-detection problem for these
circuits is solvable in time complexity O(m).

4.3 Closedness under Faults

Let n be the set of all logic function. Let 0. 1 be the set of all single-input logic
functions, i.e., n 1 = {O, I, I, N} where 0 and 1denote the constant functions,
I denotes the identity function, and N denotes the NOT function, i.e.,
O(x) = 0, 1(x) = 1, l(x) = x, and N(x) = x.
Let F be a set of logic functions. Let [F] be the set of all logic functions
that can be obtained as finitary compositions of functi ons from F. (each f
may appear any number oftimes.) [F] is said to be the closure of F. F is said
to be closed under composition if F = [Fl
The classical closed ness problem in logic and switching theory wa s
completely solved for the binary case, and all the closed classes under
composition were classified (Kuntzmann 1968). Figure 4.5 shows all the
closed clas ses that contain constants 0 and 1. The notations in the figure are
defined as follows:

L= the class of linear functions. An n-input lin ear function can be represented in the form Co $ ctx[ ttl ... $ CnX. where c i = 0 or 1 for i = 0,1 , .. . , n.

The Complexity of Testing

121

Figure 4.5
Closed sets containing constants 0 and 1

Mo !

the class of monotone functions including 0 and 1.

the class of OR functions including 0 and 1.
~ the class of AND functions including 0 and l.

LO!.~
ITO!

Let F be a set oflogic functions, and let f be a logicfunction in F. If alogic

circuit that realizes the function f is composed of the elements realizing
functions in F, then such a realization is called a closed composition with
respect to F. Henceforth we assume that any realization of a function f in F
is a closed composition with respect to F. As an example, consider a
function f in F such that f can be expressed in the form

where g! and g, is in F. Then we obtain a closed composition as shown in

figure 4.6, where 1 and 2 are the elements realizing functions gl and g"
respectively.
We will assume the standard stuck-at fault model, according to which all
faults can be modeled by lines stuck at logical 0 or at logical 1.
A set oflogic functions F is said to be closed under stuck-at faults if any
multiple stuck-at fault changes a function in F to a faulty function in F. Let
S(F) be the set of all faulty functions that can occur from each function in F
when a multiple stuck-at fault is present. Then we can say that F is closed
under stuck-at faults if and only if F covers S(F).

Logic Testing

122

x3 -----1 E2

x, -----i

Figure 4.6
Circuit realizing function

THEOREM 4.9 (Fujiwara 1981) For any subset F ofn such that F
covers S(F) if and only if F contains constants 0 and I.

[F],F

Proof Suppose that F covers S(F). Obviously S(F) contains constants 0

and I. Therefore, F also contains 0 and I. Conversely, suppose that F
contains 0 and I. Let C be a circuit realizing a function f in F. Let a be a
multiple stuck-at fault such that lines s 1- 52' ... .s, are stuck at ex l' (X2, .. . , C(k.
respectively. Let C, be the faulty circuit due to the fault a, and let fa be the
faulty function realized by the circuit Ca' Clearly, the circuit Ca is equivalent
to the circuit in which the lines 51. 52.
Sk are cut and connected with
constant elements (Xl' (X2' ... , ctk , respectively. By hypothesis, F is closed
under composition, and moreover F contains 0 and I. Therefore, the faulty
function fl1. is also in F which implies that F covers S(F).
"'j

From this theorem and figure 4.5 we have the following corollary:
COROLLARY 4.5 If F = [F] and F covers S(F), then F is n, Mal' L,
ITo" [n,], or [{O, 1, I}].

~Ol'

Corollary 4.5 shows that all the sets of logic functions that are closed
under both composition and stuck-at faults are n, Mal' L, ~o,' ITo" [n l ] ,
and [(O,
So far, we have considered only the sets that are closed under composition. However, there still exist many sets of logic functions that are not
closed under composition but are closed under stuck-at faults. Indeed, it
can be shown that there exist infinitely many sets oflogic functions F such
that F # [F] and F covers S(F). The classes of fanout-free functions and
unate functions are the examples of such sets oflogic functions.

l,In

Th e Co mplexity of Testin g

123

A single-output circuit C isfanout-free if every line in C is connected to an

input of at most one gate, where the gates are assumed to be AND, OR,
NAND, NOR, and NOT gates. A logic function is said to be e fanout-fr ee
function if f can be realized by a fanout-free circuit. The class offanout-free
functions is not closed under composition. As an example, consider three
functi on s I, g l' and 92 such that
f(XI,X2 ,X3) = X1Xl

91(XI,X l,X3)
92(X I,X2)

+ X2 X3 + X3 XI,

= XI + Xl + X 3,

= X1 Xl '

The function

can be expressed using gl and 92 in the form

Although g l and 9l are fan out-free functions, f is not fanout-free. Hence,

th e class of fanout-free func tion s is not closed under composition.
Now we define a restricted composition as follo ws. Let F be a set oflogic
functions. If a logic circuit C that realizes a function f in F is composed of
the elements realiz ing functi ons in F, a nd if every line in C is connected to
any input of at most one element in C, then such a realization is called a
closed tree composition or simply a tree composition.
The class of fanout-free functions is not closed under composition. However, if we restrict our realiza tion of a given fan out-free function to a tree
composition, we can easily show that the class of fanout-free functions is
closed under composit ion and that it it also closed under stuck-at faults.
Various properties of fanout-free functions have been studied by Hayes
(1975) and Agarwal (1978).
Similarly, although the class of unate function s is not closed under
composition, it can be shown to be closed under some restricted composition. One example of such composition is a unate gat e network introduced
by Reddy (1973). We extend the unate gate network to the closed composition as follows. If a circuit C that realizes a unate function is composed of
the elements realizing una te functions, and if the number of inversions in
any path connecting two points in C has the sam e parity (odd or even), th en
such a realization is called a unate composition.
As an example, cons ider two unate function s 91 and 92 such that
gl(Xl' Xl) = Xl + X l and 92(X l'Xz) = X 1X 2' Figure 4.7 shows a un ate cornposition using the elements realizing g l and 92' In this figure , a plus sign

124

Xl

Logic Testing

+
9,

x2

9,

+
92

x3
Figure 4.7
Unate com posit ion

denotes a positive unate va ria ble and a minus sign denotes a negative unate
variable. The functio n J realized in figure 4.7 can be expressed as
J(X I,X2, X3) = 91(91(XI,X2),92(X2,X3))

= (Xl + x 2) + (X2 X3)

It can be easily shown that the following the orem holds.
THEOREM 4.10 The class of unate functions is closed under both composition and stuck-at faults provided that the circui t under co nsideration is
reali zed by a unate composition.
N ext we will apply the property of the closed ness und er stuck-at faults to
the fault detection and location problem. For nontrivial sets oflogic fun ctions that are closed under stuck-at faults, M Ol and L , we will consider the
test complexity (the minimum number of fault-detection and fault-location
tests) and present the universal test sets de rived only from the functional
description of the circuits.
Give n a circuit C, the minimum numbers of tests req uired to detect all
sin gle fault s in C and all mu ltiple faul ts in C are deno ted by os(C) and om(C),
respectively. The minimum numbers of tests required to locate (to within an
indistingui shability class) all single faults in C and all multiple faults in C
will be denoted by }..(C) and }'m(C), resp ectively.
First, we con sider the class of monotone and un ate functi ons . An input
vector X is said to cover the input vector Y if X ha s on es everywhere Y has
on es. A minimal true vertex of a logic function is the input vector that does
not cover any other true vertex except itself, and a max imal fals e vertex of a

The Complexity of Testing

125

func tio n is th e inp ut vector that is not covered by any other false vertex
exce pt itself.

Betan co urt (1973) has shown th at the set of a ll maximal false vertices a nd
minim al tru e vertices of a unate function fa re sulTicient to detect a ny stuckat-O or stuck-at-I fault in any AND/OR realizat ion off . Betanco urt's resu lt
has been extend ed to mult iple fault s a nd unate gate net works by Reddy
(1973). The number of maximal false vert ices plus minimal true vertices of
an n-input unate functio n is at most

where

(;)
denotes the number of com bination s choosing y th ings o ut of x th ings a nd
LzJ deno tes the integer pa rt of z (Akers 1973). Th ese results ca n be extended
to the unate comp osition as follows.
THEOREM4.11 If C is any realization of an It-input unate functi on under
unate composition, then

Th is theorem ca n be pr oved similarly to th e pro ofs in the literature

(Akers 1973; Reddy 1973). using the "closedness under stuck-at faults" of
theorem 4.10 (i.e.. the prope rty that if one or more stuck-a t faults are
introduced into a unate circuit under a unate co mpos ition, the resulting
circuit is still unate).
CORO LLARY4.6 If C is an y realiza tion of a n n-input mon ot one function
under closed co mpositio n with respect to ,A1oh then

126

Logic Testing

Figure4.8
EOR tree realization

Figure4.9
EOR cascade realization

Next we shall consider the test complexity for the class oflinear functions.
A linear functionf(xhx2l ... , xn) can be expressed in the form
Co

EB C1X 1 EB ... EB CnX n

where c, ~ 0 or 1 for i ~ 0, I, ... , n. If Co = 0 (co = I), then the function is

called an odd (even) linear function. There are 211+1 linear functions of n
variables, of which only two are nondegenerate: Xl Efl X, Efl Efl X. and
1 Efl Xl Efl X, Efl .. Efl X n- The two nondegenerate functions are complements of each other. Thus, it is sufficient to consider only the odd linear
functions in order to clarify the test complexity of linear functions. Henceforth, we restrict ourselves to odd linear functions, which will be denoted
by PnMany works on the test complexity of linear functions have been reported. Figures 4.8 and 4.9 show EOR tree and cascade realizations,
respectively. For these circuits, under the assumption that any stuck-at
fault within EOR gates is considered, we have the following theorems.
THEOREM 4.12 (Hayes 1971b) If C is any EOR tree realization of an ninput linear function, then J,(C) = 4.

The Complexity of Testing

THEOREM 4.13 (Seth and Kodandapani 1977)

zat ion of an n-input linear functi on, th en
~m ( C):;:;;

127

If C is any EOR tree rea li-

L3n/2J + 1.

THEOREM 4.14 (H ayes 1971b) If C is a cascade real ization of a n n-input

linea r funct ion , then <5m(C) ~ n + 2.
Under th e more stringent fault assum ption that perm its only stuck-at
faults on the input and o utput lines of EOR gates, we have the following
theorem.
THEOR EM 4.15 (Breuer 1972) He is any EOR tree realization of an n-input
linear function, then <5,{C) = 3.
The linear functi on is usually realized in either cascade or tree structure
of EOR gates. However, th ese realizations are special ca ses of closed
compositions. There exist so me other real izations closed under composition that a re neither cascade nor tree. The next theorem shows th e test
com plexity for such closed compositions .
T HEOREM 4.16 (Fuji war a 1981) He is any realization of P under closed
compo sition with respect to L , then n + 1 tests Io , II" ' " t n are sufficient to
locate o r di stinguish a ll dist inguishable multiple stuck-at faults in C, where
to = (0,0,

, 0),

t,

= (1,0,

,0),

t2

= (0,1,0,

, 0),

t; = (0,

, 1).

Proof Any linear function of n or fewer variables can be expressed in the

form

wh ere a, = or I and A = (ao ,a" ... , an)' Since the class of linear functi ons
L is closed under co mpositio n, any faulty function of linear circuits under
closed compositio n is al so a line ar funct ion of k (k :;:;; n) variables, and
thus it can be expre ssed in the above form. When A = (0, 1, ... , 1), the

128

Logic Testing

linear function PA represents the fault-free linear function p.; Let

PB = bo EB ,, EB'" EB bnxn be a linear function realized by a circuit
under test where b, = or I . Applying the vectors to' t I ' .. . , t n to

we obtain

ao EB an = bo EB b.;
which implies

i = 0, 1, ... , n.
Therefore we can uniquely determine the values of aj> and thus distinguish
all 2n +1 line ar functions PA' applying n + I tests to, t I ' .. . , t..
Since the test set T = {to, t I ' . . . , tn} is independent of the structural
description of a given circuit, it is a universal test set under closed
composition.
THEOR EM 4.17 (Fujiwara 1981) If C is any realization of an n-input linear
function under closed composition with respect to L, then Dm(C) = }'m(C)
= n + I.

Proof By theorem 4.16, Dm(C) ~ )'m(C) ~ n + 1. Therefore, it suffices to

prove that Dm(C) ~ n + I.
Let C be any arbitrary realization of an n-input linear function Pn under
closed composition. If it can be shown that n + 1 tests are necessary to
detect all multiple stuck-at faults on the primary inputs of C, then we can
say Dm(C) ~ n + 1. This will be proved in the following.
When we consider all the multiple stuck-at faults on the primary inputs
n 1
Xl ' X2" '" x ; of C, there exist exactly 2 + - 2 faulty functions PA such that
A

= (0,

,0,0)

(0,

,0, I)

(0,

, 1,0)

129

The Complexity of Testing

(0,

,1,1)

(1,

, 1, 1)

except A = (0, 1, .... , 1)and (1, 1, . ... , 1). Therefore PAis a faulty function if
any only if aj = 0 for some i (1 ~ i ~ n).
Applying all the Z" input combinations of(x j , X2 " ' " x n ) to the equation
n
P A(X l, X 2, , x n) = X l EEl X 2 EEl . EEl Xn , we have 2 equations as follows:
Qo

= 0,

Qo

EEl Q J EEl .. . EEl an = {1

if n is even,
if . dd
I n IS 0
.

The maximum number of linearly independent equations among the

above 2n equations is n + 1. Therefore, n + 1 equations are neces sary to
determine the values aI' a2,"" an uniquely. In other words, /l + 1 tests are
necessary to detect all multiple stuck-at faults on the primary inputs of C.
Hence, we obtain bm(C) ~ n + 1.

II

DESIGN FOR TESTABILITY

Introduction to Des ign for Tes ta bility

With th e development of increasingly complex circuits, boa rds, a nd systems, test ing has become mor e difficult a nd more expensive. As compared
with the increasing cost of testin g, the cost of manufacturing is steadily
decreasing. This suggests th at circu its sho uld be designed to be tested
easily- that testab ility should be adopted as a design parameter. It is no w
generally agreed th at designers shou ld consider design for testability to a
certain extent.

5.1 Testa bility

The testability of a logic circui t has a grea t effect on the cost of generating
and applying tests for the circuit. The greate r the testa bility of a circuit is,
the easier the testing will be. Testability can be defined as the ease of testing
or as the a bility to test easily or cost-effectively.
As discussed in chapt er 4, the probl em of test genera tion is in general N Pcomplete and thus very intr actable for very large circuits. Th is demonstrate s the necessity of designing easily testable circuits. With the ad vent of
VLSI circuits, the need for meth ods of design for testabili ty becomes more
and more urgent. One approach to reducin g the difficulty o f test generatio n
is to consider the testability of a circuit as ea rly as possible in the design
cycle and then to improve its testability. T o accom plish this objective, it is
necessary to have a means of kn owing how easy or difficult it will be to
genera te tests for a circuit and of identifying the a reas of poor testability.
This is called testability analysis.
Te stability an alysis requires a testa bility measure by which the testability
of a circuit ca n be quan tified as accurat ely as possible. The testability
measure must ind icat e th e ease o r the difficulty of test generation in the
circuit in a manner that can be interpreted by logic-circuit designers. The
computational com plexity of the testability measure should be much less
than that o f the test generation. Further, since the informatio n produced by
a testability measure is used to mod ify or to redesign circuits, it must be
accurate enough to improve the ir testability. !fthe testability computation
is fast and if it accura tely predic ts the difficulty of test genera tio n, then the
testa bility measure will be useful in reducing the cost of testing.
Ma ny meth ods for meauring testability in logic circuits have been proposed (see, e.g., Stephe nson and G rason 1976; Ke iner and West 1977; Dejka
1977; Dussaul t 1978; Wood 1979; Goldstein 1979; Ko vijanic 1979; Bennetts
et al. 1981; Berg and Hess 1981; Brglez 1984). T hese meth ods in comm on

Design for Testability

134

introduce two measures, controllability and observability, to estimate

testability. Controllability is defined as a measure of how easily the internal
logic ofthe circuit can be controlled from its primary inputs. Observabilityis
defined as a measure of how easily the internal logic of the circuit can be
ob served at its primary outputs.
The process of test generation consists of the tasks of controlling and
observing internal logic values. Representatives of controlling and observing tasks in test generation are the consistency and D-drive operations of
the D-algorithm, respectively. If each of these tasks is easily achievable, then
the test-generation process can be easily accomplished. This means that
testability has a close relation with both controllability and observability.
The two typical testability measures are those of Stephenson and Grason
(1976) and Goldstein (1979). The measures of Stephenson and Grason were
developed for register-transfer-level circuits, though they can also be applied at the gate level. These measures are normalized between 0 and 1 to
reflect the ease of controlling and observing the internal logic values. On the
other hand, Goldstein (1979) considered gate-level logic circuits and intended to provide measures of the difficulty of controlling and observing the
logical values of internal signal lines. His measures are represented as cost
functions of each signal line in the circuit.

The Testability Measure of Stephenson and Grason (1976)

A register-transfer-level circuit can be assumed to be a network of components (e.g., adders, registers , multiplexers, controllers) interconnected by
unidirectional links. In general, a link may be many conductors carrying
more than one bit of information; however, to simplify our discussion we
assume here that all links have a single conductor. A link is thus referred to
as a signal line carrying logic values 0 and 1.
A controllability value CY(s) and an observability value 0 Y(s) ranging
from 0 to 1 are assigned to each signal line s. The values for the CYs and the
OYs of all the signal lines in the circuit are derived by solving a system of
simultaneous equations with the CYs a nd the OYs as unknowns. These
equations reflect how the CYs and the 0 Ys of input/output lines of each
component are related to one another.
Consider the component illustrated in figure 5.1. The expression used to
calculate CY for each output Zj is

CY(zJ

= CTF

L CY(Xi)
IJ

x -

i=1

(5.1)

Introduction to Design fo r Testability

135

x,

z,

x2

z2
Component

Figure 5.1

where CTF is the controllability transferfactor of the component and n is the

number of inputs of the component. Note that each output controllability is
assigned the same value.
The concept of the CTF is used to acco unt for the potential dim inishing
ofcontrol information as it is propagated through the circuit. Th e CTF of a
component must represent the ability to control out puts of the com po nent
by a pplying input values. It is defined by the following equation, depend ing
only on the input-output relation of the component:
CTF

=.!. f

m j_'

( I _ INj(O) -:: Nil)l)

2

(5.2)

where m is the number of outputs of the component and NiO) and "1(1) are
the nu mbers of input values for which output Zj has output valu e 0 a nd I,
respectively. The CTF of a compo nent ran ges bet ween 0 and I. It takes the
maximum value I when the component has a unifor m input-output relation, and decreases to as the degree of uniformity decreases. For example,
the CT Fs for a NOT gate and an EOR ga te a re I , since N(O) a nd N(l ) a re
equ al. On the other hand, the CTF of an n-input NAND gate is 1/2"-'.
Consider again the component diagrammed in figure 5.1. The expression
used to calculate 0 Ys for each input X, is

OY(x,) = OTF x -

L OY(z)

(5.3)

mj=l

where OTF is the observability transf erfac tor of the compon ent. Note that
each inpu t obse rvability is assigned the same value.
Th e OTF of a component mus t represent the ease of pro pagating a fault
value throu gh the component. It is expressed as

Design for Testability

136

(5.4)
where NSj is the number of input values for which outputs resulting from
changing the input value of x, are different. NS j also means the number of
input values that can sensitize a path from x, to the outputs of the component. The OTF measures the probability that a faulty value at any input of
the component will propagate to its outputs. The values of OTFs also vary
between 0 and l.
For example, the OTF of a NOT gate is 1, since n = 1 and NS 1 = 2. For
an EOR gate, n = 2 and NS 1 = NS 2 = 4, and thus the OTF is l. For an ninput NAND gate, NS = 2 and so the OTF is 1/2n - 1 .
The set of equations 5.1 for all signal lines consists of the controllability
system. The coefficients for the system are derived from equation 5.2 for
each component. The constants (CY = 1)for the system are assigned for all
primary inputs, since primary inputs have perfect controllability. Similarly,
the observability system consists of the set of equations 5.3 for all signal
lines. The coefficients are derived from equation 5.4. The constants (OY
= 1) are assigned for all primary outputs, since primary outputs have
perfect observability. By solving these two system, we can obtain all the
controllability and observability values for signal lines.
For sequential components with storage elements, clock lines, and fanout
points, special rules are considered. Sequential components are modeled
by adding feedback links around the components that represent internal
state. Clock lines that originate as primary inputs to the entire circuit and
that only define transition periods for a component are not considered. For
the fanout points, the controllability and observability values are calculated
as follows: Let S be a fanout line and lef j denote the number of fanout
branches from s. Then the CYs of the fanout branches are deduced by
dividing CY(s) by (1 + logj). This is based on the assumption that the CYs
offanout branches are less than the CY of the fanout line. The observability
value represents the probability that a fault value there can be detected at
the primary outputs, and thus the 0 Y of a fanout line s is defined as
f

OY(s) = 1 -11 [1 - OY(Sj)]

(5.5)

i= 1

where s, (i = 1,2, . .. ,f) are fanout branches of s.

Stephenson and Grason (1976) evaluated the quality of the proposed

Introduction to Design for Testability

137

measure by comparing actual test-generation effort to testability values for

two or three circuits. The correlation appeared to be good.

The Testability Measure of Goldstein (1979)

The logic circuits under consideration are composed of combinational and
sequential standard logic cells, such as AND gates, OR gates, NOT gates,
flip-flops, and more complex logic modules. Goldstein's measures consist of
six functions: combinational 0 and I controllabilities, sequential 0 and 1
controllabilities, and combinational and sequential observabilities. In contrast with the testability measures of Stephenson and Grason (1976),
Goldstein's measures are intended to represent the costs of controlling and
observing internal logic values. These are defined as follows.
The combinational 0 and 1 controllabilities of a signal line s, CCO(s) and
CCI(s), are defined as the minimum number of combinational lines that
must be set in order to, respectively, produce a 0 or a I on line s. A
combinational line is defined as a primary input or an output line of a
combinational logic cell. Sequential controllabilities of a signal line s, SCO(s)
and SCI(s), are defined as the minimum number of sequential lines that
must be set in order to, respectively, produce a 0 or a 1 on line s. A sequential
line is defined as an output line of a sequential logic cell.
The combinational and sequential observabilities, CO and SO, are defined as the minimum numbers of combinational and sequential nodes,
respectively, that must be set in order to propagate the logical value on line s
to a primary output of the circuit.
For all primary inputs I, the costs of controllabilities are defined as
CC(I) = I, CCI(I) = I, SC(I) = 0, and SCI(I) = O. For all primary
outputs U, the costs of observabilities are defined as CO(U) = 0 and
SO(U) = O.
Working breadth-first from primary inputs toward primary outputs of
the circuit, we calculate the controllability of the output line of each logic
cell as a function of the controllabilities of input lines of the logic cell. As an
example, consider a 3-input AND gate with output yand inputs Xl' X2' and
X3' The output y can be set to 0 if one of three inputs is set to O. Hence,

(5.6)
To assign y to 1 we have to set all three inputs to 1. Hence,

(5.7)

Design for Testability

138

Since an AND gate is not sequential, the sequential controllability values

are not incremented by I:

SCO{ y) = min{SCO{xl),SCO(X2),SCO(X3)},

(5.8)

SCI(y) = SCI(xd + SC

(5.9)

(X

1(X
2) + SC 3)

As an example of a sequential-logic cell, con sider a D flip-flop with data

input D, clock line C, reset line R, a nd output Q. The output Q of the flip-flop
can be set to I only if D is set to I, R is held at 0, and a clock pul se is a pplied
to C. Hen ce, we have

CC 1(Q) = CC 1(D) + CCO(C)

+ CC 1(C) + CCO(R),

SC 1 (Q) = SCi (D) + SCO(e) + SCI(e) + SCO(R) + 1.

(5.10)
(5.11 )

Similarly, we have

CCO(Q)

= min{CC1(R) + CCO(C),CCO(D) + CCI(C)

+ CCO(C) + CCO(R)},

(5.12)

SC(Q) = min{SC1(R) + SCO(C),SCO(D) + SCI(C)

+ SCO(C) + SCO(R)} +

(5.13)

I.

Such a calcul ation process from primary inputs to primary outputs

through the circuit is iterated until all the controllabil ity values stabilize
when the circuit has feedback loops external to logic cells.
Th e observabilities are calculated working back ward from pr imary outputs to primary inputs of the circuit. For a 3-input AND gate with inputs
X I ' X2 ' and X 3 and output y, the ob scrvabilities CO( xd a nd SO (xd are
calculated by

CO(x])

= CO(y) + CC 1( X 2 ) + CC I(X3) +

SO( x l )

= SO(y) + SC1(x z) + SC 1( X 3 ).

I,

(5.14)
(S.15)

The observa bility of a fanout line is defined as the minimum valu e of the
observabil ities of fano ut branches. These calcul ation proce sses are iterated
until the observability values sta bilize.
Two typical testability measures with different features have been describ ed a bove. Though existing testability measures (including the measures ment ioned abo ve) seem to pro vide some information ab out circuit
testability, it is not necessarily good information to use in the interpretation

Introduction to Design for Testability

139

of whether or not the actual testability of the circuit is sufficient. The

existing testability measure s have some limitati ons due to the restr icted
information source (circuit struc tu re only) on which they rely. Th e quality
of a testability measure depends on how accura tely it can decide whether a
design is sat isfactorily testable and on the areas in the design where a
modifica tion can ease the test generation.
The testability measure can also be applied to test generati on. As described in chapter 2, test-generation algorithms using heuri stics usually
apply a kind of testability measure to th eir heuristic operations. For
example, in path sensitization various testability measu res are used to
estima te the difficulty of se nsitizing paths.

5.2 Minimizing the Cost of Testing

One way to reduce the cost of testing is to add extra logic. Form erly, the
criteria of logic-design problems were the minimization of hardware cost
and the maximiza tio n of performance [e.g., circuit speed). Ho wever, because
of the increasing testin g cost a nd the decreasing hard ware cost, design for
testability is now becoming a cost -effective approac h to LSI and VLSI

testing.
Since design for testab ility requires extra circuitry, there occur some
prob lems such as increased hardware cost and performance degradati on. It
might be undesirable fo r man y manufacturers to allo cate any significa nt

a rea of a circuit to extra circuitry and to degrade th e speed of the circuit.

T herefore, both the testing cos t an d the cost of design a nd production
should be estimated. In prac tice, an atte mpt should be made to ma ximize
the testability of the circuit a nd to minimize the cost of its testing within the
limita tions of permitted extra ha rdware cost and tolerated performa nce
degradation.
However, if we igno re these penalties, wha t is the op timal design tha t
minimizes the cost of test ing; i.e., to what extent can the cos t of testing be
decreased and the testab ility of circuits can be increased? Th ough th is
prob lem stems from theoretical interest, it is import an t to solve such a
fundamental prob lem in order to develop design techniques for testabi lity.
The complexity or the cost of testing can be classifiedinto two categories:
the ease of test genera tion and the ease of test application. For the first
category, the opt imal design to minimize the test-generation cost can be
accomplishe d by a technique called universal testin g otfunction -indepe nd ent

140

Design for Testability

testing. Universal testing is performed with a test set that is independent of

the function realized by the circuit. Usually, such a universal test set
depends only on the size of the circuit.
In conventional testing, test patterns are generated laboriously for every
circuit under test, since the circuits differ from one another. On the other
hand, in universal testing, test patterns can be predetermined independent
of the function being realized. Hence, these test patterns can be generated
easily at a very small cost. A trivial example of universal testing is exhaustive
testing, which requires that all 2" patterns be applied to the input ofa circuit.
Some design techniques for testability using exhaustive testing have been
proposed. Representative are autonomously testable design (McCluskey
and Bozorgui-Nesbat 1980) and syndrome-testable design (Savir 1980).
Various other designs for nontrivial universal testability have been reported to be successful for circuits with regular structures, such as ReedMuller canonic circuits and programmable logic arrays. Reddy (1972) has
shown that for an arbitrary logic function there exist realizations, based on
Reed-Muller canonic expressions, that have function-independent test sets
that detect all single stuck- at faults in the circuits. The size of test sets can be
only n + 4, for any n-input Reed-Muller canonic circuit, if an extra AND
gate whose output is observable is added. Unfortunately, however, the
Reed-Muller canonic circuits are composed of a cascade of EOR gates
driven by AND gates connected to the circuit inputs, and thus the circuit
delay is so large as to make the method of only theoretical interest.
The other regular structure that can be modified to have universal
testability is a programmable logic array (PLA). The PLA, which is
conceptually a two-level AND-OR, is attractive in LSI and VLSI because of
its memorylike array structure and has become a popular and effective tool
for implementing logic functions. In the first contributions to the design of
universally testable PLAs, Fujiwara et al. (1980) and Hong and Ostapko
(1980) independently proposed designs of PLAs that can be tested easily by
function-independent test patterns. The output responses of the test patterns are also independent of the function realized by the PLA under test.
The number of tests is of order n + m where 11 and m are the numbers of
inputs and product lines of the PLA, respectively. Although the designs of
Fujiwara et al. (1980) and Hong and Ostapko (1980) differ in implementation, the essential idea is almost the same. They both have extra circuitry
to select each row line of AND array, a shift register to select each product
line, and two EOR cascades or trees to check the parity of the row and the
column in the array.

Introduction to Design for Testability

141

Next, we consider the optimal design for ease of test applicaton. Here, we
adopt the number of test patterns as a measure of the cost of applying test
patterns to the circuit under test. The minimum cost never becomes zero,
since at least one test pattern must be applied to the circuit to test it.
Therefore, the minimum cost of test application might be some positive
constant independent of the size of the circuit. If the cost of test application
never increases as the circuit becomes larger, we can say that the circuit
design achieves optimal testability in the test application. Such designs have
been reported by Hayes (1974), Saluja and Reddy (1974), Inose and
Sakauchi (1972), and DasGupta et a1. (1980). Hayes has shown that any
combinational and sequential circuit can be modified by embedding EOR
gates so that five test patterns are sufficient to detect all single and multiple
stuck-at faults in the circuit. Saluja and Reddy (1974) extended the result of
Hayes to obtain minimally testable designs. They presented a design technique to modify a circuit so that it is fully tested by only three test patterns.
Consider a two-input AND gate. It is obvious that three test patterns 01,10,
and 11 are necessary to detect all single and multiple stuck-at faults on the
input/output lines of the AND gate. Hence, we can consider that the three
tests of Saluja and Reddy constitute a minimum test set.
All the design methods mentioned above involve a lot of extra hardware
and very large circuit delays, and thus they are impractical. However, the
results show that ifsufficient extra circuitry can be added to a circuit, we can
design a circuit with optimal testability such that it requires only three test
patterns to detect all single and multiple stuck-at faults in the circuit. We
can further reduce the number of tests from three to two if we restrict our
fault assumption to the more stringent condition that we test only for faults
at input/output terminals of components or modules in the circuit. Kuhl
and Reddy (1978) have shown that by adding extra circuitry and extra
inputs and outputs it is possible to detect all stuck-at faults occurring at
module inputs/outputs with three function-independent tests . Inose and
Sakauchi (1972) developed a method of designing easily testable circuits
that require only two test patterns to detect all terminal stuck-at faults. The
same result was obtained by DasGupta et a!. (1980), who used almost the
same idea as Inose and Sakauchi. These methods are based on the idea of
dual-mode logic, in which a circuit is tested in one mode while the normal
function of the circuit is performed in another mode, with neither mode
interfering with the other.
A different approach, called compact testing, can reduce greatly the cost

142

Design for Testability

of testing. (As mentioned in section lA, compact testing is modeled by the

scheme of figure 1.22.)The circuit under test is usually fed pseudorandom
input patterns. The output responses of the circuit are compressed and then
compared against a reference value . In conventional testing, for each distinct circuit under test a set of tests must be produced by a detailed analysis
of the logic circuits, and these tests must be stored before testing. Compact
testing, however, does not require prior test generation. The test-pattern
generator is independent of the circuit under test and may be implemented
in hardware such as a linear feedback shift register. Hence, the cost of test
generation is considerably reduced. Further, a much smaller amount of
data needs to be compared against the reference value because of data
compression. In this way, compact testing can decrease the cost of testing in
both stages of test generation and test applicaton. One of the most widely
used methods of compact testing is signature analysis.

5.3 Combinational Logic versus Sequential Logic

As described in section 2.4, there are fast test-generation algorithms that
can obtain high fault coverage for rather large-scale combinational circuits.
These algorithms seem to be reasonably satisfactory for combinational
circuits. However, particularly intense difficulties ari se in the case of sequential circuits, where there are problems of setting the initial state of a
circuit and checking its final state after a test.
In section 2.5 we considered test generation for sequential circuits. The
approach taken there was to consider an iterative combinational circuit by
cutting the feedback loops as shown in figure 2.34. Test-generation algorithms for combinational circuits can be applied to this iterative model.
However, we have to consider the following points:
A single fault in the original sequential circuit corresponds to a multiple
fault consisting of the same fault in every cell of the iterative circuit.
In general, the initial state is unknown. Hence, we must set its state to the
initial state required for the test. Controllability is required to set the initial
state of the circuit under test.
The faulty signal must be propagated to at least one of the primary
outputs. If the effect of the fault causes an incorrect final state, we must
supply a sequence of input patterns that will observe the final state of the
circuit. That is, the observability of the internal state of the circuit is
required to check the faulty signal propagated to the flip-flops.

Introduction to Design for Testability

143

Con tr<l l p ------t----~r---

Clo ck

Combi nat i onal

Log ic:

Circui t

SW: Switch

Figure 5.2

Shirt-register modification (from Williams and Angell 1973; <0 1973 IEE E)

For general sequential circuits, the se problems are so difficult th at they

cannot be solved in reasonable computing time if high fault coverage is
desired. However, these problems can be solved completely if a design
approach is adop ted such that the circuits a re designed so tha t it is easy to
set the circuit to any desired interna l state and easy to observe a ny internal
sta te of the circuit. These proper ties rela te to the con trollabi lity a nd observability of the flip-flops or the lat ches in sequential circuits, respectively.
Several design tech niques have been reported to give the a bility to
control and ob serve the internal states of a circuit. A representative of these
techniques is a scan design a pproach using a shift register. (Here, the term
scali refers to the ab ility to shift int o or out of a ny sta te of a circuit.) Figu re
5.2 shows a sca n design techn ique prop osed by Willia ms and Angell (1973).
In figure 5.2 the circuit is designed so tha t it has two modes of ope ra tion: a
normal-function mode and a shift-register mode. A control signal can
switch these two modes . In the shift-register mode, all flip-flops of the circuit
are connected together in a chain to behave as shift register. T herefor e, it is
possible to shift an arbitrary test pa ttern into the flip-flops, and to shift out
the con tents of the flip-flops. Th e shi ft-register mode makes it po ssible to
control a nd observe the interna l sta te easily. By using this mode, the testin g
problem for sequential circuits can be compl etely reduced to one for
combinational circuits. The pr ocedu re for testing such circuits is roughly as
follows:
Switch to the shift-register mode and load the initial state for a test pattern
into the flip-flops.

144

Design for Testability

Return to the normal-function mode and apply the test input pattern.
Switch to the shift-register mode and shift out the final state while setting
the starting state for the next test.
As this procedure shows, one can design any sequential circuit so that it will
be treated as purely combinational by making use of the scan design
techniques.

5.4 Ad Hoc Design and Structured Design

The concept of design for testability has a very wide range. One may desire
the best testability even if the approach is expensive, or one may wish to
enhance testability by a simple and inexpensive method. Hence, there are
many different approaches to design for testability, depending on the degree
of testability required.
Many of the approaches to design for testability can be classified as either
ad hoc or structured (Williams and Parker 1982). The ad hoc techniques are
directed at solving the testing problem for a given design but are not
generally applicable to all designs. These techniques are completely heuristic rather than systematic. They are aimed at making a given design more
testable by a simple and inexpensive method. Hence, they usually cost less
than the structured approaches. The structured techniques are aimed at
solving the general problem with a design methodology that uses a set of
design rules to achieve good testability. These techniques are applied in the
early design state. They are so systematic that when the designer has
completed his design in pursuance of design rules, the expected testability
will be achieved. Usually the structured approaches are more expensive
than the ad hoc methods. However, in return for this added expense, the
procedures of test generation and fault simulation are much simpler and
more straightforward than those used with the ad hoc approaches. That is,
the structured designs generally yield much better testability than the ad
hoc designs.
Many products currently under development have boards containing
many hundreds of devices, including several VLSI chips. It will be difficult
or impossible to achieve the expected fault coverage at a reasonable cost
unless structured design techniques are used for these complex circuits. On
the other hand, to solve this problem in a simple and inexpensive way,
several ad hoc techniques have been investigated.

Introd uctio n to Design for Testability

145

In ad hoc techniques as well as in structured methods, there are two basic

guidelines tha t lighten the tasks of test generatio n and test applicati on. The
first is to divide the circuit to be tested into small one s. Thi s is based on the
"divide a nd conque r" approach. As mentioned in section 4.I, the problem of
test genera tion is in general NP-complete, a nd hence it is conjectured that
the computing time grows exponentially in the worst case as circuits

become larger. Actually, it has been observed Ihat the computer run time to
generate tests is approxima tely proporti onal to the number of gates to the
power of 3 (GoeI19 80). T herefore, dividing a circuit in half would reduce the
test-generati on task to one-eighth for each of the two divided subci rcui ts.
T he second guideline is to enhance con tro llabi lity a nd observability. As
described in section 5.1, the testability of a circui t is closely related to its
controllability and observability, and hen ce enhancing controllability and
observability is very effective in reducing the cost of test generation.
Dividing the Circuit
A circuit can be divided mecha nically or logically. M echanical partitioning
(e.g., dividing a boa rd in half ) redu ces the number of gates load ed on a
board: This goes agains t the cur rent stream ofVLSI technol ogy and defeats
the cost adva ntages of integration.
L ogical partitioning can be accomplished by adding extra logic. Degating
is a simple techn ique for separating modules in a circuit by inserting extra
gates bet ween modu les. Figure 5.3 shows two exam ples of degating logic.
Fo r bot h cases, a degat e line and a n AN D ga te are used to block signal
propaga tion from the oscilla tor and module I by forcing their ou tpu t 10
noncon trollin g values. In figure 5.3(a), when the dega te line is at the value 0
the oscillator is blocked and the extern al clock can propagate thr ough the
OR gate. As a result, all the logic in the circuit can easily be controlled by the
external clock. Similarl y, in figure 5.3(b), the control line can be used to
dr ive directly into module 2 by setting the degate line to O. In this way,
degating ca n disconnect one portion of a circuit from a nother po rtion in
order to make test ing easier.

Another approach relat ed to partitioning is the use of bus-st ructured

architecture. Th is a rchite cture has been used very successfully in microcomputers. Figure 5.4 shows a typical bus-structu red micro comp uter. The
external tester can access three buses, which go to many different modules
(microp rocessor , RO Ms, RAMs, an d I/O inte rface circ uits) on the computer boa rd. Further, it can disconnect any module from the bu ses by

Design for Testa bility

146

Ext ernal
Clock
(a )

Modul e
Module
2

Degate _ _-oJ
Contro l
(b)
F igure 5.3
Dcga ting logic

Dat a

1
External f-Tester

f-f-o

Bus

1 1

foli cr oProcessor

Fi gure 5.4

Bus-structured microcomp uter

RAMs

ROtls

1
Address

Bus

Control

Bus

I /O
f---- To/Fr om
Inter face
I/ O
Ci rcuits ~ Device s

1 1

I
I

Introduction to Design for Testability

147

putting its output into a high-impedance state. These buses can be used to
drive any module, as if they were primary inputs/outputs to that particular
module. Since each module can be isolated from the buses, the partitioning
is accomplished. The buses make it possible to test the computer boards by
applying test patterns to each module separately.
Another technique that partitions the circuit under test is in-circuit
testing, in which each chip on the board is tested independent of the other
chips on the board. Chips not under test are disabled, or their outputs are
forced to a desired state by overdriving them with large currents. Such incircuit testing is usually performed in card testing by a bed-of-nails tester
(Stewart 1977). The "nails" are spring-loaded pins arranged to contact chip
pins on the noncomponent side of the card. That is, the bed-of-nails tester
probes the underside of a board to give a larger number of points for
controllability and observability. For each chip, the appropriate nails
and/or edge pins are driven so as to prevent one chip from being driven by
the other chips on the card, and then test patterns are applied to this
logically isolated chip. The tests are much simpler and the test generation
much easier than in edge-connector testing, since only one chip is tested at a
time. On the other hand, this approach has some drawbacks. Since testing
of interconnections is incomplete and the interactions among chips are
neglected, it is not guaranteed that the board as a whole will work correctly.
Also, care must be taken not to damage the circuit when overdriving it.
Despite such disadvantages, in-circuit testing is very widely used and will
become more necessary because of the increasing complexity of products.
Enhancing Controllability and Observability
A direct approach to enhancing the controllability and observability of a
circuit is to use test points for the purpose of allowing the internal signals to
be controlled and observed. Several techniques to identify how and where
to add such test points have been studied theoretically by Hayes (1974),
Hayes and Friedman (1974),and Saluja and Reddy (1974). Although these
techniques can achieve a high level of testability, they require too many
extra gates and pins to be used in practice.
Another technique based on testability analysis is used in practice to
identify where to add test points. As mentioned in section 5.1, several
testability measures are devised to find the areas of poor testability. A good
testability measure indicates the difficulty of test generation in the circuit.
This testability analysis can identify the areas of poor controllability and

148

Design for Testability

Poor
O-controllability

f'-----------'
N

(a) Original circuit

Extra Test Input

II"W

(b) Additional control gat e

Figure 5.5
Test point for enhancing controllabi lity

poor observability, and hence one can know where to add control inputs
and observable outputs so as to enhance testability.
Using a test point as a primary input can enhance the controllability of a
circuit, and using a test point as a primary output can enhance the observability of a circuit. In some cases, a single pin can be used as both an input
and an output. For example, suppose that an internal node, say N in figure
5.5{a),is predicted to be too hard to set to value 0 by the testability analysis.
Then the O-controllability of N can be enhanced by a straightforward
technique of embedding an AND gate, as shown in figure 5.5(b). Similarly,
the I-controllability can be enhanced by using an OR gate. These extra
AND and OR gates may be replaced by wired-AND and wired-OR,
respectively, though they depend on the circuit technology. Figure 5.6
shows a technique by which the J K flip-flop can be made directly resettable.
This extra facility of resetting (or setting) a bistable flip-flop can significantly
enhance the testability of the circuit. Since resetting the flip-flop ensures

149

Introduction to Design for Testability

c
---I K R

c
KR

Extra
Input
(a) Original circu it

(b) Additional control gate

Figure 5.6
Test po int for direct resetting

that the initial state is known, this lightens the task of test generation for
sequential circuits. The drawback of this general technique for adding test
points is that its applicability has a limit of extra pins.
In addition to these techniques, in-circuit testing approaches such as the
bed-of-nails tester mentioned above also fall into the category oftest points.
Each of nails on the bed-of-nails tester can function as a test point. This
technique is effective in simplifying test generation, but its applicability is
limited since it depends on the phys ical design of electrical products. Boards
that have devices on both sides or that have large numbers of device leads
that are inaccessible to external probes cannot be tested by a bed-of-nails
strategy. Also, systems might be completely sealed in plastic or be contained
in their own cooling units. In such advanced products, in which in-circuit
testing is powerless, structured design techniques may be needed to obtain
good testability.

Design to Minimize the Cost of Test Application

The cost of testing consists mainly of the cost of test generation and the cost
of test application. This chapter focuses on design methods that decrease
the cost of test application. As a measure of the cost of applying test
patterns, we adopt the number of test patterns applied and/or the num ber
of reference comparisons made to test the circuit with the given test patterns. In general, the number of test patterns applied is the same as the
number of references. However, in certain compression techniques the two
values are independent.
Any circu it can be modified by embedding EOR gates so that the
resulting circuit requires only five test patterns. This number of test patterns
can be reduced to three by another approach, called a minimally testable
design. This number, three, is believed to be minimal under the general fault
assumption. However, to test only for faults at input/output terminals of
modules or basic elements composing a circuit, two test patterns are
sufficient for specially designed circuits using dual-mode logic. In addition
to these design techniques, there is a technique in which the response
patterns are compressed and compared with the expected value of only two
bits .
. In this chapter we consider only combinational circuits. since any sequential circuit can be designed so as to be treated as purely combinational
by the scan design techniques propo sed in chapter 8.

6.1 EOR Embedding

Hayes (1974) accomplished the design of logic circuits requiring very few
test patterns for fault detection or location by embedding EOR gates in a
given circuit so that the resulting circuit required only five test patterns. The
procedure is very simple and can be described as follows. (Here, we assume
that a given circuit N is composed only of NAND gates and inverters.)
Modification Procedure
Step 1 Decompose all NAND gates in N into a tree circuit of 2-input
NAND gates and inverters.
Step 2 Remove all inverters.
Step 3 Insert an EOR gate with a controllable input and an observable
output in the input lines of every gate.
The steps of the procedure can be understood through the example
A

f = X1X 2X3 + XIX2X3, which is the same function considered by Hayes.

Design to Minimize Cost of Test Application

151

Figure 6.1
Realizat ion of f

Xl - - X2 - X3

= x,X 2 "' ,

+ 31,;(2)(,

----1

-+-----1~.../

-.-+-+-------------l_-"
f

Figure 6.2
Realizat ion of f after step [

realization of f using on ly NAND gates and inverters is given in figure 6.1.

Each 3-input NAND gate is replaced by two 2-input NAND gates and an
inverter as shown in figure 6.2. After removing the inve rters and inserting
EaR gat es in the input lines of every 2-input NAND gate , we obtain the
circui t of figure 6.3. Note that each EOR gate has a primary input for
controllability and a primary output for observability. The circu it of figure
6.3 can be made to realize f = XtX2X 3 + X tX 2 X3 by assigning C\ = C 2
= C3 = C9 = C to = an d C4 = C s = C6 = C 7 = Cs = t. From this, we
can easi ly see that the circuit modified by the above-mentioned procedure
can be made to rea lize the same function as the origina l circui t by applying 1
or to the control inputs of the EaR gates.
The modified circuit can be decomposed into basic components like
th at shown in figure 6.4. Each ba sic component consists of two EaR gates
with controllable inputs and ob servable outputs followed by a 2-input
NAND ga te. In ord er to fully test such a component. four test patterns 00.
01,10, a nd 11 are needed to detect all stuck-a t faults in each EaR gate, and

152

Design for Testability

Figure 6.3
Fu lly mod ified circuit with additional EOR gates

*00110

*01101

Figure 6.4
Basic component and test patterns

Design to Minimize Cost of Test Application

153

three test patterns 01, 10, and 11 are needed for the 2-input NAND gate.
This is accomplished by the four test patterns not flagged by an asterisk in
figure 6.4. In these test patterns, only one 0 appears at the output y of the
NAND gate. Hence, if the NAND gate is followed by another EOR gate, an
additional 0 must appear at y. This extra test pattern is flagged by an
asterisk in figure 6.4.
These five test patterns have the property that each five-bit sequence on
the input and output lines except the control lines of EOR gates is a
permutation of the sequence 00111. There are ten such permutations,
denoted by the set P = {Po, PI"'" pg} where
Po = 00111,
PI = 01011,

P2 = 01101,
P3=0111O,

P4

= 10011,

P5 = 10101,

P6 = 10110,

P? = 11001,
Ps = 11010,
pg

= 11100.

Now we define Boolean operations on n-bit sequences. If s = a l a2 '" an is

an n-bit sequence, then the complement of s, denoted by S, is the sequence
al iiz ... an' If s = a I a2 .,. an and t = b I b 2 .. b; are two n-bit sequences, then
their AND is

and their OR is

Two sequences Pi and Pi in P are said to be compatible if their NAND

product, on a bit-far-bit basis, is in P. For example, Po' PI = 11100 = pg,

154

Design for Testability

Table 6.t
for all compatible pairs in P

PiPj

Pj
Pi

0
1

5
6

7
8
9

6
5
9

4
4
8

2
3

2
I

7
3

7
6
5

5
3
3

2
1

0
0

4
4

2
I

2
0

I
3

1
0
0

and thus Po an d PI are compatible; however, Po a nd P9 are no t com pa tible,

since Po' P. = 11011 is not in P.The results of Pi' pJor a ll com pa tible pa irs
in P a re shown in table 6.1.
Hayes (1 974) pr esented the fol1owing fundamental lemmas for compatible sequences.
LEMMA 6.1 If two com patible sequences a re applied to a 2-input NAND
gate G, they apply al1 four possible inpu t pa tterns to G.
LEMMA 6.2 Let Pi in P be a pplied to the noncontrol1ed input of an EOR
gate E and let a sequence 5 i of lengt h 5 be a pplied to the control in put of E
such that the output sequence Pj (= Pi EEl 5,) is in P. AI1 fou r po ssible input
patterns are applied to E by 5, and Pi if PI and Pj are compat ible.
Lemmas 6.1 and 6.2 guarantee that al1 stuck-a t fault s in the modified
circuit can be detected by five test patte rns if we can assign five-bit sequences to al1 intern al lines in the circuit that satisfy the fol1owing
con ditions:
The two sequ ences a pplied to the inp uts of ea ch NA ND gate are
compatible.
The two sequences appearing on the ou tpu t and on the noncontrol1ed input
of each EOR gate are com pat ible.

Design to Minimize Cost of Test Application

155

Hayes called this the compatibility constraint. The existence of such assignments satisfying the compatibility constraint is guaranteed by the following
lemma.
6.3 Given any (not necessary distinct) sequence Piand Pj in P, there
exists P in P such that both pairs {Pi' Pk} and {Pj' pd are compatible.
LEMMA

On the basis of the above observation, Hayes (1974) presented a procedure for assigning five-bit sequences to all lines such that the compatibility
constraint is satisfied .
Assignment Procedure
Step 1 Apply any Pi in P to each primary input line.
Step 2 Suppose that Pi is applied to the noncontrolled input of an EaR
gate E whose output is connected to input A of a NAND gate G. If no
sequence has yet been assigned to the other input B of G, select any Pj that is
compatible with Pi and apply Pi EJj Pi to the control input of E. Thus, Pj is
assigned to line A. On the other hand, if Pk has already assigned to line B,
then select a sequence Pm such that {Pi> Pm} and {Pk> Pm} are compatible
pairs. Assign Pi EJj Pm to the control input of E.
Step 3 Repeat step 2 until sequences have been assigned to all lines of the
circuit.
To understand this procedure, consider the circuit of figure 6.3. First, we
assign Po to all primary inputs, i.e., XI = X2 = X3 = Po = 00111. We select
PI' which is compatible with Po, and assign it to line a. Hence, Po EJj PI
= 00111 EB 01011 = 01100 is assigned to the control input C I . Line b must
be assigned a sequence that is compatible with both Po and PI ' From table
6.1 we find that both {PO,P2} and {PI,P2} are compatible pairs . Thus, we
assign P2 to line b. This implies that the output h of the gate has P6' In this
way we can assign five-bit sequences satisfying the compatibility constraint
to all lines, as shown in table 6.2.
From lemmas 6.1 and 6.2 we can easily see that all four possible input
patterns are applied to each EaR gate and the response is observed directly
at the output of the EaR gate, and similarly that all four input patterns are
applied to each NAND gate and the response is observed at the output of
the following EaR gate. Hence, all stuck-at faults in the circuit are completely detected by these five test patterns, and we have the following
theorem.

156

Design for Testability

Table 6.2
Assignment satisfying compatibility constraint
Input

Sequence

x.

Po

.'1: 2

Po

x3
C.
C2
C3
C4

Po

00111
00111
00111

+ PI
Po + P2
Po + PI
Po + PI
Po + P2
Po + P.
P6 + Po
P6 + Po
P9 + P2
P9 + P3

01100
01010
01100
01 100
01010
01100
10001
10001
10001
10010

Cs

C6
C7

C8
C9

c.,

Po

O utput

Sequence

0.

PI

O2

P2

03
04

P.

Os

P2

P.

PI

07
08
09

Po
Po

0 10

P3

P4

P2

010 11
0110 1
01011
01011
0 1101
01011
00 111
00 111
0 1101
011 10
10011

THEOREM 6.1 (Hayes 1974) Every combinational circuit N can be modified by adding control logic to yield a circuit N ' tha t requires five test
patterns to detect alI single and multiple stuck -at faults.
The procedures and results mentioned above can be extended to seq uential circuits. For furthe r discussion see Hayes (1974).

6.2 Minimally Testable Design

Saluja and Reddy (1974) reduced the number oftest patterns further. T hey
showed that any circuit can be modified such that three test patterns are
sufficient to detect all single and mu ltiple stuck -a t fault s in a circuit.
In general, any n-input gate of AND, O R, NAND, or N OR req uires
n + 1 test patterns to detect all single a nd multiple stuck-at faults on its
inputs or its outputs. For a primitive 2-inp ut AND gate, at least three test
patterns, 01, 10, and 11, are needed to detect alI stuck-at faults. Therefore,
three might be considered the lower bound on the numbe r of test patterns
needed to test alI stuck-at fa ults in a circuit. In this sense, the design of
Saluja and Reddy can be said to be the minimally testable design .
First, consider the 3-input AND gate illustrated in figure 6.5(a). Figure

157

Design to Minimize Cost of Test Application

A
B

---Df----
(a)

3-input AND

011
101

001

(b) Augme nt ed circuit

Figure 6.5
M inimally test able 3-input AND

6.5{b)gives a realization in which three input patterns can fully test all single
and multiple stuck-at faults on their inputs or outputs in the circuit. In this
figure the 3-input AND gate has been replaced by two 2-input AND gates,
and a 2-input OR gate ha s been inserted between them with a controllable
input C I and observable outputs 1 , 02 ' and 03' By expanding a 3-input
gate into 2-input gates, we can apply the three input patterns shown in the
figure to each 2-input gate and observe the response at the output of each
gate. It is easy to see th at those three input patterns can test all single and
multiple stuck-at faults in the circuit.
Similarly, we can obtain the minimally testable circuit that realizes an ninput AND gate, as shown in figure 6.6. Three test patterns ar e given in the
figure . For other types of gates, such as OR, NAND, and NOR ga tes, we
can consid er similar circuits. Figure 6.7 illustrates the minimally testable
realization for a 3-input OR gate and its test patterns.
The test patterns for a 2-input AND gate, 01,10, and 11, can be obtained
by applying any two distinct sequences from the set SI = {Oil, 101, llO}.
Similarly, the test patterns for a 2-input OR gate are 01, 10, and 00, which
can be applied by taking any two distinct sequences from the set S2
= {lOO,OIO,OOl} . Hence, the ap plication of any two distinct sequences
from SI (52) is necessary and sufficient to detect any stuck-at fault in the 2-

158

Xl
X

Design for Testab ility

011
01

101

O2
001

x3

001
010

".,l

xn

Dtfu
101

Figure 6.6
T esta ble realiz at io n of n-input gate

A
B

001
010

1
2

all
3

010
Figure 6.7
Min imally test able 3-inpu t O R

001

p _l
0p

Design to Minimize Cost of Test Applicati on

159

input ANDjNAND (OR /NOR) gate. In figure 6.5, 6.6, and 6.7, we can see
th at all test sequences assigned to the gates are taken from set SI or set S2,
depending on whether the gate is of the AND type (AND or NAND) or the
OR type (OR or NOR). Furthermore, these sets SI and S2 satisfy the
following properties:
If 5 is in SI (S2)' then sis in S2 (SI)'
If both 51 and 52 are in SI' then 51' 52 is in S2' where 51 =I 52 '
If both 51 and 52 are in S2' then 51 + 52 is in SI' where 51 =I 52'
Saluja and Reddy also introduced the term compatible in the same sense
as in section 6.1, though it is defined differently as follow s: Two 3-bit
sequences appearing at the two inputs of a gate are said to be compatible if
they can detect all stuck-at fault on its inputs or its output. Hence, for an
AND gate, if 51 and 52 are in SI and 51 =I 52' then 51 and 52 are compatible.
However, all other pairs are incompatible. For example, {1l0,01l} is a
compatible pair, but {110, 1I0}, {11O,00l},and {lOO, OOl} are incompatible
pairs for a 2-input AND gate.
The procedure for modifying a given circuit so that it can be tested only
by three test patterns is as follows. (Here, for the sake of simplicity of
argument, the circuit is a ssumed to be composed only of AND, OR, and
NOT gate s, though the procedure can be applied to more general circuits
including NAND and NOR gates.)
Modification Procedure
Step 1 Change all AND/OR gates in the realization to a tree of 2-input
AND/OR gates.
Step 2 Assign arbitrary sequences from SI U S2 to all the primary inputs.
Step 3 If th e two sequences applied to the inputs of a gate are incompatible, then modify the gate by introducing control logic such th at only the
compatible sequences appear at the inputs of the gate.
There are many cases for this modification. Figure 6.8 illustrates modification for an AND gate with incompatible sequences. Figure 6.8(a) shows
an instance where both sequences are from set SI and are the same. Figure
6.8(b) gives the modification for an instance where one seq uence is from Sj
and the other from S2 ' In figure 6.8(c), both sequences are from S2'
Step 4 Repeat step 3 until all gates in the circuit ha ve been assigned only
by compatible sequences.

160

A
B

Design for Testability

110

110

101
B

0
1
O2
3

001

C2

1
(al

A
B

110

==0---001

- ::~o
A

100

~O~

C1

(bl
C

A ===c>B

001

A ----L-'>.--..:..~----- 1

(el
Figure 6.8
Modi ficatio n for incompa tible pairs

O2
r--~:-/>-.!------- 3

161

Design to Minimize Cost of Test Application

Xl

x2 --4H-----L--.../
XJ

--...--H-------L....-'
f

Figure 6.9
Realization

or f

X 1X 2 X 3

+ ;(1;(2;(3 after step 1

As an illustration of this procedure, consider the circuit realizing

= X 1X 2X 3 + XlX2X3, which is the same example considered in section 6.L

After step 1, we obtain the circuit of figure 6.9. With the assignments Xl
= 110, X2 = 101, and X 3 = 010, two incompatible sequences first appear, as
shown in figure 6.10. Using the modification technique illustrated in figure
6.8, we can finally obtain the circuit of figure 6.11, in which only compatible
sequences appear at the inputs of all the gates. Since all the gates in the
modified circuit are applied by compatible sequences, the tests can detect all
single and multiple stuck-at faults . Thus, we have the following theorem.
THEOREM 6.2 (Saluja and Reddy 1974) Every combinational circuit can be
modified by the addition of control logic to yield a circuit that requires three
test patterns to detect all single and multiple stuck-at faults.

6.3 Dual-Mode Logic

As was shown in the preceding section, any circuit can be modified by the
addition of extra logic so that all single and multiple stuck-at faults can be
tested with only three test patterns. This number, three, is believed to be
minimal under the general fault assumption. However, if we assume a more
stringent fault condition, we can arrive at a method of designing circuits
that require only two test patterns to detect those faults. Inose and
Sakauchi (1972) and DasGupta et a1. (1980) have shown that logic circuits
built with modules they define can be tested with two test patterns. Both of
these approaches are based on the idea of dual-mode logic, where a circuit is
tested in one mode while the normal function of the circuit is performed in
another mode.

162

Design for Testability

110
101

010

Figure 6.10
Com pat ible and incompat ible pairs

100

001
Figure 6.11
M inimally testable realization of f

= x ,x 2 x, + X, X2X,

Design to Minimize Cost of Test Applicat ion

C C
2
1

x
f
y

163

II

+Y
x'Y
ll'y

(b)

(a)

Figure 6.12
Mod ule M ,

First, consider the module M I , illustrated in figure 6.12(a). The module

ha s two inputs (x and y) and two control inputs (C l and C 2 ) . It realizes three
functions (OR, NAND, and AND) by ch an ging the control inputs C l and
C2 as sh own in figure 6.12(b) . Such a module is called a function-con version
unit by lnose and Sakauchi (1972). The logic circuits of the proposed
method are constructed by using such a function-conversion unit as shown
in figure 6.13. The normal function of the circuit can be realized by converting all modules in to NANDs, since NAND is functionally complete. When
the circuit is tested, all the modules in the circuit are co nverted into ANDs
or ORs. After converting all the modules into ANDs (i.e., setting C l = C 2
= 1), we apply the test pattern (X I , X 2, ... , x n ) = (I, I, .. . , 1). This test pattern can detect any multiple stuck-at-O fault at input/output terminals of
modules provid ed that the control inputs are fault-free, since such a stuckat-Ofault cau ses at some output of the circu it. Sim ilarly , after changing all
the modules into OR functions (i.e., setting C 1 = C 2 = 0), we apply th e test
pattern ( X I,X2 ""'X n) = (0,0, ... ,0) , which can detect any multiple stuckat-l fault at input/output terminals of modules provided that the control
inputs are fau lt-free. Hence, for a circuit b uilt with such modules, as shown
in figure 6.12, two test patterns-all zeros and all ones-are sufficient to
detect any stuck-a t-O or stuck-at-l fault at input/output terminals of the
modules except control lines.
This is illustrated by the circuit realization of f = X I X 2 as shown in
figure 6.14. The test patterns a re (C l , C2 , X l , X 2 ) = (0,0,0,0) and (I, I, 1, 1).
Suppose there is a stuck-at-I fault at input A of module 2. When the test
pattern (0,0,0, 0) is applied, all the modules are converted into ORs and

164

Design for Testability

C1 C2

xl
x2

{h-- . .=5-

C1 C2

C1 C2

...

=lY=---

X
n

-u-

'0'

Figure 6.13
Logic circuit built with mod ules

Figure 6.14
Realization of f

= x I <l X z using modul e All

Design to Minimize Cost of Test Application

165

thus the above fault causes value 1 on the output of module 2, which
propagates to the output of the circuit. From the principle of duality, we can
see that the other test pattern, (1 , 1, 1, 1),detects a stuck-at-O fault at input A
of module 2. However, it is not guarant eed th at the above tw o test patterns
can det ect any single stuck-at fault at control lines C 1 and Cz . For example,
consider a stuck-at-l fault at line C 1 Obviously, the test pattern (1, 1, 1, 1)
cannot detect the fault. Further, the other test pattern, (0,0,0,0) , cannot
detect it either, as figure 6.15 shows. It has been proved by DasGupta et a1.
(1980) that at least four control inputs are necessary to detect all single
stuck-at faults, including control input faults, with two functionindependent test patterns.
A dual-mode logic circuit proposed by DasGupta et a!. (1980) also has
the structure shown in figure 6.13. A dual-mode logic circuit is composed of
modules, and extra control inputs are common to all these modules.
DasGupta et a!. showed that four con trol inputs are necessary and sufficient
to derive a dual-mode logic circu it that allows function-independent testing
of faults at the terminals with two predefined test patterns. Table 6.3 is the
general truth table of du al-mode logic modules with four control inputs: C 1 ,
Cz , C3 , and C4 If a circuit with input XI' XZ, ... , x, is built with modules
who se truth table is that shown in table 6.3, then we can show that two test
patterns, (Cl,CZ,C3,C4,XI"",Xn) =(0, ... ,0) and (1, .. . ,1), detect all
single stuck-at faults at input/output terminals of modules. From table 6.3

166

Design for Testability

Table 6.3
Truth table of dual-mode logic modules
C1 C2 C3 C4

dtd m- t dm

0
0
0

0
0
0

0
0
0

0
0
0

o ...... 0
o ...... 0

o test

0
0
0
0
1
0
0
1
0
1
1
0
1
I
I

0
0
0
1
0
0

0
0

...... 1

1
0
1
0
1
1
0
1
1
1

1
0
0
1
0
0
1
1
0
1
1
0
1
1

o ...... 1

0
1
0

x ...... x

j}

At least one
segment for an
arbitary function

n
1

x ...... x

o ...... 0

...... 1
...... 1

0
1

1 test

it is easily seen that if the test pattern (C" C" C 3 , C4 , d , ... , d m ) = (0, ... ,0)
(or (1,... , 1))is applied, any pattern of In or fewer stuck-at-I (or s-a-O) faults
at d , d" ... , dm changes the output to the complement of the expected
output, where d , d z , ... , dmare inputs of the module. Hence, any stuck-at-I
(or s-a-O) fault at noncontrol input/output terminals of modules is detected
by the test pattern (0,... , O)(or (I, ... , I)). Similarly, in table 6.3 all the input
patterns Hamming distance I from (0,... ,0) and (1, ... , I) have the different
output values from that of (0, ... ,0) and (I, ... , I), respectively. Hence, any
single stuck-at fault at control inputs can be detected by test patterns
(0, ... ,0) and (1, ... , I). Consequently, the following theorem holds.
THEOREM 6.3 (DasGupta et at. 1980) In any n-input dual-mode logic
circuit built with modules whose truth tables are as shown in table 6.3, two

Design to Minimize Co st of Test Appli cat ion

167

C1 C2 C C4
3

Modul e

(a l

x .. y

0 0 0

0 0
0 0
0 1
1 0

0 1
1 0
0

0 0

1
0
0
1
0 1
1 0

I
1
1
0

0 1 1
1 0 1
1 1 0
I 1 I

1
1
1
0

0
0
1
0
I
I

0
1
0
1

1 I

} ,.y

0
0

1 1

xy

{bl

Figure 6.16
Mod ule M,

test patterns, (C t , C2 , C3 ,C4 , X t , , x n) = (0, . .. ,0) and (1, . .. ,1), can detect
any pattern of stuck-at faults at the input/output terminals of the cir cuit or
the modules, provided that faults in the control inputs affect, at most, one
control input of each module.
As an example, cons ider the module M 2 illustrated in figure 6.16, which
has two inputs (x and y) an d four control inputs, realizes a NAND function
in the normal mod e, and satisfies the truth table 6.3. For any dual-mode
logic circuit constructed by this module, two test patterns, (0, .. . , 0) and
(1, ... , I), detect all single stuck-at faults at inpu t/output terminals of
modules in the circuit.

6.4 Testing with Fixed Refe rence Values

In the preceding sections, we con sidered severa l deign approaches to minimizing the number oftest patterns. Each technique described there achieves
a very low cost of test application. However, all require so much extra

Design for Testability

168

Refer ence Value

Circuit
Comparator

Under
Test

Tes t Sequence

Faul ty/ Good

Figure 6.17

Testing scheme for da ta com pression

hardware. including gates and I/O pins . that they can hardly be put to
practical use. This section presents another approach (described in Fujiwara
and Kino shita 1978) to minimizing the cost of test application without
changing or modifying the circuit under test. The approach is a test -datacompr ession technique in wh ich the response patterns are compressed a nd
compared with the expected value of only two bits .
The scheme considered here is illustrated in figure 6.17. A sequence of test
patterns are appl ied to the circuit under test. The response of the circuit is
transformed by some data-compression function and then compared
again st a previously obtained reference value. The circuit under test is
certifi ed to be fault-free if and only if the two values are identical.
We first consider single-output combinational circu its. In the datacompression box of figure 6.17. data-compression functions called count
functions are used. Let R = r l t z .. .rm be any binary sequence. Here we
con sid er the count functions
m

c[{R) =

Lr

i- I

EB r j

(tr ansition co unt).

j= 2
m

c2 {R) =

L ~ -l . rj

(rising ed ge count),

i= 2

c3(R) =

Lr

j_

1 .

r;

(falling edge count).

j= 2

Let T be any multiple-fault test set for a single-output combinat ional

circu it. Let T O(T I ) be all test patterns in T producing output 0 (1). and let n
= IT I.no = ITol.andn[ = IT1 1where IAI is the ca rdinality of the set A. We
define a test sequence denoted by rt.T with resp ect to the test set T as

Design to Minimize Cost of Test Application

169

In the schemes proposed in thi s section, one or more count functions will
be used to implement the data compressor shown in figure 6.17. In general,
Ci , ... , c j ) , where m ~ I, of count
we assume that an m-tuple C = (c,',2
~
functions is being used for testing.
For a given class offaults, a circuit under test is called testable by a count
function C and a test sequence S if, for every fault in the class, the value of C
is different from the reference valu e. .
Before we consider testing schemes that provide considerable compre ssion of test response data such that the respon se d ata can be compressed into two bit s independent of the number of test patterns, note the
following fundamental lemma, which gives an equivalence class of count
functions.
LEMMA 6.4

The following cond itions are all equivalent:

(I) R=OPlqforsomep >Oandq>O.

(2) c2 (R) = t and c3 (R) = O.
(3) C I (R) = 1 and c2 (R) = 1.
(4) cl(R) = 1 and c3(R) = o.
Proof It is obvious that condition 1 implies cond itions 2-4.
Assume that condition 2 holds, i.e., c 2 (R) = 1 and c 3 (R) = O. Then, c3(R)
= 0 implies that R has the form OPt q wh ere p ~ 0 and q ~ O. Moreover,
c2(R) = 1 implies that both p and q are positive. Therefore, we have that
condition 2 implies condition 1. From the definitions of count functions CI'
c2 ' and c3 we have cI(R) = c 2 (R) + c3(R). Hence, it is obvious that conditions 2, 3, and 4 are all equivalent. _
THEOREM 6.4 Let T be any multiple-fault test set for a single-output
combinational circuit. Then the circuit is testable by the test sequence aT
and any distinct pair (Ci' Cj) of count functions. The reference values of C I' C2'
and c3 are I, 1, and 0, respectively.

Proof Let T = {TO, T I }, TO = {t?,t~, ... ,t~o} ' and

T I = {t f, ti, ..., r;, }. The test seq uenee (J.T has the form

and the fault-free response R is ono+ 11"' + I.

Let (ci , cJ be any distinct pair of count functions, and let e, and ej be
reference values of c, and cj , respectively. Then, from lemma 6.4, R
= O"?" II"' + I implies ci(R) = e, and cAR) = ej

170

Design for Testability

Conversely, assume that another sequence S also has ci(S) = e, and cAS)
> 0 and q > 0 and
p + q = 11 + 2. If both sequences Sand R are distinct, then either no + 1
> p or 11 0 + 1 < p. In the case of 110 + 1 > p, the output value of test t? in S
must be 1. Thus, the leftmost value of S is also 1, and this contradicts that S
has the form OPI Q for p > 0 and q > O. In the case of no + 1 < p, the output
value of test t ~ in S must be 0, and similarly we have the contradiction.
Hence, Rand S must be identical. This implies that any response S
satisfying Ci(S) = ei and cAS) = ej is only 0"0+ II'" + 1
= ej' Then, from lemma 6.4, S has the form OPI Q where p

If we use the test sequence (J.T of length n + 2, the testing schemes

suggested in theorem 6.4 require storing only two bits of responses, since the
reference values of count functions are constants 0 and 1. Thus such testing
schemes have the following properties: Considerable compression of test
response data is achieved; very simple test equipment is required, and it is
independent of the circuit under test; and complete fault detection is
provided.
When a logic circuit has more than one output, the problem of compressing test data is not straightforward generalization of the single-output case,
because all the outputs are assumed to be monitored simultaneously. Thus,
it is no longer possible to order test patterns to suit individual outputs. In
Fujiwara and Kinoshita 1978 it was shown that, for multiple-output combinational circuits, response data can be compressed through the use of
generalized count functions. For more details, see the literature.

Design to Minimize the Cost of Test Generation

The optimal des ign to minim ize the cost of test generation is achieved by
elimina ting the expensive stage of test generation. This can be accomplished
by a technique called universal testing or function-independent testing, in
which test patterns can be predetermined independent of the function being
realized. Some of the techniques mentioned in chapter 6 belong to this
approach. However, though these techniques are of great theoretical interest, the enormous hardware requirement is practically prohibitive.
If it is required only to reduce the cost of test generation within the
limitations of permitted extra hardware complexity and tolerated performance degradation, an attempt should be made heuristically through ad
hoc methods such as inserting test points. Hayes and Friedman (1974)
proposed a method for selecting test points to reduce the number of test
patterns for fault detection in combinational circuits, but the number oftest
points required is still large. Coy and Vogel (1981) developed a method of
inserting test points to simplify test generation. The approach of Coy and
Vogel-breaking up pairs of reconvergent paths by test points-is based
on the fact th at the existence of reconvergent paths may force faults to
become difficult or impossible to detect.
In this chapter, we consider design for universal testability in which no
test generation is required. A trivial example of universal testing is exhaustive testing, which requires that all 2" patterns be applied to the inputs
of the circuit under test. One approach based on exhaustive testing is the
partitioning of the circuit into small parts by multiplexing; another is
syndrome-testable design. Other approaches to universal testing involve
designing circuits with regular structures, such as Reed-Muller canonic
circuits and programmable logic arrays.

7.1 Partitioning and Exhaustive Testing

Exhaustive testing requires the application of all 2" input combinations for
n-input circuits. It is obvious that difficulty arises immediately when 11
becomes large. Exhaustive testing might be tolerable for n ~ 20, which is
equivalent to about I second of testing with a I-MHz machine. For 11 > 20,
however, the problem is no more solvable in a reasonable amount of time .
A common approach to solving a large problem is to partition the
problem into small parts, find solutions for the parts, and then combine the
solutions for the parts into a solution for the whole. This "divide and
conquer" approach often yields efficient solutions to problems in which the

172

Design for Testability

subproblems are smaller versions of the original problem. Testing is no

exception to this rule . The problem of exhaustive testing for large circuits
can be overcome by partitioning the circuit into subcircuits such that every
subcircuit is small enough to be tested exhaustively in a reasonable amount
of time .
This was considered by Sakauchi et al. (1975), Bozorgui-Nesbat and
McCluskey (1980) (see also McCluskey and Bozorgui-Nesbat 1981), and
Oklobdzija and Ercegovac (1982). Their methods enhance the testability of
a circuit by partitioning it into subcircuits with the following properties:
Each subcircuit has few enough inputs that all possible combinations of its
inputs can be applied to test it.
It must be possible to directly control the inputs to each of the subcircuits
and to directly observe the responses of the subcircuits.
The method proposed by Sakauchi et al. (1975) is based on the concept of
bypassing subcircuits. Figure 7.1 presents the block diagrams of the implementation of this technique. In the figure, multiplexers are used to propagate the values on the inputs directly to the outputs by bypassing the
subcircuit. Figure 7.1(a) shows the case that satisfies

where 11", nj , and no are the number of primary inputs, the number of
internal linking inputs, and the number of outputs of the subcircuit, respectively. Figure 7.1(b) shows the implementation in the case of nj > 110 ,
In order to test one of these subcircuits, multiplexers are controlled so
that all subcircuits except the one under test are bypassed. This makes it
possible to access directly all the inputs and outputs of the subcircuit under
test from outside the circuit, and thus the subcircuit can be tested exhaustively. In this way, exhaustive test ing for all subcircuits is performed by
controlling multiplexers in the whole circuit. To speed up the testing of the
whole circuit, some subcircuits are tested simultaneously if the propagation
paths associated with those subcircu its are disjoint or separated from one
another.
The approach of Bozorgui-Nesbat and McCluskey (1980) is similar. Let
us decompose a circuit G with input X and output Y into two subcircuits,
G1 and G2 , with disjoint sets of inputs and outputs and internal linking
buses (figure 7.2). For direct access to linking lines, some multiplexers are
added, as shown in figure 7.3(a). In normal circuit operation, the internal

Design to Minimize Cos t of Test Ge nera tion

Pr imary

I nternal
Linki ng

Input s

Inputs

Subct rcut t

(aJ

173

In t erna l

Pri ma ry Linking
I nput s
Inputs

Subc1rcu1t

(b)

fi gure 7.1
Bypassing subcircuits {Sakauchi et at 1975; AFI PS 1975)

Fi gure 7.2
Part itioning (Bozorgui-Nesbat and M cClu skey 1980; IEE E 1980)

174

Design for Testability

Subcircuit G]

(a)

Subci rcui t

G]

I==~x~

l==========~
M

~======:::j ~ ~==::::::j

Subci rcuit G
Z

(b) Nonna l mode.

Subc1 rcu1 t Gl

Subcl rcul t GZ

(c) Test mode for subclrcult G1,

Figure 7.3
Partitioning scheme using mul tip lexers [Bozo rgui-Nesbat a nd McCluskey 1980;
IEE E 1980)

Design to Minimize Cost of Test Generation

175

input of each subcircuit is connected to the internal output of the other

subcircuit through the linking multiplexers and the external output of each
subcircuit is routed to the output pins via the output multiplexers. This is
illustrated in figure 7.3(b). On the other hand, in order to test subcircuit G1 it
is necessary to access the linking lines directly from (to) external inputs
(outputs). This is performed by controlling the linking multiplexers as
shown in figure 7.3(c). In this mode of testing, test patterns are applied
directly to G1 from external inputs independent of the other subcircuit, G2 .
Hence, exhaustive testing for G1 is possible. Similarly, subcircuit G2 can be
tested exhaustively by controlling multiplexers.
In the implementation shown in figure 7.3, the width of each link must be
less than the width of the external input/output of the corresponding
subcircuit. Moreover, in order to make such a decomposition meaningful,
the width of the input of each subcircuit must be less than the width of the
unmodified circuit input.
Bozorgui-Nesbat and McCluskey (1980) also presented a generalized
method for including an arbitrary number of partitions instead of two.
Figure 7.4 is a block diagram of a circuit partitioned into three subcircuits.
McCluskey and Bozorgui-Nesbat (1981) proposed a technique for designing autonomously testable circuits. The proposed method is based on
built-in testing in which test patterns are applied internally by built-in test
equipment. A linear-feedback shift register (LFSR) is used as built-in test
circuitry. All 2n input patterns except the (0,0, ... ,0) pattern for an II-input
circuit can be generated from an LFSR. Further, an LFSR can compact the
output pattern ofthe circuit under test by generating a "signature," which is
compared with the precomputed signature of the fault-free circuit. In this
way, LFSRs can be used as both the test-pattern source and the response
evaluator.
Figure 7.5 shows an example of a 3-bit reconfigurable LFSR module
presented by McCluskey and Bozorgui-Nesbat (1981). The block M realizes three functions, A, B, and A EEl B, depending on the values of the control
inputs Nand S. Figure 7.6 illustrates these three modes corresponding to
the three functions of each block M. In the normal mode with N = 1, the
module behaves as a register, i.e., a set ofD-flip-flops. This is shown in figure
7.6(a). In the test mode with N = and S = 0, the module realizes a 3-bit
LFSR, shown in figure 7.6{b). Here the LFSR transits all the possible seven
states, and thus the output of this module provides all the possible input

176

Design for Testability

:'J
.;:;

'u
.D
;:I

'"

"~

-5

...

.5

;:I

...u

U
..c

;:I

en

ea

"Of .5

. '"

.... 0

~ :~

;:I

"'" Q.~
t;:

Design to Minimize Cost of Test Generation

:~
II

177

N S

AG>B

Figure 7.5
Reconfigurable 3-bit LFSR module (McCluskey and Bozorgui-Nesbat 1981; IEEE 1981)

patterns for the subcircuit being tested . This mode operates as a test-pattern
generator. In general, there is a method of designing an LFSR that generates all 2" - 1 possible input patterns. The interested reader is referred to
Barzilai et al. 1983.
Figure 7.6(c) shows the third mode with N = 0 and S = I. In this mode
the module functions as a parallel signature analyzer. Generally, an LFSR
performs the basic operation of divi sion by a polynomial in G F(2) (Galois
fields of two elements) (Peterson and Weldon 1972). Hence, data cornpression of a sequence of output responses is equivalent to superpositio n of
po lynomial division processes. T he fina l signa ture is composed of the
modulo 2 summation of remainders from all the division processes. There
are severa l LFSRs associated with polynomials in GF(2). The LFSR shown
in figure 7.6(c) is an example of the LFSRs for parallel data compression.
The techniques mentioned above append multiplexers to the circuit so as
to partition it into manageable subcircuits. These subcircu its can be tested
exhaustively, so that test-pattern generation and fault modeling can be
elimin ated. However, these methods have drawbacks; the added multiplex-

178

Design for Testa bility

(aj Normal Operati on

.------~

0 Q 1 - _ - - - 10 Q 1-....----lO

1
2

(bj Test Pattern Generator

11

1
2

1
3

(c) Output Signature Analyzer

Figure 7.6
Various modes of 3-bi[ LFSR mod ule (McCluskey and Bozo rgui-Nesbat 198 1;

IEEE 1981)

Design to Minimize Cost of Test Generation

179

ing circuitry introduces an additional delay in the signal-propagation path

and a considerable hardware overhead.
Oklobdzija and Ercegovac (1982) presented a circuit-level approach for
enhancing the testability of logic circuits. The method proposed there is to
change certain gates within a given logic circuit into "controllable gates" so
that the controllability and the observability of the circuit are improved.
These controllable gates are used in partitioning the circuit into relatively
small subcircuits.
A controllable gate is defined as a gate with a control input e whose
output yis equal to j'[x.i xy, ... ,x.)ife = Kandtog(xp)ife = K,wherelis
the function of the gate in the normal mode, 9 is a function of the priority
input x p (1 ~ p ~ n) and K is a constant 0 or 1. Since g(x p ) is either x p or xp'
the value on the priority input is transmitted directly or in the complemented form to the output of the controllable gate. This makes it possible
to block all paths through the inputs of the gate except x p and to create the
path through x p ' Hence, these controllable gates can be used to create the
paths to and from an arbitrary subcircuit in order to control the inputs and

observe the outputs. The controllable gate can function as a low-cost

multiplexer.
For NAND gates, Oklobdzija and Ercegovac (1982) presented the following three types of controllable gates:

I.

Q."b
{a_

ife ~ 0
if e = 1,

Q."b
12 = { X

ife = 0
if e = I and a' b = 0,

Q."b
13 = { X

ife
ife

1.

The noMOS implementations of these controllable NAND gates are shown

in figure 7.7. Obviously, the concept of a controllable gate can be applied to
other types of gates and to different technologies.
In order to enhance the testability of a circuit, Oklobdzija and Ercegovac
(1982) proposed to partition it into small subcircuits by replacing some of

the gates with controllable gates capable of blocking or creating propagation paths. In order to test a partitioned subcircuit, the logical values on
the control lines of controllable gales are determined in such a way that the

Design forTestability

180

,
a

---I

--1

f-c

f-c

b-----l

(a)

f--

--j

(b)

'1

'2

oo

Figure 7.7
The nMOS implementation of various controllable NAND gates (Oklobdzija and

Ercegovac 1982; IEEE 1982)

Design (Q Minimize COSt of Te st Generation

181

Figure 7.8
Syndrome of va rious a-i nput gates

subcircuit can be accessed from the outside th roug h the paths created by the
controllab le gates . The text pa tterns for this subcircuit are ap plied from the
prim ary input s, a nd the responses are observed on the primar y outputs.
That is, the subcirc uit is tested ind ependent of the other parts of the circuit.
Th is 'process is repeated for all subcircuits until the whole circuit is tested.
As figure 7.7 sho ws, each controllable gate has two extr a devices. These
extra devices cau se some speed degrad ati on; however, the delay here is
much smaller than that resulting from the addition of an extra gate. The
overhead of exira I/O pins for the control lines can be reduced by using a
shift register from which the cont rol lines are cont rolled. Th e con tent of the
shift register is load ed serially from the outside through a n additional pin.
Each cell of the shift register has control ove r one or several controllable
gates.
7.2 Syndrome-Testable Design
The synd rome S(J ) of a logic function f is defined as

S(J)

K~!)

where K(J) is the number of min terms realized by the functi on f and n is
the number of inputs of [. Figure 7.8 shows the syndro me of vari ous n-input
gates. Obviously 0 " S(J) " 1, and hence the storage requ irement for test
dat a is drastically redu ced in syndrom e testing,

182

Design for Testability

Reference
Syndrome

Circuit

Syndrome

Under
Test

Register

!
Comparator

f- Good/Faulty

Figure 7.9

Testing scheme for syndrome-testable circuits

A fault in a logic circuit is said to be syndrome-testable if the syndrome of

the circuit induced by the fault does not equal the syndrome of the fault-free
circuit. Further, a logic circuit is said to be syndrome-testable with respect
to a class of faults if any fault in the fault class is syndrome-testable. The
class offaults considered here is the single stuck-at type. The testing scheme
for syndrome-testable circuits is shown in figure 7.9. All 2" possible input
patterns are applied to the circuit under test exactly once, and its syndrome
is recorded by counting the number of ones appearing on the output of the
circuit. If the actual syndrome equals the expected syndrome, the circuit is
fault-free; otherwise the circuit is faulty.
Savir (1980) reported a method of designing syndrome-testable circuits.
Here we consider the syndrome-testable design of two-level (AND-OR)
circuits. We assume that the circuits are irredundant and that all AND
gates realize prime implicants of the functions realized by the circuits.
Consider the function f realized by the circuit diagrammed in figure 7.10:

The product terms XIX"~ x,x4 , and x,x4 are all prime implicants.
Any stuck-at-O fault at the input to an AND gate causes the prime
implicant realized by the AND gate to disappear. For example, the s-a-O
fault at line c causes the function f to be the faulty function

Since S(J) = :g '" ,76 = S(J'), the fault c/Ois syndrome-testable. Any stuckat-I fault at the input of an AND gate is a growth fault. The fault c/1
changes the term x,x4 into x4 , and thus it induces the faulty function

Design to Minimize Cost of Test Generat ion

183

Xl - - - - - - l
x ------1..--.-/
2
b
X

_------r____

}-----l

Figure 7.10
T wo -le vel " ir,," it

Since S(f") = l~ -:f. S(f), th e fault ell is synd rom e-testabl e.

For a n irredundant circu it, such a disappearance fault and a grow th fault
change the number of minterms realiz ed by the function , and thus they a re
all synd ro me-testa ble. Ho wever, there exists a stuck-at fault th at doe s not
chan ge th e number of min terms, and hence its syndrome. Such a fault exists
onl y a t a fan out poin t of a primary input, say Xi ' Suppose tha t the function is
expr essed in the form
F = A . Xi

+ B Xi + C

where A, B, a nd C do no t depend on variable Xi and where not bo th of A and

B a re zero . It can be easily seen th at a stu ck-at fault (s-a-O or s-a-l) at the
fan out point X i will cau se the faulty syndrome to be identical to the fault free synd ro me if and onl y if

S(AC) = S(BC).
Fo r example, conside r th e stuck-at-O fault at the fanout point x 3 sho wn in
figure 7.10. The fault -free fun ction is

a nd hence

f = A X3 + B X3 + C
where A =

x4 B =

x 4 , a nd C =

X 1X 2'

Computing S(AC) a nd S(BC), we

184

Xl

Designfor Testability

--------i"

x2 - - - - - - L . . /
c
f

Figure 7.11
Syndrome-testable circuit

have
S(AC)

= S(X4 . XI ' X2)

_...2...

16'

S(BC) = S(X4 . XI' X2)

=

66'
1

The faulty syndrome induced by the fault X3 /0 is identical to the fault-free

syndrome, and thus such a fault is syndrorne-untestable.
Savir (1980) showed that every two-level irredundant combinational
circuit can be made syndrome-testable by attaching control (extra) inputs
to the AND gates. For example, the circuit of figure 7.10 can be made
syndrome-testable by inserting one extra input c to the second AND gate,
as shown in figure 7.11. The new function is

For thi s modified circuit, the stuck-at fault at

since

X3

or

X4

is syndrome-testable,

S(CX 3. XI x 2 ) - S(>':3 . X I xz)

and
S(CX4 . XI X2) - S(X4 . X I x 2).

Hence, the modified circuit of figure 7.11 is syndrome-testable. The effect of

adding extra inputs is to change the "size" of the prime irnplicants, and thus

185

Design to Minimize Cos t of Test Generation

to create the desired syndro me. In our example, the second product term
has shrunk as a result of the addition of input c. In thi s way the circuit ca n be
made syndrome-testable.
Sa vir (1980) presented a method of mod ifying the irredunda nt function
given in a sum of produ cts form by addi ng a nearly minimal num ber of
con trol inputs so that the resulting function is syndro me-testa ble. Roughly
speaking, the procedu re is to repeat the following process until the function
becomes syndro me-testabl e. That is, the process is to creat e a new function
F ' fro m the present function F by adding a new con trol input o r an already
added contro l input to a n ap prop riate prime implicant of F so that

IT(F')I < IT(F)I

whe re

T (F)

{xil F is syndrcme-untestable in x.}.

As an illust ratio n of the procedure, consider the following function

borrowed fro m Savir (1980):

Let f Ul denote the j th mo dified function, a nd let pOl = f. The first step is to
find all the vari ables Xi in which pOl is syndrome-untestable. Th en we have

T(f(OJ)

{x " x" x" x., x , }.

The next step is to add a new input C 1 to an ap propriate prime implicant of

p o, so that IT(fllJ)1 is minimized, where fUl is the new modified function.

In our examp le, c, is added to the first prime implican t, and we have

T(fllJ) = {x" x. ,x,}.

Next, we try to add c, to one ofprime implicants so as to red uce the size of
T(fllJ). Add ing c, to the fou rth pr ime implicant, we ha ve

T(fl")

{x, }.

To make X 3 syndrome -testable, we need a new input

the seco nd prime implican t, we have

C2'

Appending C2 to

186

Design for Testability

xl
x
2
C

x3

f(3)

x
4

Xs

Figure 7.12
Syndr ome-test able design

T(j(3)) = ~ (empty).
Hence, we have the syndrome-testable design shown in figure 7.12.
Savir (1980) also presented a me thod for modifying the desig n of a general
combinational circuit so that it will be syndrome-testable. H owever, there
was no proof th at every multilevel combinational circuit can be m odified to
be syndrome-test able by extra input insertions. Markowsky (1981) showed
that a combinational circuit can always be modified to be syndrometestable for sing le st uck-a t fau lts. Savir (1981) presented a method for
partitioning a given logic circuit into a minimal number of subcircuits
consisting of maxi mal unate componen ts that are syndrome-testable
by themselves. Barzilai et al. (1981) considered syndrome testing for
multi-o utpu t circuits and proposed the "weighted syndrome sums approach," which is based on multiplying syndromes of different outputs by
suitable factors and then summing those to form a composite syndrome.
Bhattacharya and Gupta (1983) proposed a method of designing
syndrome-testable circuits so that all single stuck-at faults and all shortcircuit faults involving any two lines can be detected by checking only the

187

Design to Minimize Cost of Test Generation

syndrome. Yamada (1983) applied the syndrome-testing approach to PLAs

for single stuck-at faults, single bridging faults, and single crosspoint faults.
Syndrome-testing has been extended further to an approach using the
Rademacher-Walsh spectral coefficients by Susskind (1981, 1983) and
Hsiao and Seth (1982). A Rademacher-Walsh spectral coefficient CI of an nvariable function f(X 1,X2, ... ,xll ) , of f(X) for short, can be calculated as
follows:

CI

2~ [f(X) EB IX

2' -

I]

LXI

Lx

where I = {iI' i 2 , . , ik } ,
= XiI ~ X i 2 EB EB X ik'
is the arithmetic
summation for all input combinations, and Co = C 1 = 0'
It is obvious that each coefficient has a value that lies in the range from
- 211 to + 2 11 Further, 211 coefficients characterize the function completely.
For a two-variable function we have the following four Rademacher-Walsh
coefficients:

Co = 22

2I f(X),

CI = 2

C2 = 2

2 2::[f(X) lie Xl],

C l 2 = 22

[f(X) lie X 2],

2 I [f(X) lie x, lie x 2 ]

x

The testing scheme using the Rademacher-Walsh spectrum is also based

on exhaustive testing; that is, the test patterns are all the possible input
combinations. The responses of the test patterns are compressed into the
corresponding Rademacher-Walsh spectrum of the circuit. Since each function has a unique Rademacher-Walsh spectrum, we can detect all faults by
determining whether or not the circuit under test has the RademacherWalsh spectrum intended. However, from a practical standpoint, the number of spectral coefficients is limited to either one or two. It was proved by
Susskind (1981, 1983) that, under the assumption of pin faults (i.e., terminal
faults), the computation of the single Rademacher-Walsh coefficient CALL
suffices for fault detection, where CALL is based on all variables, i.e., I
~ {I, 2, ... , n}. Susskind (1981, 1983) also showed that in a circuit form so
restricted that after every initial fanout point every line has unique inversion parity, any combination of stuck-at faults on all the lines up to the

Design for Testability

188

initial fanouts can be detected by verifying CALL and single stuck-at faults
on any lines following fanout can be detected by calculating Co' This result
gives us sufficient conditions for designing circuits that can be fully tested

for stuck-at faults by verifying only Co and

CALL'

As an example, every two-

level circuit, such as a PLA, satisfies the above conditions.

7.3 Reed-Muller Canonical Forms

Reddy (1972) described a design technique for realizing any arbitrary ninput function using AND and EOR gates. This technique is based on
Reed-Muller canonical expansion, in which all single stuck-at faults are
detected by only (n + 4) test patterns, independent of the function being
realized.
An arbitrary function !(x"x1, ... ,x,) can be expressed in the ReedMuller canonical form as
f(Xl ,Xb'"

,x") =

Co

EB C 1 Xl

EE> C 2 XZ EB

ED c"x"

EB C n + 1 X1 X1 EB Cn+ 2 X1 X3 EB ... ffi

C2"-lX 1

X2 "'X"

where Xi is either Xi or Xi and cj is a binary constant 0 or 1. For the sake of

simplicity we assume that only uncomplemented variables are used in the
expression. To obtain such a Reed-Muller expansion ora given function, we

first express the function with a sum of disjoint products, and replace all OR
operators in the sum of mutually exclusive products by EOR operators.
Then we convert the expression to a complement-free Reed-Muller form
using the identity

As candidates for easily testable circuits with function-independent testing, Reddy (1972) considered Reed-Muller canonical circuits, which are
direct realizations of Reed-Muller canonical expansions using AND and

EOR gates only. For example, consider

The Reed-Muller canonical circuit realizing j, is diagrammed in figure 7.13.

Each AND gate forms a product term in the expression. An extra input Xo is
used to supply Co = I.

Design to Min imize Cost of Test Gen erati on

189

Xl

x2 - -

---if---.-

+--

- f - --

-,

x3 - --+-+--- H - -H - - - h
x4

Figure 7.13
Reed-Muller canonical circuit real izing fl( X,.X 2, X3'X .)

Now let us consider the fault detection of these Reed-Muller canonical

circuits . We assume that only a single s-a-O or s-a-l fault occurs on the
inputs and outputs of AND gates or only a single EaR gate is faulty, where
any of the 15 other two-variable functions is allowed as the output of the
faulty EaR gate.
To detect a single fa ulty gate in a cascade of EaR gates , it is sufficient to
apply a set oftest patterns that will a pply all po ssible input combinations to
each Ea R gate (Kautz 1971). T his is perfo rmed by applying the following
four test patterns, independent of the number of input variables n:
Xo

T,

~ l!

Xl

X2

0
1
0
1

0
1

X.

~J

It is easy to see that the application of these four test patterns supplies all
fou r input pa tterns to each EaR gate. Furthermore, as Reddy (1972)
mentions, we can see that a s-a-Ofaul t at any AND gate input or output is
detected by applying either of the test patterns OIl. .. 1 and 11. .. 1. A s-a- l
fault at the output of any AN D gate is detected by applying either of the test
patterns 00 . .. 0 and 100 . .. O. Hence , the faults rem aining unte sted are s-a-l
faults at the inputs of the AND gates and s-a-Oor s-a-l faults at the primary
inputs.
To detect a s-a-l fault at anyone of the inputs to the AND gates , one of
the n test patterns in the set Tz is sufficient:

Design for Testability

190

Xo

Xl

X2

X3

Xn

0
1
1

1
0
1

1
1
0

1
1
1

x
x
T2 =

where x is "don't care." The ith test pattern in T2 places a zero on all ANDgate inputs to which Xi is connected, and all the other inputs are 1. Hence, if
the input connected to Xi on thejth AND gate is s-a-1, then the output of
this gate changes from 0 to 1 and this fault effect is further propagated
through the EOR gates to the primary output. For example, to detect a
s-a-l fault at line a in figure 7.13 we need only to set Xl = 1 and X 3 = O.
Hence, the fault is detected by either of the test patterns 01101 and 11101
in T2
Finally we consider the detection of single stuck-at faults at primary
inputs. Suppose that a primary input Xi is connected to an odd number of
AND gates; that is, Xi appears an odd number of times in the Reed-Muller
canonical expansion. A s-a-O fault at Xl induces an odd number of changes
at the outputs of AND gates if one ofthe test patterns 011 . .. 1 and 11... 1is
applied. This implies an odd number of changes at the input to the EOR
cascade, and hence the fault effect is propagated to the primary output.
Similarly, a s-a-l fault at Xj can be detected by one of the test patterns in T2
In this way, any single stuck-at faults at a primary input that is connected to
an odd number of AND gates can be detected by one of the (n + 4) test
patterns in T = TI U T2 In figure 7.13, XI and X 3 are connected to an odd
number of AND gates. Hence, a s-a-Ofault at Xl or x 3 is detected by either of
the tests 01111 and 11111. Further, a s-a-l fault at Xl (X3) is detected by
either of the tests 00111 and 10111 (01101 and 11101).
However, the(n + 4) test patterns detect no single stuck-at faults at those
primary inputs that are connected to an even number of AND gates, since
such faults induce an even number of changes at the input to the EOR
cascade and thus no change in the output of the cascade. For example, in
figure 7.13, X 2 and X 4 are connected to an even number of AND gates. Even
if the test patterns 01111 and 11111 are applied to detect a s-a-Ofault at X 2
or X 4, the fault effect propagates to an even number of AND gates; that is,

Design to Minimize Cost of Test Generation

191

Xl - - - - - . - - , , - - - ,

x,

x3

----t~--cl---t_--~---___,

--++--+..--+,--f-,

x4---H--++---+~--++r---t---,

Extra Gate
9

vl

-H

Figure 7.14

Modifiedcircuit for 11

an even number of changes at the input to the EOR cascade occur and no
change at the output of the cascade is induced.
Reddy (1972) proposed an approach to adding an extra AND gate so that
any fault at those primary inputs connected to an even number of AND

gates can be detected. The inputs to this AND gate are those appearing an
even number of times in the Reed-Muller canonical product terms. For the
functions

II

given above,

Xl

and x 4 appear in an even number of product

terms. Hence, the modified circuit for f, is given in figure 7.14 by adding an
AND gate whose inputs are X 2 and x, and whose output g is allowed to be
observed directly. For the modified Reed-Muller canonical circuit, we see
that the test patterns in T ~ T, U T2 are sufficient to detect single stuck-at

faults in the primary inputs and also in this extra AND gate. In the circuit
illustrated in figure 7.14, in order to detect single stuck-at faults on primary
inputs X2 and x; and inputs/outputs of the extra AND gate, it is sufficient to
apply three test patterns supplying (X2'X.) = (I, I), (0, I), and (I,D). Obviously these input patterns are included in T.
Summing up Reddy's results, we can state that for an arbitrary function f,
by adding one extra AND gate to the Reed-Muller canonical realization of
f, with inputs from all those primary input that are connected to an even
number of AND gates, we can detect all single stuck-at faults by applying
only (n + 4) test patterns, independent of the function

f.

The work of Reddy has been extended by Kodandapani (1974), Saluja

and Reddy (1975), Pradhan (1978), Page (1980), and others. Kodandapani
showed that one of the test patterns in T, can be removed by assigning the
"don't care" in the test set T2 in a specific manner. The test patterns in T2 ,

192

Design for Testability

hence, depend on the function being realized. Saluja and Reddy (1975)
extended Reddy's results to the multiple-fault assumption. It has been
shown that to detect t stuck-at faults in Reed-Muller canonical circuits, one
need only apply a predetermined test set, independent of the function being
realized, whose cardinality is

where LxJ denotes the integer part ofx. The Reed-Muller canonical circuits
proposed by Saluja and Reddy (1975) also have an extra AND gate whose
output is observable.

7.4 Programmable Logic Arrays

The programmable logic array (PLA) has many attractive features, among

them regularity of structure, simplicity of connection, and flexibility of

alteration. Because of its regular structure like memory, the PLA is very

suitable to LSI and VLSI and has become a popular and effective tool for
implementing logic functions.

Much work has been done in recent years on the design of easily testable
PLAs (Fujiwara et aJ. 1980; Fujiwara and Kinoshita 1981; Hong and
Ostapko 1980;Pradhan and Son 1980;Son and Pradhan 1980;Saluja et aJ.
1981, 1983;Yajima and Aramaki 1981;Ramanatha and Biswas 1982, 1983;
Khakbaz and McCluskey 1982; Khakbaz 1983; Fujiwara 1984). Most of
this work has been concerned with the design ofPLAs that can be tested by
function-independent test patterns. The first designs of such PLAs with
universal testability were proposed independently by Fujiwara et at. (1980),

Fujiwara and Kinoshita (1981), and Hong and Ostapko (1980). Although
the two designs differ in implementation, the essential idea is almost the
same.This section describesthe design of Fujiwara and co-workers,since it
is much simpler than that of Hong and Ostapko.
A PLA consists of three main sections as shown in figure 7.15. These are
the decoder, the AND array, and the OR array. The decoder section usually
consists of a collection of one-input or two-input decoders. Both the AND
array and the OR array are used to implement multi-output combinational
logic with sum-of-product forms. An example of a PLA is shown in figure
7.16. A PLA can be implemented in either bipolar or MOS technology. In

Design to Minimize Cost of Test Generation

f----

193

DECODER

AND ARRAY

--

--I

OR ARRAY

I
I

Figure 7.15
General struct ure of PLA

n-MOS technology, the PLA is typically implemented as a NOR-NOR

array. Figure 7.17 is a diagram of the circuit that implements the PLA of
figure 7.16 in n-MOS technology. In this section the PLA is assumed to be
NOR-NOR implemented and to consist of one-input decorders. These assumptions do not affect our argument. The results given here can easily be
modified to be applicable to PLAs implemented in another technology, or
with two or more input decoders. A PLA consists of 11inputs, 2n rows in the
AND array, 111 columns (product terms), and k rows (outputs) in the OR
array.
In order to design an easily testable PLA, we augment a given PLA by
adding extra logic: a shift register, two cascades ofEOR gates, two columns
between the decoder and the AND array, and one column and one row to
AND and OR arrays, respectively, as shown in figure 7.18. The extra
connections shown in figure 7.19 are for an implementation in n-MOS
technology.
A shift register is added to select a column (product line) in the AND
array. Each column Pj is ANDed by the complement of each variable S, of
the shift register as follows:
fori= 1,2, .. . ,m

Design for Testa bility

194

"'Il

L;
L,;
--,-------

"'Il

AIlD ARRAY
"'Il

--

----

--

____t_

OR ARRAY

Figu re 7.16
Example of PLA

where Pi is a pro duct term genera ted by the it h col umn ofthe original AND
a rray . An extra produc t line Pm + 1 is arra nged so tha t each row of the AND
array has a n odd number of connections (devices). Similarly, an extra row of
th e OR array is arra nged so that each column with in the OR array has a n
od d num ber of connections. T wo extra contro l lines C1 and C2 are added to
disab le all Xi S and X iS , respectively, as follows:

Design to Minimize Cost of Test Generation

-_--I

">o----r-I---f---1-----j--I---t--

X2 - _ - - - l

>O------l--+--+---+---i--t--

Xl

195

X3 -_---1 >O----rl--+_--+---+--1"""i--+_-

X -----...----1
4

~,o----+_--+---1"""i--+_~+_-_!_-

Figure 7.17
Exam ple of PLA in n-MOS techn ology

= 1, 2, .. . , 11

where Xi is the ith input line and Qj is thejth row of the AND array. The
section, composed of 2 x 2n crosspoints on two control lines, is called the
control array of the augmented PLA.
Th e augmented PLA has the fol1 owing properties:
The shift register can be used to select an arbitrary column of the AND
array by setting 0 to the selected column and 1 to all other columns. Since
NOR logic is assumed, to select a column or product line Pi we want S, to be
oand al1 other SjS to be 1.

196

Design for Testability

Extra colll1'lll

Extra
row

F igure 7.18
Augm ent ed PLA

----1......--+-----1'----......._

F1

- -.....---+---Dl()--.....--~~

Fk

197

Design to Minimize Cost of Test Generation

(a)

(b)

Figure 7.19
Extra device in nMOS technology

The control array can be used to select any row of the AND array, i.e., to
sensitize any output line ofthe decoder. To select Q2i-I' set Xi to 0, all other
XjS to 1, C 1 to 0, and C2 to 1.To select Q2i, set Xi to 1, all other XjS to 0, C 1 to
1, and C 2 to O. Note that in NOR logic selecting a row is equivalent to
setting the row to 1 and all other rows to O.
The cascade of EOR gates below the OR array can be used as a parity
checker to detect odd errors that propagate to it.
The cascade of EaR gates on the left of the OR array can be used as a
parity checker to detect odd errors that propagate to it.
Utilizing the above properties of the augmented PLA , we can present a
universal test set to detect all stuck-at faults in the shift register; single stuckat faults on the lines of the control array, the AND array, and the OR array;
single crosspoint faults in the AND and OR arrays, where a crosspoint fault
is an extra-device fault or a missing-device fault at the corresponding
crosspoint; and multiple stuck-at faults on the external input/output lines of
EaR gates.
Table 7.1 shows the test set A n m+ 1 used to detect the above types offaults,
where n is the number of inputs, In is the number of columns in the original
PLA, t:m = 0 if m is even, t:m = 1 if In is odd, and x represents "don't care."
For this test set A n m+ 1 we have the following theorem.
THEOREM 7.1 Let M n m + 1 be an augmented PLA as shown in figure 7.18.
For any M n m + l, the test set A n m + I can detect all stuck-at faults in the shift
register and all single stuck-at and crosspoint faults in the control array, the
AND array, and the OR array.

198

Design for TestabiIity

Table 7.1
Universal test set A

II

.", + I

Jr

1... . "'+ 1)
J/(j = 1, ... ,m+ 1)
J,' (i = 1,... , n)
J/(j ~

1/

X1 Xj.. . X..
0 . . . .. .. .. 0
0 .. . .. . .. .0
1 . . .. .. . . . 1
I . .. 0 ... 1
0 ... I . . . 0

C, C,
I
1
0
0
I

0
0

1
1
0

S I " ,Sj S",+1

I
1
I
0
0

. . . . .. . . 1
... 0 . . . 1
. .. 0 .. . 1
. .. ... . . 0
.. . . . .. . 0

2, 2 ,
0
1

1 1

'm
'm

X
X

Proof By applying the test sequence l'/t'/,' . .. /~ +, an d observing the

response from SOU" we check whether all the cells can shift in a nd out both 0
an d I.
When we apply test patterns If and Il , thejth column is set to 1 an d all
the other columns are set to O. Therefore, both If and Il can detect any
crosspoint fault on thejth column of the OR a rray by observing the output
2, a nd can detect a stuck-at-Ofault on the jth column, stuck-at- I faults on
the other co lumns, and stuck-at- l fault s on the rows of the AND array by
observing the output 2,. Any stuck-at fault on the row of the OR ar ray can
be detected by some oCthe test patterns If and Il (j = 1, 2, ... , m + I).
By applying test I,' (I,'), we set the (2i - 1)th (2ith) ro w ofthe AND a rray
to I a nd the other rows to O. Th erefore, test (I,') can det ect all crosspoint
faults and a stuck-a t-O fault on the (2i - I)th (2ith) row in the AND array
by observing the output 2
The extra-device fault at" the crosspoint of C, (C,) with Q" (Q"- I) is
detected by It (I,' ). The missing-device fault a t the cro sspoint of C, (C,) and
Q,,_, (Q,,) is detec ted by some of the test patterns If (1/ ) (j = 1, 2, . . . ,
m + I). The st uck-at-O fault on C, and the stuc k-at- I fa ult on C, a re detected by some of the test patterns If (j = 1, 2, . . . , m + 1). Similarly, the
stuck-at- I fault o n C, and the stuck-at-Ofaul t on C, are detected by some
of the test patterns 1
/ (j = 1, 2, . .. , m + I).

I,'

Next, we will see that the test set A.m + I can also detect any multiple
stuck-at fault in the EOR cascade s under the fault assumption that permits
only stuck -at fault s on the external input and ou tput lines of EOR gat es.
(Tha t is, no fault within EO R gates is con sidered.)
LEMMA

7.1 If N input vectors are linearly independent, then these N

Design to Minimize Cost of Test Generation

199

vectors plus zero vector are sufficient to detect any multiple stuck-at fault
on the external lines of EaR gates in an N-input EOR cascade.
Let 1 and 2 be the EaR cascades having the outputs ZI and Z2'
respectively, in the augmented PLA M",m+1 shown in figure 7.18. Let MOR
= [a jj ] be a matrix of k rows and In + 1 columns where au = 1 if there exists
a device at the (i,j)th position of the OR array, and aij = 0 otherwise.
By lemma 7.1 we have the following theorem for the multiple faults in two
cascades of EaR gates, 1 and 2'
THEOREM7.2 The test pattems Jv and F'{j 1,2, ... ,m+ l)inA".m+lare
sufficient to detect all multiple stuck-at faults in 1' If the column rank of
matrix M ORis equal to the number of inputs of the EaR cascade 2' then all
the multiple stuck-at faults in 2 can be detected by test patterns II, and 1/
(j = 1,2, ... , m + 1) in A".m+l'
If the column rank of matrix MORis not equal to the number of inputs of
the cascade 2' although it hardly occurs, then it is not guaranteed that all
multiple stuck-at faults in the cascade 2 can be detected by the test patterns
mentioned above. To overcome this problem, it might be necessary to add
an extra OR array so that the rank of M OR is equal to the number of inputs
of the EaR cascade 2' We permit only stuck-at faults on the external input
and output lines of EaR gates. However, by adding an extra array it is
possible to generate all test patterns for the cascades 1 and 2' This
technique was reported by Hong and Ostapko (1980).
In the argument mentioned above, fault coverage is not complete since
only single faults for stuck-at and crosspoint faults are considered and the
bridging faults, which are important in PLAs, are not considered. Fujiwara
(1984) proposed a new design of universally testable PLAs having the
following properties:
It can be tested with function-independent test patterns. For the design
of PLAs under the single-fault assumption, both the input test patterns
and the output responses are function-independent. However, under
the multiple-fault assumption the output responses are not functionindependent.
The amount of extra hardware is significantly less than with the previous
designs of universally testable PLAs. The ratio of additional hardware to
original hardware can be reasonably small for LSI and VLSI chips.
Very high fault coverage is achieved; that is, any combination of stuck-at

200

Design for Testability

Xl

Figure 7.20
Augme nted PLA for m ultiple fau lts

faults, crosspoint faults , and adjacent-line bridging faults in the PLA is

detected.
It is appropriate for built-in testing approaches, since input test patterns
and output responses are both function-independent under the single-fault
assumption .
The design can be applied to the high-density PLAs using array folding
techniques.
The augmented PLA is diagrammed in figure 7.20. It can be obtained by
excluding two EaR cascades from the PLA of figure 7.18, though the
connections of the added column and row in the AND and OR array are

Design to Minimize Cost of Test Generation

201

different. Obviously, the amount of extra hardware is significantly lower

than with the previous designs of universally testable PLAs.
An extra product line Pm + 1 is added. This line has devices on all crosspoints in the AND array, i.e.,
Pm+1 = QlQ2Q2n Sm+1

where Qj is the ith row of the AND array. An extra output line Z is added.
This line has devices on all product lines, i.e,

The extra column Pm + 1 in the AND array can be used to test stuck-at,
crosspoint, and bridging faults in the decoder and the control array, and
also to test stuck-at and bridging faults on the rows of the AND array. The
extra row and output line Z of the OR array can be used to test stuck-at and
bridging faults on the columns (product lines) and crosspoint faults in the
AND array in cooperation with other extra hardware.
The types of faults considered here are multiple faults such that any
combination of the following types of faults occurs simultaneously:
Stuck faults in the augmented PLA, i.e., stuck-at-O and stuck-at-l faults on
lines, XjS, CiS, Qjs, PiS, Fis, Z, and Sjs.
Crosspoint faults in the control array, the AND array, and the OR array.
Adjacent line bridging faults in the control array, the AND array, and the
OR array, i.e., bridging faults between C I and C2 , Qj and Qi+I ' Pj and Pi + I '
F, and Fi+ I ' and Fk and Z.
The technology used will determine what effect the bridging will have. In
n-MOS circuits, low voltage will dominate, and hence a bridging fault between two lines will produce an AND function between the lines. However,
the results given here can easily be modified to OR-type bridging faults.
Table 7.2 shows the test set B n m + I , which detects all multiple faults
mentioned above (where n and In are the numbers of inputs and product
terms, respectively) in the original PLA before augmentation. It will be
proved that B n m + 1 is the multiple-fault test set for the PLAs of figure 7.20 in
the following lemmas and theorem.
LEMMA 7.2 II and 1/ U = 1,2, ... , m + 1) can detect all stuck-at faults in
the shift register, all stuck-at faults on the product lines and rows of the OR
array, all bridging faults between adjacent product lines and between
adjacent rows of the OR array, and all devices missing from between the

202

Design for Testability

Table 7.2
U niversal test set B"....

1~+1

0 ... .. . . . 0
0
0
1
1

TS(i=l, ... ,n;j=l . . .. ,m+l)

o
o

I,J(i= I ... n;j= l . . . m+ 1) 0

II
I/ (j~

1. ... m + 1)

1
1

0
0
1
1
0

1
1

1
0

cells of the shift register and from the bottom row (output line Z ) of the OR
array, indepe ndent of the presence of a ny other faults.

Proof By applying the test sequence [ '[,' If .. . [~+ , and observing the
respo nse from S" " it is checked whether all the cells can shift in an d out
bo th 0 a nd 1, inde pendent olthe rest of the PLA. Th erefore, all thefaults in
the shift register can be detected by the test sequence.
Next, consider each output line (row of the OR array) F'(i = 1, 2, .. . , k)
and Z. Th e lest sequence ['[,2[ f " [~+1 cha nges each output line from 0 to
1 at least once if it has a t least one device on it. An output line F, is called
redundant if there exists no device on the line in the OR array [i.e., Ff = 0) or
if there exists an other output line Fj realizing the same function (i.e. Fj
= F,). We assume here that there are no such redundant output lines in the
OR array. If such outpu t lines exist, th ey should be removed from it since
they tak e unnecessary spac e. Hence, all the st uck-at faults on the rows of the
OR a rray can be detected by the test sequence. A bridging fault between the
adjace nt ro ws of the O R a rray imp lies that the corresponding two output
functions become the same. This is detected by [ , a nd [/ (j = I, 2, .. . ,
In + I)' since no out put line is redundant. Hence, all bridging faults between
the adjacent rows of the O R array are detected.
Hencefort h, we can assume that both the shift register and Z a re faultfree. Consider the device Dl at the crosspoint of the cell S, with the product
line P" a nd the device Dl a t the cross point of the product line f\ with output
line Z. Applicati on of the test patt ern s [, and Ii should cha nge Z from 0 to
I. In these test patt erns the only chan ge occurs in S" which affects only D,',
Pi' Dj2 , and Z. If Dl is missing, or Pi is stuck-at-Oj'l, or Dl is missing, or
bridging between P, and its adjacent column exists. or if any combination of
these fault s exists. then Z will not change its value. Hen ce. all devices
missing from between the cells of the shift register, all stuck-at faults on

Design to Minimize Cost of Test Generation

203

product lines, all bridging faults between adjacent product lines, and all
devices missing from output line Z are detected by II and
(j = 1,2, ... ,

1/

+ 1).

By lemma 7.2, we can henceforth assume that the shift register, the
product lines, the rows of the OR array, the crosspoints between the cells of
the shift register, and the crosspoints on line Z are all fault-free, and that no
bridging faults between the adjacent columns or between the adjacent rows
of the OR array exist.
LEMMA 7.3 I/U = 1,2, ... ,m + 1)detects any crosspoint faults in theOR
array, independent of the presence of any other faults.

Proof By applying I/, we set Sj to 0 and all other cells to I. By hypothesis,

the shift register, the product lines, the rows of the OR array, the crosspoints
between the cells of the shift register, and the crosspoints on line Z are all
fault-free, and no bridging faults between the adjacent columns or between
the adjacent rows of the OR array exist. This guarantees that applying I/
sets P, to 1 and all other product lines to 0, independent of any other faults,
and that all crosspoints in the jth column of the OR array are identified
(whether a device exists or not) by the observation of the output lines of the
OR array.
7.4 1;+1' I~+l' Ii~m+I' and Ii: m + 1 (i = 1, 2, ... , n) can detect all
devices missing from the column P m+! of the AND array, independent of
the existence of any other faults.

LEMMA

Proof By hypothesis, the shift register including the cross points between
the cells, the product lines, and output line Z (including the cross points on
Z) are fault-free, and no bridging faults between the adjacent product lines
or between the adjacent rows of the OR array exist. Consider the device at
the crosspoint of the row Q,,_! with the column Pm +! . Application of the
test patterns I~+! and Itm+! should change Z from I to O. The only change
in the two patterns occurs in Xi' which changes Q2i-! from 0 to 1 normally
and may change Q2i from 1 to 0 if any faults exist. Suppose that there is a
missing-device fault at the crosspoint of Q2i-l with Pm + ! . If Z does not
change from 1to 0, a fault is indicated. Otherwise, Z changes from I to 0 (i.e.,
Pm +! changes from I to 0) in spite of the missing-device fault. This is possible
only when Q2i changes from 0 to I. However, Q" never changes from 0 to I
in the test patterns I~+ 1 and Ii~m+ t - Hence, the missing-device fault at the
crosspoint ofQ2i-l with Pm+! can be detected by I~+l and I~+l'

204

Design for Testability

Similarly, one can prove that the missing-device fault at the crosspoint of
the row Q 2i with the column Pm + 1 can be detected by the two test patterns
/;;+1 and I?m+l'
By lemmas 7.2 and 7.4, we can henceforth assume that the shift register,
the product lines, the rows of the OR array, the crosspoints between the
cells of the shift register, and the crosspoints on lines Z and Pm + 1 are all
fault-free, and that no bridging faults between the adjacent columns or
between the adjacent rows of the OR array exist.

LEMMA 7.5 /;;+1' /~+l' Ii~m+l' and /?m+l = I, 2, . . . , n) can detect all
stuck-at faults on the rows of the AND array and all bridging faults between
adjacent rows of the AND array, independent of the existence of any other
faults .
Proof Application of the test patterns /~+1 and /i~m+l changes Xi from 1
to 0 and Q2i-l from 0 to 1.However, if there exists a stuck-at fault on Q2i-l
and /or a bridging fault between Q2i -l and its adjacent row, then Pm + 1 never
changes from I to O. Hence, such a stuck-at fault and a bridging fault can be
detected by observing Z. Similarly, we can show that /~+1 and /;:m+l can
detect a stuck-at fault on Q2i and a bridging fault between Q2i and its
adjacent row, independent of the existence of any other faults . _

By lemmas 7.2-7.5, it has been proved that all faults in the PLA except
faults in the control array and crosspoint faults in the AND array are
detected by the test set B n,m+l ' Hence, lemmas 7.6 and 7.7 below assume
that the only faults present are the fault s in the control array and/or
crosspoint faults in the AND array except Pm + l'
LEMMA 7.6 /;;+1' /~+1> /i~m +I' and /?m+l (i = I, 2, ... , n) can detect all
stu ck-at faults on C 1 and C z , bridging faults between C 1 and C z , and
crosspoint faults on C 1 and C 2 , independent of the existence of any other
faults .
Proof The extra-dev ice fault at the crosspoint of C 1 with Q2i is detected
by /;;+1 and I?m+l' independent of any other faults. Similarly, the extradevicefault at the cro sspoint of C2 with Q2i-l is detected by 1;'+1 and li~m+ l'
Further, we can see that the missing-device fault at the crosspoint of C 1 and
Q2i-1 is detected by /;; +1' independent of any other faults . Similarly, the
missing-device fault at the crosspoint of C2 with Q2i is detected by 1;+ l'
Henceforth, we can assume that all crosspoints in the control array are

Design to Minim ize Cost of Test Generation

205

fault-free. The stuck-at-O faults on C 1 and C:z are easily shown to be detected
by I~ +I and I~+l' respectively, under the assumption. Similarly, the stuckat-I faults on C 1 and C2 are detected by Ii?m+1 and Ii;m+l, respectively, for
any i.
LEMMA 7.7 IS and Ii] (i = 1, 2, .. . , 11; j = 1,2, ... ,111 + 1) can detect all
crosspoint faults in the AND array except the column Pm + l , independent of
the existence of any other faults.

Proof

Now we can assume that the only faults present are the crosspoint
faults in the AND array except Pm + I ' because all other faults are detected by
B n m + 1 as shown in lemmas 7.2-7.6. By applying IS, we can detect the
presence or absence of a device at the crosspoint of Q2i -l with ~. If the
value of Z is 0 (1), then there exists a device (no device) at the crosspoint.
Similarly, by the application of I;], it can be checked whether there exists a
device at the crosspoint of Q:Zi with P, Hence, all the crosspoint faults in the
AND array are detected by IS and I;J(i = 1,2, ... , n;j = 1,2, ... , m + 1).
Now we can complete the following theorem by collecting lemmas 7.27.7.
THEOREM 7.3 The augmented PLA of figure 7.20 can be tested for all
multiple faults (that is, any combination of stuck-at faults, crosspoint faults,
and bridging faults in the PLA) by the test set Bnm + 1 given in table 7.2.
By theorem 7.3, the test set B n m + 1 is shown to be the multiple-fault test
set for the augmented PLAs of figure 7.20. Further the test patterns are
function-independent, but their responses are not. However, the responses
of test patterns can easily be derived from the personality matrix of the
PLA. Another design for PLAs, in which both the input test patterns and
their responses are independent of the function under the single-fault
assumption, is presented in Fujiwara 1984.

Scan Design for Seqnential Logic Circuits

In chapters 6 and 7 we considered the problem of enhancing testability in

combinational circuits and several methods of designing combinational

circuits that are easy to test. This chapter treats the subject of sequential
circuits. When we generate a test sequence for a sequential circuit, we are

confronted with two added difficulties that do not arise in the case of a
combinational circuit:
In general, the initial state of the circuit is unknown. Hence, we must set its
state to the initial state required for the test. That is, the controllability is
required to set the initial state of the circuit under test.
The faulty signal must be propagated to at least one of the primary
outputs. If the effect of the fault causes an incorrect final state, we must
supply a sequence of input patterns that will observe the final state of the
circuit. That is, the observability of the final state of the circuit is required to
check the faulty state.
Such controllability and observability requirements are not easily met in
general sequential circuits. To overcome this problem, several approaches
have been proposed in which a sequential circuit is designed in such a way
that the circuit can easily be set to any desired internal state and the internal
states of the circuit can easily be observed.

This chapter presents several techniques of designing sequential circuits

having such properties. Most of the approaches are based on scan design, in
which all flip-flops in a circuit are interconnected into one or more shift
registers and the contents of the shift registers are shifted in and out.
8.1 State-Shiftable Machines
A sequential machine M is defined by a quintuple M = (S, I, 0, N, Z) where
S = (S" S2' ... , S,) is a set of states, I = {I" 12, ... , 1m } is a set of input
symbols,O = {O" O2 , , ,, , Ok} is a set of output symbols, N: S x 1-+ S is the
next-state function, and Z: S x 1-+ 0 is the output function. This quintuple
can be represented by a state table.
We assume that each fault transforms the normal machine Mo into some
other state table M, with n or fewer states. That is, any fault that occurs is
assumed not to increase the number of states. A test sequence is thus a

sequence of inputs that distinguishes Mo from each of M, defined by a fault.

Such a test sequence is referred to as a checking sequence.

Scan Design for Sequential Logic Circuits

x~--~

207

Ivl-r-r : z

Figure 8.1
The p-stagc binary shift register

A synchronizingsequence for a sequential machine M is an input sequence

whose application is guaranteed to leave M in a certain final state, regardless of the particular initial state of M. A homingsequence for M is an input
sequence whose application makes it possible to determine the final state of
M by observing the corresponding output sequence that M produces. A
distinguishing sequence is an input sequence whose application makes it
possible to determine the initial state of M by observing the corresponding
output sequence M produces.
We define an easily testable machine referred to as a state-shiftable
machine as a reduced and strongly connected machine possessing a distinguishing sequence X d oflength flog, n1 that forces the machine into a
specific final state S, (i.e., X d is also a synchronizing sequence) and also
possesses transfer sequences T(i) with a length that is at most flog, n1 to
move the machine from state S, to state S, for all i, where n is the number of
states of the machine.

Example 8.1 Consider the p-stage binary shift register shown in figure 8.1,
a serial connection of p flip-flops interconnected so that at the occurrence of
a shift signal the contents of the ilh flip-flop are shifted into the (i + I)st flipflops, Let Y" Y" ... , 1;, be the state variables, let X be the input variable, and
let 2 be the output variable. For the p-stage shift register, a p-tuple state
assignment Y, Y,'" 1;, can be found for each state such that Y,(t + I)
= Y,-, (t) for i = 2, 3, ... , p, 1'; (t + I) = X(t), and 2(t) = 1;,(t), where Y, (t),
y,(t), ... , 1;,(t), and 2(t) are the values of Y" Y" ... , 1;" X, and 2 at time t,
respectively. Then it is easily seen that any input sequence oflength p will be
both a distinguishing and a synchronizing sequence, and that 1;, l;,-1 ... Y1 is
a transfer sequence of length p that carries the p-stage shift register to state
S, with state assignment Y, Y,'" 1;,. Therefore, the p-stage shift register
shown in figure 8.1 is a state-shiftable machine.
Fujiwara et aJ. (1975) presented the following procedure to augment a
given machine by adding two extra input symbols so that the augmented
machine is a state-shiftable machine. Let M ~ (S, I, 0, N, 2) be a given

Design for Testabi lity

208

machine, where S

= {SI' S2' . .. , So}, I = {II' 12, ... , 1m} , and 0 = {0 1' 02'

... , O~}.
Augmentation Procedure
Add new sta tes SO+I' Sn+2, ... , Sn- to M if is not a n integral po wer of 2,
where * = 2P and p = rtOg2 n1Assign a p-b it binary code to all st ate s such that each state has only one
ass ignment.
Add new input symbols 60 ' 6 1 to M . The next function N and th e output
function Z for the new input sym bols 6 0, 6. are defined as follows: For each
state Sj, with state assignment Yl Y2"'~' N(Si> 60) = Su, and N(Si,6 1 )

= Sv'
if~ =

if~ = 1

where S; and S; have st ate assignm ents

resp ectively.

Y1 Y2 . . . ~_. and 1 Y1Y2 ' "

~-1'

The effect of this state transition is to shift the state assignment one d igit
to the right and introduce a 0 or a 1 as new leftmost digit according to input
60 or 6" respectively. Thus, this two-column submachine restricted to
inputs 60 and 6 1 is isomorphic to the p-stage binary shift register. Since the P:
stage shift register is a sta te-shifta ble machine, this two-column submachine
is a lso state-shiftable, and hence the augmented machine M* is too. Indeed,
in the aug mented machine M * obtained above, an y input sequence of
length p = rtOg21consisting of 6 0 and e 1 is both a distinguishing sequence
an d a synchronizing sequ en ce, and 6r.6 y, ., . 6 Y,ey, is a transfer sequence of
leng th p that transfers M * from an arbitrary state to state S, with state
assignment Y. Y2 ' " ~ . The augmented machine M * ha s * stat es and
(m + 2) input symbols, where log2 n* = rtOg2 n] ,
Ex ample 8.2 Consider machine A, defined in table 8.1. Machine A is not
strongly connected and does not have a distinguishing sequence. By applying th e above procedure, we obtain the augment ed machine A* (table 8.2).
Machine A* has a d ist ingui shin g sequence 6060, which is also a synchronizing sequence whose final state is SI' The transfer sequences for machine A*
are as given in tab le 8.3. He nce, the a ugmented machine A* is a statesh iftable machine.

209

Scan Design for Sequential Logic Circuits

Tab le 8.1
Machine A

Input
State

S,
S,
S,

52' 1

51,1
53,0

-, I

52, 0

Dash means "d on't care,"

Table 8.2
Augmented machine A

Input
State
00
01

10
11

S,
S,
S,
S.

S, . I

S,. O

5h l

S,. O

S,. O

S,. O

S,. I

- .I

S,. O

5 3. 1
54,0

51, 1

54,1

Ta ble 8.3
Tra nsfer sequences T(i ) for
machine A*

T(l}

T(2)

T(3)

T(4)

" means the null sequence.

210

Design for Testability

Now let us derive checking sequences for state-shiftable machine. Let M

(S, I , 0, N, Z) be a n n-state, m-input state- shiftable machine. Let Xd be an
input seq uence of length [Iog, nl that is both a d istinguishing sequence an d
a synchro nizing sequence. Let S, be the final sta te resulting from the
a pplicatio n of Xd Th e transfer sequence with a length that is a t most
[log, n1 to move M from state S, to sta te S, is den oted by T( i).
The checking seque nce consists of five parts.The first part of the checking
sequence, the initiali zing part, brin gs the machine under test to the sta rting
state St . Thi s ca n be done by a synchronizing sequence Xd Hence, the first
par t has the form
=

Input:
Stale:
Output:

(8.1)

where the dash mean s "don't care ."

The second part of the checkin g sequence carries the correctly o perating
mac hine th rou gh all its Slates, d isplays all the different responses to X d ' a nd
thus verifies that X d is a distinguishing sequence. Th us, the secon d part has
the form
Input:
Sta te:
Ou tput:

Xd

S,

(8.2)

S,
Z,

for all state s S, of M , where Z, = Z(S" X d ) .

The third part of the checking sequence verifies, by the use of a distinguishing sequence X d validate d by 8.2, that X d is a synchronizing sequ ence
used to force the co rrectly opera ting machin e into sta te S, . Thus, this part
has the form
Input:
Stat e:
Output:

x,
S,

x,
S,

Z,

S,

(8.3)

2,

for all states S, of At.

The fourth pa rt of the checking sequence verifies tha t T(i) tran sfers the
correctly operating machine from state S, to state S,. Th is can be done by
using a distinguishing sequence X d as follows:

Scan Design for Sequent ial Logic Circuits

Input:
State:
Output :

T(i)

Xd

s,

SI

z;

211

x,
(8.4)

SI
Zi

for a ll sta tes Si, wh ere Zli = Z(Si' T(i)).

The fifth part of the checking sequence is to be de signed to ch eck all the
tr ansitions and ha s the form

x,

Input:
State:
O utput:

T(i)

Ij

s,

SI

z.,

Xd

Sij = N (Si, Ij )
Oij = Z (Si. IA

SI

(8.5)

for a ll states S, a nd input symbols I j

Because the distinguishing sequence Xd a nd th e transfer seq uenc e T(i)
ha ve been val id ated b y the previous parts of the checking sequence. S, is
uniquely d et er m ined by T(i) and Sij is rec o gnized by Xd.lfboth N(Si' Ij ) and
Z(Si> Ij ) are un specified , then such a transition from S, under input Ij need
no t be chec ked.
Although the checking seq uence is functionally subdivided into five
parts, these parts need not be physically se pa ra ted from each other. Parts 14 ca n be co m pletely contained in the seq ue nces

x,

Input:
St at e:
Output:

T(i)

s,

SI

Zli

Xd

Xd

51

Zi

(8.6)

SI
ZI

for a ll states Si'

Thus, the t otal checking sequence is to be organized from the subsequences 8.5 a nd 8.6, a nd we ha ve the following checking sequence.

X.

Input :
Slate:

x.x,

T(1)
SI

T(n )

X.
Xd

T{i)
S,

51

i,x,
S,

51
fjX. .

S;

X.X.. ..

S2

T(1)

X.X.

S.

SI

T(2)
S.

SI

T(n)

Xd
SI

12 Xd '"

T{I)
S,

SI
f" X d

S.

Let us d erive the bound on the len gth of the checking seq ue nce. Since
the m a chine M is a sta te-s hifta ble m a ch ine , IXdl = [l og j ] a nd IT(i)1
< [l og ; n1 for i = 1, 2, .. . , It, where IX I is the len gth of X . From the
organization of the checking seq uence, it can be seen that the total length of
the sequence is at most

212

Design for Testability

IXdl +
=

I (IT(i)1 + 21 Xdl) + j;l/;

I I l (IT(i)1 + IIjl + IXdl)
;;1

(2n + 1)IXd l +

I IT(i) + mn(lXdl + 1) + m 1=1

I IT(i)1
1=1

~ (2n + l ) rIog2111

+ nflog2nl + mn(rIog2nl + 1) + mn rlog2nl

= (3n + 1)f1og2nl

+ nl1l(2rIog2nl + 1).

Thus, the upper bound on the length of the checking sequence is

(3n + l) flog2nl

+ mn(2f1og2111 + 1),

which is O(mn flognl).

Example 8.3 Let us construct a checking sequence for the machine A *

defined by table 8.2. X d = i:oi:o is a distinguishing and synchronizing sequence whose final state is SI' The transfer sequences T(i) from state SI to
each state S; are given in table 8.3.
The total checking sequence is
Input:

Xd

O utput:

T(l) Xd Xd
A
00 00

T(I ) 0
1
A

Xd T( l)

T(2) 1
00 0

Xd T(2)

T(4)
00

10 A

0
1

01 00

Xd T(3 )

T(3)
0

T(2) Xd Xd
10 00
00

T(3) Xd
01
0

Xd T(I) GO
00 A
0

00

Xd T(2)

Xd

00 00

Xd

Xd

Xd T(3)

Xd

10 0

1l

Gl

Xd

01

T(3) 0
0
0

Xd

T(4)
00

Xd

T(l)
A

01

T(4) Xd Xd
00 1l 00

00

10

10

Xd
11

In the above checking sequence, some subsequences are equivalent and

thus ca n be deleted. Then we obtain the reduced che cking sequence
Input:
Outpu t:

Eo
-

T(l)

i:o

eo i:o i:o
0 0 0

T(2) eo i:o i:o eo T(3)

00

eo i:o i:o Co T(4) eo i:o eo Eo

1 1 0 0
0 1 0 0 00

T(l) 0 EO Eo T(I)
A

Scan Design for Sequential Logic Circuits

213

Clock - - - t - + - - - I

Combinational
Log ic

Fig ure 8.2

Sequential circuit wit h clocked 0 flip-flops

So

eo T(2) 1

60

eo T(4) e1

00

So SO

0 0

00

T(2)

1 00

61

eo

SO

T(3) 0

So So

0 1

So So

1 1

8.2 Scan D esign Approaches

Th e term scan refers to the a bility to shift int o or o ut of any state of
sequentia l circ uits. In scan design approaches, all flip-flops in the circuit are
interconnected int o one or more shift registers and the contents of the shift
registers are shifted in anti out. All the states of the circuit are completely
controlled and observed from primary inputs and outputs, and thus all flipflops can behave as primary inputs/outputs. Therefore, it turns out that the
sequential circuit can be thought of as purely combinational and the
complexity of test gen eration for the circuit can be substantially reduced.
This section presents three typical scan design approaches: the shiftregis ter-modification a pproach of Williams and Angell (1973), the Scan
Path ap proach of Ko bayashi et al. (1968) and F unatsu et al. (1975), an d the
Level-Sensitive Scan Design (LSSD) approach of Eichelberger and Williams (1977,1978).
Shift-Register Modificatio n
Let us consider a sequential circuit in which clocked D flip-flops are used as
the storage elements, as sh own in figure 8.2. The structure of the shiftregister-modification approach proposed by Williams and Angell (1973) is

Design for Testability

214

Mode control

,---1 sw

f--<r--~ sw

CJ oCk

---lr---+-'----+--+---'
Contlf nati onal

Logic

Figure 8.3
Modified sequential circuit (Williams and Ange ll 1973; IEEE 1973)

p
p

- -t--L.J
pa+pb

b -----I-J

Figure8.4
Do uble-throw switch

illustrated in figure 8.3. T he modifica tion is d one by inser ting a dou blethrow switch at each input lead of every flip-flop an d in the lead that dri ves
one of the pr imary outputs of the circuit. Each of th e double-thro w switches
may be implemented as shown in figure 8.4. The modified sequential circuit
shown in figure 8.3 ca n opera te either in its normal mode or in the shiftregister mode. When the mode cont rol is supplied with a 0, the circuit
operat es in the normal mode; that is, it behaves exactly as it did before the
modifications were carr ied out. O n the other hand , when the mode-control
signal is a 1, a ll nip-flops in the circuit are connected in a cha in and the
circuit behaves as a shift register. In this shift-register mode, the first flipflop can be set directly from a prima ry inpu t an d the outpu t oft he last flipflop can be directly mon ito red at a primary out put. Hence, we ca n easily set
the mo dified circuit to any desired internal state by supplying the co rresponding values to the shift register, a nd we can easily observe the internal

Scan Design for Sequential Logic Circu its

215

state of the circuit by shifting out the contents of the shift register. Thus the
test-generation problem for sequential circuits can be reduced to that of
combinational circuits, since all flip-flops can behave as primary
inputs/outputs. The procedure for testing the modified circuit is as follows:
(1) Switch to the shift-register mode and check the shift-register operation
by shifting in and out an alternating sequence of ones and zeros.
(2) Set the initial state into the shift register.
(3) Return to the normal mode and apply the test input pattern.
(4) Switch to the shift-register mode and shift out the final state while setting
the starting state for the next test. Return to step 3.
Here, for the sake of simplicity, we have considered a sequential circuit
with D flip-flops. However, shift-register modification can be performed in
the same fashion for J K and other l1ip-l1ops. Since a switch is inserted in
each input lead of every flip-flop, the number of switches used is doubled for
two-input flip-flops.
Scan Path

Before Williams and Angell presented the shift-register-modification approach mentioned above, an approach to scan design called the Scan Path
had already been developed (Kobayashi et al. 1968; Funatsu et al. 1975).
Kobayashi et al. reported that the Scan Path approach had been to practical use for a system with 100,000 gates or more (the NEC system 2200/700).
The Scan Path approach was the first practical implementation of shift
registers for testing to be incorporated in a complete system.
The Scan Path approach uses as a memory element the raceless D-type
flip-flop, illustrated in figure 8.5. These raceless D-type flip-flops are connected in a serial scan path as shown in figure 8.6. The flip-flop is composed
of two latches operating in master-slave fashion, and has two clocks to
select either scan input (called test input) or data input. These clocks
operate exclusively so that the value of the data input can be inhibited while
the value of the test input is being loaded into the flip-flop and vice versa.
In the normal mode, clock 2 retains logic value 1 to block the test input
(scan input) from affecting the values in latch 1, and also not to disturb the
values in latch 2. Clock 1 is used to load the value of the data input into the
flip-flop. When clock 1 is at value 0, the value of the data input can be
loaded into latch 1. After sufficient time has passed to load the data, clock 1

216

Design for Testability

Clock 2-

......- - - - - 1

Test
I nput
(Scan in)

Outp ut

Data

Input

...-1._...,.<:......- - -

Sea n ou t

Cl oCk 1

Lat ch 1

Lat ch 2

Figure 8.5
Raceless D-type flip -flop with Scan Path (Kobayashi et al. 1968; Funatsu ct al. 1975;
I EEE 1975)

Logic Card

r
xy

-- ----- _..- _

---

_..,

Test Input

( Scan i n) o--;.-t-i- - - - - --,

Cloc k 2

~---L-'"

,l __

Figure 8.6
Co nfiguration of Scan Path

Test
~ t~ t

_ _ ... ... . . . . .

_.

..

. __ . _ . __

Scan Design for Sequential Logic Circuits

Pri ma ry
Input s

Input

Comhll'lat1ona l

Ci rcuit

Shift
Register

217

Pri mary
Outpu ts

Output
Shift
Regi ster

(e )

c
(b )

Figure 8.7
Transformed combinational model and partitioning

changes from 0 to I. It th en makes latch 2 sensitive to th e dat a output of

latch 1. Wh ile clock I retains valu e I , the da ta from latch I are loaded into
lat ch 2.
In the shift-register mod e, clock I is set to I to prev en t the dat a inp ut fro m
affecting th e values in la tch I. Th e value of th e test input is loaded into latch
I by clock 2 when clock 2 is 0, a nd the results ofla tch I are loaded into latch
2 when clock 2 is I. Since all flip-Oop s are int erconnected to form a serial
scan path as sho wn in figure 8.6, test input data appli ed to the first flip-Ilop
ca n be shifted thro ugh the cha in of flip-Oo ps.
Many advantages a re brough t abo ut by thi s Sca n Path approach. T he
mo st prom inent o ne is that a sequential circuit is co nverted into a cornbinational circuit, thus red ucing th e cost of test genera tion sign ificantly. T he
circuit can be modeled as shown in figure 8.7(a), where each flip-flop
belongs either to the input shift register o r to the o utput shift register.
Another advant age of the Scan Path appr oach is logical circ uit part itioning. In the model of figure 8.7(a), it is possible to partition th e circuit int o

218

Design for Testability

small subcircuits. Figure 8.7(b) shows the subcircuits A, B, and C that make
up the original circuit. A partition can be generated automatically by
backtracing from the flip-flops through the combinational logic until a flipflop or a primary input is encountered in the back trace. In figure 8.7(b),
outputs of subcircuit A are determined solely by the inputs 1, and do not
depend on any other inputs. Subcircuit C and a section of subcircuit B do
not have any effect on the test generation of subcircuit A. Hence, test
generation for each subcircuit can be performed independent of other parts.
When the partition is too large, it can be further partitioned by the insertion
of extra flip-flops.
Level-Sensitive Scan Design (LSSD)
Using an approach similar to the Scan Path approach, Eichelberger and
Williams (1977,1978) introduced a concept oflevel-sensitive design coupled
with the scan operation mentioned above. This method, called LevelSensitice Scan Design (LSSD), ensures race-free system operation as well as
race-free testing. LSSD is IBM's discipline for structural design for testability and has been used in many IBM systems.
To provide reliable operation in timing, the designer must consider the

testing of several AC design parameters, such as rise time, fall time, and
delay. However, with LSI and VLSI it will become impossible or impractical to test each circuit for all the AC design parameters. The LSSD
approach aims at obtaining logic circuits that are insensitive to those ac
characteristics. The term level-sensitive is defined by Eichelberger and
Williams (1977, 1978)as follows: A logic circuit is level-sensitive if and only
if the steady-state response to any allowed input state change is independent of the delays within the circuit. Also, ifan input signal, then the response
must be independent of the order in which they change. Steady-state
response is the final value of all logic gate outputs after all change activity
has terminated.
To obtain such level-sensitive logic circuits, we need a level-sensitive
memory element that does not contain a hazard or a race condition. Figure

8.8 shows the polarity-hold latch, which is level-sensitive. When C = 0, the

latch cannot change state. When C = I, the internal state of the latch is set
to the value of the data input D. This polarity-hold latch is further augmented to include shift capability. Figure 8.9 shows the shift register latch
(SRL) used in LSSD as the basic memory element. The polarity-hold SRL
consists of two latches, L, and L" which have the scan input 1,the data input

Scan Design for Sequential Logic Circu its

219

Figure 8.8
H azard-free po larity-hold la tch

D
C
I
A

B
(a l

c -----'

B
( b)

Figure 8.9
Pola rity- ho ld SRL (Eichelber ger and Williams 1977, 1978; IEE E 1977)

220

Design for Testability

D, the system clock C, and two shift-control inputs, A and B. In the normal
operation mode, the shift signals A and B are both set to 0 and the L 1 latch
operates exactly like a polarity-hold latch. The clock signal C is 0 during the
time when the data input 0 may be changed. After the data input has
become stable at eith er 1 or 0, the clock C will chang e to 1, which cause s the
L 1 lat ch to be set to the value of the data input D . In th e shift-register mode,
th e clock C is set to 0 and both shift signals A and B are alterna tely changed
to shift data through latches L 1 and L 2 . First, by chan ging A to 1, data from
the preceding stage can be loaded into latch L 1 through the scan input I .
Then, after A has changed back to 0, th e B shift sign al changes to 1 to load
the data from latch L 1 into latch L 2 The +L 2 output of latch L 2 is
connected to the scan input I of the next-state SRL. All SRLs ar e interconnected into a shift register, as sho wn in figure 8.10.
Eichelberger and Williams (1977, 1978) presented the follo wing set of
design rules or co nstraints, which will result in level-sensitive and scannable
des ign to aid testing.
(1) All internal st orage is implemented in haz ard-free polar ity-hold latches.
(2) The lat ches ar e controlled by two o r more non-overlapping clocks such
th at
(i) A latch, X, may feed the data port of another latch, Y, if and only if the
clock that sets the data into latch Y does not clock latch X.
(ii) A latch, X, may gate a clock Cj to produce a gated clock Cj g which drives
another latch, Y, if and o nly if clock Cj g does not clock latch X, where Cj g is
an y clock deri ved from Cj
(3) It must be poss ible to identify a set of clock primary inputs from which
the clock inputs to SRLs a re controlled either through simp le po wering
tree s or throu gh logic that is gated by SRLs and/or non-clock primary
inputs. Gi ven this st ructure, the following rules must hold:
(i) All clock inputs to all SRLs must be at their "off" states when all clock
primary inputs are held to their "off" state.
(ii) Th e clock signal that appears at any clock input of an SRL must be
contollable from o ne or more clock PIs such that it is possible to set the
clock input of th e SRL to an "on" state by turning any o ne of the corresponding clock PI s to its "on" state and also setting th e required ga ting
conditions from SRLs and/or non-clock PIs.
(iii) No clock can be ANDed with either the true or complement value of
an other clock .

221

Scan Design for Seq uential Logic Circuits

Sea n ; n

0--+----=---1

Sean out

Modules
(Chip)

Scan in
A
B

Scan out

0--+--,

Board

Figure 8.10
In ter con necti on o f S R Ls

(4) Clock primary inputs may not feed the data inputs to latches either
directly or through combinational logic, but may only feed the clock input
to the latches or primary outputs.
(5) All SRLs must be interconnected into one or more shift registers, each of
which has an input, an output, and shift clocks available at the terminals of
the package.
(6) There must exist some primary-input sensitizing condition (referred to
as the scan state) such that
(i) Each SRL or scan-out PO is a function of only the single preceding SRL
or scan-in PI in its shift register during the shifting operation.

222

Design for Testability

Out put s

I n pu t ~, _~ ./

Scan out
COlTb l nat ional
Cir cuit

t---r==~~~:J

T
C1
A s hi ft
Scan 1n

C or

B shift

Figure 8.11
General structure for d ouble- latch LSSD (Eichelberger and Williams 1977, 1978; IEEE

1977)

(ii) All clocks except the shift clocks a re held "off" a t the SRL inpu ts.
(iii) Any shi ft clock to a n SRL may be turn ed "on" a nd "off " by changing the
corres ponding clock prima ry input for each clock.
Whether a logic circuit is designed in compliance with these rules can be
checked by a met hod developed by G od oy et aJ.(1977). Figure 8.11 shows a
general structure for a logic circuit tha t follows the above LSSD rules. T he
circuit in figure 8.11 is called a double-latch design, since all the feedback
inputs into the combinational circuit N are taken from the L 2 latch.
All sto rage elemen ts a re implemented as a set of master-slave latches L ,
and L 2 Each of the master-slave latches is connected in series and clocked
by two nonoverlapping clocks C, an d C 2 , where C 2 is equiv alent to B.
Wh en C, is active, C 2 is 0 an d the inputs an d outputs of N are stable. Some
of the L 1 latches change their states while C, is 1. As soo n as C, is cha nged

Scan Design for Sequential Logic Circuits

223

back to 0, the next clock C, occurs; that is, C, chan ges to I. Th e value s of the
L, la tches are loaded into the L, latch es while C, is I.
In the shift-register mode , the SRLs are chained to form a shift register
under the con tro l of clocks A and B. Test pattern s are applied to the
combinational circuit by scanning them into the shift register and apply ing
them at the primary inpu ts. Then the clock C, is set to I and th e respons e of
the combination al circuit is captured in the L, latches and at the primary
outputs. Th e result of the test captu red in the register is then scanned out.
Since the LSSD has the scan capability, it also has the same advantages
as the shift-register modifica tion of Williams an d Angell and the Scan Path.
The scan capability reduces the sequential test-genera tion problem to a
combinational one and makes logical partitior.ing of the circuit possible,
thus significantly simplifying the testing problem. Another adva ntage of the
LSSD is th at ac testing, test generation, an d fault simulati on ar e greatly
simplified, becau se the correct operat ion of the logic circuit is near ly
independent of the ac characteristics and also becau se hazards and races a re
eliminated.
However, the LSSD has also some negative aspects. T he SRLs are
logically 2-3 times as complex as simple latches, requ iring up to four
ad diti onal prim ary inpu ts/o utputs for control of the shift registers. Eichelberger and William s (1977, 1978) comment that the actua l logic gate
overhead for implemen ting the LSSD has been in the ran ge of 4-20 percent.
The difference is due to the exten t to which the designer made use of the L,
latches for the system function. As mentio ned ear lier, LSSD circuits can be
designed in double-latch o r single-la tch mod e. In the former case, as in
figure 8.11, system-design considerations require both L, and L, latches to
be in the system path, an d both are therefore considered as system latches.
In the latter case, however, only the L, latch is in the system dat a path and
the L, latch is used only for shifting in test mode. Hence, the L, latch is an
overhead for testability.
DasG upta et al. (1982) ha ve reported a variati on of the SR L that can
reduce the ga te overhead for LSSD (figure 8.12). The difference between the
L, of figure 8.9 and the q of figu re 8.12 is tha t the q latch has two
indepen dent data ports. T he first port is fed by the related L, latch an d
clocked by shift clock B.This allows the L! latch to behav e as the slave latch
in the shift-register path. The second dat a port serves as an independent
system da ta port clocked by system clock C' to permit different system dat a
to be stored in the q latch during system operation. In this way, the two
lat ches in the new SRL pro posed by DasGupta et al. a re fully used even in

224

Design for Testability

D
C

1---...------ II

I
A

--1 L2

0*

C* - - - - - - - - 1
(a)

o
C

C
X

c**

,""

(b)

Figure 8.12
SRL with q lat ch (DasGupta et al. 1982; IEEE 1982)

the normal operation. Therefore, the gate overhead for the LSSD is significantly reduced as compared with the sin gle-latch LSSD using the SRLs of
figure 8.9.
Another variation of the SRL has been reported by Saluja (1982). Figure
8.13 illustrates this latch, which is called a polarity-hold parallel and shiftregister latch (PSRL). The PSRL has two modes of op eration, as shown in
figure 8.14. The difference between the PSRL and the SRL of Eichelberger
and Williams (1977) is that, in the normal mode, Q and Q outputs of the
PSRL are obtained from two different latches. This allows an increase in the
number of controllable inputs to combinational logic, and hence it can be
expected that the test-generation process will be easier and will provide
better test coverage.

225

Scan Design for Sequential Logic Circuits

Q
I

A
C

L,

L
2

Q
(al

---...--~

B
(b)

Figure 8.13
Pola rity-hold PSR L (Saluja 1982; IEEE 1982)

226

Design for Testability

L]
0

C
L
2

(a}

Norma l mode.

8----1

L2

(b) Shi f t r egi ster mode.

Figure 8.14
Two modes of opera tion for PSRL

8.3 Variations of Scan Design

Som e vari ations of th e sca n design a pproach have been proposed by T oth
and Holt (1974), Stewart (1977), Me rcer et al. (1981 ), and And o (1 980). The
first three are very similar to the scan design techniques mentioned in the
preceding section, since shift registers are used to load and unload data.
Ando's approa ch differs from o thers in that an add ressing scheme similar to
a rand om- access mem ory is used instead of shift register s.
Shift-Register Modification
Th e approa ches of Toth and Holt (1974) and Mercer et al. (1 981) ar e very
similar to the sh ift-register-modification method of William s and Angell
(1973). Toth and Holt presented an implementation using MSI shift registers ava ilable o n the market. The proposed shift reg ister has the capability
of shifting data right and left as well as parallel loading and unl oading.
Add itional control logic is added to the circuit to allow m ode control
(load /shift) over the sh ift path.

Scan Design for Sequential Logic Circuits

227

Whereas most of the scan design techniques have been developed for
designing completely synchronous circuits, the approac h of Mercer et al.
(1 981) allows some asynchro nous designs. T he meth od is to modify flipflop s in a given sequential circuit to form sca n (shift) registers. Figure 8.15
shows a flip-flop modified to allow scan a nd norm al opera ting modes as
specified by the control value of SW. Th ese modified flip-flops a re interconnected into on e o r more scan registers.
As shown in figure 8.15, multiplexers are placed on the clock inputs as
well as the data inpu t. Also, preset and clear inputs are gated by co ntrol
input SW to disabl e them in scan mode. A realization ofa multiplexer using
transmission ga tes is illustrated in figure 8.1 6. If the nor mal circuit is
already synchro nous, the multiplexing of clocks will no t be req uired.
Hence, the multiplexers and the disabl ing gates are used as and where
needed. Flip-flops can have asynchronous preset and clear inputs. and
clocking by an asynchro nou s signal is also allowed. In th is way, the design
rules of Mercer et aJ. (1 981) permit some asynchro nou s designs a nd hence
are more flexible than those ofthe Scan Pa th and the LSSD. However, the
price one pays for this design flexibility is that races and hazards may occur
in scan-testab le circuits, thus complicati ng test generation.
Scan/Set Logic
A sca n design technique called Scan/Set Logic has been used to enh an ce the
con trollability an d the obse rvability of sequential circui ts (Stewa rt 1977).
Scan/Set Logic is separa te from the functional logic an d provides a da ta
path to obser ve a nd/or control some nodes in the circuit. Because of this
sepa ration, the performa nce of the functional logic suffers little degradation. T his differs from the Scan Path and LSSD approaches, in which all
flip-naps are used to operat e in bo th shift-register and normal moues.
Figure 8.17 shows an example of bit-serial Scan/Set Logic, in which the
values of up to 64 nodes in the circuit ca n be loaded int o the 64-bit shift
register with a single clock and then serially sca nned out th rough the scanou t pin. Th is shifting occurs after each test input patt ern has been a pplied,
and the sca nned dat a are monitored by the tester as th e respon se dat a
together with the usual primary ou tput response of the circuit under test.
Th e shift register is also used to provide a set capa bility from the tester. Test
patt erns are serially shifted into the shift register and then gated into the
flip-flops of the functiona l logic. In this way, any internal node can be
scan ned and / or set by con necting it to one of the flip-flop s in the Scan/Set

228

Design for Testability

CC

SW

cc

Output
1-........- _ CC

Preset

From Prev10us--lr""lFlip-Flop

.--~

To Scan

CC

Flip-Flop

Master Clock

CC

Input of

Next Flip-Flop

I_r----,

Slave Cl ock

CC
Figure 8.15
M od ificat ion of flip-flop to form sca n regis ter (Mercer et at. 1981; IEEE 1981)

Normal
I~ode

Input

Multi plexer
Output

Scan

Mode
I nput

sw
Figure 8.16
Implementation of mult iplexer

229

Scan Design for Sequential Logic Circuits

Load/Shift Control
Scan Clock

Scan Enable

Sequential Circuit

Scan
;------- Input/Output

Figure8.17
Bit-serial Scan/Set logic (Stewart 1977; IEEE 1977)

shift register. However, not all internal nodes need to be scanned and/or set.
To reduce the test-generation problem of sequential logic to a combinational one, it suffices to give scan/set capability to all flip-flops in the functionallogic. Of course, not all flip-flops need to be scanned and/or set by
the shift register, since some of them are already readily controllable and
observable. This design flexibility is one of the advantages of the Scan/Set
Logic technique. Another advantage is that the separation of the scan/set
logic and the functional logic allow the scan/set operation to be performed
during the normal function operation. This enables us to get a "snapshot"
of the sequential circuit without degradating its performance.
Random-Access Scan

Random-Access Scan [Ando 1980) is a technique of providing a direct

access path to each internal storage element and thereby enhancing its
controllability and observability. To create such a direct access path, an
addressing scheme very similar to that of a random-access memory is
employed in which each latch is selected uniquely to be scanned in/out by
specifying its address.
As a basic storage element in the Random-Access Scan approach, an
addressable latch or flip-flop is used. Such a latch is one whose state can be
controlled and observed through scan in/out lines only when it is selected
by addressing. Figure 8.18illustrates such an addressable latch. The latch has

230

Design for Testability

Data

SOL
-CK

SCK

-SOo

X- Adr

-t------------J

Y-Adr

~----

__J

Figure 8.18
Polarity-hold type addressable latch (Ando 1980; IEEE 1980)

Data - - - - - - r......

-CK
Q

-CL
PR

-SOD

X-Adr _ _...---tY-Adr

4.-

--'
---J

Fiaure 8.19
Sct/re set-type addressable latch (Ando 1980; IEEE 1980)

two data inputs [one for normal data (DATA) and the other for scan data
(SOl)] and two clocks (- CK and SCK). The normal data on DATA are
clocked into the lat ch by the - CK clock independent of the two addressing
lines. The scan-in data on the SDI are clocked into the latch by the clock
SCK only when both the X and Y addresses are one. The state of the latch
can be ob served in the complemented form at the Scan Data Output (SDO)
when both the X and Y addresses are 1. Latch-state - SDO signals from all
latches are ANDed together to produce a scan-out signal of the circuit.
Ando (1980) also presented another type of addressable latch, called a
set/reset-type addressable latch (figure 8.19).
The configuration of sequential circuits designed by the Random-Access
Scan aproach is illustrated in figu re 8.20. A pair of address decoders, an
AND gate tree to combine all latch-state signals, and several clear inputs
are required, as well as the add ressable storage elements. An addressable

Scan Design for Sequential Logic Circuits

231

Combinational

Inputs

Outputs

Clear
and
Clocks
SOl

Addressable

PR

SCK

Storage
Elements

Scan
Address

1 - - - - SOD

Figure 8.20
Configuration of Random-Access Scan (Ando 1980; IEEE 1980)

latch located at the intersection of selected X and Y address lines is accessed

like a memory cell in an array. The clear inputs of all latches are tied
together to form one or several groups depending on the initialization
requirement. The preset signal PR gated by the scan clock SCK is propagated to all latches, but only one accessed latch is affected.
The Random-Access Scan technique has the following advantages: By
the control and observation of all storage elements, the sequential testgeneration problem can be reduced to a combinational one. Since the array
of addressable latches is similar to a memory array, both addressable
latches and memory arrays can be tested in a unified way. Further, each
scanout operation can be performed without disturbing the states of all
latches. The drawbacks of the Random-Access Scan approach are as follows: The extra gates are two address gates for each storage element, two
address decoders, and an output AND tree. This overhead is about 3-4
gates per storage element. The extra pins are scan control, data, and address
pins. This pin overhead is between 10 and 20, which can be reduced to
around 6 pins by the use of a serially loadable address counter.

232

Design forTestability

8.4 Incomplet e Scan Design and E nha nced Sca n D esign

Most of the scan design approaches mentioned earlier, such as the Scan
Path a nd the LSSD , require the deco mpositio n of a circuit into a purely
combinational pa rt and a scan path. H owever, in some cases this decomposition is not possible, because of some asynchro no us flip-flops or the
prohibitive co st of ext ra hardware. Hence, one needs to consider an incomplete scan design suc h that only so me of the nip-nap s can be chained
toge ther into the scan pat h.
A sca n design is sa id to be eithe r complete or incomplete, depend ing on
whether a ll o r only some of the flip-flo ps a re cha ined togethe r. O bvio usly, in
the complete sca n de sign the remaining ci rcu it afte r the scan path has bee n
removed fro m the or iginal seq uent ial circuit is a pu rely combinat ional
circuit. On the other hand, in the incomplete scan de sign the rem aining
circuit after the scan path has been remo ved is still a seq uen tial circuit.
However, if the sequen tial de pth of the remaining circuit is not so deep [e.g,
less tha n 3), then the cost of test generati on will be grea tly reduced. To this
end, T rischler (1980) pro posed the incomplete-sca n-pa th (ISP) app roach to
enhance circui t testability at a low overhead cost, and present ed th e design
rules and the test-generation meth od s for the ISP circuits. Th e ru les or
recommendat ions for the implemen tat ion of the ISP are the follow ing.

(1)The scan connection in thescan-path (SP) chain must be used as a source

of information and not as a point to receive informatio n.
In figu re 8.21, connection a is allo wed, but co nnection b is no t allowed
beca use the combinational logic ac ts as a so urce of informatio n to the sca nin port of the flip-flop.
The sequent ial pa rt of the circu it th at is not inclu ded in the SP should not
exceed a sequential depth of 3. Also, asynchronous loo ps th rough many
ga tes sho uld not be used.

(2) Whether o r not a nip-na p sho uld be linked into a n SP must be det ermined by the following rules:
(i) All nip-n aps th at are eas ily controllable from prima ry inpu ts (dire ctly or
through combinat ional logic) need not be linked into the SP.
(il) All flip-n aps that are easily controllable and observa ble from primary
inputs and ou t pu ts (short logical de pth) need not be link ed in to the SP.
(iii) Flip-flops tha t are not easily accessible m ust be linked into the SP.

Scan D esign for Sequential Logic Circuits

233

SCM Pa th

(a)

(bl

Combinationa l Pa rt of l ogi c

Figure 8.21
C onnection of scan path to combinationa l logic

(iv) When easily controllable async hro nous flip-flops ca nno t be lin ked into
the SP, th ey must be at least isola ted fro m influence of the SP .
!fthe remai ning sequential part outside the SP is ea sily controllab le from
primary inp ut s an d eas ily observable eith er at primary out puts o r through
the SP, as shown in figure 8.22, then th e seque ntial part outsid e the SP can
be easily test ed. Th erefore, for such circu its it may be possible to make
approxima tely the same amo unt of cost reduct ion in test genera tio n as in
th e case of the com plete sca n path. T his lSI' will be referre d to as an optima l
lSI' (O IS P).
In contrast, if the sequential pa rt outside the SP is controlled by the scan
pat h, as shown in figure 8.23, the total circuit with the SP must be simu late d.
For example, as shown in figure 8.24, the state of the asynchron ous flipflops ca n be influenced d uring the shift ing operation of the scan path.
Hence, the gene rated test pa tterns have to be ver ified fo r the total seq uential
circ uit. T his type of lSI' will be referred to as a no no ptima l lSP (N ISP). Fo r
a circui t with NI SI', lest pattern s are genera ted for the remai ning circ uit
excep t the scan pa th and then the generated test pattern s are simulat ed for
th e total circuit including th e scan path.
A problem for no nop timal l SI' such as th at illustrated in figure 8.24 can
be solved by enhancing the capability of flip-flops. DasGupta et al. (1981)
present ed an en hanced LSSD approach that allows int erfacing of LSSD
logic circuits with non-LSSD circuits. F igure 8.25 shows a modified SRL,

234

Design for Testa bility

Pr imary Inputs (PI)

PI

Scan Pa th

Pri mary Out put s (PO)

(a)

PO
(b)

Figure 8.22
O ptimal configura tions or ISP

PI

PI

Scan Path

PO
(a)

Figure 8.23
Nono ptimal configurat ions or ISP

PO
( b)

Scan Design for Sequential Logic Circui ts

o1

1 0 1

Scan Path

DQ

0 Q

tf

tf

l
1
0
0

Figure 8.24
Effect of scan-in pattern on flip-flops in scan path

o
c

- +--------- L1

l>-......
I
A

Figure 8.25
Stable shift-register latc h [DasGupta et al. [981; IEEE 1981)

235

236

Design for Testability

to scan-out

v,
SRL

#,
LSSD

Non-lSSD

Log; c

Logic
SRL

#2

C
1 _ _...J
A _ _...J
B _ _---J

Figure 8.26
Boundary betwee n LSSD and nonLS SD logic

called a stable SRL (SSRL), that is used as the basic storage element
together with the SRL proposed by Eichelberger and Williams (1977). The
SSRL is composed of an SRLand a third latch, L" which is clocked by shift
clock P.
Consider the boundary between LSSD and non-LSSD logic shown in
figure 8.26. In this circuit, it is impossible to apply a sequence Y, Y, = I I
followed by Y, Y, = 01 only by shifting, since the intermediate pattern
Y,Y, ~ 10 appears between II and 01.
The L, latch in an SSRL can be used to break a path from an LSSD to
non-LSSD circuits so that they do not interfere with each other. For this
example, SSRLs are replaced by SRLs as shown in figure 8.27. First, Y, Y,
= II can be applied from the L, latches, and then the pattern 01 is shifted
into the SRLs without affecting the states of the L, latches. The pattern 01
loaded into the SRLs is then transferred to the L, latches by applying the
clock P. In this way, with the aid of the L, latches in SSRLs, the intermediate pattern 10 is not fed to the non-LSSD circuit.

Scan Design for Seq uenti al Logic Circu its

237

t o sca n-o ut

Y,

LSSO

Logi c

I
A
B

Figure 8.27
LSSD to non- LSSD bou nda ry with SSRL (Das G upta et al. 1981; IEE E 1981)

To mak e th e mo st of the SSRL , DasGupta et a t. (1981) commen t, the

following design ru les must be followed.
When a n LSSD circuit feeds a non-LSSD circu it, the boundar y is defined
by SSRLs, whose L 3 outputs feed the non-LSSD circuit. Also, in order for
th e single-input change format for race-free testin g of the non-LSSD circuit
to be preserved , the L 1 and L 2 latches of these SSRLs cannot feed the nonLSSD circuit.
When a non-LSSD circuit feeds an LSSD circu it, the boundary is defined
by SRLs.
A clock that controls the L 3 latch of an SSRL that feeds a non-LSSD
circuit cannot clock the system data input of an SR L fed by the same nonLSSD circuit.
Clocks controlling SRLs and SSRL s on the periphery of a non-LSSD
circuit cannot feed the same circuit.

Design for Built-In Self-Testing

So far, we have been concerned with external testin g-that is, testing
appro aches in which explicit tests ar e applied by test equipment external to
the un it und er test. A primary weakness of a conventional testing philosophy based on externally applied test patterns is that a technique is
extremely constra ined by limited access to internal points in the unit under
test. As digital systems grow more complex and more difficult to test , it
becomes increas ingly a tt ractive to build self-testi ng a ids into the unit under
test. Self-t estin g as used here do es not refer to the total self-checking
capability defined in section 1.4. In this chapter the term is used in a broad
sense to refer to var ious testing approaches in which test patterns are
applied internally to the unit under test without the use of external test
equipment. The term built-in testing is also used in distinction from external
testing approaches. This chapter is concerned mainly with ofT-line built-in
self-testing approaches .
In th e preced ing chapter we considered various scan design approaches,
such as Scan Path and LSSD , to off-line external testing. Although those
scan design techn iques ha ve ind eed succeeded in red ucing the difficulty of
testing sequ ential log ic, th is type of testing still has some drawbacks:
Storage of a hu ge a mo unt of test patterns and responses is required, testpattern generation is still bothersome since special test-generation software
for scan design is required, and testing is slow because of the shifting of
patterns through the scan path.
Moreover, two special characteristics of VLSI and VHSI (very-highspeed intergrated) circuits-their very high speed of operation and their
very poor accessibility to external probing -will further aggravate the
burden of test generation and application. As circuit technologies advance
to higher speeds and la rger scales of int egration , new approaches will be
required for the testin g, at high log ic sp eeds, of large complex circuits that
may contain both multiple stuck-type and non-stuck-type fault s. Hence, it
might be necessary to consider testing approaches in a new light. Built-in
self-test approaches, which will be described in this chapter, seem to be
preferred over external testing and hold a good prospect for testing in the
future.

9.1 Signature Analysis

In a con vention al test ing scheme, test responses ar e all compared with the
co rrect reference values , which usually contain a high volume of data. An

239

Design for Built-in Self-Testing

--"F

Input

FF

'1

Ou tput

'2

Figure 9.1

lFSR for dividing polynomials

approach called compac t resting can avoid thi s difficulty of ana lysis and
sto rage of hu ge amounts of test response data. In compact testing, instead
of the en tire responses, compressed resp onse data are used for comparison .
Signarure analysis fa lls under the cat egory of compact testing.
Linea r feed back shift registers (LFS Rs) ca n be used to com press test
response da ta . Figure 9.1 shows an LFS R th at perfor ms polynomial division. As shown in th e figure, an LF SR consis ts of th ree types of devices;
memory elements (D flip-flops), m odulo-2 ad ders (EOR gates), and binary
co nstant multipliers. The constant multipli er for the con stant I is simply a
con nection in the LFSR, an d that for the constant 0 is simpl y no connection
in the LFSR. Such a data-compression techniq ue using LFSR s is based on
the cyclic redundancy check (eRe) codes, which a re widely used in systems
where da ta are tran smitted o r received. The fundament al results of CRC
codes can be found in algebraic codin g th eory (Pete rson and Weldo n 1972).
A serial input stream int o an LFSR co rre sponds to a po lynom ial; the
coefficients of th e polyno mial appear o n the input line high-order coefficien t first. T hat is, the polynomial

pIX)

P.X + P._IX -' + ... + PIX + Po

wo uld be en tered o n an input line, with P corni ng first, then P" _I one unit of
time lat er,
afte r ano the r unit of time, and so on. T he LFSR shown in
figure 9.1 ha s its characterist ic polynomial defined by th e constants co' c"

P._,

Cr

as foll ows:

240

Input

Design forTestability

I-..-..j FF

FF

FF

I--<~_Output

'r
Figure 9.2
Alternative LFSR for dividing polynomials

The LFSR divides any input polynomial p(X) by the characteristic

polynomial c(X). All the storage elements are set to 0 initially. The dividend
p(X) is shifted in serially via the input of the LFSR, and the quotient
appears serially at the output of the LFSR. After a total ofn shifts, the entire
quotient has appeared at the output, and the remainder is in the shift
register.

The LFS R shown in figure 9.1 is called the internal EO R type, since EO R
gates are located only between shift-register stages. There is an alternative
LFSR form that also performs the same division. Figure 9.2 shows the
LFSR dividing the input polynomial p(X) by the characteristic polynomial
c(X), where selected flip-flop output signals are fed back to the least
significant bit position via EOR gates. This type of LFSR is called the
external EOR type. Note that the order of constant multipliers in figure 9.2
is the reverse of that in figure 9.1. The external EOR type LFSR is more
suitable for LSI and VLSI than the internal EOR type, since the former does
not require irregularly placed EOR gates between shift-register stages. In
the LFSR of figure 9.2, the quotient can be obtained from the output
serially, but the final content of the shift register is not the remainder. This
differs from the internal EOR type LFSR.
LFSRs of both the internal and the external EOR type compress the
serial input stream to the length of the LFSR and form a signature. That is,
the final contents or the remainder of the LFSR is the signature. By
analyzing the signature, one can determine whether the circuit under test is
faulty or not. However. some faults are not detected when the erroneous

Design for Built-in Self-Testing

241

sequences caused by the faults are compressed to the same signature as the
correct one.
Let c(X) be the degree r polynomial forming the divisor, that is, the
characteristic polynomial of the LFSR. Let i(X) be a polynomial representing an input stream of length k, let q(X) be the quotient, and let s(X) be the
signature. Obviously, the degree of i(X) is k - 1 and the degree of s(X) is less
then r. For an internal EaR type LFSR, the signature is the remainder after
division, and thus we have

i(X) = c(X)' q(X) + s(X).

Errors in the input stream can be expressed by an error pattern such that
each nonzero bit represents an error in the corresponding bit position. Each
error pattern can be further represented as a polynomial e(X). For example,
if the correct input stream is 11001 (Le., the correct input polynomial is
(X) = X 4 + X 3 + l)and if an erroneous input stream is 01011 [Le.,i'(X) =
X 3 + X + IJ, then the error pattern is 11001EB 01011 = 10010 and is represented by e(X) = X 4 + X. In general, an erroneous input polynomial
t(X) can be repre sented by

t(X)

i(X) + e(X)

where e(X) is the corresponding error polynomial.

An error is not detected when i(X) and i'(X) have the same signature.
Hence, for an internal EOR type LFSR,

t(X) = c(X)q'(X) + s(X).

Further,

i'(X) = i(X) + e(X)

and

i(X) = c(X)q(X) + s(X),

so

e(X) = c(X} (q'(X) - q(X)).

Therefore, it follows that, for an error polynomial e(X), i(X) and i(X)
+ e(X) have the same signature s(X} ifand only if e(X) is a multiple of c(X).
The same result also holds true for an external EaR type LFSR (Smith

1980).

242

Design for Testability

Measures of the effectiveness of LFSRs at detecting faults have been

proposed by Frohwerk (1977) and Smith (1980). Since faults cannot be
observed directly (that is, since only errors can be detected), measures are
formulated in terms of errors detected. Frohwerk evaluated the errordetection capability of LFSRs by presenting the following two theorems.
Here th e proofs are borrowed from Smith (1980) since th ey are simpler than
those of Frohwerk (1977).
THEOREM 9.1 For either the LFSR shown in figures 9.1 or that shown in
figure 9.2, if its characteristic polynomial has two or more nonzero coefficients, then it can detect all single-bit errors.

Proof Let c(X) be the characteristic polynomial with two or more nonzero
coefficients. Then all nonzero multiples of c(X) must have at least two
nonzero coefficients. Hence, any error with only one nonzero coefficient
cannot be a multiple of c(X) and must be detectable. _
THEOREM 9.2 For a k-bit response sequence, if a ll possible error patterns
are equally likely, then the probability of failing to detect an error by either
LFSR of len gth r (figures 9.1 or figure 9.2) is

Proof A k-bit response can be represented by a polynomial of degree

k - I, a nd hence an error can be represented by an error polynomial of
degree k - I or less. Sin ce there are k coefficients in a polynomial of degree
k - I, the number of po ssible error pol yn omials is 2k - 1.
As mention ed earlier, all undetectable errors are rep resented by one of
the multiples of th e characteristic polynomial c(X); for example, an error
polynomial e(X) is represented by e(X) = c(X)p(X) for some polynomial
p(X). Since the degree of e(X) is less than k and the degree of c(X) is r, the
number of nonzero polynomials p(X) satisfying e(X) = c(X)' p(X) is
2k - r - 1. Hence, the probability of failing to dete ct an error is
Undetectable errors
2k - ' - I
Total errors
= 2k - I ' For lon g sequences, the probability of not detecting an error approaches
1/2', and hence the error coverage approaches I - 1/2', For a 16-b it LFSR,
this gives rise to the certainty of 99.998 percent that an error, if present, can

Design for Built-in Self-Testing

243

be detected. However, Smith (1980) pointed out that these measures are of
questionable validity because of unrealistic fault or error assumptions. For
example, theorem 9.2 holds regardless of the polynomial chosen. This
indicates that LFSRs based on very simple polynomials such as X' without
feedback are as effective as those based on more complex polynomials such
as X l 6 + X 9 + X 7 + X 4 + 1 (Frohwerk 1977). That is, the choice of a
characteristic polynomial has no effect on error coverage. Therefore, the
error coverage proposed in theorem 9.2 cannot be taken as a direct measure
of the effectiveness of the LFSR, since errors due to faults are not equally
likely and not independent. To provide a more accurate measure, Smith
(1980) considered two classes of dependent errors that are likely to occur:
burst errors and errors with incorrect bits spaced at intervals equal to some
power of 2. However, the best available measure might be the fault coverage
as determined by fault simulation.
So far we have considered serial input LFSRs monitoring only one
output line of the circuit under test. To monitor multiple outputs of the
circuit under test, data compression would require a parallel-to-serial
converter to use the serial LFSR described above. However, this is not an
effective approach. To implement effective compression of parallel data,
parallel input LFSRs are used. Figures 9.3(a) and 9.3(b) show internal and
external EOR type parallel LFSRs, respectively. Such a multiple-input
LFSR monitoring several lines in parallel is called a parallel signature
analyzer. On the other hand, the serial-input LFSR mentioned earier is
called a serial signature analyzer. Analytical results on the effectiveness of
parallel signature analyzers in detecting errors in response data from multiple outputs have been reported by Bhavsar and Heckelman (1981), Sridhar
et al. (1982), and J. L. Carter (1982).
9.3 (Bhavsar and Heckelman 1981) Let the response sequence
consist of L vectors of m bits each. If all possible error sequences are equally
likely, then the probability of failing to detect an error in the response
sequence by an r-bit parallel signature analyzer is

THEOREM

Proof For L response vectors of m bits each, there are 2 mL - 1 possible

error sequences. It can be shown that an r-bit parallel signature analyzer
maps 2mL possible sequences into 2' signatures uniformly. Hence, the num-

244

Design for Testability

(e)

Int ern al EOR type

FF

(bl

Figure 9.3
Parallel LFSRs

External EOR t ype

Design for Built-In Self-Testing

245

Si gnatu re Analyzer

Board Under Test

Data Probe

Cl ock Start Stop

Figure 9.4
Hewlett-Packa rd sign atu re ana lyzer

ber of error sequences that results in the same signature as the correct
signature is 2m L/2r - 1. The probability of failing to detect an error is thus

In theorem 9.3, it is assumed that all possible error sequences are equally
likely, i.e., that the erroneous bits produced by a faulty circuit are distributed randomly. However, this assumption is not realistic . J. L. Carter
(1982) showed a bound of the probability of masking errors by requiring
almost no assumptions about the behavior of faulty circuits. It has been
proved that if the order of the L test patterns is chosen randomly, then the
probability offailing to detect an error in the response sequence by an r-bit
parallel signature analyzer is less than 4/L, where r > log, (L - I). This
result holds for a set of randomly generated or carefully chosen test
patterns.
Serial signature analyzers are used commercially for field testing of
microprocessor-based systems. Figure 9.4 shows the configuration of the
Hewlett-Packard signature analyzer (Frohwerk 1977). The signa ture analy-

246

Design for Testability

zer uses a 16-bit LFSR. Data streams at designated circuit nodes can be
obtained by probing. A serial data stream at a circuit node is compressed to
a unique four-digit hexadecimal signature by the signature analyzer. Each
signature of suspect circuit nodes is compared with the precomputed correct signature. Three gating signals are supplied to the signature analyzer
through an active pad by the unit under test. A clock signal generated by the
unit under test ensures synchronous acceptance of data and gating signals
by the signature analyzer. A start signal initiates the measurement window
during which data are clocked into a 16-bit LFSR in the signature analyzer.
A stop signal closes the measurement window.

A microprocessor-based system under test is divided into the kernel and

the outlying circuitry. The kernel is the minimum configuration of microprocessor and ROM necessary to run the simplest test program, including
the clock and the power supply. In order to test the kernel first, a freerunning test makes the microprocessor run through its entire address fields.
The start/stop signals for the free running are derived from the lines of its
address bus. After the free running of the microprocessor, software-driven
tests start by running a test program stored in ROM, which generates
start/stop signals and sends data streams onto the data bus in order to test
the outlying circuitry. The ROM contains a special program for stimulating
the various nodes in the circuit under test. Guided by a troubleshooting
procedure, the field engineer can discover the cause of an incorrect signa-

ture by probing designated nodes, observing signatures, and tracing the

faults back to their source. To make the back tracing possible, it is necessary
to prevent a fault fom being fed back around and perturbing all data nodes.
Hence, feedback paths within the circuit must be broken, either by the use of
hardware switches, jumpers, or connectors, or by the disabling of gates with
software.
A serial signature analyzer is also used in a built-in test mechanism

proposed by Benowitz et al. (1975). The proposed system (figure 9.5) is

called the Advanced Avionics Fault Isolation System (AAFIS). In the
AAF1S, each sybsystem consisting of several boards contains a test-pattern
source, while the evaluation of the test data is performed by a serial
signature analyzer on each board.
As mentioned earlier, parallelsignatureanalyzersare more effective than
serial signature analyzers. Hence, many methods of incorporating parallel
signature analyzers in VLSI circuits for on-chip testing have been explored
recently. These methods are described in sections 9.2 and 9.3.

D esign for Built-In Self-Testing

247

Subsy s t em

Ie s t Patte rn
Source

Subsys tern
{'lput s

Modul e 1
Pass/Fa il

SA

Pass/ Fail

Su bsys t en
Faul t

Detection

P~ s s / Fail

L-t:~r--3
Fig ure 9.5

AAFIS built-in test mechanism

9.2 Built -In Logic Block Observer

One of the most popular (off-line)bu ilt-in self-test approaches is the built -in
logic block obse rver (BILBO) of Ko enemann et al. (1979), which aims at
realizing a bu ilt-in self-test mechani sm for highly integra ted modu lar a nd
bus-oriented systems, such as microprocessor-based systems. BILBO integra tes scan design with signature a nalysis by making use of an LFSR as an
on-c hip test generator and analyzer. An LFSR ca n work as a signa ture
a nalyzer, as ment ioned in section 9.1, and further can genera te a pseudorandom da ta pattern that can be used as a test pattern for a circui t unde r test.
Figure 9.6(a) is the logic diagram of an 8-bit BILBO composed of eight
Ilip-Ilops and some gates for shift an d feedback operations. S" and Soo, are
the scan-in inpu t and scan-o ut output for the 8-bit register, respectively.
The control inputs H, and H, can select four functional mode s of BILBO:

Zz

Z1

Qz

Z,

Z3

Q31

Z6

'S

Q,I

Q5

Q6

(a) logic diagram of BILBO.

z,

Z1

1
4

1
3

Q,

Q3

1
6

IS

Q,

Qs

(b) Normal mode ( 8]',,1. 8 "' 1 ).

2
Figure 9.6

Z7

Q6

Sin~

(c)

1
1

12

13

14

(d)

Shift register mode (

IS

Bl~O. B2~0

16

).

1
7

Parallel input lFSR mode ( B1 zl. 82=0 ).

Figure 9.6

Configuration of Scbit BILBO (Koenemann ct al. 1979; IEEE 1979)

Design forTestability

250

B, = I. B2 = I In this mode BILBO acts as a set of latc hes. as shown in

figur e 9.6(b). This is the normal system-operation mode. in which the data
2,.22 2 8 are loaded into the flip-flops and th e con ten ts of the flip-flops
are rea d fro m the o u tpu ts Q; for syst em operat ion .
B. = O. B, = 0 As shown in figu re 9.6(c). this second mo de form s a linear
sh ift register. D ata are serially loaded into the register th ro ugh
shifted
th rough so me inve rte rs. an d un loaded from t he register through SO"" T he
shift register is used in th e tes t mode in the same fashio n as the Scan Pat h
an d the LSSD.
B, = I. B, = 0 In the third mod e. BILBO is functio na lly co nverted into
a par allel in p ut L FS R as shown in figure 9.6(d). Th e parallel inp ut LFSR
can be utilized as a parallel signature analyzer a s disc ussed in section 9.1. If
all inputs 2,. 2, . . . 2 8 are kep t o n fixed logical va lues (say. all zeros). the
register becomes an au to nomous linear feedback shi ft register. a nd hence
the co ntents of the regis ter run th rou gh a pseudorand om sequence with
maximum peri od leng t h 2 8 - 1. In general. the period length of a pseudorand om seq uence depends o n the number of stag es of the LFSR and its
charac teristic polynomial. F urt her mo re. th e pe riod of a non- ma ximallength seq uence depends o n the initial co nte nts of the LFSR, ca lled t he seed.
In this way. t he pa ralle l LFSR can work as a pseudo rand om-patt ern

S,,,

generator .

B,

= 0, B, =

T he fourth m od e is used for resett ing the cont ent s of the

register.
Th e BILB O approac h is aimed at applying to hig hly integra ted mo d ular
and bus -orien ted systems in which funct io nal modu les, suc h as RO Ms.
RAMs. ALDs (arithm etic logic units). an d I/ O s. are connected by bus
routin g. Since clocke d latches a re usually used to inter face the m odules and
th e bu ses. BILBO s ca n take the place o f the latches. as shown in figu re 9.7.
Each mod ule has two BILBOs; o ne is used as a built -in tes t-pa tte rn
generat or to stim ulate the mod ule. an d the othe r as a parallel signa tu re
analyzer to compress the correspondi ng test resp onses into a signature.
First. the system is set to a shift-registe r mode in order to init ialize the
BIL BO s. Eac h BILBO is initia lized to gene rate pseud or a nd om pattern s o r
to compress the test responses. T he system is then swi tche d to a self-test
m ode; that is. BILBO s are con ver ted into LFS Rs. In this self-test mode.
each circuit und er test will have pseud orand om patterns applied to its
inputs and will have its o u tputs stored in the parallel signatur e ana lyzer.
Afte r a fixed number of patterns have been a pplie d. the system is switched

251

Design for Built-In Self-Testing

BU S
'I

I
Sin

B I LBO

I
I

B I LB O

CIRCUIT
UNDER
TEST
Sout

I
CIRCUIT
UNDER
TEST

I
BILBO

MO DULE i

I
BILBO

l-

MODUL E 1+1

Figure 9.7
Modular bus-o riented design with BlLBOs

back to the shift-register mode, and the resulting signatures in BILBOs are
scanned out and compared with the expected signatures. In th is way, each
module can be tested automatically apart from the rest of the system.
Since the LFSR creates pseudorandom patterns, the testing approach
mentioned above is suited to those circuits that are susceptible to pseudorandom patterns. However, circuits with large fan-in, such as programmable logic arrays (PLAs), are not tested efficiently by pseudorandom
patterns. For example, consider an n-input AN D gate. The stuck-at-O fault
on the first input line can be detected only by a test pattern 111 ... 1. Hence,
each pseudorandom pattern would have probability 1/2" of detecting the
fault. The random logic circuits with low fan-in of the gates may be tested
quite well with pseudorandom patterns. However, most PLAs have large
fan-in, and thus the probability of generating an appropriate test pattern
becomes quite low if pseudorandom patterns are utilized. To test PLAs
efficiently, a set of determin istic test patterns might be required. Daehn a nd
Mucha (1981a) presented a method for designing nonrandom test pattern
generators by means of nonlinear feedback shift registers, and applied it
with BILBO to the PLA problem .

252

Design fo r Testability

Figure 9.8
Test-pattern generato r fo r NO R arrays

Co nsider NOR-NO R type PLA s in noMOS technology. It is easily seen

that all the stuck-at faults, crosspoint faults, an d bridging fau lts between
adja cent lines in a naked n-input NOR array can be detected by applying
the following n + I patterns:

0 0
I 0 0
o 1 0

0 0
0 0
0 0

0 0 0 01.
T hese test pa tte rns a re read ily genera ted by means of a no nlinea r feedback
shift register as shown in figure 9.8. Th is type of nonlin ear feedback shift
register can be used for testing NOR arrays. By modifying the BILBO so
that it has a mode of a nonlinear feedback shift register, one ca n use the
resulti ng BILBO for both nonran dom patt ern generation a nd parallel
signa ture a nalysis of PLAs. Figure 9.9 shows a general structure of built-in
self-testa ble PLAs proposed by Daehn and Mucha (198Ib) .
Each of the NO R arrays is tested separately. Th e test patterns for the first
NOR a rray are generat ed by BILBO I, and the test responses a re mon itored by BILBO 2. After n + I clock cycles, the signature in BILBO 2 is
shifted ou t for inspecti on. The second NOR ar ray is similarly tested by

253

Design for Built-In Self-Testing

!8IL80 1

.
I

--

V)

cc
w

0
0

I.

NO R
,

ARRAY 1

'"

'---

r-

-. .

.,

a::l

...J

cc

'---

.--V)

NOR

cc
w

I-

cc
W

>

:z

ARRAY 2

,
I

'---

8 IL80

31

Figure 9.9
Self-testable PLA with BILBOs (D aehn a nd M ucha 1981; IE EE 1981)

converting BILBO 2 into a pattern generator and BILBO 3 into a signature

analyzer.
Testing of the decoders and the output inverters can be performed by
connecting the outputs of the inver ters with the inpu ts of the decoders and
by using BILBO 3 as a pattern generator and BILBO 1 as a parallel
signature analyzer. Wh en the decoders are all one-b it decoders, the test
pattern s for NOR arrays are sufficient to det ect all the stuck-at and brid ging faults in the decoders. However, these test patterns are not sufficient to
test two-b it decoders. The test patterns for two-bit decoders are
0 0 0
1 0 0
1 1 0
0 1 1
0 0

...

0
0
0
0

0
0
0
0

1.

Design for Testability

254

00

1
1

0
1

0
0

o
o

0
0

Figure 9.10
Test-pattern generato r for two-bi t decoders

These patt erns can be generated by means of a nonlinear feedback shift

register shown in figure 9.10.
As shown in figure 9.11(a).each line of the NOR a rray passes throu gh the
array a nd hence can be controlled from and observed a t either side of the
array. Considering this feature, we can place BILBO s properly as shown in
figure 9.l l( b). Furthermore, if the PLA has input/outpu t registers, the
overhead for BILBOs will be reduced by replacing these registers with
BIL BOs as shown in figure 9.1I(c).
T he BIL BO approach mentioned abo ve has the following adva ntages.
Since a built-in test-pat tern genera tor is used, the time-consuming process
of test genera tion is elimina ted.
Since a built-in data-compression techniqu e is used, the amount of test da ta
is greatly red uced.
External operations are reduced to initializing the registers and checking
th e signatures.
T he circuits are tested a t their norm al speed.
Simultaneous testing of several modules becomes possible.
T he built-in test is also applicab le in the field.
In spite of these advantag es, the technique has some disadvan tages. T he
overhead is higher than for scan design approaches such as LSSD a nd Scan

255

Design for Built-In Self-Testing '

NOR ARRAY

' I~

"~
~

(al

( bl

Figur e 9.11
Placeme nt of BILB Os

(el

256

Design for Testability

Clock
Rest

BUS

Parallel I/O
Int erface

Par allel Ports

Figure 9.12
Block diagram or MICROBlT I (Fasang 1982; IEEE 1982)

Path because the re ar e extra EOR gates in LFSRs. Furthermore, these

extra EOR gat es and some gates used for mode switching cause more delay
in the system data path th an the scan design techniques. Ho wever, if we
consider the growing cost and complexity of testing VLSI circu its, the builtin self-test approach seems to be an effective and attractive method.
Built-in self-testable architectures for microcomputers have been reported in which parallel signature an alysis (BILBO) and serial signature
analysis techn iques were implem ented as on-chip testing aids. Fasang
(1982) has reported a microprocessor-based system in which a built-in selftest technique called MICROBIT was imp lemented. Figure 9.12 is the
block diagram of MICROBIT I. The system is typically bus-oriented and
composed of the following major blo cks: a microprocessor (the 8085), clock
and reset circuits, ROM, RAM, parallel input/output ports, a serial I/O
port, a nd a n extern al system bus access a rbitra tor. The 8085 is a n noMOS 8bit gener al- purpose microcomputer chip. In addition to these standard
blocks, the M ICRO BIT has two BILBOs: a pseudorandom-pattern generator (PRPG) and a parall el signature analyzer (PSA). The PRPG generates a rep etitive sequence of 255 pseudorandom patterns, which are used

Design for Built-In Self-Testing

257

for testing RAM and the multi bus ada ptor. In the MICROB ITsystem, the
function al or o perationa l testin g is basically performed. T he 808 5 microprocessor is lested by runnin g a test program . First, the most funda mental
test, called the kern el test, checks the 8085 with respect to only a few
instructions, as well as the address, data, and control buses. The n the
remaini ng instructions of th e 8085 are executed and compared with the
expected result s. In the testing of the 8085, BILBOs (PRPG and PSA) are
not used. BILB Os are used for testing RAM, RO M, the mul tibus ad aptor,
an d themse lves. In the ROM test, the contents of the ROM are read out ,
one byte a t a time, a nd compressed by the PSA. The final content s of the
PSA are compared with the expect ed signature by the 8085. In the RAM
test, the first 256 bytes of RAM a re filled with the 256 patt erns from PRPG,
the next 256 bytes with the 256 patt erns from PRPG + I, and so on. After
all bytes of RAM are filled, the contents are tra nsferred to the PSA, one byte
at a time, and compre ssed into a signa ture. Then the signa ture is transferr ed
to the 8085 an d compared with the expected signa ture stored in PRO M. In
this way, the MI CROBIT system implements a microprocessor-based
system with built-in self-test function,
Thatte et a!. (1982) proposed a n a rchitecture for on-chip built-in testa ble
VLSI process ors. The proposed meth od ology is bas ed on bit-sliced, busoriented arc hitecture, which is am enable to on-chip built-in impleme ntation using BILBOs. Figu re 9.13 shows the general con figuration of the
processor. In general, a typica l single-chip VLSI processor is comp osed of
three main sec tio ns; a data-path sectio n, a control section, and an o n-chip

memory section. Th e data-pat h section stores, manipulates, and tran sfers

data. It is usually composed of registers, ALUs, a nd dat a buses. The contro l
section, which decodes machine instructions and generates con trol signals
for the dat a- path section an d other logic, is composed of a control ROM,
PLA , and dec oders. Oth er on -chip mem ory, such as program RO M for

storing machine-level program s and da ta RAM for stor ing data, is contained in the on-chip memory sectio n.
As shown in figure 9.13, the proposed testable processor has two monitors:a control monito r and a da ta monit or. Both are the same a nd have four
modes of operat ion: the norma l mode, the signatu re-ana lysis mode, the

scan (shift) mode, and the rotate mode. Except for the rotate mode, the
monitor work s in the same way as th e BIL BO. The control monitor can be
configured as a parallel signature analyzer to monito r the control signals of
the data-path section. The control ROM is tested by readin g out the ent ire

Design for Testability

258

CONTROL

SECTION
.....---_ _

Scan-Out

Vl

ON-CHIP

DATA PATH

ii?

SECTION

MEMORY
SECTION
Scan-In
Scan-Out

Scan-In

Figure 9.13
A configura tion o r built-in testable VLSI proce ssors [Tha tte et al. 1982; IEEE 1982)

ROM and compressing the control signals into a signature. In a similar

fashion, the data monitor is configured as a parallel signature analyzer to
monitor and compress the output data produced by the data-path section.
Each functional test pattern for the data-path section consists of control
signals and data operands. Data operands can be generated by the use of
simple hardware such as counters and sifters. Control signals can be
generated by a microprogram stored in an additional ROM or by a
machine-instruction program.
The on-chip program ROM is tested by reading out the entire ROM and
compressing the ROM outputs into a signature by means of the data
monitor. For data RAM testing, test patterns stored in on-chip program
ROM are applied to RAM and the outputs are compared with the expected
values by means of a comparator.
Thatte et al. (1982) implemented on a CMOS gate array a test vehicle
consisting of a four-bit wide, bit-sliced data path equipped with th e data
and control monitors. According to their study, the additional silicon area
required for the data and control monitors is expected to be 4 percent of the
total chip area for a 16-bit processor and 2.2 percent for a 32-bit processor.
In the above-mentioned architectures, the BILBO technique based on
parallel signature analysis is utilized. Another built-in self-test scheme using
an on-chip seri al signature-analysis technique has been implemented on a

259

Design for Built-In Self-Testing

X BUS

PROGRAM
ROM

CONTROL

Figure 9.14
Block diag ram of MC6 804P2 (Kuban and Bruce 1983; IEEE 1983)

commercial MOS microcomputer, the MC6804P2 (Kuban and Bruce

1983). A block diagram of the MC6804P2 is given as figure 9.14. Since this
computer is designed for 4-bit and low-end 8-bit applications, all data
transactions are performed serially and parallel conversions are performed
locally where necessary. The ALU and the buses are all one bit wide.
Because of its serial architecture, the MC6804P2 makes use of a serial
signature analyzer (SSA) for the compression of test response data. Each
circuit in the MC6804P2 is tested by means of a self-test program stored in
program ROM and data ROM. The self-test program occupies 288 bytes of
the program ROM and 16 bytes of the data ROM. Test results are compressed into a single 16-bit signature, which is shifted out for off-chip
verification. According to Kuban and Bruce, the overhead for the built-in
self-test scheme is less than 5 percent of the total chip area.

9.3 Self-Test with Scan Design

As was described in chapter 8, scan design approaches such as the Scan
Path and the LSSD can simplify testing of complex sequential logic circuits.
Such techniques were developed by mainframe manufacturers and so are

260

Design for Testability

Memory 1 ements

Shift

Register

Combinational
I
I

Logic

'--------------

Figure 9.15
External self-test using shift register (Segers 1981;

IEEE (981)

mainly used in large computers. Even with the scan design approach, test
generation is still a heavy burden. Moreover, test application is time
consuming, because the test patterns have to be serially shifted in and the
responses have to be shifted out through a string of latches. To overcome
these shortcomings, a number of self-test approaches combining the scan
design concept and linear feedback shift registers (LFSRs) have been
proposed. Those techniques that make use of LFSRs as both pseudorandom-pattern generators (PRPGs) and signature analyzers (SAs) have
been classified by El-ziq and Butt (1983).
First, the self-test techniques can be classified as either external or internal, depending on the position of the LFSRs. In the external technique, all
the self-test aids or LFSRs are external to the circuit under test. Hence, the
external technique has the advantages that the self-test aids will be just an
overlay on an existing scan design, so no changes are needed inside the
circuit. ("External" self-testing does not mean the conventional testing
using external equipment, nor does it preclude on-chip implementation of
external self-test schemes.) The internal technique puts the self-test aids into
the circuit under test; that is, LFSRs are included in the circuit under test as
a part of the scan path. The internal technique seems to be a more attractive
solution because it is flexible in realizing various self-test schemes, from low
levels to higher levels.
There are four major techniques of the external type. The first is a self-test
method proposed by Segers (1981). Figure 9.15 shows the general configuration of the proposed method. The pseudorandom-pattern generator and
the signature analyzer are combined into one m-bit feedback (via an EOR

Design for Built-In Self-Testing

261

Circuit

Under
Test

Figure 9.16
External self-test using LFSRs (Bardell and McA nney 1982; IEEE 1982)

gate) shift register, which is placed outside the module under test. The
memory elements or latches of the circuit under test are designed to form a
shift register for the scan path technique. Briefly, the self-testing is performed as follows: By shifting a fixed first pattern into the feedback shift
register and, as a consequence, into the latches of the scan path, the circuit
under test is initialized. After shiftng a test pattern into the latches, the
circuit is switched to normal mode and the system clocks are cycled to
capture the test responses into the latches. Then the contents of the latches
are shifted out and compressed into the feedback shift register. At the same
time, the next pseudorandom pattern is shifted into the scan path. After the
above operations have been executed a fixed number of times, the final
signature of the feedback shift register is compared with the expected
signature. This results in a go/no-go signal.
The second external self-test scheme, proposed by Bardell and McAnney
(1982), is illustrated in figure 9.16. The primary inputs (PIs) of the circuit
under test are driven by an LFSR, which generates pseudorandom patterns.
The scan input to the scan path shift register is driven serially by another
pseudorandom-pattern generator, an LFSR. The responses at the primary
outputs are compressed in parallel into a signature by a parallel signature
analyzer, and the response at the scan output is compressed serially by a
serial signature analyzer. Both parallel and serial signature analyzers can be
implemented using LFSRs, as mentioned in section 9.1.

262

Design for Testability

Figure 9.17
Self-lest with multiple scan pa ths (Segers 1981; IEEE 1981)

The third technique for external self-test is a variation of the abovementioned scheme of Segers (1981). In order to make the random patterns
more effective and to reduce the test time, the scan path is split up into
several parallel paths. The configuration of the multiple scan paths is
illustrated in figure 9.17.
The fourth technique is also based on multiple scan paths. Figure 9.18
shows the configuration of the self-test scheme, which was present ed by
Bardell and McAnney (1982). A parallel pseudorandom-pattern generator
and a parallel signa ture analyzer are connected to multiple scan paths, each
of which forms a string of latches for each partitioned circuit.
Internal self-test techniques ba sed on LFSRs can be further classified into
two types: centralized and distributed. Figure 9.19 illustrates the centralized
technique proposed by Komonytsky (1982). This technique is based on the
LSSD and has the following features.
All pr imary inputs and prim ary outputs are buffered by additional shiftregister latches (SRLs), which are call ed input latches and output latches,

Design for Built-In Self-Testing

263

Pseudorandom Pattern Generator (PRPG)

Chip 1

Chip

Chip n

Parallel Signature Analyzer (PSA)

Figure 9.18
Self-test using par allel input LFSR s (Ba rdell and McAnney 1982; IEEE (982)

respecti vely. Those SRLs that ar e not input or output latches are called
int erior latches.
All the SRLs form a shift-register string for parallel and serial pattern
load ing a nd unloading.
The first group of SRLs form a pseudorandom-pattern generator.
The last group of SRLs form a signature analyzer.
F or the circuit of figure 9.19, the self-testing proceeds as follows .
(1) Initial ize all SRLs to 0 but initialize the PRPG latches to 1 in order to
provide a deterministic point for the self-test. The PRPG latches must not
be cleared to zeros or they wiII stay locked in a zero state forev er. After all
latches have been initialized, apply the first test pattern to the combinational logic.
(2) Clo ck all system clocks, capturing responses from the combinational
logic in the interior latches and output lat ches.
(3) Shift out all interior and output latches to compress the responses into a
signature by means of the sign ature analyzer (the last group of the SRLs) .
While the contents oflatches are shifted, pseudorandom patterns are shifted
from the PRPG (th e first group of the SRLs) into the interior latches.
(4) Rep eat steps 2 and 3 until th e test is complete.

Design for Testability

264

Pr ima ry Inputs

Pr-t eary Inputs

,,r--- ~

,,
,
,,I
Scan
In

Input Regis te r

- - -

- - , Extra Reets t er

C. C.

--t}(

- --,,

Internal Regi s t er

~1
Con:b ina t ional Cfreu; t

\1

\,
I ext ra

')

(C. C.)

Regist er

- - - - '1- - - ~ Output Regis ter

"-----S

,,,
,
,
,

,
I

MU X

Pri mary Outputs

I
Scan Ou t

Primary Ou t puts

Figure 9.19
Centralized internal self-test app roach (Komonytsky 1982; IEE E 1982)

(5) Compare the final signature compressed in the signatu re analyzer with
the expected signature.
In the self-test technique pr oposed by Komonytsky (1982), either the test
responses are gathered by an external signat ure analyzer or the signa ture is
computed internally. In bot h cases, serial signa ture ana lysis is used. and

hence the testing is relat ively slow. If a signature an alyzer can compress
da ta fro m parallel an d serial di rections, less test time will be required than
when onl y a serial signature ana lyzer is used . EI-ziq a nd BUll (1983)
presente d a techn ique called a mixed-m ode built-in self-test (figure 9.20),
which is similar to the technique of K om onytsky but differs in signature
analysis. Much as in the scheme of figure 9.19, the first group ofla tches form
a pseudor andom-patt ern generator, which can feed the output data in both
parallel and serial d irections. (This is denoted in figure 9.20 as the mixed

Design for Built-In Self-Testing

265

Primary Inputs

Primary Inputs

Scan
In

c..:.:=rT'==.J
Comb1national

-,
,,

,,

Circuit

I
I
I

r - - - - -L-

Internal Register
==:;-;::=="-----------'

,
-~

,,,
,,
I

--

Scan

--

Out

Primary Outputs

Primary Outputs

Figure9.20
Mixed-mode self-test approach (EI-ziq and Butt 1983; IEEE 1983)

PRPG.) The last group of latches form a signature analyzer (called the
mixed SA), which collects the output data from the combinational logic
feeding into it (in the parallel direction) and mixes it with the output data
stored in the output registers (in the serial direction). Note that in the selftest procedure of Komonytsky (1982) all the response data captured in the
interior latches are also serially shifted into the signature analyzer.
Another type of internal self-test techniques is the distributed technique,
in which every register element has some extra logic that enables it to perform as part of a test-pattern generator or a signature analyzer. The BILBO
approach of Koenemann et al. (1979) belongs to this class. Bardell and
McAnney (1982) proposed a self-test approach called simultaneous self test,
which is also of the distributed type. In this approach, every SRL is required
to be replaced by a self-test SRL, as shown in figure 9.21. With +Test
Mode at a logical 0, the self-test SRL behaves as an SRL, i.e., a normal

system latch or a shift-register element. With

+ Test Mode at a logical! and

266

Design for Testability

System Data
System Clock - - t - - - - - - - - - - i
Cl

+Test Mode
Scan Data

Shift /l C l o c k - - - - - - - - - J
System Clock C

or Shi f t B Clock

Figure 9.21
Self-test SRL (Barden a nd McAnney 1982; IEEE 1982)

the system clock at a logical 0, the self-test SRL can be used as an element of
LFSRs. The configuration of this self-test mode is illustrated in figure 9.22.
The distributed technique is well suited to system-level testing, since the
testing can be performed much more rapidly than with all other techniques
that need to sh ift the data through th e scan path. However, it requires extra
hard ware, which may also affect the system performance. Furthermore, it
doe s not test for the I/O logic lying between the PIs and the self-test SRLs
and between the self-test SRLs and the POs. Hence, for manufacturing
testing of individual modules, the test procedure must be augmented to
allow testing of the I/O logic. One approach is to connect the POs and PIs
by making use of socket wiring. Another approach is to use external
PRPGs and SAs for testing the I/O logic.

9.4 Self-Verification
In general, testing appro aches are classified as on-line or off-line. On-line
testing is performed during system run time, concurrent with normal system operation. Data patterns from normal computation serve as test
patterns, and a failure occurrence caused by some intermittent or solid fault
can be detected by means of built-in fault-detection circuits (FOCs). During
normal system o pera tion, the FOCs continuously monitor the intermediate
as well as the final o utputs of the circuit under test and immedi ately detect
an y intermittent or solid failures . These FOCs for on-line testing can also be
useful for off-line self-testing. Although the o bject of off-line testing seems
different from that of on-line test ing, they have a common goal: th e detection and isolati on of faults and the verificati on of fault-free operation of

267

Design for Built-In Self-Testing

Scan-In

Scan-In

Scan-Out

Scan-Out

Figure 9.22
Distributed internal self-test approach (Bardell and McAnncy 1982; IEEE 1982)

circuits. This goal may become more achievable if both on -line and off-line
techniques are used together harmoniously.
A self-test approach called self-verification, proposed by Sedmak (1979),
reflects an attempt to merge off-line and on-line testing techniques. Selfverification is defined by Sedmak as the ability of logic to verify a failurefree status automatically, without the need for externally applied test
stimuli (other than power and the clock) and without the need for the logic
to be part of a running system.
The general configuration of the self-verification approach is illustrated
in figure 9.23. As shown in the figure, the self-verification scheme requires
automatic fault-detection circuits and test-pattern generators (TPGs).
FOCs are used to detect any intermittent or solid failures by monitoring the
outputs of the circuit under test. The error-status generator assembles and
encodes information about the presence and location of detected faults.
Examples of FOCs are checking circuits for error-detecting codes (parity
codes, m-out-of-n codes, residue codes, and the like) and comparators for
checking duplicated logic. To guarantee the correctness of test results, these
FOCs are usually designed so as to be "self-checking."
Test-pattern generators provide the test patterns necessary to stimulate
the circuit under test and expose any faults to the FOCs. The TPGs can be
implemented in various ways (random-pattern generator, rn-out-of-n code

268

Design for Testability

TPG
Super vi sor

Primary
Inputs

Primary
Under

Outputs

Test

Error
Status
Generator
Error Signa 1s
Figure 9.23
General configurat ion of self-verification approach (Sedmak 1979; IEEE 1979)

generator, and so on), depending on the nature of the circuit under test. In
the proposed self-verification approach, the TPG illustrated in figure 9.24 is
utilized. This TPG consists of a binary counter and a parallel-in/serial-out
shift register. It generates all Z"possible input combinations to test exhaustively a combinational circuit having n inputs. Although such exhaustive
testing has the advantage that all stuck-at faults as well as non-stuck-at
faults can be detected, the test application appears to consume far too much
time. However, the test time can be reduced by partitioning the logic to be
tested so that partitioned subcircuits have few enough inputs to allow
exhaustive testing and so that many of the subcircuits can be tested in
parallel.
The TPGs are coordinated by the TPG supervisor shown in figure 9.23.
The TPG supervisor is normally used for controlling the starting and the
stopping ofTPGs only during self-verification and not during normal operation of the system. Hence, in normal system operation, FOes can also be
used for on-line automatic fault detection.
Figure 9.25 shows an example of the application of self-verification using

269

Design for Built-I n Self-Testing

From TPG Superv isor

To Ci r cuit
Under Test
Figu re 9.24
Exhaustive test- pa tte rn generator

Pari ty Checker

Combinat ional
Logic

Register 2

Fig ure 9.25

Self-verification using par ity codes

Design for Testability

270

Functional Logic

Combi nationa 1
Logic

Dupl i cate Complementary Logic

Combinational
Logic

Figure 9.26
Self-verification using d uplicat ion

parity codes. Two registers have the added parity bits, and a parity checker
is placed at the o utput of each register. In this example it is su pposed that
the combinational logic may not pre serve parit y, and hence the parity bits
are regenerat ed at the outputs by a parity generator. On the other hand,
faults in the parity generato r can be detected by means of the parity check at
register 2 and the parity prediction/c omparison check spanning the combinational logic and register 2.
Figure 9.26 shows another example of the self-verification approach. The
technique is based on duplication of logic in complementary form . The left
side of the figure shows the function al circuit; the right side is the duplicate
complem entary logic. Comparators compare the funct ional-logic signals
with the duplicate complementary-logic signals at the outputs of registers.
Both comparators a re designed so as to be self-checking.
As described above, the self-ver ification approach falls under the
category of self-testing. Hence, simil ar to a number of other self-test approaches, the self-verification approach ha s the follo wing advantages:
The time-consuming process of test generation is elimin at ed.
Sto ra ge of a hu ge am ount of test data is elimin ated.

Design for Built-In Self-Testing

271

Circuits are tested a t their full machi ne speed.

Testing is possible a t all packa ging levels, such as the chip, ca rd, an d system
levels.

In addi tion to these adva ntages, the self-verifica tion a pproach has a uniq ue
a ttr ibute: A major porti on of the logic req uired for self-verification is also
used for automatic fault detection a nd recovery d uring normal operation of
th e assembled system.

Bibliography

Abramovici, M., Y. H. Levendcl, and P. R. Menon. 1982. A logic simulation machine. Proc.
19th Design Automation Con!, pp. 65-73.

Agarwal, V. K. 1978. Fanout-free Boolean functions and Lexpressions. Proc. Con! Information Sciences and Systems, Johns Hopkins University, pp. 227-233.
Agarwal, V. K., and A. S. F. Fung. 1981. Multiplefault testing of large circuits by single fault
test sets. IEEE Trans. Comput. C-30 (11): 855-865.
Aho, A., J. Hopcroft, and J. Ullman. 1976. The Design and Analysis of Computer Algorirhms.
Reading, Mass: Addison-Wesley.
Ak ers, S. B. 1973. Universal test sets for logic networks. IEEE Trans. Comput, C-22 (9): 835839.

Akers, S. B. 1976. A logic system for fault test generation. IEEE Trans. Compui. C-25 (6): 620629.
Ando, H. 1980. Testing VLSI with random access scan. Proc. COMPCON 1980, pp. 50-52.
Armstrong, D. B. 1966. On finding a nearly minimal set of fault detection tests for combinatorial nets. IEEE Trans. Electron. Comput. EC15 (2): 63-73.
Armstrong, D. B. 1972. A deductive method for simulating faults in logic circuits. I EEE Trans.
Comput. C-21 (5): 464-471.
Bardell, P. H., and W. H. McAnney. 1982. Self-testing of multichip logic modules. Proc. 1982
IEEE Test COIlf., pp. 200-204.
Barzilai, Z., J. Sa vir, G. Markowsky, and M. G. Smith. 1981. The weighted syndrome sums
approach to VLSI testing. IEEE Trans. Comput. C-30 (12): 996-1000.
Barzilai, Z., D. Coppersmith, and A. L. Rosenberg, 1983, Exhaustive generation orbit patterns
with applications to VLSI self-testing. IEEE Trans. Comput. C-32 (2): 190-194.
Bennetts, R. G., C. M. Maunder, and G. D. Robinson. 1981. CAMELOT: A computer-aided
measure for logic testability. lEE Proc, 128 (5): 177-189.
Benowitz, N., D. F. Calhoun, G. E. Alderson.J. E. Bauer, and C. T. Joeckel. 1975.An advanced
fault isolation system for digital logic. IEEE Trans. Comput. C-24 (5): 489-497.
Berg, W. C, and R. D. Hess. 1982. COMET: A testability analysis and design modification
package. Proc.1982 IEEE Test Conf.; pp. 364-378.
Betancourt, R. 1973. Derivation of minimum test sets for unate logical circuits. IEEE Trans.
Comput. C-20 (1l)' 1264-1269.
Bhattacharya, B. B., and B. Gupta. 1983. Syndrome testable design of combinational networks
for detecting stuck-at and bridging faults. Proc. 1983 Int. Test Conf., pp. 446-452.
Bhavsar, D. K., and R. W. Heckelman. 1981. Self-testing by polynomial division. Proc. 1981
IEEE Test Conf.; pp. 208-216.
Bossen, D. C, and S. J. Hong. 1971. Cause and effect analysis for multiple fault detection in
combinational networks. IEEE Trans. Comput. C-20 (11): 1252-1257.
Bozorgui-Nesbat, S., and E. J. McCluskey. 1980. Structured design for testability to eliminate
test pattern generation. Proc.Ltnn Int. Symp. Fault-Tolerant Computing, pp. 158-163.
Breuer, M. A. 1972. Generation of fault tests for linear logic networks. IEEE Trans. Comput.
C-21 (1)' 79-83.
Breuer. M. A., and A. D. Friedman. 1979. TEST/80-A proposal for an advanced automatic
test generation system. Proc.IEEE Autotestcon, pp. 305-312.
Brglcz. F. 1984. On testability analysis of combinational networks. Proc. Int. Symp. Circuits
and Systems, pp. 221-225.

Bibliography

273

Carter, J. L. 1982. The theory of signature testing for VLSI. Proc. 14th Ann. ACM Symp.
Theory of Computing, pp. 66-76.
Carter, W. C. 1982. Signature testing with guaranteed bound for fault coverage. Proc. 1982
I EEE Test Con!, pp. 75-82.
Cha, C. W" W. Donath. and F. Ozguner. 1978. 9-V algorithm for test pattern generation of
combinational digital circuits. IEEE Trans. Comput, C-27 (3): 193-200.
Chang, H. Y., S. G. Chappell, C. H. Elmensdorf, and L. D. Schmidt. 1974. Comparison of
parallel and deductive fault simulation methods. IEEE Trans. Comput. C-23 (II): 1132-1138.
Chappell, S. G., C. H. Elrnensdorf and L. D. Schmidt. 1974. LAMP: Logic circuit simulation.
Bell System Tech. J. 53: 1451-1476.
Clegg, F. W. 1973. Use of SPOOFs in the analysis of faulty logic networks. IEEE Trans.
Comput. C-22 (3): 229-234.
Cook, S. A. 1971. The complexity of theorem proving procedures. Proc. Brd ACM Symp.
TlJeol'y of Computing, pp. 151-158.
Coy, W., and A. Vogel. 1981. Inserting test points for simple test generation. Proc. 4ch InC.
Conf. Fault- Tolerant Systems and Diagnostics, pp. 180-186.
Daehn, W., and J. Mucha. 1981a. Hardware test pattern generation for built-in testing.
19811 Test cs, pp. 110-113.

Proc.

Daehn, W., and J. Mucha. 1981b. A hardware approach to self-testing of large programmable
logic arrays. IEEE Trans. Comput. C-30 (I I): 829-833.
DasGupra, S., C. R. P. Hartmann, and L. D. Rudolph. 1980. Dual-mode logic for functionindependent fault testing. IEEE Trans. Comput, C-29 (11): 1025-1029.
DasGupta, S., R. G. Walther, T. W. Williams, and E. B. Eichelberger. 1981. An enhancement to
LSSD and some applications of LSSD in reliability, availability, and serviceability. Pvoc.
11th Symp. Fault- Tolerant Computing, pp. 32-34.
DasGupta, S., P. Goel, R. G. Walther, and T. W. Williams. 1982. A variation of LSSD and its
implications on design and test pattern generation in VLSI. Proc. 1982 IEEE Test Conf.;

pp.63-66.
Dejka, W. J. 1977. Measure of testability in device and system design. 20th Midwest Symp.
Circuits and Systems, pp. 39-52.
Dermeau, M. M. 1982. The Yorktown simulation engine. Proc. 19th Design Automation Conf.;

pp.55-59.
Dussault,J. A. 1978. A testability measure. Proc.IEEE Semiconductor Test Conf., pp. 113-116.
Eichelberger. E. 8. 1965. Hazard detection in combinational and sequential switching circuits.
IBM J. Res. Dev. 9: 90-99.
Eichelberger, E. 8., and T. W. Williams. 1977. A logic design structure for LSI testability. Proc.
14th Design Automation Conf., pp. 462-468.
Eichelberger. E. B. and T. W. Williams. 1978. A logic design structure for LSI testability.

J. Design Automation and Fault-Tolerant Computing 2 (2): 165-178.

EI-ziq, Y. M., and H. H. Butt. 1983. A mixed-mode built-in self-test technique using scan path
and signature analysis. Proc. 1983 Test Conf.; pp. 269-274.
Fantauzzi, G. 1974. An algebraic model for the analysis of logical circuits. IEEE Trans.
Comput, C-23 (6): 576-581.
Fasang, P. P. 1982. A fault detection and isolation technique for microprocessors. Proc. 1982
1EEE Test Conf., pp. 214-219.

Bibliography

274

Frohwerk, R. A. 1977. Signature analysis: A new digitalfield service method. Hev-iett-Packard

J. (May), 2-8.

Fujiwara, E. 1983. A self-testing group-parity prediction checker and its use for built-in testing.
Proc.13th Int. Symp. Fault-Tolerant Computing, pp.146-153.
Fujiwara, H. 1981. On closedness and test complexity of logic circuits. J EEE Trans. Comput.
C-30 (8)' 556-562.
Fujiwara, H. 1984. A new PLA design for universal testability. IEEE Trans. Camput. C-33 (8):
745-750.

Fujiwara, H.; and K. Kinoshita. 1978. Testing logic circuits with compressed data. Proc.Bth
Int. Conf. Fault-Tolerant Computing, pp. 108-113.
Fujiwara, H., and K. Kinoshita. 1981. A design of programmable logic arrays with universal
tests. IEEE Trans. Comput. C-30 (II): 823-838.

Fujiwara, H., and T. Shimono. 1983a. On the acceleration of test generation algorithms. Proc.
13th Int. Symp. Fault- Tolerant Computing, pp. 98-105.
Fujiwara, H., and T. Shimono. 1983b. On the acceleration of test generation algorithms. IEEE
Trans. Comput, C-32 (12): 1137-1144.
Fujiwara, H., and S. Toida. 1981. The complexity of fault detection problems for combinational circuits. Techincal report 78-P-HW-15068I, Dept. of System Design, University of
Waterloo, Canada.
Fujiwara, H., and S. Toida. 1982a.The complexity offault detection: An approach to design for
testability. Proc. 12th Inc. Symp. Fault- Tolerant Computing, pp. 101-108.
Fujiwara, H., and S. Toida. 1982b. The complexity

0:"

fault detection problems for combi-

national logic circuits. IEEE Trans. Comput. C-31 (6): 555-560.

Fujiwara, H., Y. Nagao, T. Sasao, and K. Kinoshita. 1975. Easily testable sequential machines
with extra inputs. 11:;1:. "j;'aI1S. Compia. C-24 (8): 821-826.
Fujiwara, H., K. Kinoshita, and H. Ozaki. 1980. Universal test sets for programmable logic
arrays. Proc. 10th lilt. Conf. Fault-Tolerant Computing, pp. 137-142.
Funatsu, S., N. Wakatsuki, and T. Arima. 1975. Test generation systems in Japan. Proc.12th
Design Automation Symp., vol. 6, pp. 114-122.
Garey, M. R. and D. S. Johnson. 1979. Computers and Intractability: A Guide to the Theory of
NP-Completeness. W. H. Freeman and Company.
Godoy, H. C; G. B. Franklin, and P. S. Bottoroff. 1977. Automatic checking of logic design
structure for compliance with testability groundru'es. Proc. 14th Design Automation Conf.,
pp.460-478.
Gocl, P. 1980. Test generation costs analysis and projections. Proc, 17th Design Automation
Conf.; pp. 77-84.

Gael, P. 1981a. An implicit enumeration algorithm to generate tests for combinational logic
circuits. 1 EEE Trans. Comput. C-30 (3): 215-222.
Goel, P. 1981b. PODEM-X: An automatic test generation system for VLSI logic structures.
PI'OC. l Stli Design Automation Conf.; pp. 260-268.
Gold, E. M.1974. Complexity of automaton identification from given data, Unpublished.
Goldstein, L H. 1979. Controllabilityjohservability analysis of digital circuits. IEEE Trans.
Circuits and Systems CAS-26 (9): 685-693.
Hardie, F. H., and R. J. Suhocki. 1967. Design and use offault simulation for Saturn computer
design. IEEE Trans. Elec. Comput. EC-I6 (8): 412-429.

Bibliography

275

Hayes, J. P. 1971a. A NAND model for fault diagnosis in combinational logic networks. IEEE
TI"QIlS. Comout. C-20 (12): 1496-1506.
Hayes, J. P. 1971b. On realizations of Boolean functions requiring a minimal or near-minimal
number ol tests. IEEE Trans. Comput. C-20 (12): 1506-1513.
Hayes, J. P. 1974. On modifying logic networks to improve their diegnosebiliry. IEEE Trans.
Comput. C-23 (1): 56-62.

Hayes, J. P. 1975. The fanout structure of switching functions. J. ACM 22 (4): 551-571.

Hayes,J. P.,and A. D. Friedman, 1974. Test point placement to simplifyfault detection, IEEE
Trans. Comput. C-23 (7): 727-735.

Hong, S. J., and D. L. Ostapko. 1980. FITPLA: A programmable logic array for function
independent testing. Proc. 10th Int. Symp. Fault-Tolerant Computing, pp. 131-136.
Hsiao, T. C; and S. C. Seth. 1982. The use of Rademacher- Walsh spectrum in testing and
design of digital circuits. Proc. ICCC, pp. 202-205.
Ibarra, 0, H" and S. K. Sahni. 1975. Polynomially complete fault detection problems. IEEE
Trans. Comput. C-24 (3): 242-249.
loose, H. and M. Sakauchi. 1972. Synthesis of automatic fault diagnosable logical circuits by
function conversion method. Pvoc. First USA-Japan Computer Conf., pp. 426-430.
Kautz, W. H. 1971. Testing faults in combinational cellular logic arrays. Proc. 8th Ann. Symp.
Switching and Automata Theory, pp. 161-174.
Keiner, W., and R. WesL1977. Testability measures. Proc.IEEE Autotestcon. pp. 49-55.

Kbakbaz.J. 1983. A testable PLA design with low overhead and high fault coverage. Proc. 13th
Int. Symp. Fault- Tolerant Compuring, pp. 426-429.

Khakbaz, J., and E. J. McCluskey. 1982. Concurrent error detection and testing for large
PLAs. IEEE J. Solid-State Circuits SC-17 (2): 386-394.
Kinoshita, K., Y. Takamatsu, and M. Shibata. 1980. Test generation for combinational circuits
by structure description functions. Proc. 10th Int. Symp. Fault-Tolerant Computing, pp. 152154.
Kobayashi, T., T. Matsue, and H. Shiba. 1968. Flip-flop circuit with FLT capability. Proc.
ICO Conf., p. 692. In Japanese.

Kodandapani, K. L. 1974. A note on easily testable realizations for logic functions. IEEE
Trans. Comous. C-23 (3): 332-333.
Koenemann, B., J. Mucha, and G. Zwiehoff. 1979. Built-in logic block observation techniques.
Proc. 19791E Test Con!, pp. 37-41.
Komonytsky, D. 1982. LSI self-test using level sensitive scan design and signature analysis.
Proc. 1982 IEEE Test Conf., pp. 414-424.

Kovijanic, P. G. 1979. Testability analysis. Proc.1979 IEEE Test Conf., pp. 310-316.
Kronstadt, E. K., and G. Pfister. 1982. Software support for the Yorktown simulation engine.
Proc. 19th Design Automation Conf., pp. 60-64.
Ku, C. T., and G. M. Masson. 1975. The Boolean difference and multiple fault analysis. 1EEE
TrQIlS. Comput. C-24 (1): 62-71.
Kuban, 1., and B. Bruce. 1983. The MC6804P2 built-in self-test. Proc. 1983 Int. Test Conf.;
pp.295-300.
Kubo, H. 1968. A procedure for generating test sequences to detect sequential circuit failures.
NEC Res. Dev. 12: 69-78.

Bibliography

276

K uhl, J. G .. and S. M. Redd y. 1978. O n t he detection of term inal stu ck faults. JEEE Trans.
C O/JI pul. C-2? (5): 467-4 69.

Kuntzma nn. J. 1968. Alaebre de Boote. Pa ris: Du no d .

La i. H. C. and S. Mu rcga. 1979. Minimum para llel bina ry ad de rs with NO R (NA ND) gates
I EEE Trans. Comput; C-28 (9): 648 -659.

Lineback, J . R. 1982. Log:c simulatio n speeded with new special hardware . Electronics (June
16), 45-46.
McCluskey, E. J., and S. Bozorgui- Nesbat. 1980. Design fo r a uto nomous test. Proc.1980 IEEE
Test COIlf., pp. 15- 21.

McClus key, E. J., and S. Bozorgui-Nesbat. 1981. Design for auto nomous test./ EEE Trans.
Camput. CJO (li r. 866- 875.
Ma rkowsky, G . 1981. Synd rome-testa bility can be achieved by circuit modificati o n. I EEE
Trans. Com put , C-30 (8): 604-606.
Meno n, P. R., a nd S. Ch a ppell. 1978. Ded ucti ve fault simulatio n with funct ional blocks. I EEE

Trans. Cov uxu. C-27 (8): 689-695.

Mercer, M. R., V. D. Agra wal, and C. M. Ro man . 1981.Test gener ati on fo r h igh ly sequ en tial
sca n-testable circuits th ro ugh logic t ransformation. Proc. IE EE Test Conf. , pp. 561-5 65.
M uth , P. 1976. A nine-val ued circu it mod el fo r test generati on. IEEE Trans. Com pI/I. C-25 ( 6~
630- 636.
O klobd zija , V. G ., and M. D. Erccgova c. 1982. Testa b ility enhan cement of VLSI usi ng circu it
structures. Proc. IEEE I C C C '82, pp. 198- 201.
Pa ge, E. W. 1980. Mi nima lly testab le Reed -M ulle r can onica l forms. IEEE TraIlS. Compvt,
C29 (8)' 746- 753.
Peterson, W. W., and E. J . Weldon . 1972. Error-Correctinq Codes. Cambridge, Mass.: M IT
P ress.
Pfiste r, G. F. 1982. T he Yorktown simul at io n engine: Introduction. Proc. 19/h Design Automat ion Co nf. ; pp. 51-54.
Poage, J. F. 1963. De rivat ion of op tim um tests to de tect faults in co mbina tion al circuits.
M athematical Th eory and Au tomat ion. New Yo rk: Polytechnic Press.

P radhan. D. K . 1978. U niversal test sets fo r multiple fa ult detection in AND -EXOR a rra ys.
IEEE Trans. Compui . C-27 (2): 181-1 87.
Pradh an, D. K ., and K. So n. 1980. The effect of unte sta ble fau lts in P LAs and a design for
testabilit y. Proc. /980 IEEE Tesl
pp . 359-3 67.

cs .

Putzolu, G . R.. and J. P. Rot h. 1971. A heuri stic algorithm (or testing ol asmchronous circu its.
I EEE Trans. Compvt. C::!O(6): 639 ~ 64 7 .

Rama natha. K . S., and N. N. Biswas. 1982 A design fo r complete testa bility of p rogram ma ble
logic a rra y_Proc. / 981 IEE Test Corif-, pp. 67- 74.
Raman atha. K. S. and N. N. Biswas. 1983. A design fo r testa bility of und etect a ble cr osspoi nt
faults in p rogram mable lo gic arrays. / EEE Tr ans. Co mpul. C-32 (6): 55 1-55 7.
Reddy, S. M. 1972. Easily testa ble rea lizati ons for logic functions. IEEE Tr ailS. Comp ut. C-21
(Ii)' 1183-1188.
Reddy, S. M. 1973. Complete test sets for logic fun ctions. IEEE Trans. Comput. C-22 (11):
1016-1020.
Roth. J. P. 1966. Diagn osis of automata failur es: A calc ulus and a met hod. ! 8M J . R es. Dev. 10:
278-2 81.

Bibliography

277

Roth, J. P. 1980. Computer Logic, Testing and Verification. Rockville, Md.: Computer Science
Press.
Roth, J. P., W. G. Bouricius, and P. R. Schneider. 1967. Programmed algorithms to compute
tests to detect and distinguish between failures in logic circuits. IEEE Trans. Electron. Compl/t.
EC-16(10)'567-580.
Sakaucbi, M., K. Hawiuke, and H. Inose. 1975. Synthesis and realization of diagnosable
processor with necessary hardware redundancy for locating faulty packages. Proc. 2nd USAJapan Compui. Conf.; pp. 122-125.
Scluja, K. K. 1982. An enhancement of SSD to reduce lest pattern generation effort and
increase fault coverage. Proc. 19th Design Automation Conf, pp. 489-494.
Saluja, K. K., and M. Karpovsky. 1983. Testing computer hardare through data compression
in space and time. Proe. 1983 Int. Test Conf.; pp. 83-88.
Saluja, K. K., and S. M. Reddy. 1974. On minimally testable logic networks. IEEE Trans.
Comput. C-2J (I), 552-554.
Saluja, K. K., and S. M. Reddy. 1975. Fault detecting test sets for Reed-Muller canonic
networks. IEEE Trans. Comput. C-24 (10): 995-998.
Saluja, K. K., K. Kinoshita, and H. Fujiwara. 1981. A multiple fault testable design of
programmable logic arrays. Proc. 11til Symp. Fault- Tolerant Comp!lIil1{J, pp. 137-142.
Saluja, K. K., K. Kinoshita, and H. Fujiwara. 1983. An easily testable design of programmable
logic arrays for multiple faults. IEEE Trans. Comput. C-32 (11): 1038-1046.
Sasaki, T., N. Koike, K. Ohmori, and K. Tomita. 1983. HAL: A block level hardware logic
simulator. Proc. zoit, Design Auromation Conf., pp. 150-156.
Savir, J. 1980. Syndrome-testable design of combinational circuits. IEEE Trans. Comput. C-29
(6): 442-451. Corrections: November 1980.
Sa vir, J. 1981. Syndrome testing of syndrome-untestable combinational circuits. IEEE Trans.
Comput. C-30 (8) 606-608.
Sedmak, R. M. 1979. Design for self-verification; An approach for dealing with testability
problems in VLSI-based designs. Proe. f980 IEEE Test Conf, pp. 112-120.
Segers, M. T. M. 1981. A self-test method for digital circuits. Proc. 1981 IEEE Test Conf,
pp.79-85.
Sellers, E. F., M. Y. Hsiao, and L. W. Bearnson. 1968a. Analyzing errors with the Boolean
difference. IEEE Trans. Com put. C-17 (7): 676-683.
Sellers, E. F., M. Y. Hsiao, and L. W. Bearnson. 1968b. Error Detecting Logic for Digital
Computers. New York: MctIraw-Hill.
Scshu, S. 1965. On an improved diagnosis program. IEEE Trans. Electron. Comput. EC12 (2):
76-79.
Seth, S. C, and K. L. Kodandapani. 1977. Diagnosis of faults in linear tree networks. IEEE
Trans. Comput. C-26 (I): 29-33.
Smith, J. E. 1980. Measures of the effectiveness of fault signature analysis. IEEE Trans.
Comput. C-29 (6)' 510-514.
Son, K., and D. K. Pradhan. 1980. Design of programmable logic arrays for testability. Proc.
1980 IEEE Tesl Conf, pp. 163-166.
Sridhar, T., D. S. Ho, T. J. Powell. and S. M. Thatte. 1982. Analysis and simulation of parallel
signature analysis. Proc. 1982 IEEE Test Conf, pp. 656-661.
Stephenson, J. E. and J. Grason. 1976. A testability measure for register transfer level digital
circuits. Proc. 6th Int. Symp. Fault-Tolerant Computing, pp. 101-107.

278

Bibliography

Stewart, J. H. 1977. Future testing of large LSI circuit cards. Proc.1977 Semiconductor Test
Symp., pp. 6-17.
Susskind, A. K. 1981. Testing by verifying Walsh coefficients. Proe. 11th lnt. Symp. FaultTolerant Computing, pp. 206-208.

Susskind, A. K. 1983. Testing by verifying Walsh coefficients. IEEE Trans. Comput. C-32 (2):
198-201.
Szygcnda, S. A., D. M. Rouse, and E. W. Thompson. 1970. A model for implementation of a
universal time delay simulation for large digital networks. Proe. AFIPS Conf., pp. 207-216.
Takamatsu, Y., M. Hiraishi, and K. Kinoshita. 1983. Test generation for combinational
circuits by a ten-valued calculus. Trans. ojInformation Processing Society ofJapan, 24 (4): 542548. In Japanese.
Thatte, S. M., D. S. Ho, H.-T. Yuan, T. Sridhar, and T. J. Powell. 1982. An architecture for
testable VLSI processors. Proe. 19821 EEE Test COIJj., pp. 484-492.
Toth, A., and C. Holt. 1974. Automated database-driven digital testing. Computer 1: 13-19.
Trischlcr, E. 1980. Incomplete scan path with an automatic test-generation methodology.
Proe. 1980 JEEE Test Conf, pp. 153-162.
Ulrich, E. G., and T. Baker. 1973. The concurrent simulation of nearly identical digital
networks. Proe. 10th Design Automation Workship, vel. 6, pp. 145-150.
Williams, M. J. Y., and J. B. Angell. 1973. Enhancing testability of large scale integrated circuits
via test points ar.d additional logic. I EEE Trans. Com put. C-22 (1): 46-60.
Williams, T. W., and K. P. Parker. 1982. Design for testability-A survey. IEEE Trails.
Comout. C-31 (1): 2-15.
Wood, C. T. 1979. The quantitative measure of testability. Proe.IEEE AI/totesteon, pp. 286291.
Yajima, S., and T. Aramaki. 1981. Autonomously testable programmable logic arrays. Proe.
11th Symp. Fault- Tolerant Computing, pp. 41-43.
Yamada, T. 1983. Syndrome-testable design of programmable logic arrays. Proe. lnt. Test
Conj., pp. 53-458.

Index

AAFIS. See Advanced Avionics Fault

Isolation System
Aborted fault, 67

Abramovici, M., 102, 104

247-259
Built-in self-test, 238, 247, 256-259, 264
Built-in test, 19,238,246,254
Bus-structured architecture, 145

Ad hoc design technique, 144-149

Advanced Avionics Fault lsolation System

Butt, H. H., 260, 264

(AAFIS),246
Agarwal, V. K., 123
Aha, A., 110
Akers, S. 8., 45, 125
ALU. See Arithmetic-logic unit

CAD. See Computer-aided design

Carter, J. L., 243, 245
Centralized self-test, 262

Ando, n., 226, 229

Angell, J. B., 143,213,226

Aramaki, T., 192

Arithmetic-logic unit (ALU), 257, 259

Armstrong, D. B., 30, 89

Asynchronous sequential circuit. 4-8,67,

81-82
ATE. See Automatic test equipment
ATG. See Automatic test generation
Automatic test equipment (ATE), 21
Automatic test generation (ATG), 17

Backtrace, 50-52, 56-59

multiple, 58-62, 64
Backtrack, 38, 41-42, 46-47, 50, 53-54, 56,

58,61,64-67,117
Backward-trace phase. 31
BakerT. 96
Bardell, P. H., 261-262, 265
Barailai, Z., 177, 186
Bed-of-nails, 147, 149
Bennetts, R. G., 133
Benowitz, N . 246
Berg, W.
133
Betancourt, R., 125
Bhattacharya, B. B., 186

c..

Bhavsar. D. K., 243

BILBO. See Built-in logic block observer
Bipolar transistor, 8
Biswas, N. N., 192
Boolean difference, 24-30
Boolean function, 1-3. See a/so Logic
function
Boolean operation, 1-3. See a/so Logic
operation
Bossen, D. c., 30
Bound line, 57
Bozorgui-Ncsbat. 5.,140,172,175
Breuer, M. A., 127
Brglez, F., 133
Bridging fault. 9, II, 199-201,204
Bruce, B., 259
Built-in logic block observer (BILBO),

Ccfrontier, 45
Cha, C. W., 45
Chang, H. Y., 89
Chappell, S. G., 89, 96
Characteristic polynomial, 239, 241-242
Checking sequence, 206, 210-212
Clause, 110
Clause-monotone expression, 111-113

Clegg, F. W., 30
Clock, 7,145,215,217,220-223,230-231
Clocked flip-flop, 7, 67, 69
Clock pulse, 7
Closed composition, 121, 125, 128
Closedness
under composition, 120-123, 127
under faults, 120-129
Closed tree composition, 123
Closure, 120
CMOS. See MOSFET, complementary
CNF. See Conjunctive normal form
Code word, 19
Combinational circuit, 3-8
iterative, 67, 69, 74, 76-77, 81-82
Compact testing, 23,141-142,239
Compatibility constraint, 155
Compatible sequence, 153-155, 159
Compiler-driven simulator, 84
Complementary MOSFET (CMOS), 8
Computer-aided design (CAD), 102
Concurrent fault simulation, 84, 96-102
Concurrent testing, 19
Conjunctive normal form (CNF), 110III
Consistency operation. 40, 42, 66, 79. See
a/so Line justification
Controllability, 52,134-139,142-143,145,

147-149,151,206
Controllability transfer factor (CTF), 135
Controlling state, 50

Cook, S. A., 110, 111

Count function, 168-170
Cover, 124
Coy, W., 171
CRe code. See Cyclic redundancy check
code

280

Crosspoint fault, 12, 197. 199-205

CTF. See Controllability transfer factor
Cubes
set of, 1-2
singular, 33-34, 41
Cyclic redundancy check (eRC) code, 239
Daehn, W., 251-252
Dcalgorithm, 24, 30-35
extended. 67, 74
DasGupta, S., 141, 161, 165-166,223,233,
237
D-calculus, 33
D-cubc
primitive, 33-35, 38, 77-79
propagation, 35-37, 41-42, 79
Dcdrive, 41-42, 44-45, 74
Deductive fault simulation, 84, 89-96
Degating, 145
Deika. W. J. 133
Delay fault, 9
Dcnneau, M. M. 102
Design for testability, 133, 139-140, 171
Deterministic testing, 21
Dcfrontier, 41-42, 45, 64
Diagnostic resolution, 14
Dvintcrscction, 37-38, 41-42. 44
Distinguishing sequence, 207-212
Distributed self-test, 262, 212
Dual-mode logic, 161-167
Dussault, J. A" 133
ECL See Emitter-coupled logic
Eichelberger, E. 8., 82, 83, 213, 218, 220,
223-224,236
EI-ziq, Y. M .. 260, 264
Emitter-coupled logic (ECL), 8, II
Equivalent fault, 15~ 16. See also Indistinguishable fault
Equivalent normal form. 30
Ercegovac, M. D., 172, 179
Error polynomial, 241-242
Error-propagation phase, 31
Event-directed simulation, 85, 89, 104, 106,
108. See also Selective trace
Exhaustive testing, 140, 171-180, 187
Exponential lime algorithm, 109
External self-test, 260-262
External testing, 19
FAN. See Fanout-oriented test-generation
algorithm
Fanout-free circuit, 123
Fanout-free function,122-123

Index

Fanout-oriented test generation algorithm

(FAN), 24, 53-67
Fantauzzi, G., 82
Fasang, P. P., 256
Fault
aborted,67
bridging, 9, II, 199-201,204
crosspoint, 12, 197, 199-205
delay, 9
equivalent, 15-16
indistinguishable, 15-16
intermittent, 9
logical,8
multiple, 14, 73-74, 77, 81-82,124,127129,156-157,161,192,201,205
parametric,8
permanent. 9
redundant, 15
representative, 16
single, 14,73,124,161,182,189-191
solid,9
stuck-at, 9, 14-15, 17-28,30, 112, 121122,125,127-129,151,155-157,161,
167,182,197,201
Fault coverage, 17,84. See also Test
coverage
Fault detection, 14, 112
Fault-detection circuit (FDC), 266-268
Fault diagnosis. 14. 18
Fault dictionary, 17
Fault injection. 86
Fault isolation, 14. See also Fault location
Fault location. 14. See also Fault isolation
Fault modeling, 8-12
Fault-secure circuit. 19
Fault simulation, 17,84-108
concurrent, 84, 96-102
deductive, 84, 89-96
parallel, 84, 85-89
Fault table, 16
FDe. See Fault-detection circuit
Finite-state machine, 3-8
Flip-flop (FF)
clocked, 7, 67. 69
D (Delay), 6- 7
JK,6-7
pseudo, 69
SR (Set-Reset), 6-7
T (Trigger), 6-7
Flow table, 4. See also State table
Forward-trace phase, 31
Free line, 57, 66
Friedman, A. D., 147, 171
Frohwerk, R. A, 242-243, 245

281

Index

F ujiwar a, H ., 24,53,67,113,1 20,122,127,

128,1 40,1 68,170,192,199,205,207
Funat su, S., 213, 215
F unction-conversion uni t, 163
Fun cti on -independent testing, 139, 188,
192, [99
Fundam ental mode op era tio n, 8
G arey, M . R., 110
Gate, [-3
A ND, I
EDR,3
OR,I
N AN D, I
NOR, 3
N OT , I
G odoy, H . C, 222
G oel, P., 24,45,50, 145
Gold, E. M ., I I I
G old circuit, 21
Goldstein, L. H ., 133-134, 137
Grason,J ., [33- 134, 136-137
Gupta, B., 186
HAL, 107,108
Har die, F . H., 86
Ha rdwa re simul ator, 102- 108
Hayes, J. P., 123, 127, 14 1, 147, 150, 154156, [71
Hazard, 8, 8 1-83
Head- b ou nded circu it, 118
Head line, 57-58,61
Head po int, 116
Head-p oin t set, 116- 117
H eckelman, R . W ., 243
Hess, R. D ., 133
Ho lt, C. 226
Homing seq uence, 207
Ho ng, S. J ., 30,140,192, 199
Hsia o, T . C, 187
Impli cation, 40, 47,5 2,54,57,61,64,66
extended, 115-1 16
In-c ircuit testing, 147, 149
Incon sistency, 40,56,58,6[,74
Ind istingui shable fau lt, 15-16. See also
Eq uivalent fault
Inose, H ., 14[ , 161, 163
Intermittent fau lt, 9
Intern a l self-test. 260. 262. 265
Iterati ve combina tion al circuit, 67, 69, 74,
76-77,8 1- 82,142
Johnson, D . S., 110

K arnaugh ma p, [- 2
Kautz, W. H ., [89
Keiner, W., 133
Kernel,246
Khakbaz, J. , 192
Kinoshita, K ., 30, 168. [70, 192
Ko bayashi, T., 2 13, 215
Kodanda pani, K . L, 127, 191
Ko enemann, B., 247, 265
Komonytsky, D ., 262, 264- 265
K ovijanic, P. G ., 133
Kronstadt, E. K ., 102
Ku, C. T ., 30
Kuban , J., 259
Kubo, H., 67
Kuhl, J. G ., 141
Kuntzm ann, J., 120
LAMP system, 89, 96
Large-scale int egration (LSI), 8, 17-1 8,
140,192,199,218
Levelizing, 84
Level-sensit ive logic circuit, 218
Level-Sensitive Scan Desig n (LSSD), 213,
218-227,232-233,236-237,250,259 ,
262
LFSR. See Linear-feedback shift register
Linea r-feedback shift regist er (LFS R),
175- 178,239-251,256,260-262,266
Linear function, 120, 126-129
Lineback , J. R ., 102
Line -justific ation phase, 31, 40, 42-45, 58,
66, 74, 79-80
Literal, 110
Logic circuit, 1-8
Logie func tion, [- 3. See also Boolean
fun ction
Logic op erati on, 1- 3. S ee also Boolean
opera tion
Logic testing, 1
Logical fau lt, 8
Logical partition ing, [45
LSI. See Lar ge-scale int egration
LSSD . See Level-Sensitive Scan Des ign
McA nney, W . H ., 261-262, 265
McCluskey, E. J ., 140, 172, 175, 192
Markowsky, G ., 186
M asson, G . M ., 30
Maximal false vertex , 124
Menon, P. R., 96
Mercer, M . R ., 226-227
Met al oxide semiconductor field effect
transistor. S ee MOSFET

282

MICROBIT system, 256-257

Microcomputer, 145,256,259
Microprocessor, 145,245 -247,256-257
Minimal true vertex, 124
Monotone circuit, 112-115
Monotone expression, 11I-112
Monotone function, 121, 124-125
MOSFET (metal oxide semiconductor
field-effect transistor), 8,11-12,192-193,
201,259
complementary (CMOS), 8
n-channel (N-MOS), 8, 11, 179, 192-193,
201,256
p-channel (p~MOS), 8
Mucha. J., 251-252
Multiple backtrace, 58-62, 64
Multiple fault 14,73-74,77,81-82,124,
127-129,156-157,161,192,201,205
Muth, P., 67, 76
Nine-value circuit model, 76-81
n-MOS. See MOSFET, n-channel
Noncode word, 19
Noncontrolling state, 50
Nonlinear feedback shift register, 252, 254
NP-complcteness, 109-115
NP-complete problem, 109-115

Objective, 50-52, 59-61

current, 59, 61
fanout-point, 59, 61, 64
final, 61, 64
head, 59, 61
initial, 50, 52, 59-60, 64
Objective line, 50
Objective value, 50
Observability, 52,134-139,142-143,145,
147-149,151,206
Observability transfer factor (OTF), 135136
Off-line testing, 19,266-267
Oklobdzija, v, G., 172, 179
One-dimensional path sensitization. 31. See
also Single path sensitization
On-line testing, 19,266-267
Ostapko, D. L., 140, 192, 199
OTF. See Observability transfer factor
Page, E. W., 191
Parallel signature analyzer (PSA). 243, 245,
250,253,256-258,261,263
Parallel fault simulation, 84, 85-89
Parametric fault, 8
Parker, K. P., 144

Index

Partitioning. 145, 171-177, 179, 186

logical, 145
mechanical. 145
Path-oriented decision-making (PODEM)
algorithm, 24, 45-59, 61, 64, 67
Path sensitization
one-dimensional, 31
single, 31-33, 67
Permanent fault, 9
Peterson, W. W., 177,239
Pfister, G. F., 102
PLA. See Programmable logic array
p-MOS. See MOSFET, p-channel
Posage. J. F . 30
PODEM. See Path-oriented decisionmaking algorithm
Polarity-hold parallel and shift-register
latch (PSRL), 224
Polynomial time algorithm 109-112,114120
Polynomially transformable problem, 110111,113-114
Pradhan. D. K.. 191-192
Programmable logic array (PLA), 12, 140,
192-205,251-255,257
PRPG. See Pseudorandom-pattern
generator
PSA. See Parallel signature analyzer
Pseudo flip-flop, 69
Pseudo input, 69, 73-74
Pseudo output. 69
Pseudorandom-pattern generator (PRPG).
256-257,260,263-264,266
PSRL. See Polarity-hold parallel and shiftregister latch
Putzolu, G. R., 67
Race, 8, 81-83
critical, 8
Rademacher-Walsh spectral coefficient, 187
Rademacher-Walsh spectrum, 187
RAM. See Random-access memory
Ramanatha, K. S., 192
Random-access memory (RAM), 107, 108,
145,256-258
Random-Access Scan, 229-231
Random testing. 21
Read-only memory (ROM), 107, 145,256259
Reddy, S. M., 123, 125, 140-141, 147, 156,
161, 188-189. 191-192
Redundancy, 19
dual, 20
Redundant fault, 15

Index

Reed-Muller canonical circuit, 140, 188192

Representative fault. 16
ROM. See Read-only memory
Roth, J. P., 24, 33, 35, 40, 45, 67
SA. See Signature analysis; Signature
analyzer
Sakauchi, M., 141. 161,163,172
Saluja, K. K., 141, 147, 156, 161, 191-192,
224
Sasaki. T . 102, 107
SAT. See Satisfiability
Satisflability, llO-114
Savir, J . 140. 182. 184-186
Scan, 143,206,213-237,261-262
Scan design, 206, 213-237, 259
complete. 232-233
enhanced, 232, 236-237
incomplete, 232-233
Scan Path, 213, 215-218, 250, 259
Scan/Set Logic, 227-229
Scdmak, R. M., 267
Segers. M. T. M., 260, 262
Selective trace. 85, 89
Self-checking circuit, 19-20,267, 270
Self-test, 238. 247. 250. 257-266. See also
Built-in self-test; Built-in test
centralized. 262
distributed, 262, 265
external, 260-262
internal, 260. 262. 265
simultaneous. 265
with scan design. 259-266
Self-testing. 20. See also Self-test
Self-verification. 266-271
Seller, E. F., 30
Sequential circuit. 3-8.
asynchronous. 4-8, 67, 81-82
synchronous, 4-8, 67, 81
Sequential machine, 3-8, 206-207
Serial signature analyzer (SSA). 243, 246,
259,261
Seshu, S. 86
Seth, S. C, 127, 187
Shift-register latch (SRL). 218-224, 236237, 262-263, 265
stable (SSRL1, 236
Shift-register modification. 143.213-215.
226-227
Shimono, T., 24, 53, 67
Signature, 23,175,240
Signature analysis, 23, 238-247
Signature analyzer, 243-247, 253, 260,

283

263-266
parallel, 243, 245-246, 250, 253, 256-258,
261,263
serial. 243. 246, 259, 261
Simultaneous self-test. 265
Single fault. 14.73.124.161,182,189-191
Single-path sensitization, 31-33, 67, See
also One-dimensional path sensitization
Smith, J. E., 241-243
Solid fault, 9
Son, K., 192
SPOOF,30
Sridhar, T.. 243
SRL. See Shift-register latch
SSA. See Serial signature analyzer
SSRL. See Stable shift-register latch
State
next, 3
present, 3
State diagram, 4
State-shiftable machine, 206-213
State table, 4. See also Flow table
Stephenson, J. E., 133-134, 136~137
Stewart, J. H., 147,226-227
Structured design technique, 144
Stuck-at fault, 9,14-15,17-28,30,112,
121-\22,125, \27-129,151,155-\57,
16\,167,182,197,201
Suhocki, R. J., 86
Susskind, A. K., 187
Synchronizing sequence, 76, 207-210
Synchronous sequential circuit, 4-8, 67, 81
Syndrome testing, 181-188
Szygenda, S. A., 86
Table-driven simulator, 84, 108
Takamatsu, Y., 45
TEGAS simulator, 86
Testability, 133-134, 139-141, 144-145,
\48-149,206
analysis of, 133-139. 147-148
design for, 133, 139-140, 144, 171
measuring of, 52,133-139,147
Test application, 16. 141, 150, 167
Test coverage, 17,67,70,224
Test data, 14,21,168,170
Test generation, 16.24-83,133,142,149,
17\
Testing
built-in, 19,238,246,254 (see also Built-in
self-test; Self-test)
compact, 23,141-142,239
complexity of, 109-129
concurrent, 19

284

Testing (COlli.)
deterministic, 21
exhaustive, 140, 171-180, 187
external, 19
function- inde pendent, 139, 188, 192, 199
in-circui t. 147, 149
o ff-line, 19,266-267
on- line, 19,266-267
random , 21
universal, 139, 171, 192, 197, 199
Test pattern , 14. 16-17,21,23,26,30,69,
80,140-141,153-158,161-167,1 89199,1 98-200,203
Test-p a ttern generator (TPG), 267-268
Test po int, 147, 149
Test sequence, 14,74,76-77,80,159,168170, 198, 202
Test set, 14, 16, 27-30, 169, 197-198,201,
205
Thane, S. M., 257-258
Time complexity, 109
Toid a, S., 113, 120
Toth, A., 226
TPG . See Test pattern genera to r
Transistor-transistor logic (TTL), 8-9
Tree compo sition, 123
Tris chler, E., 232
TTL. See Tra nsistor-tran sistor logic
Ulrich, E. G ., 96
Unate circuit, 112-1 [4
Unate comp osition , 123-125
U nate expres sion, [11-112
Unate funct ion, 123-125
Unate gate network, 123
Unique sensitizatio n, 54-56, 58, 64, 66
Universal testi ng, [39, 17J. 192, 197, 199
Unj ustified line, 42, 44-45, 57, 64, 66
Very-high-speed integrat ed (VHSI) circ uit,
238
Very-lar ge-scale integration (VLSI), 1, 8,
17-1 8,l40, 144-145, 192,199,218,238
VHSI circuit. See Very-hi gh-speed integrated cireuit
VLSI. See Very-large-sc ale integration
VLSI processor, 257-258. See also Microcomputer; Micr op rocessor
Vogel, A., 171
Weldon , E. J ., 177,239
West, R., 133
Williams, M. J. Y., 143,213,226
William s, T. W., 144,213, 218,220,223-

Index

224,236
Wood , C. T ., 133
X-path check, 50, 56
Yajima, S., 192
Y am a d a , T. , IS?
Yorktown sim ulation engine (YSE), 102,
106-108