Delay Modeling: Timing Checks.

Keywords: $setup, $hold, $width

This section, the final part of the delay modeling chapter, discusses some of the various system
tasks that exist for the purposes of timing checks. Verilog contains many timing-check system
tasks, but only the three most common tasks are discussed here: $setup, $hold and $width.
Timing checks are used to verify that timing constraints are upheld, and are especially important
in the simulation of high-speed sequential circuits such as microprocessors. All timing checks
must be contained within specify blocks as shown in the example below.
The $setup and $hold tasks are used to monitor the setup and hold constraints during the
simulation of a sequential circuit element. In the example, the setup time is the minimum
allowed time between a change in the input d and a positive clock edge. Similarly, the hold time
is the minimum allowed time between a positive clock edge and a change in the input d.
The $width task is used to check the minimum width of a positive or negative-going pulse. In
the example, this is the time between a negative transition and the transition back to 1.

Syntax:
NB: data_change, reference and reference1 must be declared wires.
$setup(data_change, reference, time_limit);
data_change: signal that is checked against the reference
reference: signal used as reference
time_limit: minimum time required between the two events.
Violation if: Treference - Tdata_change < time_limit.

$hold(reference, data_change, time_limit);

reference: signal used as reference
data_change: signal that is checked against the reference
time_limit: minimum time required between the two events.
Violation if: Tdata_change - Treference < time_limit

$width(reference1, time_limit);
reference1: first transition of signal
time_limit: minimum time required between transition1 and transition2.
Violation if: Treference2 - Treference1 < time

Example:
module d_type(q, clk, d);
output q;
input clk, d;
reg

q;

always @(posedge clk)

q = d;
endmodule // d_type
module stimulus;
reg clk, d;
wire q, clk2, d2;
d_type dt_test(q, clk, d);
assign d2=d;
assign clk2=clk;
initial
begin
$display ("\t\t
clock d q");
$display ($time,"
%b
%b %b", clk, d, q);
clk=0;
d=1;
#7 d=0;
#7 d=1; // causes setup violation
#3 d=0;
#5 d=1; // causes hold violation
#2 d=0;
#1 d=1; // causes width violation
end // initial begin
initial
#26 $finish;
always
#3 clk = ~clk;
always
#1 $display ($time,"

%b

specify
$setup(d2, posedge clk2, 2);
$hold(posedge clk2, d2, 2);
$width(negedge d2, 2);
endspecify
endmodule // stimulus

%b %b", clk, d, q);

Output:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

clock
x
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1

d
x
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1

q
x
x
x
x
1
1
1
1
1
1
0
0
0
0
0
0

"timechecks.v", 46: Timing violation in stimulus

$setup( d2:14, posedge clk2:15, 2 );
16
17
18
19
20
21
22

1
1
0
0
0
1
1

1
0
0
0
0
0
1

1
1
1
1
1
1
0

"timechecks.v", 47: Timing violation in stimulus

$hold( posedge clk2:21, d2:22, 2 );
23
24
25

1
0
0

1 0
0 0
1 0

"timechecks.v", 48: Timing violation in stimulus

$width( negedge d2:24, : 25, 2 );

Priority Encoder:
In this device each input has a priority level associated with it. The encoder outputs indicate the active input that has
the highest priority. When an input with a high priority is asserted, the other inputs with lower priority are ignored.
Truth table:
W3
0
0
0
0
1

W2
0
0
0
1
X

W1
0
0
1
X
X

W0
0
1
X
X
X

Y1
X
0
0
1
1

Y0
X
0
1
0
1

Z
0
1
1
1
1

W3 to W0 are the inputs and Y1, Y0 are the outputs, Z is set to 1 when at least one of the inputs is set to 1.
For the first case Y1, Y0 assumes X values.
Verilog code:
Module priority(W, Y, Z);
Input [3:0]W;
Output reg[1:0]Y;
Output reg Z;
always @(W)
begin
Z=1;
Casex(W)
4b1xxx: Y=3;
4b01xx: Y=2;
4b001x: Y=1;
4b0001: Y=0;
Default: begin
Z=0; Y=2bx;
end
endcase
end
endmodule

4-bit ripple carry adder using parameter block:

module addern(carryin, x, y, s, carryout);
parameter n=32;
input carryin;
input [n-1: 0]x, y;
output reg [n-1:0]s;
output reg carryout;
reg [n:0]c;
integer k;
always @(x, y, carryin)
begin
c[0]= carryin;
for(k=0; k<n; k=k+1)
begin
s[k]= x[k]^y[k]^c[k];
c[k+1]= (x[k] & y[k]) | (y[k] & c[k]) | (c[k] & x[k]);
end
carryout= c[n];
end
endmodule

4-bit ripple carry adder using generate block:

module addern(carryin, x, y, s, carryout)
parameter n=32;
input carryin;
input [n-1: 0]x, y;
output [n-1:0]s;
output carryout;
wire [n:0]c;
genvar i;
assign c[0]= carryin;
assign carryout= c[n];
generate
for(i=0; i<n-1; i=i+1)
begin: addbit
fulladd stage(c[i], x[i], y[i], s[i], c[i+1]);
end
endgenerate
endmodule

module fulladd(cin, a, b, sum, carry);

input cin, a, b;
output sum, carry;
assign sum = a^b^cin;
assign carry=( a & b)|(b & c)|(c & a);
endmodule

Tasks and Functions:

Verilog Task:
A task is declared by the keyword task and it comprises a block of statements that ends with the keyword endtask.
The task must be included in the module that calls it. It may have input and output ports. These are not the ports of
the module that contain the task, which are used to make external connections to the module. The task ports are
used only to pass values between the module and the task.
Example:
16:1 MUX
module mux16to1(w, s16, f);
input [0:15]w;
input [3:0]s16;
output reg f;
always @ (w, s16)
case(s16[3:2])
0:mux4to1(w[0:3], s16[1:0], f);
1:mux4to1(w[4:7], s16[1:0], f);
2:mux4to1(w[8:11], s16[1:0], f);
3:mux4to1(w[12:15], s16[1:0], f);
endcase
task mux4to1;
input [0:3] x;
input [1:0]s4;
output reg g;
case(s4)
0: g= x[0];
1: g= x[1];
2: g= x[2];
3: g= x[3];
endcase
endtask
endmodule

Verilog Function:
A function is declared by the keyword function and it comprises a block of statements that ends with the keyword
endfunction. The function must have atleast one input and it returns a single value that is placed where the function
is invoked.
A Verilog function can invoke another function but it cannot call a Verilog task.
A task may call another task and it may invoke a function.
Example:
16:1 Mux:module mux16to1(w, s16, f);
input [0:15]w;
input [3:0]s16;
output reg f;
function mux4to1;
input [0:3]x;
input [1:0]s4;
case (s4)
0: mux4to1= x[0];
1: mux4to1= x[1];
2: mux4to1= x[2];
3: mux4to1= x[3];
endcase
endfunction
always @(w, s16)
case (s16[3:2])
0: f=mux4to1(w[0:3], s16[1:0]);
1: f=mux4to1(w[4:7], s16[1:0]);
2: f=mux4to1(w[8:11], s16[1:0]);
3: f=mux4to1(w[12:15], s16[1:0]);
endcase
endmodule

Lab Viva Voce:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.

What are CAD tools, CAE tools, EDA tools?

What are design specifications?
What is simulation?
What is Logic synthesis?
What are HDLs? Name them.
What do you mean by Gate level net list?
What are the two design methodologies, name them?
What is the significance of MODULES?
Name the levels of abstraction? Explain.
Define RTL.
What are instances and instantiation?
What is testbench or Stimulus block?
What do you understand by the term top level module?
In what ways you can specify comments in your code?
Explain wire and reg data type.
What are Arrays and memories, explain?
Name the various variable data types. Ans: reg, integer, real, time.
Explain the use of parameters.
Explain the use of defparam keyword.
Explain the use of localparam keyword.
How many bits are used by each character in the string?
What are the various escaped characters? Ans: \n, \t, %%, \\, \, \ooo.
Name the various string format specifications. (pg no: 83, samir palnitkar).
Name the various value levels and strength levels associated with it. (pg no: 74, samir palnitkar).
What do understand by scalar and vector declaration?
Mention the ANSI C style declaration.
What is hierarchical name referencing?
Differentiate predefined primitives and UDPs.
Explain the various delays associated with Rise, Fall and turn-off delays.
How many numbesr of operands can we have in replication operator, conditional, reduction, logical
operators?
What do you mean by behavioral modeling?
Differentiate always and initial statement.
Differentiate between blocking and non-blocking assignments.
When should we use non-blocking assignment?
Which symbol is used to specify an event control? Ans: @
A named event is declared by the keyword _____________.
What is event OR control?
Which keyword is used for level-sensitive timing control?
Name the various behavioral statements. Ans: if-else, case, loops.
Differentiate Sequential and Parallel blocks.
Name the keyword to generate Verilog code dynamically at elaboration time before the simulation begins.
Differentiate Tasks and Functions.
Explain procedural continuous assignments.
What is the significance of `timescale compiler directive?
What is conditional compilation and conditional execution?
How are timing checks useful?
Explain switch level modeling.
Rules of UDPs.
Explain the PLI concept.
Define Synthesis and design partitioning.

51. Explain the following:

(a) $monitor, $monitoron, $monitoroff
(b) $display
(c) $time
(d) $stop
(e) $start
(f) $finish
(g) `include
(h) `define
(i) `if
52. Explain system tasks and compiler directives.
53. How to invoke minimum, maximum and typical delays?
54. What is the necessity of delay back annotation?
55. What are sequential circuits?
56. When to use casex and casez statements?
P.S: Go through the Lab programs and try out in every modeling style also please refer your earlier semester notes
for combinational and sequential machines (eg: flip-flops, counters, code converters) and the introductory notes from
the manual which was sent earlier, questions can be expected from these topics.