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VLSI Testing: 18-322 Fall 2003

The document discusses VLSI testing techniques. It covers defects and faults in integrated circuits and how they are modeled. Common fault models include stuck-at faults where a node is stuck at 0 or 1, and bridge and stuck-open faults. Automatic test pattern generation algorithms like the D-algorithm are used to generate test patterns that target these faults. Path delay faults due to timing defects are also discussed. The document also covers design for testability techniques like scan-based testing and built-in self-testing that make chips more easily testable.

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Devith Menon Thirumangalath
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© © All Rights Reserved
Available Formats
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49 views

VLSI Testing: 18-322 Fall 2003

The document discusses VLSI testing techniques. It covers defects and faults in integrated circuits and how they are modeled. Common fault models include stuck-at faults where a node is stuck at 0 or 1, and bridge and stuck-open faults. Automatic test pattern generation algorithms like the D-algorithm are used to generate test patterns that target these faults. Path delay faults due to timing defects are also discussed. The document also covers design for testability techniques like scan-based testing and built-in self-testing that make chips more easily testable.

Uploaded by

Devith Menon Thirumangalath
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Testing

Lecture 25
18-322 Fall 2003

Announcement
Homework 9 is due next Thursday (11/20)
Exam II is on Tuesday (11/18) in class
Review Session:
When: Next Monday (11/17) afternoon, 4pm 6pm
Where: B131, HH

Outline
Defects and Faults
Reasons for IC malfunctioning

Fault Modeling
Types of faults (Stuck-At, bridge, Stuck Open)
Automatic Test Pattern Generation
Path Delay Fault

Design for Testability


3

Why Testing?
Manufacturing is imperfect
Y=

No. of good chips on wafer


Total no. of chips

Yield (Y) depends on technology, chip area and layout


Y

decreases as the area of chip is increased


Defect density (D)
Modern technologies yield a value of 1-5 defects/cm2

Yield starts out low (~10%) moves up (95%)

High quality expectation


The earlier you detect a fault, the cheaper it is to fix
4

Reasons for IC Malfunction - Contamination,


Defects and Faults
Contamination / Instabilities - Process induced
impurities and random fluctuations of process
conditions
Defects - Permanent deformation in IC layer which may
but does not have to result in fault
Faults - Functional misbehaviors i.e. IC malfunctions
5

Reasons for IC Malfunction Defects and Faults


B

VDD

13
VDD

N1
M9

Metal
M11

M14

Poly

M12

N13

M13

C OUT

M10

13

Contact

N+

C
M25
M27
M23

M24

M28

M26

B
N2

N13

GND

GND
B

13

Reasons for IC Malfunction Defects and Faults

V DD

M10
M9

M13

N3

N1

M12

M11

N13

M25

M14

C OUT
N2

M26

M28

N4
M24
M23

M27

GND

Reasons for IC Malfunction Defects and Faults


B

VDD

13
VDD

M9

M11

N1
M9

Metal
M14

Poly

M12
M13

C OUT

M10

13

Contact
N+

A
N

M27
M24

B
N2

M25

M23

N13

M28

N13

GND

M26

GND
B

13

Reasons for IC Malfunction Defects and Faults


C out

M10
M9

M13

M11

M12

VDD

M14

M25

M26

M24
M23

M27

OUT

M28

GND
GND

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

Defect
no yes
0 0
0 0
0 0
1 1
0 0
1 0
1 0
1 1

N1 - N13 short

Outline
Defects and Faults
Reasons for IC malfunctioning

Fault Modeling
Types of faults (Stuck-At, bridge, Stuck Open)
Automatic Test Pattern Generation
Path Delay Fault

Design for Testability


10

Test Complexity

In
n

Out

Exhaustive test 2

n+m

Combinational
Logic

Q
Q
QQ

Circuit with n = 25 and m = 50


1sec/test
Exhaustive test time is over 1 billion years!
(Registers make life harder!)

D
D
DD
clock

Registers
m
11

Testing Strategies
Functional Test: (go/no go)
Does the part work?
Do this fast & cheap

Diagnostic Test:
What in the chip is broken?

Parametric Test:
What is:
max

clock frequency
min supply voltage
max operating temp
12

Test Implementation
Runs Test Vectors/Programs on Device Under Test
(DUT)
Goal: Find a SMALL set of test vectors that has a BIG fault
coverage

Testers
Clock rate in the range of GHz
Resolutions measured in psec
Large very fast memory
Cost 1 - 5 million dollars
13

Fault Models
Modeling physical faults is complex
Need models that simplify the behavior of faults
a
b

c
d

h
x

14

Stuck-At Fault
Stuck-at-0

a
b

c
d

h S-A-0
x

Stuck-at-1

a
b

c
d

h
S-A-1

e
15

Bridge & Stuck Open


a
b

c
d

h
x
Bridging
fault

a
b

c
d

h
x
Open
fault

e
16

Automatic Test Pattern Generation (ATPG)


Given a logic circuit:
Generate test program to cover all SA faults

The D-Algorithm
The D-Calculus
Problem:

Reconvergent Fanouts

17

D-Algorithm
Step 1: Choose a fault to insert
Select from a fault dictionary

Step 2: Activate (excite) the fault


Drive the faulty node to the opposite value of the fault
Example: for SA-1, drive the node to 0

Step 3: Sensitize a path to an output


Propagate the fault so that it can be observed at the output
pin
18

Path Sensitization
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)

Fault enabling
Fault propagation

1
1
1
1

sa0
1

Out

Techniques Used: D-algorithm, Podem


19

D-Algorithm
a
b

c
d

h
x

D = 1/0

e
a
b

c
d

value in
good ckt

value in
faulty ckt

h S-A-0
x

D = 0/1

20

D-Algorithm
Five value logic simulation
X = AB

X =NOT(A)
A

0
0

1
0

X
0

D
0

D
0

21

D-Algorithm
Five value logic simulation
X=A+B
A

0
0

1
1

X
X

D
D

D
D

22

D-Algorithm
1/0 = D
a
b
c
d
e

1
1
1
0

f
g

1
1

h S-A-0

D x

23

D-Algorithm
1/0 = D
a
b
c
d

1
1

Conflict !
Need backtracks
Reconvergent Fanout
x
24

Fault Simulation
Test Program

Random Number Generator,


Genetic Algorithm, etc.

Fault Free

Circuit w/

Circuit

One Fault

Compare

25

Path Delay Fault


A defect can affect the speed of a path in the circuit

Lets see a Path Delay Fault example


a
T0
b

slow

slow

11

e slow

T1+T

11

26

Path Delay Fault


Path

c-g2-g4-g5-x

a
g1
b
c
00 g2
d
e

11 g3

00
g4

g5

00

27

Outline
Defects and Faults
Reasons for IC malfunctioning

Fault Modeling
Types of faults (Stuck-At, bridge, Stuck Open)
Automatic Test Pattern Generation
Path Delay Fault

Design for Testability


28

Scan-based Test
Modified to support two
operation modes

ScanIn

Combinational
Logic
A

Register

Register

In

ScanOut

Combinational

Out

Logic
B

29

Scan Based Methods


Logic

Logic

Logic

Level Sensitive Scan Design (LSSD) - IBM

Test Mode: OFF

Test Mode: ON

30

Boundary Scan (JTAG: IEEE 1149.1b)


Printed-circuit board
Logic

Scan-out

si

so
scan path

normal interconnect

Scan-in

Packaged IC

Bonding Pad

Board testing becomes as problematic as chip testing


31

Built-In Self-Testing (BIST)

(Sub)-Circuit
Stimulus Generator

Under

Response Analyzer

Test

Test Controller

Rapidly becoming more important with increasing


chip-complexity and larger modules
32

Linear-Feedback Shift Register (LFSR)

S0

S1

S2

1
0
1
1
1
0
0
1

0
1
0
1
1
1
0
0

0
0
1
0
1
1
1
0

Pseudo-Random Pattern Generator


33

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