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Chapter 4 Verilog

This document discusses combinational logic building blocks including multiplexers, decoders, encoders, and other circuits. It provides examples of how to implement logic functions using multiplexers and decoders. Figures show the logic symbols, truth tables, and circuit implementations for various multiplexers, decoders, encoders, and other combinational logic blocks. Application examples include priority encoders, binary-to-Gray code converters, ALU components, and barrel shifters.

Uploaded by

Griffin Moe
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
44 views

Chapter 4 Verilog

This document discusses combinational logic building blocks including multiplexers, decoders, encoders, and other circuits. It provides examples of how to implement logic functions using multiplexers and decoders. Figures show the logic symbols, truth tables, and circuit implementations for various multiplexers, decoders, encoders, and other combinational logic blocks. Application examples include priority encoders, binary-to-Gray code converters, ALU components, and barrel shifters.

Uploaded by

Griffin Moe
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 4

Combinational-Circuit
Building Blocks

s
w0
w1

0
1

0
1

w0

w1

(b) Truth table

(a) Graphical symbol

w0

w0
s

w1

s
w1

(c) Sum-of-products circuit

(d) Circuit with transmission gates

Figure 4.1. A 2-to-1 multiplexer.

s0
s1
w0
w1
w2
w3

s1 s0
00
01
10
11

0
0
1
1

(a) Graphic symbol

0
1
0
1

f
w0
w1
w2
w3

(b) Truth table

s0
w0
s1
w1
f
w2

w3

(c) Circuit

Figure 4.2. A 4-to-1 multiplexer.

s1
s0
w0

w1

1
0

w2

w3

Figure 4.3. Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.

s0
s1
w0
w3

w4

s2
s3

w7
f
w8
w11

w12
w15

Figure 4.4. A 16-to-1 multiplexer.

x1

y1

x2

y2

(a) A 2x2 crossbar switch

x1

0
1

y1

s
x2

0
1

y2

(b) Implementation using multiplexers

Figure 4.5. A practical application of multiplexers.

w1 w2

w2
w1

0
1
1
0

(a) Implementation using a 4-to-1 multiplexer

w1 w2

(b) Modified truth table

w1

w2

w2

w1
w2
f

(c) Circuit

Figure 4.6. Synthesis of a logic function using multiplexers.

w1 w2 w3

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

w1 w2

0
0
0
1
0
1
1
1

0
0
1
1

0
1
0
1

0
w3
w3

(a) Modified truth table


w2
w1

w3

1
(b) Circuit

Figure 4.7. Implementation of the three-input majority function


using a 4-to-1 multiplexer.

w1 w2 w3
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

f
0
1
1
0
1
0
0
1

w2 w3

w2

w1

w3
f
w2 w3

(a) Truth table

(b) Circuit

Figure 4.8. Three-input XOR implemented with


2-to-1 multiplexers.

w1 w2 w3
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

f
0
1
1
0
1
0
0
1

w3
w3

w2
w1
w3
f

w3
w3

(a) Truth table

(b) Circuit

Figure 4.9. Three-input XOR function implemented with


a 4-to-1 multiplexer.

w1 w2 w3
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

f
0
0
0
1
0
1
1
1

w1

0
1

w2w3
w2 + w3

(b) Truth table


w1

w2
w3

(b) Circuit

Figure 4.10. The three-input majority function implemented


using a 2-to-1 multiplexer.

w1

w3
w

(a) Using a 2-to-1 multiplexer

w2
w1
w3
f
1

(b) Using a 4-to-1 multiplexer

Figure 4.11. The circuits synthesized in Example 4.5.

w2

w1

0
w3
f

Figure 4.12. The circuit synthesized in Example 4.6.

Figure 4.13. A 2-to-4 decoder.

Figure 4.14. Binary decoder.

w0
w1
w2

En

w0
w1

En

w0
w1
En

y0
y1
y2
y3

y0
y1
y2
y3

y0
y1
y2
y3

y4
y5
y6
y7

Figure 4.15. A 3-to-8 decoder using two 2-to-4 decoders.

w0
w1

w0
w1
En
w0
w1

w2
w3

w0
w1

En

En

y0
y1
y2
y3

En
w0
w1
En
w0
w1
En

y0
y1
y2
y3

y0
y1
y2
y3

y0
y1
y2
y3

y4
y5
y6
y7

y0
y1
y2
y3

y8
y9
y10
y11

y0
y1
y2
y3

y12
y13
y14
y15

Figure 4.16. A 4-to-16 decoder built using a decoder tree.

w0

w1
s0
s1

w0
w1
En

y0
y1
y2
y3

f
w2

w3

Figure 4.17. A 4-to-1 multiplexer built using a decoder.

w0

y0

2n
inputs

n
outputs
w2n 1

yn 1

Figure 4.18. A 2n-to-n binary encoder.

w3 w2 w1 w0
0
0
0
1

0
0
1
0

0
1
0
0

1
0
0
0

y1 y0
0
0
1
1

0
1
0
1

(a) Truth table


w0
w1

y0

w2
y1

w3

(b) Circuit

Figure 4.19. A 4-to-2 binary encoder.

w3 w2 w1 w0
0
0
0
0
1

0
0
0
1
x

0
0
1
x
x

0
1
x
x
x

y1 y0

d
0
0
1
1

0
1
1
1
1

d
0
1
0
1

Figure 4.20. Truth table for a 4-to-2 priority encoder.

Figure 4.21. A hex-to-7-segment display code converter.

Figure 4.22. A four-bit comparator circuit.

Table 4.1. The functionality of the 74381 ALU.

w3
w2
w1

w0
w1
w2

y0
y1
y2

y3
y4
y5
y6
1

En

y7

Figure 4.44. Circuit for Example 4.24.

Figure 4.45. Truth table for an 8-to-3 binary encoder.

Figure 4.46. Circuit for Example 4.26.

Figure 4.47. Binary to Gray code conversion.

Figure 4.48. Circuits for Example 4.28.

Figure 4.49. Circuits for Example 4.29.

Figure 4.50. A shifter circuit.

Figure 4.51. A barrel shifter circuit.

i1
i2
i

i4
i5
i6

i7

i8

Figure P4.1. A multiplexer-based circuit.

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